mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c@181:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
181:57724642e740
Parent:
149:156823d33999 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <stddef.h>
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 19 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #define CHANNEL_NUM 8
<> 144:ef7eb2e8f9f7 22 #define LPC_GPIO_X LPC_GPIO_PIN_INT
<> 144:ef7eb2e8f9f7 23 #define PININT_IRQ 0
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
<> 144:ef7eb2e8f9f7 26 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 static inline void handle_interrupt_in(uint32_t channel) {
<> 144:ef7eb2e8f9f7 29 uint32_t ch_bit = (1 << channel);
<> 144:ef7eb2e8f9f7 30 // Return immediately if:
<> 144:ef7eb2e8f9f7 31 // * The interrupt was already served
<> 144:ef7eb2e8f9f7 32 // * There is no user handler
<> 144:ef7eb2e8f9f7 33 // * It is a level interrupt, not an edge interrupt
<> 144:ef7eb2e8f9f7 34 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
<> 144:ef7eb2e8f9f7 35 (channel_ids[channel] == 0 ) ||
<> 144:ef7eb2e8f9f7 36 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
<> 144:ef7eb2e8f9f7 39 irq_handler(channel_ids[channel], IRQ_RISE);
<> 144:ef7eb2e8f9f7 40 LPC_GPIO_X->RISE = ch_bit;
<> 144:ef7eb2e8f9f7 41 }
<> 144:ef7eb2e8f9f7 42 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
<> 144:ef7eb2e8f9f7 43 irq_handler(channel_ids[channel], IRQ_FALL);
<> 144:ef7eb2e8f9f7 44 }
<> 144:ef7eb2e8f9f7 45 LPC_GPIO_X->IST = ch_bit;
<> 144:ef7eb2e8f9f7 46 }
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 void gpio_irq0(void) {handle_interrupt_in(0);}
<> 144:ef7eb2e8f9f7 49 void gpio_irq1(void) {handle_interrupt_in(1);}
<> 144:ef7eb2e8f9f7 50 void gpio_irq2(void) {handle_interrupt_in(2);}
<> 144:ef7eb2e8f9f7 51 void gpio_irq3(void) {handle_interrupt_in(3);}
<> 144:ef7eb2e8f9f7 52 void gpio_irq4(void) {handle_interrupt_in(4);}
<> 144:ef7eb2e8f9f7 53 void gpio_irq5(void) {handle_interrupt_in(5);}
<> 144:ef7eb2e8f9f7 54 void gpio_irq6(void) {handle_interrupt_in(6);}
<> 144:ef7eb2e8f9f7 55 void gpio_irq7(void) {handle_interrupt_in(7);}
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 58 if (pin == NC) return -1;
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 irq_handler = handler;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 int found_free_channel = 0;
<> 144:ef7eb2e8f9f7 63 int i = 0;
<> 144:ef7eb2e8f9f7 64 for (i=0; i<CHANNEL_NUM; i++) {
<> 144:ef7eb2e8f9f7 65 if (channel_ids[i] == 0) {
<> 144:ef7eb2e8f9f7 66 channel_ids[i] = id;
<> 144:ef7eb2e8f9f7 67 obj->ch = i;
<> 144:ef7eb2e8f9f7 68 found_free_channel = 1;
<> 144:ef7eb2e8f9f7 69 break;
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72 if (!found_free_channel) return -1;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Enable AHB clock to the GPIO domain. */
<> 144:ef7eb2e8f9f7 75 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* Enable AHB clock to the FlexInt, GroupedInt domain. */
<> 144:ef7eb2e8f9f7 78 LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* To select a pin for any of the eight pin interrupts, write the pin number
<> 144:ef7eb2e8f9f7 81 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
<> 144:ef7eb2e8f9f7 82 * @see: mbed_capi/PinNames.h
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 // Interrupt Wake-Up Enable
<> 144:ef7eb2e8f9f7 87 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 void (*channels_irq)(void) = NULL;
<> 144:ef7eb2e8f9f7 90 switch (obj->ch) {
<> 144:ef7eb2e8f9f7 91 case 0: channels_irq = &gpio_irq0; break;
<> 144:ef7eb2e8f9f7 92 case 1: channels_irq = &gpio_irq1; break;
<> 144:ef7eb2e8f9f7 93 case 2: channels_irq = &gpio_irq2; break;
<> 144:ef7eb2e8f9f7 94 case 3: channels_irq = &gpio_irq3; break;
<> 144:ef7eb2e8f9f7 95 case 4: channels_irq = &gpio_irq4; break;
<> 144:ef7eb2e8f9f7 96 case 5: channels_irq = &gpio_irq5; break;
<> 144:ef7eb2e8f9f7 97 case 6: channels_irq = &gpio_irq6; break;
<> 144:ef7eb2e8f9f7 98 case 7: channels_irq = &gpio_irq7; break;
<> 144:ef7eb2e8f9f7 99 }
<> 144:ef7eb2e8f9f7 100 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
<> 144:ef7eb2e8f9f7 101 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 return 0;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 void gpio_irq_free(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 107 channel_ids[obj->ch] = 0;
<> 144:ef7eb2e8f9f7 108 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
<> 144:ef7eb2e8f9f7 112 unsigned int ch_bit = (1 << obj->ch);
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // Clear interrupt
<> 144:ef7eb2e8f9f7 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
<> 144:ef7eb2e8f9f7 116 LPC_GPIO_X->IST = ch_bit;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // Edge trigger
<> 144:ef7eb2e8f9f7 119 LPC_GPIO_X->ISEL &= ~ch_bit;
<> 144:ef7eb2e8f9f7 120 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 121 if (enable) {
<> 144:ef7eb2e8f9f7 122 LPC_GPIO_X->IENR |= ch_bit;
<> 144:ef7eb2e8f9f7 123 } else {
<> 144:ef7eb2e8f9f7 124 LPC_GPIO_X->IENR &= ~ch_bit;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126 } else {
<> 144:ef7eb2e8f9f7 127 if (enable) {
<> 144:ef7eb2e8f9f7 128 LPC_GPIO_X->IENF |= ch_bit;
<> 144:ef7eb2e8f9f7 129 } else {
<> 144:ef7eb2e8f9f7 130 LPC_GPIO_X->IENF &= ~ch_bit;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 void gpio_irq_enable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 136 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 void gpio_irq_disable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 140 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
<> 144:ef7eb2e8f9f7 141 }