Diff: targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c

Revision:

187:0387e8f68319

Parent:

182:a56a73fd2a6f

Child:

188:bcfe06ba3d64

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c	Fri Jun 22 16:45:37 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c	Thu Sep 06 13:40:20 2018 +0100
@@ -30,7 +30,7 @@
 **/
 
 #include "stm32f7xx.h"
-#include "mbed_assert.h"
+#include "mbed_error.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -63,7 +63,7 @@
 {
     /* FPU settings ------------------------------------------------------------*/
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
 #endif
     /* Reset the RCC clock configuration to the default reset state ------------*/
     /* Set HSION bit */
@@ -123,8 +123,8 @@
             if (SetSysClock_PLL_HSI() == 0)
 #endif
             {
-                while(1) {
-                    MBED_ASSERT(1);
+                {
+                    error("SetSysClock failed\n");
                 }
             }
         }
@@ -180,7 +180,7 @@
     RCC_PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
     RCC_PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
     RCC_PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
-    if(HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct)  != HAL_OK) {
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct)  != HAL_OK) {
         return 0; // FAIL
     }