mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 /**
AnnaBridge 172:7d866c31b3c5 18 * This file configures the system clock as follows:
AnnaBridge 172:7d866c31b3c5 19 *-----------------------------------------------------------------
AnnaBridge 172:7d866c31b3c5 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
AnnaBridge 172:7d866c31b3c5 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
AnnaBridge 172:7d866c31b3c5 22 * | 3- USE_PLL_HSI (internal 16 MHz)
AnnaBridge 172:7d866c31b3c5 23 *-----------------------------------------------------------------
AnnaBridge 172:7d866c31b3c5 24 * SYSCLK(MHz) | 32
AnnaBridge 172:7d866c31b3c5 25 * AHBCLK (MHz) | 32
AnnaBridge 172:7d866c31b3c5 26 * APB1CLK (MHz) | 32
AnnaBridge 172:7d866c31b3c5 27 * USB capable | YES
AnnaBridge 172:7d866c31b3c5 28 *-----------------------------------------------------------------
AnnaBridge 172:7d866c31b3c5 29 */
AnnaBridge 172:7d866c31b3c5 30
AnnaBridge 172:7d866c31b3c5 31 #include "stm32l0xx.h"
AnnaBridge 187:0387e8f68319 32 #include "mbed_error.h"
AnnaBridge 172:7d866c31b3c5 33
AnnaBridge 172:7d866c31b3c5 34 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 172:7d866c31b3c5 35 Internal SRAM. */
AnnaBridge 172:7d866c31b3c5 36 /* #define VECT_TAB_SRAM */
AnnaBridge 172:7d866c31b3c5 37 #define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
AnnaBridge 172:7d866c31b3c5 38 This value must be a multiple of 0x100. */
AnnaBridge 172:7d866c31b3c5 39
AnnaBridge 172:7d866c31b3c5 40 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
AnnaBridge 172:7d866c31b3c5 41 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 172:7d866c31b3c5 42 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 172:7d866c31b3c5 43
AnnaBridge 172:7d866c31b3c5 44 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 172:7d866c31b3c5 45 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 172:7d866c31b3c5 46 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 172:7d866c31b3c5 47
AnnaBridge 172:7d866c31b3c5 48 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 172:7d866c31b3c5 49 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 172:7d866c31b3c5 50 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 172:7d866c31b3c5 51
AnnaBridge 172:7d866c31b3c5 52
AnnaBridge 172:7d866c31b3c5 53 /**
AnnaBridge 172:7d866c31b3c5 54 * @brief Setup the microcontroller system.
AnnaBridge 172:7d866c31b3c5 55 * @param None
AnnaBridge 172:7d866c31b3c5 56 * @retval None
AnnaBridge 172:7d866c31b3c5 57 */
AnnaBridge 187:0387e8f68319 58 void SystemInit(void)
AnnaBridge 172:7d866c31b3c5 59 {
AnnaBridge 172:7d866c31b3c5 60 /*!< Set MSION bit */
AnnaBridge 172:7d866c31b3c5 61 RCC->CR |= (uint32_t)0x00000100U;
AnnaBridge 172:7d866c31b3c5 62
AnnaBridge 172:7d866c31b3c5 63 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
AnnaBridge 172:7d866c31b3c5 64 RCC->CFGR &= (uint32_t) 0x88FF400CU;
AnnaBridge 172:7d866c31b3c5 65
AnnaBridge 172:7d866c31b3c5 66 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
AnnaBridge 172:7d866c31b3c5 67 RCC->CR &= (uint32_t)0xFEF6FFF6U;
AnnaBridge 172:7d866c31b3c5 68
AnnaBridge 172:7d866c31b3c5 69 /*!< Reset HSI48ON bit */
AnnaBridge 172:7d866c31b3c5 70 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
AnnaBridge 172:7d866c31b3c5 71
AnnaBridge 172:7d866c31b3c5 72 /*!< Reset HSEBYP bit */
AnnaBridge 172:7d866c31b3c5 73 RCC->CR &= (uint32_t)0xFFFBFFFFU;
AnnaBridge 172:7d866c31b3c5 74
AnnaBridge 172:7d866c31b3c5 75 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
AnnaBridge 172:7d866c31b3c5 76 RCC->CFGR &= (uint32_t)0xFF02FFFFU;
AnnaBridge 172:7d866c31b3c5 77
AnnaBridge 172:7d866c31b3c5 78 /*!< Disable all interrupts */
AnnaBridge 172:7d866c31b3c5 79 RCC->CIER = 0x00000000U;
AnnaBridge 172:7d866c31b3c5 80
AnnaBridge 172:7d866c31b3c5 81 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 172:7d866c31b3c5 82 #ifdef VECT_TAB_SRAM
AnnaBridge 172:7d866c31b3c5 83 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 172:7d866c31b3c5 84 #else
AnnaBridge 172:7d866c31b3c5 85 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 172:7d866c31b3c5 86 #endif
AnnaBridge 172:7d866c31b3c5 87
AnnaBridge 172:7d866c31b3c5 88 }
AnnaBridge 172:7d866c31b3c5 89
AnnaBridge 172:7d866c31b3c5 90 /**
AnnaBridge 172:7d866c31b3c5 91 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 172:7d866c31b3c5 92 * AHB/APBx prescalers and Flash settings
AnnaBridge 172:7d866c31b3c5 93 * @note This function should be called only once the RCC clock configuration
AnnaBridge 172:7d866c31b3c5 94 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 172:7d866c31b3c5 95 * @param None
AnnaBridge 172:7d866c31b3c5 96 * @retval None
AnnaBridge 172:7d866c31b3c5 97 */
AnnaBridge 172:7d866c31b3c5 98 void SetSysClock(void)
AnnaBridge 172:7d866c31b3c5 99 {
AnnaBridge 172:7d866c31b3c5 100 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 172:7d866c31b3c5 101 /* 1- Try to start with HSE and external clock */
AnnaBridge 172:7d866c31b3c5 102 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 172:7d866c31b3c5 103 #endif
AnnaBridge 172:7d866c31b3c5 104 {
AnnaBridge 172:7d866c31b3c5 105 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 172:7d866c31b3c5 106 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 172:7d866c31b3c5 107 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 172:7d866c31b3c5 108 #endif
AnnaBridge 172:7d866c31b3c5 109 {
AnnaBridge 172:7d866c31b3c5 110 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 172:7d866c31b3c5 111 /* 3- If fail start with HSI clock */
AnnaBridge 172:7d866c31b3c5 112 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 172:7d866c31b3c5 113 #endif
AnnaBridge 172:7d866c31b3c5 114 {
AnnaBridge 187:0387e8f68319 115 {
AnnaBridge 187:0387e8f68319 116 error("SetSysClock failed\n");
AnnaBridge 172:7d866c31b3c5 117 }
AnnaBridge 172:7d866c31b3c5 118 }
AnnaBridge 172:7d866c31b3c5 119 }
AnnaBridge 172:7d866c31b3c5 120 }
AnnaBridge 172:7d866c31b3c5 121
AnnaBridge 172:7d866c31b3c5 122 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 172:7d866c31b3c5 123 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
AnnaBridge 172:7d866c31b3c5 124 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
AnnaBridge 172:7d866c31b3c5 125 }
AnnaBridge 172:7d866c31b3c5 126
AnnaBridge 172:7d866c31b3c5 127 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 172:7d866c31b3c5 128 /******************************************************************************/
AnnaBridge 172:7d866c31b3c5 129 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 172:7d866c31b3c5 130 /******************************************************************************/
AnnaBridge 172:7d866c31b3c5 131 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 172:7d866c31b3c5 132 {
AnnaBridge 172:7d866c31b3c5 133 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 172:7d866c31b3c5 134 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 172:7d866c31b3c5 135
AnnaBridge 172:7d866c31b3c5 136 /* Used to gain time after DeepSleep in case HSI is used */
AnnaBridge 172:7d866c31b3c5 137 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
AnnaBridge 172:7d866c31b3c5 138 return 0;
AnnaBridge 172:7d866c31b3c5 139 }
AnnaBridge 172:7d866c31b3c5 140
AnnaBridge 172:7d866c31b3c5 141 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 172:7d866c31b3c5 142 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 172:7d866c31b3c5 143 regarding system frequency refer to product datasheet. */
AnnaBridge 172:7d866c31b3c5 144 __PWR_CLK_ENABLE();
AnnaBridge 172:7d866c31b3c5 145 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 172:7d866c31b3c5 146
AnnaBridge 172:7d866c31b3c5 147 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
AnnaBridge 187:0387e8f68319 148 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
AnnaBridge 172:7d866c31b3c5 149 if (bypass == 0) {
AnnaBridge 172:7d866c31b3c5 150 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
AnnaBridge 172:7d866c31b3c5 151 } else {
AnnaBridge 172:7d866c31b3c5 152 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
AnnaBridge 172:7d866c31b3c5 153 }
AnnaBridge 172:7d866c31b3c5 154 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
AnnaBridge 172:7d866c31b3c5 155 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
AnnaBridge 172:7d866c31b3c5 156 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
AnnaBridge 172:7d866c31b3c5 157 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 172:7d866c31b3c5 158 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 172:7d866c31b3c5 159 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
AnnaBridge 172:7d866c31b3c5 160 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
AnnaBridge 172:7d866c31b3c5 161 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 172:7d866c31b3c5 162 return 0; // FAIL
AnnaBridge 172:7d866c31b3c5 163 }
AnnaBridge 172:7d866c31b3c5 164
AnnaBridge 172:7d866c31b3c5 165 /* Select HSI48 as USB clock source */
AnnaBridge 172:7d866c31b3c5 166 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 172:7d866c31b3c5 167 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 172:7d866c31b3c5 168 PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
AnnaBridge 172:7d866c31b3c5 169 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
AnnaBridge 172:7d866c31b3c5 170 return 0; // FAIL
AnnaBridge 172:7d866c31b3c5 171 }
AnnaBridge 172:7d866c31b3c5 172
AnnaBridge 172:7d866c31b3c5 173 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 172:7d866c31b3c5 174 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 172:7d866c31b3c5 175 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
AnnaBridge 172:7d866c31b3c5 176 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
AnnaBridge 172:7d866c31b3c5 177 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 172:7d866c31b3c5 178 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 172:7d866c31b3c5 179 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
AnnaBridge 172:7d866c31b3c5 180 return 0; // FAIL
AnnaBridge 172:7d866c31b3c5 181 }
AnnaBridge 172:7d866c31b3c5 182
AnnaBridge 172:7d866c31b3c5 183 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 172:7d866c31b3c5 184 //if (bypass == 0)
AnnaBridge 172:7d866c31b3c5 185 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
AnnaBridge 172:7d866c31b3c5 186 //else
AnnaBridge 172:7d866c31b3c5 187 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
AnnaBridge 172:7d866c31b3c5 188
AnnaBridge 172:7d866c31b3c5 189 return 1; // OK
AnnaBridge 172:7d866c31b3c5 190 }
AnnaBridge 172:7d866c31b3c5 191 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 172:7d866c31b3c5 192
AnnaBridge 172:7d866c31b3c5 193 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 172:7d866c31b3c5 194 /******************************************************************************/
AnnaBridge 172:7d866c31b3c5 195 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 172:7d866c31b3c5 196 /******************************************************************************/
AnnaBridge 172:7d866c31b3c5 197 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 172:7d866c31b3c5 198 {
AnnaBridge 172:7d866c31b3c5 199 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 172:7d866c31b3c5 200 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 172:7d866c31b3c5 201 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
AnnaBridge 172:7d866c31b3c5 202
AnnaBridge 172:7d866c31b3c5 203 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 172:7d866c31b3c5 204 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 172:7d866c31b3c5 205 regarding system frequency refer to product datasheet. */
AnnaBridge 172:7d866c31b3c5 206 __PWR_CLK_ENABLE();
AnnaBridge 172:7d866c31b3c5 207 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 172:7d866c31b3c5 208
AnnaBridge 172:7d866c31b3c5 209 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
AnnaBridge 172:7d866c31b3c5 210 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
AnnaBridge 172:7d866c31b3c5 211 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 172:7d866c31b3c5 212 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 182:a56a73fd2a6f 213 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 172:7d866c31b3c5 214 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
AnnaBridge 172:7d866c31b3c5 215 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
AnnaBridge 172:7d866c31b3c5 216 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 172:7d866c31b3c5 217 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 172:7d866c31b3c5 218 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
AnnaBridge 172:7d866c31b3c5 219 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
AnnaBridge 172:7d866c31b3c5 220 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 172:7d866c31b3c5 221 return 0; // FAIL
AnnaBridge 172:7d866c31b3c5 222 }
AnnaBridge 172:7d866c31b3c5 223
AnnaBridge 172:7d866c31b3c5 224 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 172:7d866c31b3c5 225 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 172:7d866c31b3c5 226 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
AnnaBridge 172:7d866c31b3c5 227 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
AnnaBridge 172:7d866c31b3c5 228 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 172:7d866c31b3c5 229 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
AnnaBridge 172:7d866c31b3c5 230 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
AnnaBridge 172:7d866c31b3c5 231 return 0; // FAIL
AnnaBridge 172:7d866c31b3c5 232 }
AnnaBridge 172:7d866c31b3c5 233
AnnaBridge 172:7d866c31b3c5 234 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
AnnaBridge 172:7d866c31b3c5 235 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
AnnaBridge 172:7d866c31b3c5 236 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
AnnaBridge 172:7d866c31b3c5 237 return 0; // FAIL
AnnaBridge 172:7d866c31b3c5 238 }
AnnaBridge 172:7d866c31b3c5 239
AnnaBridge 172:7d866c31b3c5 240 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 172:7d866c31b3c5 241 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 172:7d866c31b3c5 242
AnnaBridge 172:7d866c31b3c5 243 return 1; // OK
AnnaBridge 172:7d866c31b3c5 244 }
AnnaBridge 172:7d866c31b3c5 245 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */