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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 168:9672193075cf 1 /* mbed Microcontroller Library
AnnaBridge 168:9672193075cf 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 168:9672193075cf 3 *
AnnaBridge 168:9672193075cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 168:9672193075cf 5 * you may not use this file except in compliance with the License.
AnnaBridge 168:9672193075cf 6 * You may obtain a copy of the License at
AnnaBridge 168:9672193075cf 7 *
AnnaBridge 168:9672193075cf 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 168:9672193075cf 9 *
AnnaBridge 168:9672193075cf 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 168:9672193075cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 168:9672193075cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 168:9672193075cf 13 * See the License for the specific language governing permissions and
AnnaBridge 168:9672193075cf 14 * limitations under the License.
AnnaBridge 168:9672193075cf 15 */
AnnaBridge 168:9672193075cf 16
AnnaBridge 168:9672193075cf 17 /**
AnnaBridge 168:9672193075cf 18 * This file configures the system clock as follows:
AnnaBridge 168:9672193075cf 19 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
AnnaBridge 168:9672193075cf 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
AnnaBridge 168:9672193075cf 22 * | 3- USE_PLL_HSI (internal 16 MHz)
AnnaBridge 168:9672193075cf 23 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 24 * SYSCLK(MHz) | 180
AnnaBridge 168:9672193075cf 25 * AHBCLK (MHz) | 180
AnnaBridge 168:9672193075cf 26 * APB1CLK (MHz) | 45
AnnaBridge 168:9672193075cf 27 * APB2CLK (MHz) | 90
AnnaBridge 168:9672193075cf 28 * USB capable | YES
AnnaBridge 168:9672193075cf 29 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 30 **/
AnnaBridge 168:9672193075cf 31
AnnaBridge 168:9672193075cf 32 #include "stm32f4xx.h"
AnnaBridge 187:0387e8f68319 33 #include "mbed_error.h"
AnnaBridge 168:9672193075cf 34
AnnaBridge 168:9672193075cf 35
AnnaBridge 168:9672193075cf 36 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 168:9672193075cf 37 Internal SRAM. */
AnnaBridge 168:9672193075cf 38 /* #define VECT_TAB_SRAM */
AnnaBridge 168:9672193075cf 39 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 168:9672193075cf 40 This value must be a multiple of 0x200. */
AnnaBridge 168:9672193075cf 41
AnnaBridge 168:9672193075cf 42
AnnaBridge 168:9672193075cf 43 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 168:9672193075cf 44 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
AnnaBridge 168:9672193075cf 45 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 168:9672193075cf 46 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 168:9672193075cf 47
AnnaBridge 168:9672193075cf 48 //#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
AnnaBridge 168:9672193075cf 49
AnnaBridge 168:9672193075cf 50
AnnaBridge 168:9672193075cf 51 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 52 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 168:9672193075cf 53 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 54
AnnaBridge 168:9672193075cf 55 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 56 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 168:9672193075cf 57 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 168:9672193075cf 58
AnnaBridge 168:9672193075cf 59
AnnaBridge 168:9672193075cf 60 /**
AnnaBridge 168:9672193075cf 61 * @brief Setup the microcontroller system
AnnaBridge 168:9672193075cf 62 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 168:9672193075cf 63 * configuration.
AnnaBridge 168:9672193075cf 64 * @param None
AnnaBridge 168:9672193075cf 65 * @retval None
AnnaBridge 168:9672193075cf 66 */
AnnaBridge 168:9672193075cf 67 void SystemInit(void)
AnnaBridge 168:9672193075cf 68 {
AnnaBridge 168:9672193075cf 69 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 168:9672193075cf 70 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 71 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
AnnaBridge 168:9672193075cf 72 #endif
AnnaBridge 168:9672193075cf 73 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 168:9672193075cf 74 /* Set HSION bit */
AnnaBridge 168:9672193075cf 75 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 168:9672193075cf 76
AnnaBridge 168:9672193075cf 77 /* Reset CFGR register */
AnnaBridge 168:9672193075cf 78 RCC->CFGR = 0x00000000;
AnnaBridge 168:9672193075cf 79
AnnaBridge 168:9672193075cf 80 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 168:9672193075cf 81 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 168:9672193075cf 82
AnnaBridge 168:9672193075cf 83 /* Reset PLLCFGR register */
AnnaBridge 168:9672193075cf 84 RCC->PLLCFGR = 0x24003010;
AnnaBridge 168:9672193075cf 85
AnnaBridge 168:9672193075cf 86 /* Reset HSEBYP bit */
AnnaBridge 168:9672193075cf 87 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 168:9672193075cf 88
AnnaBridge 168:9672193075cf 89 /* Disable all interrupts */
AnnaBridge 168:9672193075cf 90 RCC->CIR = 0x00000000;
AnnaBridge 168:9672193075cf 91
AnnaBridge 168:9672193075cf 92 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 168:9672193075cf 93 SystemInit_ExtMemCtl();
AnnaBridge 168:9672193075cf 94 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 168:9672193075cf 95
AnnaBridge 168:9672193075cf 96 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 168:9672193075cf 97 #ifdef VECT_TAB_SRAM
AnnaBridge 168:9672193075cf 98 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 168:9672193075cf 99 #else
AnnaBridge 168:9672193075cf 100 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 168:9672193075cf 101 #endif
AnnaBridge 168:9672193075cf 102
AnnaBridge 168:9672193075cf 103 }
AnnaBridge 168:9672193075cf 104
AnnaBridge 168:9672193075cf 105
AnnaBridge 168:9672193075cf 106 /**
AnnaBridge 168:9672193075cf 107 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 168:9672193075cf 108 * AHB/APBx prescalers and Flash settings
AnnaBridge 168:9672193075cf 109 * @note This function should be called only once the RCC clock configuration
AnnaBridge 168:9672193075cf 110 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 168:9672193075cf 111 * @param None
AnnaBridge 168:9672193075cf 112 * @retval None
AnnaBridge 168:9672193075cf 113 */
AnnaBridge 168:9672193075cf 114
AnnaBridge 168:9672193075cf 115 void SetSysClock(void)
AnnaBridge 168:9672193075cf 116 {
AnnaBridge 168:9672193075cf 117 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 168:9672193075cf 118 /* 1- Try to start with HSE and external clock */
AnnaBridge 168:9672193075cf 119 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 168:9672193075cf 120 #endif
AnnaBridge 168:9672193075cf 121 {
AnnaBridge 168:9672193075cf 122 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 168:9672193075cf 123 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 168:9672193075cf 124 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 168:9672193075cf 125 #endif
AnnaBridge 168:9672193075cf 126 {
AnnaBridge 168:9672193075cf 127 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 128 /* 3- If fail start with HSI clock */
AnnaBridge 168:9672193075cf 129 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 168:9672193075cf 130 #endif
AnnaBridge 168:9672193075cf 131 {
AnnaBridge 187:0387e8f68319 132 {
AnnaBridge 187:0387e8f68319 133 error("SetSysClock failed\n");
AnnaBridge 168:9672193075cf 134 }
AnnaBridge 168:9672193075cf 135 }
AnnaBridge 168:9672193075cf 136 }
AnnaBridge 168:9672193075cf 137 }
AnnaBridge 168:9672193075cf 138
AnnaBridge 168:9672193075cf 139 // Output clock on MCO2 pin(PC9) for debugging purpose
AnnaBridge 168:9672193075cf 140 #if DEBUG_MCO == 1
AnnaBridge 168:9672193075cf 141 HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
AnnaBridge 168:9672193075cf 142 #endif
AnnaBridge 168:9672193075cf 143 }
AnnaBridge 168:9672193075cf 144
AnnaBridge 168:9672193075cf 145 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 146 /******************************************************************************/
AnnaBridge 168:9672193075cf 147 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 168:9672193075cf 148 /******************************************************************************/
AnnaBridge 168:9672193075cf 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 168:9672193075cf 150 {
AnnaBridge 168:9672193075cf 151 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 152 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 153 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 168:9672193075cf 154
AnnaBridge 168:9672193075cf 155 /* Enable Power Control clock */
AnnaBridge 168:9672193075cf 156 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 157
AnnaBridge 168:9672193075cf 158 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 159 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 160 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 161 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 162
AnnaBridge 168:9672193075cf 163 /* Enable HSE oscillator and activate PLL with HSE as source */
AnnaBridge 168:9672193075cf 164 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 165 if (bypass == 0) {
AnnaBridge 168:9672193075cf 166 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
AnnaBridge 168:9672193075cf 167 } else {
AnnaBridge 168:9672193075cf 168 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
AnnaBridge 168:9672193075cf 169 }
AnnaBridge 168:9672193075cf 170 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 171 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 168:9672193075cf 172 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
AnnaBridge 168:9672193075cf 173 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
AnnaBridge 168:9672193075cf 174 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
AnnaBridge 168:9672193075cf 175 RCC_OscInitStruct.PLL.PLLQ = 7; //
AnnaBridge 168:9672193075cf 176 RCC_OscInitStruct.PLL.PLLR = 2; //
AnnaBridge 168:9672193075cf 177 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 178 return 0; // FAIL
AnnaBridge 168:9672193075cf 179 }
AnnaBridge 168:9672193075cf 180
AnnaBridge 168:9672193075cf 181 // Activate the OverDrive to reach the 180 MHz Frequency
AnnaBridge 168:9672193075cf 182 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
AnnaBridge 168:9672193075cf 183 return 0; // FAIL
AnnaBridge 168:9672193075cf 184 }
AnnaBridge 168:9672193075cf 185
AnnaBridge 168:9672193075cf 186 // Select PLLSAI output as USB clock source
AnnaBridge 168:9672193075cf 187 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
AnnaBridge 168:9672193075cf 188 PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
AnnaBridge 168:9672193075cf 189 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
AnnaBridge 168:9672193075cf 190 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
AnnaBridge 168:9672193075cf 191 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
AnnaBridge 168:9672193075cf 192 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 168:9672193075cf 193
AnnaBridge 168:9672193075cf 194 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 195 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 196 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 197 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
AnnaBridge 168:9672193075cf 198 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
AnnaBridge 168:9672193075cf 199 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
AnnaBridge 168:9672193075cf 200 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
AnnaBridge 168:9672193075cf 201 return 0; // FAIL
AnnaBridge 168:9672193075cf 202 }
AnnaBridge 168:9672193075cf 203
AnnaBridge 168:9672193075cf 204 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 168:9672193075cf 205 #if DEBUG_MCO == 1
AnnaBridge 187:0387e8f68319 206 if (bypass == 0) {
AnnaBridge 187:0387e8f68319 207 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
AnnaBridge 187:0387e8f68319 208 } else {
AnnaBridge 187:0387e8f68319 209 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
AnnaBridge 187:0387e8f68319 210 }
AnnaBridge 168:9672193075cf 211 #endif
AnnaBridge 168:9672193075cf 212
AnnaBridge 168:9672193075cf 213 return 1; // OK
AnnaBridge 168:9672193075cf 214 }
AnnaBridge 168:9672193075cf 215 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 216
AnnaBridge 168:9672193075cf 217 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 218 /******************************************************************************/
AnnaBridge 168:9672193075cf 219 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 168:9672193075cf 220 /******************************************************************************/
AnnaBridge 168:9672193075cf 221 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 168:9672193075cf 222 {
AnnaBridge 168:9672193075cf 223 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 224 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 225 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 168:9672193075cf 226
AnnaBridge 168:9672193075cf 227 /* Enable Power Control clock */
AnnaBridge 168:9672193075cf 228 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 229
AnnaBridge 168:9672193075cf 230 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 231 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 232 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 233 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 234
AnnaBridge 168:9672193075cf 235 /* Enable HSI oscillator and activate PLL with HSI as source */
AnnaBridge 168:9672193075cf 236 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 237 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 168:9672193075cf 238 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 239 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 168:9672193075cf 240 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 241 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 168:9672193075cf 242 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
AnnaBridge 168:9672193075cf 243 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
AnnaBridge 168:9672193075cf 244 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
AnnaBridge 168:9672193075cf 245 RCC_OscInitStruct.PLL.PLLQ = 7; //
AnnaBridge 168:9672193075cf 246 RCC_OscInitStruct.PLL.PLLR = 6; //
AnnaBridge 168:9672193075cf 247 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 248 return 0; // FAIL
AnnaBridge 168:9672193075cf 249 }
AnnaBridge 168:9672193075cf 250
AnnaBridge 168:9672193075cf 251 /* Select PLLSAI output as USB clock source */
AnnaBridge 168:9672193075cf 252 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
AnnaBridge 168:9672193075cf 253 PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
AnnaBridge 168:9672193075cf 254 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
AnnaBridge 168:9672193075cf 255 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
AnnaBridge 168:9672193075cf 256 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
AnnaBridge 168:9672193075cf 257 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 168:9672193075cf 258
AnnaBridge 168:9672193075cf 259 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 260 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 261 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
AnnaBridge 168:9672193075cf 262 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
AnnaBridge 168:9672193075cf 263 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
AnnaBridge 168:9672193075cf 264 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
AnnaBridge 168:9672193075cf 265 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
AnnaBridge 168:9672193075cf 266 return 0; // FAIL
AnnaBridge 168:9672193075cf 267 }
AnnaBridge 168:9672193075cf 268
AnnaBridge 168:9672193075cf 269 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 168:9672193075cf 270 #if DEBUG_MCO == 1
AnnaBridge 168:9672193075cf 271 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 168:9672193075cf 272 #endif
AnnaBridge 168:9672193075cf 273
AnnaBridge 168:9672193075cf 274 return 1; // OK
AnnaBridge 168:9672193075cf 275 }
AnnaBridge 168:9672193075cf 276 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */