mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 168:9672193075cf 1 /* mbed Microcontroller Library
AnnaBridge 168:9672193075cf 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 168:9672193075cf 3 *
AnnaBridge 168:9672193075cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 168:9672193075cf 5 * you may not use this file except in compliance with the License.
AnnaBridge 168:9672193075cf 6 * You may obtain a copy of the License at
AnnaBridge 168:9672193075cf 7 *
AnnaBridge 168:9672193075cf 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 168:9672193075cf 9 *
AnnaBridge 168:9672193075cf 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 168:9672193075cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 168:9672193075cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 168:9672193075cf 13 * See the License for the specific language governing permissions and
AnnaBridge 168:9672193075cf 14 * limitations under the License.
AnnaBridge 168:9672193075cf 15 */
AnnaBridge 168:9672193075cf 16
AnnaBridge 168:9672193075cf 17 /**
AnnaBridge 168:9672193075cf 18 * This file configures the system clock as follows:
AnnaBridge 168:9672193075cf 19 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
AnnaBridge 168:9672193075cf 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
AnnaBridge 168:9672193075cf 22 * | 3- USE_PLL_HSI (internal 16 MHz)
AnnaBridge 168:9672193075cf 23 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 24 * SYSCLK(MHz) | 100
AnnaBridge 168:9672193075cf 25 * AHBCLK (MHz) | 100
AnnaBridge 168:9672193075cf 26 * APB1CLK (MHz) | 50
AnnaBridge 168:9672193075cf 27 * APB2CLK (MHz) | 100
AnnaBridge 168:9672193075cf 28 * USB capable | YES
AnnaBridge 168:9672193075cf 29 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 30 **/
AnnaBridge 168:9672193075cf 31
AnnaBridge 168:9672193075cf 32 #include "stm32f4xx.h"
AnnaBridge 187:0387e8f68319 33 #include "mbed_error.h"
AnnaBridge 188:bcfe06ba3d64 34 #include "nvic_addr.h"
AnnaBridge 168:9672193075cf 35
AnnaBridge 168:9672193075cf 36 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 168:9672193075cf 37 Internal SRAM. */
AnnaBridge 168:9672193075cf 38 /* #define VECT_TAB_SRAM */
AnnaBridge 168:9672193075cf 39 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 168:9672193075cf 40 This value must be a multiple of 0x200. */
AnnaBridge 168:9672193075cf 41
AnnaBridge 168:9672193075cf 42
AnnaBridge 168:9672193075cf 43 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 168:9672193075cf 44 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
AnnaBridge 168:9672193075cf 45 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 168:9672193075cf 46 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 168:9672193075cf 47
AnnaBridge 168:9672193075cf 48 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 49 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 168:9672193075cf 50 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 51
AnnaBridge 168:9672193075cf 52 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 53 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 168:9672193075cf 54 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 168:9672193075cf 55
AnnaBridge 168:9672193075cf 56
AnnaBridge 168:9672193075cf 57 /**
AnnaBridge 168:9672193075cf 58 * @brief Setup the microcontroller system
AnnaBridge 168:9672193075cf 59 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 168:9672193075cf 60 * configuration.
AnnaBridge 168:9672193075cf 61 * @param None
AnnaBridge 168:9672193075cf 62 * @retval None
AnnaBridge 168:9672193075cf 63 */
AnnaBridge 168:9672193075cf 64 void SystemInit(void)
AnnaBridge 168:9672193075cf 65 {
AnnaBridge 168:9672193075cf 66 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 168:9672193075cf 67 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 68 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
AnnaBridge 168:9672193075cf 69 #endif
AnnaBridge 168:9672193075cf 70 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 168:9672193075cf 71 /* Set HSION bit */
AnnaBridge 168:9672193075cf 72 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 168:9672193075cf 73
AnnaBridge 168:9672193075cf 74 /* Reset CFGR register */
AnnaBridge 168:9672193075cf 75 RCC->CFGR = 0x00000000;
AnnaBridge 168:9672193075cf 76
AnnaBridge 168:9672193075cf 77 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 168:9672193075cf 78 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 168:9672193075cf 79
AnnaBridge 168:9672193075cf 80 /* Reset PLLCFGR register */
AnnaBridge 168:9672193075cf 81 RCC->PLLCFGR = 0x24003010;
AnnaBridge 168:9672193075cf 82
AnnaBridge 168:9672193075cf 83 /* Reset HSEBYP bit */
AnnaBridge 168:9672193075cf 84 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 168:9672193075cf 85
AnnaBridge 168:9672193075cf 86 /* Disable all interrupts */
AnnaBridge 168:9672193075cf 87 RCC->CIR = 0x00000000;
AnnaBridge 168:9672193075cf 88
AnnaBridge 168:9672193075cf 89 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 168:9672193075cf 90 SystemInit_ExtMemCtl();
AnnaBridge 168:9672193075cf 91 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 168:9672193075cf 92
AnnaBridge 168:9672193075cf 93 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 168:9672193075cf 94 #ifdef VECT_TAB_SRAM
AnnaBridge 168:9672193075cf 95 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 168:9672193075cf 96 #else
AnnaBridge 188:bcfe06ba3d64 97 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 168:9672193075cf 98 #endif
AnnaBridge 168:9672193075cf 99
AnnaBridge 188:bcfe06ba3d64 100 /* In DISCO_F413ZH board, Arduino connector and Wifi embeded module are sharing the same SPI pins */
AnnaBridge 188:bcfe06ba3d64 101 /* We need to set the default SPI SS pin for the Wifi module to the inactive state i.e. 1 */
AnnaBridge 188:bcfe06ba3d64 102 /* See board User Manual: WIFI_SPI_CS = PG_11*/
AnnaBridge 188:bcfe06ba3d64 103 __HAL_RCC_GPIOG_CLK_ENABLE();
AnnaBridge 188:bcfe06ba3d64 104 GPIO_InitTypeDef GPIO_InitStruct;
AnnaBridge 188:bcfe06ba3d64 105 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
AnnaBridge 188:bcfe06ba3d64 106 GPIO_InitStruct.Pull = GPIO_NOPULL;
AnnaBridge 188:bcfe06ba3d64 107 GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
AnnaBridge 188:bcfe06ba3d64 108 GPIO_InitStruct.Pin = GPIO_PIN_11;
AnnaBridge 188:bcfe06ba3d64 109 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
AnnaBridge 188:bcfe06ba3d64 110 HAL_GPIO_WritePin(GPIOG, GPIO_PIN_11, GPIO_PIN_SET);
AnnaBridge 168:9672193075cf 111 }
AnnaBridge 168:9672193075cf 112
AnnaBridge 168:9672193075cf 113
AnnaBridge 168:9672193075cf 114 /**
AnnaBridge 168:9672193075cf 115 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 168:9672193075cf 116 * AHB/APBx prescalers and Flash settings
AnnaBridge 168:9672193075cf 117 * @note This function should be called only once the RCC clock configuration
AnnaBridge 168:9672193075cf 118 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 168:9672193075cf 119 * @param None
AnnaBridge 168:9672193075cf 120 * @retval None
AnnaBridge 168:9672193075cf 121 */
AnnaBridge 168:9672193075cf 122
AnnaBridge 168:9672193075cf 123 void SetSysClock(void)
AnnaBridge 168:9672193075cf 124 {
AnnaBridge 168:9672193075cf 125 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 168:9672193075cf 126 /* 1- Try to start with HSE and external clock */
AnnaBridge 168:9672193075cf 127 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 168:9672193075cf 128 #endif
AnnaBridge 168:9672193075cf 129 {
AnnaBridge 168:9672193075cf 130 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 168:9672193075cf 131 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 168:9672193075cf 132 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 168:9672193075cf 133 #endif
AnnaBridge 168:9672193075cf 134 {
AnnaBridge 168:9672193075cf 135 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 136 /* 3- If fail start with HSI clock */
AnnaBridge 168:9672193075cf 137 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 168:9672193075cf 138 #endif
AnnaBridge 168:9672193075cf 139 {
AnnaBridge 187:0387e8f68319 140 {
AnnaBridge 187:0387e8f68319 141 error("SetSysClock failed\n");
AnnaBridge 168:9672193075cf 142 }
AnnaBridge 168:9672193075cf 143 }
AnnaBridge 168:9672193075cf 144 }
AnnaBridge 168:9672193075cf 145 }
AnnaBridge 168:9672193075cf 146
AnnaBridge 168:9672193075cf 147 /* Output clock on MCO2 pin(PC9) for debugging purpose */
AnnaBridge 168:9672193075cf 148 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
AnnaBridge 168:9672193075cf 149 }
AnnaBridge 168:9672193075cf 150
AnnaBridge 168:9672193075cf 151 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 152 /******************************************************************************/
AnnaBridge 168:9672193075cf 153 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 168:9672193075cf 154 /******************************************************************************/
AnnaBridge 168:9672193075cf 155 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 168:9672193075cf 156 {
AnnaBridge 168:9672193075cf 157 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 158 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 159 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 168:9672193075cf 160
AnnaBridge 168:9672193075cf 161 /* Enable Power Control clock */
AnnaBridge 168:9672193075cf 162 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 163
AnnaBridge 168:9672193075cf 164 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 165 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 166 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 167 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 168
AnnaBridge 168:9672193075cf 169 /* Enable HSE oscillator and activate PLL with HSE as source */
AnnaBridge 168:9672193075cf 170 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 171 if (bypass == 0) {
AnnaBridge 168:9672193075cf 172 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
AnnaBridge 168:9672193075cf 173 } else {
AnnaBridge 168:9672193075cf 174 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
AnnaBridge 168:9672193075cf 175 }
AnnaBridge 168:9672193075cf 176
AnnaBridge 168:9672193075cf 177 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 178 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 168:9672193075cf 179
AnnaBridge 168:9672193075cf 180 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
AnnaBridge 168:9672193075cf 181 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200)
AnnaBridge 168:9672193075cf 182 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
AnnaBridge 168:9672193075cf 183 RCC_OscInitStruct.PLL.PLLQ = 7;
AnnaBridge 168:9672193075cf 184 RCC_OscInitStruct.PLL.PLLR = 2;
AnnaBridge 168:9672193075cf 185
AnnaBridge 168:9672193075cf 186 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 187 return 0; // FAIL
AnnaBridge 168:9672193075cf 188 }
AnnaBridge 168:9672193075cf 189
AnnaBridge 168:9672193075cf 190 /* Select PLLSAI output as USB clock source */
Anna Bridge 180:96ed750bd169 191 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
AnnaBridge 168:9672193075cf 192 PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
AnnaBridge 168:9672193075cf 193 PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
AnnaBridge 168:9672193075cf 194 PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
Anna Bridge 180:96ed750bd169 195 PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
AnnaBridge 168:9672193075cf 196 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
Anna Bridge 180:96ed750bd169 197 PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
AnnaBridge 168:9672193075cf 198
AnnaBridge 168:9672193075cf 199 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 168:9672193075cf 200
AnnaBridge 168:9672193075cf 201 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 202 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 203 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 204 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
AnnaBridge 168:9672193075cf 205 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
AnnaBridge 168:9672193075cf 206 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
AnnaBridge 168:9672193075cf 207
AnnaBridge 168:9672193075cf 208 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
AnnaBridge 168:9672193075cf 209 return 0; // FAIL
AnnaBridge 168:9672193075cf 210 }
AnnaBridge 168:9672193075cf 211
AnnaBridge 168:9672193075cf 212 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 168:9672193075cf 213 //if (bypass == 0)
AnnaBridge 168:9672193075cf 214 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
AnnaBridge 168:9672193075cf 215 //else
AnnaBridge 168:9672193075cf 216 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
AnnaBridge 168:9672193075cf 217
AnnaBridge 168:9672193075cf 218 return 1; // OK
AnnaBridge 168:9672193075cf 219 }
AnnaBridge 168:9672193075cf 220 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 221
AnnaBridge 168:9672193075cf 222 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 223 /******************************************************************************/
AnnaBridge 168:9672193075cf 224 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 168:9672193075cf 225 /******************************************************************************/
AnnaBridge 168:9672193075cf 226 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 168:9672193075cf 227 {
AnnaBridge 168:9672193075cf 228 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 229 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 230 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 168:9672193075cf 231
AnnaBridge 168:9672193075cf 232 /* Enable Power Control clock */
AnnaBridge 168:9672193075cf 233 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 234
AnnaBridge 168:9672193075cf 235 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 236 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 237 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 238 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 239
AnnaBridge 168:9672193075cf 240 /* Enable HSI oscillator and activate PLL with HSI as source */
AnnaBridge 168:9672193075cf 241 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 242 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 168:9672193075cf 243 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 244 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 168:9672193075cf 245 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 246 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 168:9672193075cf 247 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
AnnaBridge 168:9672193075cf 248 RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100)
AnnaBridge 168:9672193075cf 249 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
AnnaBridge 168:9672193075cf 250 RCC_OscInitStruct.PLL.PLLQ = 2;
AnnaBridge 168:9672193075cf 251 RCC_OscInitStruct.PLL.PLLR = 2;
AnnaBridge 168:9672193075cf 252
AnnaBridge 168:9672193075cf 253 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 254 return 0; // FAIL
AnnaBridge 168:9672193075cf 255 }
AnnaBridge 168:9672193075cf 256
AnnaBridge 168:9672193075cf 257 /* Select PLLI2S output as USB clock source */
Anna Bridge 180:96ed750bd169 258 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
AnnaBridge 168:9672193075cf 259 PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
AnnaBridge 168:9672193075cf 260 PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
AnnaBridge 168:9672193075cf 261 PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
Anna Bridge 180:96ed750bd169 262 PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
AnnaBridge 168:9672193075cf 263 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
Anna Bridge 180:96ed750bd169 264 PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
AnnaBridge 168:9672193075cf 265
AnnaBridge 168:9672193075cf 266 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 168:9672193075cf 267
AnnaBridge 168:9672193075cf 268 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 269 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 270 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 271 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
AnnaBridge 168:9672193075cf 272 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
AnnaBridge 168:9672193075cf 273 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
AnnaBridge 168:9672193075cf 274
AnnaBridge 168:9672193075cf 275 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
AnnaBridge 168:9672193075cf 276 return 0; // FAIL
AnnaBridge 168:9672193075cf 277 }
AnnaBridge 168:9672193075cf 278
AnnaBridge 168:9672193075cf 279 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 168:9672193075cf 280 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 168:9672193075cf 281
AnnaBridge 168:9672193075cf 282 return 1; // OK
AnnaBridge 168:9672193075cf 283 }
AnnaBridge 168:9672193075cf 284 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */