mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_sdmmc.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 167:e84263d55307
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f2xx_ll_sdmmc.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.2.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief Header file of SDMMC HAL module. |
<> | 144:ef7eb2e8f9f7 | 8 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 9 | * @attention |
<> | 144:ef7eb2e8f9f7 | 10 | * |
AnnaBridge | 167:e84263d55307 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 19 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 21 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 22 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 36 | */ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 39 | #ifndef __STM32F2xx_LL_SDMMC_H |
<> | 144:ef7eb2e8f9f7 | 40 | #define __STM32F2xx_LL_SDMMC_H |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 43 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 47 | #include "stm32f2xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /** @addtogroup STM32F2xx_Driver |
<> | 144:ef7eb2e8f9f7 | 50 | * @{ |
<> | 144:ef7eb2e8f9f7 | 51 | */ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /** @addtogroup SDMMC_LL |
<> | 144:ef7eb2e8f9f7 | 54 | * @{ |
<> | 144:ef7eb2e8f9f7 | 55 | */ |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 58 | /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types |
<> | 144:ef7eb2e8f9f7 | 59 | * @{ |
<> | 144:ef7eb2e8f9f7 | 60 | */ |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | /** |
<> | 144:ef7eb2e8f9f7 | 63 | * @brief SDMMC Configuration Structure definition |
<> | 144:ef7eb2e8f9f7 | 64 | */ |
<> | 144:ef7eb2e8f9f7 | 65 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 66 | { |
<> | 144:ef7eb2e8f9f7 | 67 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
AnnaBridge | 167:e84263d55307 | 68 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
<> | 144:ef7eb2e8f9f7 | 69 | |
AnnaBridge | 167:e84263d55307 | 70 | uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is |
<> | 144:ef7eb2e8f9f7 | 71 | enabled or disabled. |
AnnaBridge | 167:e84263d55307 | 72 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
<> | 144:ef7eb2e8f9f7 | 73 | |
AnnaBridge | 167:e84263d55307 | 74 | uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or |
<> | 144:ef7eb2e8f9f7 | 75 | disabled when the bus is idle. |
AnnaBridge | 167:e84263d55307 | 76 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
<> | 144:ef7eb2e8f9f7 | 77 | |
AnnaBridge | 167:e84263d55307 | 78 | uint32_t BusWide; /*!< Specifies the SDMMC bus width. |
AnnaBridge | 167:e84263d55307 | 79 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
<> | 144:ef7eb2e8f9f7 | 80 | |
AnnaBridge | 167:e84263d55307 | 81 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. |
AnnaBridge | 167:e84263d55307 | 82 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
<> | 144:ef7eb2e8f9f7 | 83 | |
AnnaBridge | 167:e84263d55307 | 84 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. |
<> | 144:ef7eb2e8f9f7 | 85 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | }SDIO_InitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /** |
AnnaBridge | 167:e84263d55307 | 91 | * @brief SDMMC Command Control structure |
<> | 144:ef7eb2e8f9f7 | 92 | */ |
<> | 144:ef7eb2e8f9f7 | 93 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 94 | { |
AnnaBridge | 167:e84263d55307 | 95 | uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent |
<> | 144:ef7eb2e8f9f7 | 96 | to a card as part of a command message. If a command |
<> | 144:ef7eb2e8f9f7 | 97 | contains an argument, it must be loaded into this register |
<> | 144:ef7eb2e8f9f7 | 98 | before writing the command to the command register. */ |
<> | 144:ef7eb2e8f9f7 | 99 | |
AnnaBridge | 167:e84263d55307 | 100 | uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and |
<> | 144:ef7eb2e8f9f7 | 101 | Max_Data = 64 */ |
<> | 144:ef7eb2e8f9f7 | 102 | |
AnnaBridge | 167:e84263d55307 | 103 | uint32_t Response; /*!< Specifies the SDMMC response type. |
AnnaBridge | 167:e84263d55307 | 104 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
<> | 144:ef7eb2e8f9f7 | 105 | |
AnnaBridge | 167:e84263d55307 | 106 | uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is |
<> | 144:ef7eb2e8f9f7 | 107 | enabled or disabled. |
AnnaBridge | 167:e84263d55307 | 108 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
<> | 144:ef7eb2e8f9f7 | 109 | |
AnnaBridge | 167:e84263d55307 | 110 | uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) |
<> | 144:ef7eb2e8f9f7 | 111 | is enabled or disabled. |
AnnaBridge | 167:e84263d55307 | 112 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
<> | 144:ef7eb2e8f9f7 | 113 | }SDIO_CmdInitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | /** |
AnnaBridge | 167:e84263d55307 | 117 | * @brief SDMMC Data Control structure |
<> | 144:ef7eb2e8f9f7 | 118 | */ |
<> | 144:ef7eb2e8f9f7 | 119 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 120 | { |
<> | 144:ef7eb2e8f9f7 | 121 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
AnnaBridge | 167:e84263d55307 | 126 | This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
<> | 144:ef7eb2e8f9f7 | 129 | is a read or write. |
AnnaBridge | 167:e84263d55307 | 130 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
AnnaBridge | 167:e84263d55307 | 133 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
<> | 144:ef7eb2e8f9f7 | 134 | |
AnnaBridge | 167:e84263d55307 | 135 | uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) |
<> | 144:ef7eb2e8f9f7 | 136 | is enabled or disabled. |
AnnaBridge | 167:e84263d55307 | 137 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
<> | 144:ef7eb2e8f9f7 | 138 | }SDIO_DataInitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | /** |
<> | 144:ef7eb2e8f9f7 | 141 | * @} |
<> | 144:ef7eb2e8f9f7 | 142 | */ |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 145 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
<> | 144:ef7eb2e8f9f7 | 146 | * @{ |
<> | 144:ef7eb2e8f9f7 | 147 | */ |
AnnaBridge | 167:e84263d55307 | 148 | #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ |
AnnaBridge | 167:e84263d55307 | 149 | #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ |
AnnaBridge | 167:e84263d55307 | 150 | #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ |
AnnaBridge | 167:e84263d55307 | 151 | #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ |
AnnaBridge | 167:e84263d55307 | 152 | #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ |
AnnaBridge | 167:e84263d55307 | 153 | #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ |
AnnaBridge | 167:e84263d55307 | 154 | #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ |
AnnaBridge | 167:e84263d55307 | 155 | #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ |
AnnaBridge | 167:e84263d55307 | 156 | #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the |
AnnaBridge | 167:e84263d55307 | 157 | number of transferred bytes does not match the block length */ |
AnnaBridge | 167:e84263d55307 | 158 | #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ |
AnnaBridge | 167:e84263d55307 | 159 | #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ |
AnnaBridge | 167:e84263d55307 | 160 | #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ |
AnnaBridge | 167:e84263d55307 | 161 | #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock |
AnnaBridge | 167:e84263d55307 | 162 | command or if there was an attempt to access a locked card */ |
AnnaBridge | 167:e84263d55307 | 163 | #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ |
AnnaBridge | 167:e84263d55307 | 164 | #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ |
AnnaBridge | 167:e84263d55307 | 165 | #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ |
AnnaBridge | 167:e84263d55307 | 166 | #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ |
AnnaBridge | 167:e84263d55307 | 167 | #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ |
AnnaBridge | 167:e84263d55307 | 168 | #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ |
AnnaBridge | 167:e84263d55307 | 169 | #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ |
AnnaBridge | 167:e84263d55307 | 170 | #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ |
AnnaBridge | 167:e84263d55307 | 171 | #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ |
AnnaBridge | 167:e84263d55307 | 172 | #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ |
AnnaBridge | 167:e84263d55307 | 173 | #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out |
AnnaBridge | 167:e84263d55307 | 174 | of erase sequence command was received */ |
AnnaBridge | 167:e84263d55307 | 175 | #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ |
AnnaBridge | 167:e84263d55307 | 176 | #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ |
AnnaBridge | 167:e84263d55307 | 177 | #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ |
AnnaBridge | 167:e84263d55307 | 178 | #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ |
AnnaBridge | 167:e84263d55307 | 179 | #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ |
AnnaBridge | 167:e84263d55307 | 180 | #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ |
AnnaBridge | 167:e84263d55307 | 181 | #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ |
AnnaBridge | 167:e84263d55307 | 182 | #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ |
AnnaBridge | 167:e84263d55307 | 183 | #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ |
<> | 144:ef7eb2e8f9f7 | 184 | |
AnnaBridge | 167:e84263d55307 | 185 | /** |
AnnaBridge | 167:e84263d55307 | 186 | * @brief SDMMC Commands Index |
AnnaBridge | 167:e84263d55307 | 187 | */ |
AnnaBridge | 167:e84263d55307 | 188 | #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ |
AnnaBridge | 167:e84263d55307 | 189 | #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ |
AnnaBridge | 167:e84263d55307 | 190 | #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ |
AnnaBridge | 167:e84263d55307 | 191 | #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ |
AnnaBridge | 167:e84263d55307 | 192 | #define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ |
AnnaBridge | 167:e84263d55307 | 193 | #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its |
AnnaBridge | 167:e84263d55307 | 194 | operating condition register (OCR) content in the response on the CMD line. */ |
AnnaBridge | 167:e84263d55307 | 195 | #define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ |
AnnaBridge | 167:e84263d55307 | 196 | #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ |
AnnaBridge | 167:e84263d55307 | 197 | #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information |
AnnaBridge | 167:e84263d55307 | 198 | and asks the card whether card supports voltage. */ |
AnnaBridge | 167:e84263d55307 | 199 | #define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ |
AnnaBridge | 167:e84263d55307 | 200 | #define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ |
AnnaBridge | 167:e84263d55307 | 201 | #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ |
AnnaBridge | 167:e84263d55307 | 202 | #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ |
AnnaBridge | 167:e84263d55307 | 203 | #define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ |
AnnaBridge | 167:e84263d55307 | 204 | #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */ |
AnnaBridge | 167:e84263d55307 | 205 | #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ |
AnnaBridge | 167:e84263d55307 | 206 | #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands |
AnnaBridge | 167:e84263d55307 | 207 | (read, write, lock). Default block length is fixed to 512 Bytes. Not effective |
AnnaBridge | 167:e84263d55307 | 208 | for SDHS and SDXC. */ |
AnnaBridge | 167:e84263d55307 | 209 | #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
AnnaBridge | 167:e84263d55307 | 210 | fixed 512 bytes in case of SDHC and SDXC. */ |
AnnaBridge | 167:e84263d55307 | 211 | #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by |
AnnaBridge | 167:e84263d55307 | 212 | STOP_TRANSMISSION command. */ |
AnnaBridge | 167:e84263d55307 | 213 | #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ |
AnnaBridge | 167:e84263d55307 | 214 | #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ |
AnnaBridge | 167:e84263d55307 | 215 | #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ |
AnnaBridge | 167:e84263d55307 | 216 | #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
AnnaBridge | 167:e84263d55307 | 217 | fixed 512 bytes in case of SDHC and SDXC. */ |
AnnaBridge | 167:e84263d55307 | 218 | #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ |
AnnaBridge | 167:e84263d55307 | 219 | #define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ |
AnnaBridge | 167:e84263d55307 | 220 | #define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ |
AnnaBridge | 167:e84263d55307 | 221 | #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ |
AnnaBridge | 167:e84263d55307 | 222 | #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ |
AnnaBridge | 167:e84263d55307 | 223 | #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ |
AnnaBridge | 167:e84263d55307 | 224 | #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ |
AnnaBridge | 167:e84263d55307 | 225 | #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ |
AnnaBridge | 167:e84263d55307 | 226 | #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command |
AnnaBridge | 167:e84263d55307 | 227 | system set by switch function command (CMD6). */ |
AnnaBridge | 167:e84263d55307 | 228 | #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. |
AnnaBridge | 167:e84263d55307 | 229 | Reserved for each command system set by switch function command (CMD6). */ |
AnnaBridge | 167:e84263d55307 | 230 | #define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ |
AnnaBridge | 167:e84263d55307 | 231 | #define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ |
AnnaBridge | 167:e84263d55307 | 232 | #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ |
AnnaBridge | 167:e84263d55307 | 233 | #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by |
AnnaBridge | 167:e84263d55307 | 234 | the SET_BLOCK_LEN command. */ |
AnnaBridge | 167:e84263d55307 | 235 | #define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather |
AnnaBridge | 167:e84263d55307 | 236 | than a standard command. */ |
AnnaBridge | 167:e84263d55307 | 237 | #define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card |
AnnaBridge | 167:e84263d55307 | 238 | for general purpose/application specific commands. */ |
AnnaBridge | 167:e84263d55307 | 239 | #define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */ |
AnnaBridge | 167:e84263d55307 | 240 | |
AnnaBridge | 167:e84263d55307 | 241 | /** |
AnnaBridge | 167:e84263d55307 | 242 | * @brief Following commands are SD Card Specific commands. |
AnnaBridge | 167:e84263d55307 | 243 | * SDMMC_APP_CMD should be sent before sending these commands. |
AnnaBridge | 167:e84263d55307 | 244 | */ |
AnnaBridge | 167:e84263d55307 | 245 | #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus |
AnnaBridge | 167:e84263d55307 | 246 | widths are given in SCR register. */ |
AnnaBridge | 167:e84263d55307 | 247 | #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ |
AnnaBridge | 167:e84263d55307 | 248 | #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with |
AnnaBridge | 167:e84263d55307 | 249 | 32bit+CRC data block. */ |
AnnaBridge | 167:e84263d55307 | 250 | #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to |
AnnaBridge | 167:e84263d55307 | 251 | send its operating condition register (OCR) content in the response on the CMD line. */ |
AnnaBridge | 167:e84263d55307 | 252 | #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ |
AnnaBridge | 167:e84263d55307 | 253 | #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ |
AnnaBridge | 167:e84263d55307 | 254 | #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ |
AnnaBridge | 167:e84263d55307 | 255 | #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ |
AnnaBridge | 167:e84263d55307 | 256 | |
AnnaBridge | 167:e84263d55307 | 257 | /** |
AnnaBridge | 167:e84263d55307 | 258 | * @brief Following commands are SD Card Specific security commands. |
AnnaBridge | 167:e84263d55307 | 259 | * SDMMC_CMD_APP_CMD should be sent before sending these commands. |
AnnaBridge | 167:e84263d55307 | 260 | */ |
AnnaBridge | 167:e84263d55307 | 261 | #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43) |
AnnaBridge | 167:e84263d55307 | 262 | #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44) |
AnnaBridge | 167:e84263d55307 | 263 | #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) |
AnnaBridge | 167:e84263d55307 | 264 | #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) |
AnnaBridge | 167:e84263d55307 | 265 | #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) |
AnnaBridge | 167:e84263d55307 | 266 | #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) |
AnnaBridge | 167:e84263d55307 | 267 | #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) |
AnnaBridge | 167:e84263d55307 | 268 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) |
AnnaBridge | 167:e84263d55307 | 269 | #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) |
AnnaBridge | 167:e84263d55307 | 270 | #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) |
AnnaBridge | 167:e84263d55307 | 271 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) |
AnnaBridge | 167:e84263d55307 | 272 | |
AnnaBridge | 167:e84263d55307 | 273 | /** |
AnnaBridge | 167:e84263d55307 | 274 | * @brief Masks for errors Card Status R1 (OCR Register) |
AnnaBridge | 167:e84263d55307 | 275 | */ |
AnnaBridge | 167:e84263d55307 | 276 | #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U |
AnnaBridge | 167:e84263d55307 | 277 | #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U |
AnnaBridge | 167:e84263d55307 | 278 | #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U |
AnnaBridge | 167:e84263d55307 | 279 | #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U |
AnnaBridge | 167:e84263d55307 | 280 | #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U |
AnnaBridge | 167:e84263d55307 | 281 | #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U |
AnnaBridge | 167:e84263d55307 | 282 | #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U |
AnnaBridge | 167:e84263d55307 | 283 | #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U |
AnnaBridge | 167:e84263d55307 | 284 | #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U |
AnnaBridge | 167:e84263d55307 | 285 | #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U |
AnnaBridge | 167:e84263d55307 | 286 | #define SDMMC_OCR_CC_ERROR 0x00100000U |
AnnaBridge | 167:e84263d55307 | 287 | #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U |
AnnaBridge | 167:e84263d55307 | 288 | #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U |
AnnaBridge | 167:e84263d55307 | 289 | #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U |
AnnaBridge | 167:e84263d55307 | 290 | #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U |
AnnaBridge | 167:e84263d55307 | 291 | #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U |
AnnaBridge | 167:e84263d55307 | 292 | #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U |
AnnaBridge | 167:e84263d55307 | 293 | #define SDMMC_OCR_ERASE_RESET 0x00002000U |
AnnaBridge | 167:e84263d55307 | 294 | #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U |
AnnaBridge | 167:e84263d55307 | 295 | #define SDMMC_OCR_ERRORBITS 0xFDFFE008U |
AnnaBridge | 167:e84263d55307 | 296 | |
AnnaBridge | 167:e84263d55307 | 297 | /** |
AnnaBridge | 167:e84263d55307 | 298 | * @brief Masks for R6 Response |
AnnaBridge | 167:e84263d55307 | 299 | */ |
AnnaBridge | 167:e84263d55307 | 300 | #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U |
AnnaBridge | 167:e84263d55307 | 301 | #define SDMMC_R6_ILLEGAL_CMD 0x00004000U |
AnnaBridge | 167:e84263d55307 | 302 | #define SDMMC_R6_COM_CRC_FAILED 0x00008000U |
AnnaBridge | 167:e84263d55307 | 303 | |
AnnaBridge | 167:e84263d55307 | 304 | #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U |
AnnaBridge | 167:e84263d55307 | 305 | #define SDMMC_HIGH_CAPACITY 0x40000000U |
AnnaBridge | 167:e84263d55307 | 306 | #define SDMMC_STD_CAPACITY 0x00000000U |
AnnaBridge | 167:e84263d55307 | 307 | #define SDMMC_CHECK_PATTERN 0x000001AAU |
AnnaBridge | 167:e84263d55307 | 308 | |
AnnaBridge | 167:e84263d55307 | 309 | #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU |
AnnaBridge | 167:e84263d55307 | 310 | |
AnnaBridge | 167:e84263d55307 | 311 | #define SDMMC_MAX_TRIAL 0x0000FFFFU |
AnnaBridge | 167:e84263d55307 | 312 | |
AnnaBridge | 167:e84263d55307 | 313 | #define SDMMC_ALLZERO 0x00000000U |
AnnaBridge | 167:e84263d55307 | 314 | |
AnnaBridge | 167:e84263d55307 | 315 | #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U |
AnnaBridge | 167:e84263d55307 | 316 | #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U |
AnnaBridge | 167:e84263d55307 | 317 | #define SDMMC_CARD_LOCKED 0x02000000U |
AnnaBridge | 167:e84263d55307 | 318 | |
AnnaBridge | 167:e84263d55307 | 319 | #define SDMMC_DATATIMEOUT 0xFFFFFFFFU |
AnnaBridge | 167:e84263d55307 | 320 | |
AnnaBridge | 167:e84263d55307 | 321 | #define SDMMC_0TO7BITS 0x000000FFU |
AnnaBridge | 167:e84263d55307 | 322 | #define SDMMC_8TO15BITS 0x0000FF00U |
AnnaBridge | 167:e84263d55307 | 323 | #define SDMMC_16TO23BITS 0x00FF0000U |
AnnaBridge | 167:e84263d55307 | 324 | #define SDMMC_24TO31BITS 0xFF000000U |
AnnaBridge | 167:e84263d55307 | 325 | #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU |
AnnaBridge | 167:e84263d55307 | 326 | |
AnnaBridge | 167:e84263d55307 | 327 | #define SDMMC_HALFFIFO 0x00000008U |
AnnaBridge | 167:e84263d55307 | 328 | #define SDMMC_HALFFIFOBYTES 0x00000020U |
AnnaBridge | 167:e84263d55307 | 329 | |
AnnaBridge | 167:e84263d55307 | 330 | /** |
AnnaBridge | 167:e84263d55307 | 331 | * @brief Command Class supported |
AnnaBridge | 167:e84263d55307 | 332 | */ |
AnnaBridge | 167:e84263d55307 | 333 | #define SDIO_CCCC_ERASE 0x00000020U |
AnnaBridge | 167:e84263d55307 | 334 | |
AnnaBridge | 167:e84263d55307 | 335 | #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ |
AnnaBridge | 167:e84263d55307 | 336 | #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ |
AnnaBridge | 167:e84263d55307 | 337 | |
AnnaBridge | 167:e84263d55307 | 338 | |
AnnaBridge | 167:e84263d55307 | 339 | /** @defgroup SDIO_LL_Clock_Edge Clock Edge |
<> | 144:ef7eb2e8f9f7 | 340 | * @{ |
<> | 144:ef7eb2e8f9f7 | 341 | */ |
AnnaBridge | 167:e84263d55307 | 342 | #define SDIO_CLOCK_EDGE_RISING 0x00000000U |
<> | 144:ef7eb2e8f9f7 | 343 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
AnnaBridge | 167:e84263d55307 | 346 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
<> | 144:ef7eb2e8f9f7 | 347 | /** |
<> | 144:ef7eb2e8f9f7 | 348 | * @} |
<> | 144:ef7eb2e8f9f7 | 349 | */ |
<> | 144:ef7eb2e8f9f7 | 350 | |
AnnaBridge | 167:e84263d55307 | 351 | /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass |
<> | 144:ef7eb2e8f9f7 | 352 | * @{ |
<> | 144:ef7eb2e8f9f7 | 353 | */ |
AnnaBridge | 167:e84263d55307 | 354 | #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U |
AnnaBridge | 167:e84263d55307 | 355 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
<> | 144:ef7eb2e8f9f7 | 356 | |
AnnaBridge | 167:e84263d55307 | 357 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 358 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 359 | /** |
<> | 144:ef7eb2e8f9f7 | 360 | * @} |
AnnaBridge | 167:e84263d55307 | 361 | */ |
<> | 144:ef7eb2e8f9f7 | 362 | |
AnnaBridge | 167:e84263d55307 | 363 | /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving |
<> | 144:ef7eb2e8f9f7 | 364 | * @{ |
<> | 144:ef7eb2e8f9f7 | 365 | */ |
AnnaBridge | 167:e84263d55307 | 366 | #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U |
AnnaBridge | 167:e84263d55307 | 367 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
AnnaBridge | 167:e84263d55307 | 368 | |
AnnaBridge | 167:e84263d55307 | 369 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 370 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 371 | /** |
AnnaBridge | 167:e84263d55307 | 372 | * @} |
AnnaBridge | 167:e84263d55307 | 373 | */ |
<> | 144:ef7eb2e8f9f7 | 374 | |
AnnaBridge | 167:e84263d55307 | 375 | /** @defgroup SDIO_LL_Bus_Wide Bus Width |
AnnaBridge | 167:e84263d55307 | 376 | * @{ |
AnnaBridge | 167:e84263d55307 | 377 | */ |
AnnaBridge | 167:e84263d55307 | 378 | #define SDIO_BUS_WIDE_1B 0x00000000U |
AnnaBridge | 167:e84263d55307 | 379 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
AnnaBridge | 167:e84263d55307 | 380 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
AnnaBridge | 167:e84263d55307 | 381 | |
AnnaBridge | 167:e84263d55307 | 382 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
AnnaBridge | 167:e84263d55307 | 383 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
AnnaBridge | 167:e84263d55307 | 384 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
<> | 144:ef7eb2e8f9f7 | 385 | /** |
<> | 144:ef7eb2e8f9f7 | 386 | * @} |
<> | 144:ef7eb2e8f9f7 | 387 | */ |
<> | 144:ef7eb2e8f9f7 | 388 | |
AnnaBridge | 167:e84263d55307 | 389 | /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control |
AnnaBridge | 167:e84263d55307 | 390 | * @{ |
AnnaBridge | 167:e84263d55307 | 391 | */ |
AnnaBridge | 167:e84263d55307 | 392 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U |
AnnaBridge | 167:e84263d55307 | 393 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
AnnaBridge | 167:e84263d55307 | 394 | |
AnnaBridge | 167:e84263d55307 | 395 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 396 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 397 | /** |
AnnaBridge | 167:e84263d55307 | 398 | * @} |
AnnaBridge | 167:e84263d55307 | 399 | */ |
AnnaBridge | 167:e84263d55307 | 400 | |
AnnaBridge | 167:e84263d55307 | 401 | /** @defgroup SDIO_LL_Clock_Division Clock Division |
AnnaBridge | 167:e84263d55307 | 402 | * @{ |
AnnaBridge | 167:e84263d55307 | 403 | */ |
AnnaBridge | 167:e84263d55307 | 404 | #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) |
AnnaBridge | 167:e84263d55307 | 405 | /** |
AnnaBridge | 167:e84263d55307 | 406 | * @} |
AnnaBridge | 167:e84263d55307 | 407 | */ |
AnnaBridge | 167:e84263d55307 | 408 | |
AnnaBridge | 167:e84263d55307 | 409 | /** @defgroup SDIO_LL_Command_Index Command Index |
<> | 144:ef7eb2e8f9f7 | 410 | * @{ |
<> | 144:ef7eb2e8f9f7 | 411 | */ |
AnnaBridge | 167:e84263d55307 | 412 | #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) |
AnnaBridge | 167:e84263d55307 | 413 | /** |
AnnaBridge | 167:e84263d55307 | 414 | * @} |
AnnaBridge | 167:e84263d55307 | 415 | */ |
AnnaBridge | 167:e84263d55307 | 416 | |
AnnaBridge | 167:e84263d55307 | 417 | /** @defgroup SDIO_LL_Response_Type Response Type |
AnnaBridge | 167:e84263d55307 | 418 | * @{ |
AnnaBridge | 167:e84263d55307 | 419 | */ |
AnnaBridge | 167:e84263d55307 | 420 | #define SDIO_RESPONSE_NO 0x00000000U |
AnnaBridge | 167:e84263d55307 | 421 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
AnnaBridge | 167:e84263d55307 | 422 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
AnnaBridge | 167:e84263d55307 | 423 | |
AnnaBridge | 167:e84263d55307 | 424 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
AnnaBridge | 167:e84263d55307 | 425 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
AnnaBridge | 167:e84263d55307 | 426 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
AnnaBridge | 167:e84263d55307 | 427 | /** |
AnnaBridge | 167:e84263d55307 | 428 | * @} |
AnnaBridge | 167:e84263d55307 | 429 | */ |
AnnaBridge | 167:e84263d55307 | 430 | |
AnnaBridge | 167:e84263d55307 | 431 | /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt |
AnnaBridge | 167:e84263d55307 | 432 | * @{ |
AnnaBridge | 167:e84263d55307 | 433 | */ |
AnnaBridge | 167:e84263d55307 | 434 | #define SDIO_WAIT_NO 0x00000000U |
AnnaBridge | 167:e84263d55307 | 435 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
AnnaBridge | 167:e84263d55307 | 436 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
AnnaBridge | 167:e84263d55307 | 437 | |
AnnaBridge | 167:e84263d55307 | 438 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
AnnaBridge | 167:e84263d55307 | 439 | ((WAIT) == SDIO_WAIT_IT) || \ |
AnnaBridge | 167:e84263d55307 | 440 | ((WAIT) == SDIO_WAIT_PEND)) |
<> | 144:ef7eb2e8f9f7 | 441 | /** |
<> | 144:ef7eb2e8f9f7 | 442 | * @} |
<> | 144:ef7eb2e8f9f7 | 443 | */ |
<> | 144:ef7eb2e8f9f7 | 444 | |
AnnaBridge | 167:e84263d55307 | 445 | /** @defgroup SDIO_LL_CPSM_State CPSM State |
AnnaBridge | 167:e84263d55307 | 446 | * @{ |
AnnaBridge | 167:e84263d55307 | 447 | */ |
AnnaBridge | 167:e84263d55307 | 448 | #define SDIO_CPSM_DISABLE 0x00000000U |
AnnaBridge | 167:e84263d55307 | 449 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
AnnaBridge | 167:e84263d55307 | 450 | |
AnnaBridge | 167:e84263d55307 | 451 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 452 | ((CPSM) == SDIO_CPSM_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 453 | /** |
AnnaBridge | 167:e84263d55307 | 454 | * @} |
AnnaBridge | 167:e84263d55307 | 455 | */ |
AnnaBridge | 167:e84263d55307 | 456 | |
AnnaBridge | 167:e84263d55307 | 457 | /** @defgroup SDIO_LL_Response_Registers Response Register |
<> | 144:ef7eb2e8f9f7 | 458 | * @{ |
<> | 144:ef7eb2e8f9f7 | 459 | */ |
AnnaBridge | 167:e84263d55307 | 460 | #define SDIO_RESP1 0x00000000U |
AnnaBridge | 167:e84263d55307 | 461 | #define SDIO_RESP2 0x00000004U |
AnnaBridge | 167:e84263d55307 | 462 | #define SDIO_RESP3 0x00000008U |
AnnaBridge | 167:e84263d55307 | 463 | #define SDIO_RESP4 0x0000000CU |
<> | 144:ef7eb2e8f9f7 | 464 | |
AnnaBridge | 167:e84263d55307 | 465 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
AnnaBridge | 167:e84263d55307 | 466 | ((RESP) == SDIO_RESP2) || \ |
AnnaBridge | 167:e84263d55307 | 467 | ((RESP) == SDIO_RESP3) || \ |
AnnaBridge | 167:e84263d55307 | 468 | ((RESP) == SDIO_RESP4)) |
AnnaBridge | 167:e84263d55307 | 469 | /** |
AnnaBridge | 167:e84263d55307 | 470 | * @} |
AnnaBridge | 167:e84263d55307 | 471 | */ |
AnnaBridge | 167:e84263d55307 | 472 | |
AnnaBridge | 167:e84263d55307 | 473 | /** @defgroup SDIO_LL_Data_Length Data Lenght |
AnnaBridge | 167:e84263d55307 | 474 | * @{ |
AnnaBridge | 167:e84263d55307 | 475 | */ |
AnnaBridge | 167:e84263d55307 | 476 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) |
<> | 144:ef7eb2e8f9f7 | 477 | /** |
<> | 144:ef7eb2e8f9f7 | 478 | * @} |
<> | 144:ef7eb2e8f9f7 | 479 | */ |
<> | 144:ef7eb2e8f9f7 | 480 | |
AnnaBridge | 167:e84263d55307 | 481 | /** @defgroup SDIO_LL_Data_Block_Size Data Block Size |
<> | 144:ef7eb2e8f9f7 | 482 | * @{ |
<> | 144:ef7eb2e8f9f7 | 483 | */ |
AnnaBridge | 167:e84263d55307 | 484 | #define SDIO_DATABLOCK_SIZE_1B 0x00000000U |
AnnaBridge | 167:e84263d55307 | 485 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
AnnaBridge | 167:e84263d55307 | 486 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
AnnaBridge | 167:e84263d55307 | 487 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
AnnaBridge | 167:e84263d55307 | 488 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
AnnaBridge | 167:e84263d55307 | 489 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
AnnaBridge | 167:e84263d55307 | 490 | #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
AnnaBridge | 167:e84263d55307 | 491 | #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
AnnaBridge | 167:e84263d55307 | 492 | #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 |
AnnaBridge | 167:e84263d55307 | 493 | #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) |
AnnaBridge | 167:e84263d55307 | 494 | #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
AnnaBridge | 167:e84263d55307 | 495 | #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
AnnaBridge | 167:e84263d55307 | 496 | #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
AnnaBridge | 167:e84263d55307 | 497 | #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
AnnaBridge | 167:e84263d55307 | 498 | #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
<> | 144:ef7eb2e8f9f7 | 499 | |
AnnaBridge | 167:e84263d55307 | 500 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
AnnaBridge | 167:e84263d55307 | 501 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
AnnaBridge | 167:e84263d55307 | 502 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
AnnaBridge | 167:e84263d55307 | 503 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
AnnaBridge | 167:e84263d55307 | 504 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
AnnaBridge | 167:e84263d55307 | 505 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
AnnaBridge | 167:e84263d55307 | 506 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
AnnaBridge | 167:e84263d55307 | 507 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
AnnaBridge | 167:e84263d55307 | 508 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
AnnaBridge | 167:e84263d55307 | 509 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
AnnaBridge | 167:e84263d55307 | 510 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
AnnaBridge | 167:e84263d55307 | 511 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
AnnaBridge | 167:e84263d55307 | 512 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
AnnaBridge | 167:e84263d55307 | 513 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
AnnaBridge | 167:e84263d55307 | 514 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
<> | 144:ef7eb2e8f9f7 | 515 | /** |
<> | 144:ef7eb2e8f9f7 | 516 | * @} |
<> | 144:ef7eb2e8f9f7 | 517 | */ |
<> | 144:ef7eb2e8f9f7 | 518 | |
AnnaBridge | 167:e84263d55307 | 519 | /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction |
<> | 144:ef7eb2e8f9f7 | 520 | * @{ |
<> | 144:ef7eb2e8f9f7 | 521 | */ |
AnnaBridge | 167:e84263d55307 | 522 | #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U |
AnnaBridge | 167:e84263d55307 | 523 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
<> | 144:ef7eb2e8f9f7 | 524 | |
AnnaBridge | 167:e84263d55307 | 525 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
AnnaBridge | 167:e84263d55307 | 526 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
<> | 144:ef7eb2e8f9f7 | 527 | /** |
<> | 144:ef7eb2e8f9f7 | 528 | * @} |
<> | 144:ef7eb2e8f9f7 | 529 | */ |
<> | 144:ef7eb2e8f9f7 | 530 | |
AnnaBridge | 167:e84263d55307 | 531 | /** @defgroup SDIO_LL_Transfer_Type Transfer Type |
<> | 144:ef7eb2e8f9f7 | 532 | * @{ |
<> | 144:ef7eb2e8f9f7 | 533 | */ |
AnnaBridge | 167:e84263d55307 | 534 | #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U |
AnnaBridge | 167:e84263d55307 | 535 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
AnnaBridge | 167:e84263d55307 | 536 | |
AnnaBridge | 167:e84263d55307 | 537 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
AnnaBridge | 167:e84263d55307 | 538 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
AnnaBridge | 167:e84263d55307 | 539 | /** |
AnnaBridge | 167:e84263d55307 | 540 | * @} |
AnnaBridge | 167:e84263d55307 | 541 | */ |
AnnaBridge | 167:e84263d55307 | 542 | |
AnnaBridge | 167:e84263d55307 | 543 | /** @defgroup SDIO_LL_DPSM_State DPSM State |
AnnaBridge | 167:e84263d55307 | 544 | * @{ |
AnnaBridge | 167:e84263d55307 | 545 | */ |
AnnaBridge | 167:e84263d55307 | 546 | #define SDIO_DPSM_DISABLE 0x00000000U |
<> | 144:ef7eb2e8f9f7 | 547 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
<> | 144:ef7eb2e8f9f7 | 548 | |
<> | 144:ef7eb2e8f9f7 | 549 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
AnnaBridge | 167:e84263d55307 | 550 | ((DPSM) == SDIO_DPSM_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 551 | /** |
<> | 144:ef7eb2e8f9f7 | 552 | * @} |
<> | 144:ef7eb2e8f9f7 | 553 | */ |
<> | 144:ef7eb2e8f9f7 | 554 | |
AnnaBridge | 167:e84263d55307 | 555 | /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode |
<> | 144:ef7eb2e8f9f7 | 556 | * @{ |
<> | 144:ef7eb2e8f9f7 | 557 | */ |
AnnaBridge | 167:e84263d55307 | 558 | #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U |
AnnaBridge | 167:e84263d55307 | 559 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
<> | 144:ef7eb2e8f9f7 | 562 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
<> | 144:ef7eb2e8f9f7 | 563 | /** |
<> | 144:ef7eb2e8f9f7 | 564 | * @} |
<> | 144:ef7eb2e8f9f7 | 565 | */ |
<> | 144:ef7eb2e8f9f7 | 566 | |
AnnaBridge | 167:e84263d55307 | 567 | /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources |
<> | 144:ef7eb2e8f9f7 | 568 | * @{ |
<> | 144:ef7eb2e8f9f7 | 569 | */ |
<> | 144:ef7eb2e8f9f7 | 570 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
<> | 144:ef7eb2e8f9f7 | 571 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
<> | 144:ef7eb2e8f9f7 | 572 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
<> | 144:ef7eb2e8f9f7 | 573 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
<> | 144:ef7eb2e8f9f7 | 574 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
<> | 144:ef7eb2e8f9f7 | 575 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
<> | 144:ef7eb2e8f9f7 | 576 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
<> | 144:ef7eb2e8f9f7 | 577 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
<> | 144:ef7eb2e8f9f7 | 578 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
<> | 144:ef7eb2e8f9f7 | 579 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
<> | 144:ef7eb2e8f9f7 | 580 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
<> | 144:ef7eb2e8f9f7 | 581 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
<> | 144:ef7eb2e8f9f7 | 582 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
<> | 144:ef7eb2e8f9f7 | 583 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
<> | 144:ef7eb2e8f9f7 | 584 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
<> | 144:ef7eb2e8f9f7 | 585 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
<> | 144:ef7eb2e8f9f7 | 586 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
<> | 144:ef7eb2e8f9f7 | 587 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
<> | 144:ef7eb2e8f9f7 | 588 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
<> | 144:ef7eb2e8f9f7 | 589 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
<> | 144:ef7eb2e8f9f7 | 590 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
<> | 144:ef7eb2e8f9f7 | 591 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
<> | 144:ef7eb2e8f9f7 | 592 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
<> | 144:ef7eb2e8f9f7 | 593 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
<> | 144:ef7eb2e8f9f7 | 594 | /** |
<> | 144:ef7eb2e8f9f7 | 595 | * @} |
<> | 144:ef7eb2e8f9f7 | 596 | */ |
<> | 144:ef7eb2e8f9f7 | 597 | |
AnnaBridge | 167:e84263d55307 | 598 | /** @defgroup SDIO_LL_Flags Flags |
<> | 144:ef7eb2e8f9f7 | 599 | * @{ |
<> | 144:ef7eb2e8f9f7 | 600 | */ |
<> | 144:ef7eb2e8f9f7 | 601 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
<> | 144:ef7eb2e8f9f7 | 602 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
<> | 144:ef7eb2e8f9f7 | 603 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
<> | 144:ef7eb2e8f9f7 | 604 | #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT |
<> | 144:ef7eb2e8f9f7 | 605 | #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR |
<> | 144:ef7eb2e8f9f7 | 606 | #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR |
<> | 144:ef7eb2e8f9f7 | 607 | #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND |
<> | 144:ef7eb2e8f9f7 | 608 | #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT |
<> | 144:ef7eb2e8f9f7 | 609 | #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND |
<> | 144:ef7eb2e8f9f7 | 610 | #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR |
<> | 144:ef7eb2e8f9f7 | 611 | #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND |
<> | 144:ef7eb2e8f9f7 | 612 | #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT |
<> | 144:ef7eb2e8f9f7 | 613 | #define SDIO_FLAG_TXACT SDIO_STA_TXACT |
<> | 144:ef7eb2e8f9f7 | 614 | #define SDIO_FLAG_RXACT SDIO_STA_RXACT |
<> | 144:ef7eb2e8f9f7 | 615 | #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE |
<> | 144:ef7eb2e8f9f7 | 616 | #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF |
<> | 144:ef7eb2e8f9f7 | 617 | #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF |
<> | 144:ef7eb2e8f9f7 | 618 | #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF |
<> | 144:ef7eb2e8f9f7 | 619 | #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE |
<> | 144:ef7eb2e8f9f7 | 620 | #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE |
<> | 144:ef7eb2e8f9f7 | 621 | #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL |
<> | 144:ef7eb2e8f9f7 | 622 | #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL |
<> | 144:ef7eb2e8f9f7 | 623 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
<> | 144:ef7eb2e8f9f7 | 624 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
AnnaBridge | 167:e84263d55307 | 625 | #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ |
AnnaBridge | 167:e84263d55307 | 626 | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ |
AnnaBridge | 167:e84263d55307 | 627 | SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ |
AnnaBridge | 167:e84263d55307 | 628 | SDIO_FLAG_DBCKEND)) |
<> | 144:ef7eb2e8f9f7 | 629 | /** |
<> | 144:ef7eb2e8f9f7 | 630 | * @} |
<> | 144:ef7eb2e8f9f7 | 631 | */ |
<> | 144:ef7eb2e8f9f7 | 632 | |
<> | 144:ef7eb2e8f9f7 | 633 | /** |
<> | 144:ef7eb2e8f9f7 | 634 | * @} |
<> | 144:ef7eb2e8f9f7 | 635 | */ |
AnnaBridge | 167:e84263d55307 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 638 | /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros |
<> | 144:ef7eb2e8f9f7 | 639 | * @{ |
<> | 144:ef7eb2e8f9f7 | 640 | */ |
<> | 144:ef7eb2e8f9f7 | 641 | |
<> | 144:ef7eb2e8f9f7 | 642 | /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region |
<> | 144:ef7eb2e8f9f7 | 643 | * @{ |
<> | 144:ef7eb2e8f9f7 | 644 | */ |
<> | 144:ef7eb2e8f9f7 | 645 | /* ------------ SDIO registers bit address in the alias region -------------- */ |
<> | 144:ef7eb2e8f9f7 | 646 | #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) |
<> | 144:ef7eb2e8f9f7 | 647 | |
<> | 144:ef7eb2e8f9f7 | 648 | /* --- CLKCR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 649 | /* Alias word address of CLKEN bit */ |
AnnaBridge | 167:e84263d55307 | 650 | #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) |
AnnaBridge | 167:e84263d55307 | 651 | #define CLKEN_BITNUMBER 0x08U |
AnnaBridge | 167:e84263d55307 | 652 | #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | /* --- CMD Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 655 | /* Alias word address of SDIOSUSPEND bit */ |
AnnaBridge | 167:e84263d55307 | 656 | #define CMD_OFFSET (SDIO_OFFSET + 0x0CU) |
AnnaBridge | 167:e84263d55307 | 657 | #define SDIOSUSPEND_BITNUMBER 0x0BU |
AnnaBridge | 167:e84263d55307 | 658 | #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 659 | |
<> | 144:ef7eb2e8f9f7 | 660 | /* Alias word address of ENCMDCOMPL bit */ |
AnnaBridge | 167:e84263d55307 | 661 | #define ENCMDCOMPL_BITNUMBER 0x0CU |
AnnaBridge | 167:e84263d55307 | 662 | #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 663 | |
<> | 144:ef7eb2e8f9f7 | 664 | /* Alias word address of NIEN bit */ |
AnnaBridge | 167:e84263d55307 | 665 | #define NIEN_BITNUMBER 0x0DU |
AnnaBridge | 167:e84263d55307 | 666 | #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | /* Alias word address of ATACMD bit */ |
AnnaBridge | 167:e84263d55307 | 669 | #define ATACMD_BITNUMBER 0x0EU |
AnnaBridge | 167:e84263d55307 | 670 | #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 671 | |
<> | 144:ef7eb2e8f9f7 | 672 | /* --- DCTRL Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 673 | /* Alias word address of DMAEN bit */ |
AnnaBridge | 167:e84263d55307 | 674 | #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) |
AnnaBridge | 167:e84263d55307 | 675 | #define DMAEN_BITNUMBER 0x03U |
AnnaBridge | 167:e84263d55307 | 676 | #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | /* Alias word address of RWSTART bit */ |
AnnaBridge | 167:e84263d55307 | 679 | #define RWSTART_BITNUMBER 0x08U |
AnnaBridge | 167:e84263d55307 | 680 | #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 681 | |
<> | 144:ef7eb2e8f9f7 | 682 | /* Alias word address of RWSTOP bit */ |
AnnaBridge | 167:e84263d55307 | 683 | #define RWSTOP_BITNUMBER 0x09U |
AnnaBridge | 167:e84263d55307 | 684 | #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | /* Alias word address of RWMOD bit */ |
AnnaBridge | 167:e84263d55307 | 687 | #define RWMOD_BITNUMBER 0x0AU |
AnnaBridge | 167:e84263d55307 | 688 | #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 689 | |
<> | 144:ef7eb2e8f9f7 | 690 | /* Alias word address of SDIOEN bit */ |
AnnaBridge | 167:e84263d55307 | 691 | #define SDIOEN_BITNUMBER 0x0BU |
AnnaBridge | 167:e84263d55307 | 692 | #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) |
<> | 144:ef7eb2e8f9f7 | 693 | /** |
<> | 144:ef7eb2e8f9f7 | 694 | * @} |
<> | 144:ef7eb2e8f9f7 | 695 | */ |
<> | 144:ef7eb2e8f9f7 | 696 | |
AnnaBridge | 167:e84263d55307 | 697 | /** @defgroup SDIO_LL_Register Bits And Addresses Definitions |
AnnaBridge | 167:e84263d55307 | 698 | * @brief SDIO_LL registers bit address in the alias region |
<> | 144:ef7eb2e8f9f7 | 699 | * @{ |
<> | 144:ef7eb2e8f9f7 | 700 | */ |
<> | 144:ef7eb2e8f9f7 | 701 | /* ---------------------- SDIO registers bit mask --------------------------- */ |
<> | 144:ef7eb2e8f9f7 | 702 | /* --- CLKCR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 703 | /* CLKCR register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 704 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ |
<> | 144:ef7eb2e8f9f7 | 705 | SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ |
<> | 144:ef7eb2e8f9f7 | 706 | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) |
<> | 144:ef7eb2e8f9f7 | 707 | |
<> | 144:ef7eb2e8f9f7 | 708 | /* --- DCTRL Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 709 | /* SDIO DCTRL Clear Mask */ |
<> | 144:ef7eb2e8f9f7 | 710 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ |
<> | 144:ef7eb2e8f9f7 | 711 | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) |
<> | 144:ef7eb2e8f9f7 | 712 | |
<> | 144:ef7eb2e8f9f7 | 713 | /* --- CMD Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 714 | /* CMD Register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 715 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
<> | 144:ef7eb2e8f9f7 | 716 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
<> | 144:ef7eb2e8f9f7 | 717 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
<> | 144:ef7eb2e8f9f7 | 718 | |
<> | 144:ef7eb2e8f9f7 | 719 | /* SDIO Initialization Frequency (400KHz max) */ |
AnnaBridge | 167:e84263d55307 | 720 | #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) |
<> | 144:ef7eb2e8f9f7 | 721 | |
<> | 144:ef7eb2e8f9f7 | 722 | /* SDIO Data Transfer Frequency (25MHz max) */ |
<> | 144:ef7eb2e8f9f7 | 723 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) |
AnnaBridge | 167:e84263d55307 | 724 | |
<> | 144:ef7eb2e8f9f7 | 725 | /** |
<> | 144:ef7eb2e8f9f7 | 726 | * @} |
<> | 144:ef7eb2e8f9f7 | 727 | */ |
<> | 144:ef7eb2e8f9f7 | 728 | |
AnnaBridge | 167:e84263d55307 | 729 | /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration |
AnnaBridge | 167:e84263d55307 | 730 | * @brief macros to handle interrupts and specific clock configurations |
AnnaBridge | 167:e84263d55307 | 731 | * @{ |
AnnaBridge | 167:e84263d55307 | 732 | */ |
AnnaBridge | 167:e84263d55307 | 733 | |
<> | 144:ef7eb2e8f9f7 | 734 | /** |
<> | 144:ef7eb2e8f9f7 | 735 | * @brief Enable the SDIO device. |
AnnaBridge | 167:e84263d55307 | 736 | * @param __INSTANCE__: SDIO Instance |
<> | 144:ef7eb2e8f9f7 | 737 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 738 | */ |
AnnaBridge | 167:e84263d55307 | 739 | #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 740 | |
<> | 144:ef7eb2e8f9f7 | 741 | /** |
<> | 144:ef7eb2e8f9f7 | 742 | * @brief Disable the SDIO device. |
AnnaBridge | 167:e84263d55307 | 743 | * @param __INSTANCE__: SDIO Instance |
<> | 144:ef7eb2e8f9f7 | 744 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 745 | */ |
AnnaBridge | 167:e84263d55307 | 746 | #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | /** |
<> | 144:ef7eb2e8f9f7 | 749 | * @brief Enable the SDIO DMA transfer. |
AnnaBridge | 167:e84263d55307 | 750 | * @param __INSTANCE__: SDIO Instance |
<> | 144:ef7eb2e8f9f7 | 751 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 752 | */ |
AnnaBridge | 167:e84263d55307 | 753 | #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 754 | /** |
<> | 144:ef7eb2e8f9f7 | 755 | * @brief Disable the SDIO DMA transfer. |
AnnaBridge | 167:e84263d55307 | 756 | * @param __INSTANCE__: SDIO Instance |
<> | 144:ef7eb2e8f9f7 | 757 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 758 | */ |
AnnaBridge | 167:e84263d55307 | 759 | #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 760 | |
<> | 144:ef7eb2e8f9f7 | 761 | /** |
<> | 144:ef7eb2e8f9f7 | 762 | * @brief Enable the SDIO device interrupt. |
<> | 144:ef7eb2e8f9f7 | 763 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 764 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. |
<> | 144:ef7eb2e8f9f7 | 765 | * This parameter can be one or a combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 766 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 767 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 768 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 769 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 770 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 771 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 772 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 773 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
<> | 144:ef7eb2e8f9f7 | 774 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
<> | 144:ef7eb2e8f9f7 | 775 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 776 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 777 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 778 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 779 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
<> | 144:ef7eb2e8f9f7 | 780 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
<> | 144:ef7eb2e8f9f7 | 781 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
<> | 144:ef7eb2e8f9f7 | 782 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
<> | 144:ef7eb2e8f9f7 | 783 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
<> | 144:ef7eb2e8f9f7 | 784 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
<> | 144:ef7eb2e8f9f7 | 785 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
<> | 144:ef7eb2e8f9f7 | 786 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
AnnaBridge | 167:e84263d55307 | 787 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
<> | 144:ef7eb2e8f9f7 | 788 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 789 | */ |
<> | 144:ef7eb2e8f9f7 | 790 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | /** |
<> | 144:ef7eb2e8f9f7 | 793 | * @brief Disable the SDIO device interrupt. |
<> | 144:ef7eb2e8f9f7 | 794 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 795 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. |
<> | 144:ef7eb2e8f9f7 | 796 | * This parameter can be one or a combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 797 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 798 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 799 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 800 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 801 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 802 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 803 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 804 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
<> | 144:ef7eb2e8f9f7 | 805 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
<> | 144:ef7eb2e8f9f7 | 806 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 807 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 808 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 809 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 810 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
<> | 144:ef7eb2e8f9f7 | 811 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
<> | 144:ef7eb2e8f9f7 | 812 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
<> | 144:ef7eb2e8f9f7 | 813 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
<> | 144:ef7eb2e8f9f7 | 814 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
<> | 144:ef7eb2e8f9f7 | 815 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
<> | 144:ef7eb2e8f9f7 | 816 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
<> | 144:ef7eb2e8f9f7 | 817 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
AnnaBridge | 167:e84263d55307 | 818 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
<> | 144:ef7eb2e8f9f7 | 819 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 820 | */ |
<> | 144:ef7eb2e8f9f7 | 821 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 822 | |
<> | 144:ef7eb2e8f9f7 | 823 | /** |
<> | 144:ef7eb2e8f9f7 | 824 | * @brief Checks whether the specified SDIO flag is set or not. |
<> | 144:ef7eb2e8f9f7 | 825 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 826 | * @param __FLAG__: specifies the flag to check. |
<> | 144:ef7eb2e8f9f7 | 827 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 828 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
<> | 144:ef7eb2e8f9f7 | 829 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
<> | 144:ef7eb2e8f9f7 | 830 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
<> | 144:ef7eb2e8f9f7 | 831 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
<> | 144:ef7eb2e8f9f7 | 832 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
<> | 144:ef7eb2e8f9f7 | 833 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
<> | 144:ef7eb2e8f9f7 | 834 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
<> | 144:ef7eb2e8f9f7 | 835 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
<> | 144:ef7eb2e8f9f7 | 836 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
<> | 144:ef7eb2e8f9f7 | 837 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
<> | 144:ef7eb2e8f9f7 | 838 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
<> | 144:ef7eb2e8f9f7 | 839 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
<> | 144:ef7eb2e8f9f7 | 840 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
<> | 144:ef7eb2e8f9f7 | 841 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
<> | 144:ef7eb2e8f9f7 | 842 | * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
<> | 144:ef7eb2e8f9f7 | 843 | * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
<> | 144:ef7eb2e8f9f7 | 844 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
<> | 144:ef7eb2e8f9f7 | 845 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
<> | 144:ef7eb2e8f9f7 | 846 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
<> | 144:ef7eb2e8f9f7 | 847 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
<> | 144:ef7eb2e8f9f7 | 848 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
<> | 144:ef7eb2e8f9f7 | 849 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
<> | 144:ef7eb2e8f9f7 | 850 | * @retval The new state of SDIO_FLAG (SET or RESET). |
<> | 144:ef7eb2e8f9f7 | 851 | */ |
AnnaBridge | 167:e84263d55307 | 852 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 853 | |
<> | 144:ef7eb2e8f9f7 | 854 | |
<> | 144:ef7eb2e8f9f7 | 855 | /** |
<> | 144:ef7eb2e8f9f7 | 856 | * @brief Clears the SDIO pending flags. |
<> | 144:ef7eb2e8f9f7 | 857 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 858 | * @param __FLAG__: specifies the flag to clear. |
<> | 144:ef7eb2e8f9f7 | 859 | * This parameter can be one or a combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 860 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
<> | 144:ef7eb2e8f9f7 | 861 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
<> | 144:ef7eb2e8f9f7 | 862 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
<> | 144:ef7eb2e8f9f7 | 863 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
<> | 144:ef7eb2e8f9f7 | 864 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
<> | 144:ef7eb2e8f9f7 | 865 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
<> | 144:ef7eb2e8f9f7 | 866 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
<> | 144:ef7eb2e8f9f7 | 867 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
<> | 144:ef7eb2e8f9f7 | 868 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
<> | 144:ef7eb2e8f9f7 | 869 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
<> | 144:ef7eb2e8f9f7 | 870 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
<> | 144:ef7eb2e8f9f7 | 871 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 872 | */ |
AnnaBridge | 167:e84263d55307 | 873 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
<> | 144:ef7eb2e8f9f7 | 874 | |
<> | 144:ef7eb2e8f9f7 | 875 | /** |
<> | 144:ef7eb2e8f9f7 | 876 | * @brief Checks whether the specified SDIO interrupt has occurred or not. |
<> | 144:ef7eb2e8f9f7 | 877 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 878 | * @param __INTERRUPT__: specifies the SDIO interrupt source to check. |
<> | 144:ef7eb2e8f9f7 | 879 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 880 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 881 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 882 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 883 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 884 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 885 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 886 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 887 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
<> | 144:ef7eb2e8f9f7 | 888 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
<> | 144:ef7eb2e8f9f7 | 889 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 890 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 891 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 892 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
<> | 144:ef7eb2e8f9f7 | 893 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
<> | 144:ef7eb2e8f9f7 | 894 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
<> | 144:ef7eb2e8f9f7 | 895 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
<> | 144:ef7eb2e8f9f7 | 896 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
<> | 144:ef7eb2e8f9f7 | 897 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
<> | 144:ef7eb2e8f9f7 | 898 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
<> | 144:ef7eb2e8f9f7 | 899 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
<> | 144:ef7eb2e8f9f7 | 900 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
<> | 144:ef7eb2e8f9f7 | 901 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
<> | 144:ef7eb2e8f9f7 | 902 | * @retval The new state of SDIO_IT (SET or RESET). |
<> | 144:ef7eb2e8f9f7 | 903 | */ |
AnnaBridge | 167:e84263d55307 | 904 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 905 | |
<> | 144:ef7eb2e8f9f7 | 906 | /** |
<> | 144:ef7eb2e8f9f7 | 907 | * @brief Clears the SDIO's interrupt pending bits. |
<> | 144:ef7eb2e8f9f7 | 908 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 909 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
<> | 144:ef7eb2e8f9f7 | 910 | * This parameter can be one or a combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 911 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 912 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
<> | 144:ef7eb2e8f9f7 | 913 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 914 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
<> | 144:ef7eb2e8f9f7 | 915 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 916 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
<> | 144:ef7eb2e8f9f7 | 917 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
<> | 144:ef7eb2e8f9f7 | 918 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
<> | 144:ef7eb2e8f9f7 | 919 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
<> | 144:ef7eb2e8f9f7 | 920 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
<> | 144:ef7eb2e8f9f7 | 921 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 922 | */ |
AnnaBridge | 167:e84263d55307 | 923 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 924 | |
<> | 144:ef7eb2e8f9f7 | 925 | /** |
<> | 144:ef7eb2e8f9f7 | 926 | * @brief Enable Start the SD I/O Read Wait operation. |
AnnaBridge | 167:e84263d55307 | 927 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 928 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 929 | */ |
AnnaBridge | 167:e84263d55307 | 930 | #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 931 | |
<> | 144:ef7eb2e8f9f7 | 932 | /** |
<> | 144:ef7eb2e8f9f7 | 933 | * @brief Disable Start the SD I/O Read Wait operations. |
AnnaBridge | 167:e84263d55307 | 934 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 935 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 936 | */ |
AnnaBridge | 167:e84263d55307 | 937 | #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 938 | |
<> | 144:ef7eb2e8f9f7 | 939 | /** |
<> | 144:ef7eb2e8f9f7 | 940 | * @brief Enable Start the SD I/O Read Wait operation. |
AnnaBridge | 167:e84263d55307 | 941 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 942 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 943 | */ |
AnnaBridge | 167:e84263d55307 | 944 | #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 945 | |
<> | 144:ef7eb2e8f9f7 | 946 | /** |
<> | 144:ef7eb2e8f9f7 | 947 | * @brief Disable Stop the SD I/O Read Wait operations. |
AnnaBridge | 167:e84263d55307 | 948 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 949 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 950 | */ |
AnnaBridge | 167:e84263d55307 | 951 | #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 952 | |
<> | 144:ef7eb2e8f9f7 | 953 | /** |
<> | 144:ef7eb2e8f9f7 | 954 | * @brief Enable the SD I/O Mode Operation. |
AnnaBridge | 167:e84263d55307 | 955 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 956 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 957 | */ |
AnnaBridge | 167:e84263d55307 | 958 | #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 959 | |
<> | 144:ef7eb2e8f9f7 | 960 | /** |
<> | 144:ef7eb2e8f9f7 | 961 | * @brief Disable the SD I/O Mode Operation. |
AnnaBridge | 167:e84263d55307 | 962 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 963 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 964 | */ |
AnnaBridge | 167:e84263d55307 | 965 | #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 966 | |
<> | 144:ef7eb2e8f9f7 | 967 | /** |
<> | 144:ef7eb2e8f9f7 | 968 | * @brief Enable the SD I/O Suspend command sending. |
AnnaBridge | 167:e84263d55307 | 969 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 970 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 971 | */ |
AnnaBridge | 167:e84263d55307 | 972 | #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 973 | |
<> | 144:ef7eb2e8f9f7 | 974 | /** |
<> | 144:ef7eb2e8f9f7 | 975 | * @brief Disable the SD I/O Suspend command sending. |
AnnaBridge | 167:e84263d55307 | 976 | * @param __INSTANCE__ : Pointer to SDIO register base |
<> | 144:ef7eb2e8f9f7 | 977 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 978 | */ |
AnnaBridge | 167:e84263d55307 | 979 | #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) |
AnnaBridge | 167:e84263d55307 | 980 | |
<> | 144:ef7eb2e8f9f7 | 981 | /** |
<> | 144:ef7eb2e8f9f7 | 982 | * @brief Enable the command completion signal. |
<> | 144:ef7eb2e8f9f7 | 983 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 984 | */ |
<> | 144:ef7eb2e8f9f7 | 985 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 986 | |
<> | 144:ef7eb2e8f9f7 | 987 | /** |
<> | 144:ef7eb2e8f9f7 | 988 | * @brief Disable the command completion signal. |
<> | 144:ef7eb2e8f9f7 | 989 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 990 | */ |
<> | 144:ef7eb2e8f9f7 | 991 | #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 992 | |
<> | 144:ef7eb2e8f9f7 | 993 | /** |
<> | 144:ef7eb2e8f9f7 | 994 | * @brief Enable the CE-ATA interrupt. |
<> | 144:ef7eb2e8f9f7 | 995 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 996 | */ |
AnnaBridge | 167:e84263d55307 | 997 | #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) |
<> | 144:ef7eb2e8f9f7 | 998 | |
<> | 144:ef7eb2e8f9f7 | 999 | /** |
<> | 144:ef7eb2e8f9f7 | 1000 | * @brief Disable the CE-ATA interrupt. |
<> | 144:ef7eb2e8f9f7 | 1001 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1002 | */ |
AnnaBridge | 167:e84263d55307 | 1003 | #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | /** |
<> | 144:ef7eb2e8f9f7 | 1006 | * @brief Enable send CE-ATA command (CMD61). |
<> | 144:ef7eb2e8f9f7 | 1007 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1008 | */ |
<> | 144:ef7eb2e8f9f7 | 1009 | #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1010 | |
<> | 144:ef7eb2e8f9f7 | 1011 | /** |
<> | 144:ef7eb2e8f9f7 | 1012 | * @brief Disable send CE-ATA command (CMD61). |
<> | 144:ef7eb2e8f9f7 | 1013 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1014 | */ |
<> | 144:ef7eb2e8f9f7 | 1015 | #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) |
AnnaBridge | 167:e84263d55307 | 1016 | |
<> | 144:ef7eb2e8f9f7 | 1017 | /** |
<> | 144:ef7eb2e8f9f7 | 1018 | * @} |
<> | 144:ef7eb2e8f9f7 | 1019 | */ |
<> | 144:ef7eb2e8f9f7 | 1020 | |
<> | 144:ef7eb2e8f9f7 | 1021 | /** |
<> | 144:ef7eb2e8f9f7 | 1022 | * @} |
<> | 144:ef7eb2e8f9f7 | 1023 | */ |
<> | 144:ef7eb2e8f9f7 | 1024 | |
<> | 144:ef7eb2e8f9f7 | 1025 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1026 | /** @addtogroup SDMMC_LL_Exported_Functions |
<> | 144:ef7eb2e8f9f7 | 1027 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1028 | */ |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | /* Initialization/de-initialization functions **********************************/ |
<> | 144:ef7eb2e8f9f7 | 1031 | /** @addtogroup HAL_SDMMC_LL_Group1 |
<> | 144:ef7eb2e8f9f7 | 1032 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1033 | */ |
<> | 144:ef7eb2e8f9f7 | 1034 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
<> | 144:ef7eb2e8f9f7 | 1035 | /** |
<> | 144:ef7eb2e8f9f7 | 1036 | * @} |
<> | 144:ef7eb2e8f9f7 | 1037 | */ |
<> | 144:ef7eb2e8f9f7 | 1038 | |
<> | 144:ef7eb2e8f9f7 | 1039 | /* I/O operation functions *****************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1040 | /** @addtogroup HAL_SDMMC_LL_Group2 |
<> | 144:ef7eb2e8f9f7 | 1041 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1042 | */ |
<> | 144:ef7eb2e8f9f7 | 1043 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
<> | 144:ef7eb2e8f9f7 | 1044 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
<> | 144:ef7eb2e8f9f7 | 1045 | /** |
<> | 144:ef7eb2e8f9f7 | 1046 | * @} |
<> | 144:ef7eb2e8f9f7 | 1047 | */ |
<> | 144:ef7eb2e8f9f7 | 1048 | |
<> | 144:ef7eb2e8f9f7 | 1049 | /* Peripheral Control functions ************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1050 | /** @addtogroup HAL_SDMMC_LL_Group3 |
<> | 144:ef7eb2e8f9f7 | 1051 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1052 | */ |
<> | 144:ef7eb2e8f9f7 | 1053 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); |
<> | 144:ef7eb2e8f9f7 | 1054 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); |
<> | 144:ef7eb2e8f9f7 | 1055 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); |
<> | 144:ef7eb2e8f9f7 | 1056 | |
<> | 144:ef7eb2e8f9f7 | 1057 | /* Command path state machine (CPSM) management functions */ |
AnnaBridge | 167:e84263d55307 | 1058 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); |
<> | 144:ef7eb2e8f9f7 | 1059 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1060 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); |
<> | 144:ef7eb2e8f9f7 | 1061 | |
<> | 144:ef7eb2e8f9f7 | 1062 | /* Data path state machine (DPSM) management functions */ |
AnnaBridge | 167:e84263d55307 | 1063 | HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); |
<> | 144:ef7eb2e8f9f7 | 1064 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); |
<> | 144:ef7eb2e8f9f7 | 1065 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); |
<> | 144:ef7eb2e8f9f7 | 1066 | |
AnnaBridge | 167:e84263d55307 | 1067 | /* SDMMC Cards mode management functions */ |
AnnaBridge | 167:e84263d55307 | 1068 | HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); |
AnnaBridge | 167:e84263d55307 | 1069 | |
AnnaBridge | 167:e84263d55307 | 1070 | /* SDMMC Commands management functions */ |
AnnaBridge | 167:e84263d55307 | 1071 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); |
AnnaBridge | 167:e84263d55307 | 1072 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
AnnaBridge | 167:e84263d55307 | 1073 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
AnnaBridge | 167:e84263d55307 | 1074 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
AnnaBridge | 167:e84263d55307 | 1075 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
AnnaBridge | 167:e84263d55307 | 1076 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
AnnaBridge | 167:e84263d55307 | 1077 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
AnnaBridge | 167:e84263d55307 | 1078 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1079 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1080 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); |
AnnaBridge | 167:e84263d55307 | 1081 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1082 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1083 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
AnnaBridge | 167:e84263d55307 | 1084 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType); |
AnnaBridge | 167:e84263d55307 | 1085 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); |
AnnaBridge | 167:e84263d55307 | 1086 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1087 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1088 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
AnnaBridge | 167:e84263d55307 | 1089 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); |
AnnaBridge | 167:e84263d55307 | 1090 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); |
AnnaBridge | 167:e84263d55307 | 1091 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); |
AnnaBridge | 167:e84263d55307 | 1092 | |
AnnaBridge | 167:e84263d55307 | 1093 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); |
AnnaBridge | 167:e84263d55307 | 1094 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); |
AnnaBridge | 167:e84263d55307 | 1095 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
AnnaBridge | 167:e84263d55307 | 1096 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
<> | 144:ef7eb2e8f9f7 | 1097 | |
<> | 144:ef7eb2e8f9f7 | 1098 | /** |
<> | 144:ef7eb2e8f9f7 | 1099 | * @} |
<> | 144:ef7eb2e8f9f7 | 1100 | */ |
<> | 144:ef7eb2e8f9f7 | 1101 | |
<> | 144:ef7eb2e8f9f7 | 1102 | /** |
<> | 144:ef7eb2e8f9f7 | 1103 | * @} |
<> | 144:ef7eb2e8f9f7 | 1104 | */ |
<> | 144:ef7eb2e8f9f7 | 1105 | |
<> | 144:ef7eb2e8f9f7 | 1106 | /** |
<> | 144:ef7eb2e8f9f7 | 1107 | * @} |
<> | 144:ef7eb2e8f9f7 | 1108 | */ |
<> | 144:ef7eb2e8f9f7 | 1109 | |
<> | 144:ef7eb2e8f9f7 | 1110 | /** |
<> | 144:ef7eb2e8f9f7 | 1111 | * @} |
<> | 144:ef7eb2e8f9f7 | 1112 | */ |
<> | 144:ef7eb2e8f9f7 | 1113 | |
<> | 144:ef7eb2e8f9f7 | 1114 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 1115 | } |
<> | 144:ef7eb2e8f9f7 | 1116 | #endif |
<> | 144:ef7eb2e8f9f7 | 1117 | |
<> | 144:ef7eb2e8f9f7 | 1118 | #endif /* __STM32F2xx_LL_SDMMC_H */ |
<> | 144:ef7eb2e8f9f7 | 1119 | |
<> | 144:ef7eb2e8f9f7 | 1120 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |