mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 #include <stddef.h>
<> 144:ef7eb2e8f9f7 19 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 20 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 21 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /* The LPC43xx implements GPIO pin and group interrupts. Any pin in the
<> 144:ef7eb2e8f9f7 24 * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can
<> 144:ef7eb2e8f9f7 25 * only interrupt on the rising or falling edge, not both as required
<> 144:ef7eb2e8f9f7 26 * by mbed. Also, group interrupts can't be cleared individually.
<> 144:ef7eb2e8f9f7 27 * This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
<> 144:ef7eb2e8f9f7 28 * A future implementation may provide group interrupt support.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 31 #define CHANNEL_MAX 8
<> 144:ef7eb2e8f9f7 32 #else
<> 144:ef7eb2e8f9f7 33 #define CHANNEL_MAX 1
<> 144:ef7eb2e8f9f7 34 #endif
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 static uint32_t channel_ids[CHANNEL_MAX] = {0};
<> 144:ef7eb2e8f9f7 37 static uint8_t channel = 0;
<> 144:ef7eb2e8f9f7 38 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 static void handle_interrupt_in(void) {
<> 144:ef7eb2e8f9f7 41 uint32_t rise = LPC_GPIO_PIN_INT->RISE;
<> 144:ef7eb2e8f9f7 42 uint32_t fall = LPC_GPIO_PIN_INT->FALL;
<> 144:ef7eb2e8f9f7 43 uint32_t pmask;
<> 144:ef7eb2e8f9f7 44 int i;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 for (i = 0; i < CHANNEL_MAX; i++) {
<> 144:ef7eb2e8f9f7 47 pmask = (1 << i);
<> 144:ef7eb2e8f9f7 48 if (rise & pmask) {
<> 144:ef7eb2e8f9f7 49 /* Rising edge interrupts */
<> 144:ef7eb2e8f9f7 50 if (channel_ids[i] != 0) {
<> 144:ef7eb2e8f9f7 51 irq_handler(channel_ids[i], IRQ_RISE);
<> 144:ef7eb2e8f9f7 52 }
<> 144:ef7eb2e8f9f7 53 /* Clear rising edge detected */
<> 144:ef7eb2e8f9f7 54 LPC_GPIO_PIN_INT->RISE = pmask;
<> 144:ef7eb2e8f9f7 55 }
<> 144:ef7eb2e8f9f7 56 if (fall & pmask) {
<> 144:ef7eb2e8f9f7 57 /* Falling edge interrupts */
<> 144:ef7eb2e8f9f7 58 if (channel_ids[i] != 0) {
<> 144:ef7eb2e8f9f7 59 irq_handler(channel_ids[i], IRQ_FALL);
<> 144:ef7eb2e8f9f7 60 }
<> 144:ef7eb2e8f9f7 61 /* Clear falling edge detected */
<> 144:ef7eb2e8f9f7 62 LPC_GPIO_PIN_INT->FALL = pmask;
<> 144:ef7eb2e8f9f7 63 }
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 68 uint32_t portnum, pinnum; //, pmask;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 if (pin == NC) return -1;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 irq_handler = handler;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Set port and pin numbers */
<> 144:ef7eb2e8f9f7 75 obj->port = portnum = MBED_GPIO_PORT(pin);
<> 144:ef7eb2e8f9f7 76 obj->pin = pinnum = MBED_GPIO_PIN(pin);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* Add to channel table */
<> 144:ef7eb2e8f9f7 79 channel_ids[channel] = id;
<> 144:ef7eb2e8f9f7 80 obj->ch = channel;
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* Clear rising and falling edge detection */
<> 144:ef7eb2e8f9f7 83 //pmask = (1 << channel);
<> 144:ef7eb2e8f9f7 84 //LPC_GPIO_PIN_INT->IST = pmask;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Set SCU */
<> 144:ef7eb2e8f9f7 87 if (channel < 4) {
<> 144:ef7eb2e8f9f7 88 LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3));
<> 144:ef7eb2e8f9f7 89 LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3));
<> 144:ef7eb2e8f9f7 90 } else {
<> 144:ef7eb2e8f9f7 91 LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3));
<> 144:ef7eb2e8f9f7 92 LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3));
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 96 NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in);
<> 144:ef7eb2e8f9f7 97 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel));
<> 144:ef7eb2e8f9f7 98 #else
<> 144:ef7eb2e8f9f7 99 NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in);
<> 144:ef7eb2e8f9f7 100 NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn);
<> 144:ef7eb2e8f9f7 101 #endif
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // Increment channel number
<> 144:ef7eb2e8f9f7 104 channel++;
<> 144:ef7eb2e8f9f7 105 channel %= CHANNEL_MAX;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 return 0;
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 void gpio_irq_free(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 111 channel_ids[obj->ch] = 0;
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
<> 144:ef7eb2e8f9f7 115 uint32_t pmask;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Clear pending interrupts */
<> 144:ef7eb2e8f9f7 118 pmask = (1 << obj->ch);
<> 144:ef7eb2e8f9f7 119 LPC_GPIO_PIN_INT->IST = pmask;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /* Configure pin interrupt */
<> 144:ef7eb2e8f9f7 122 LPC_GPIO_PIN_INT->ISEL &= ~pmask;
<> 144:ef7eb2e8f9f7 123 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 124 /* Rising edge interrupts */
<> 144:ef7eb2e8f9f7 125 if (enable) {
<> 144:ef7eb2e8f9f7 126 LPC_GPIO_PIN_INT->SIENR |= pmask;
<> 144:ef7eb2e8f9f7 127 } else {
<> 144:ef7eb2e8f9f7 128 LPC_GPIO_PIN_INT->CIENR |= pmask;
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130 } else {
<> 144:ef7eb2e8f9f7 131 /* Falling edge interrupts */
<> 144:ef7eb2e8f9f7 132 if (enable) {
<> 144:ef7eb2e8f9f7 133 LPC_GPIO_PIN_INT->SIENF |= pmask;
<> 144:ef7eb2e8f9f7 134 } else {
<> 144:ef7eb2e8f9f7 135 LPC_GPIO_PIN_INT->CIENF |= pmask;
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 void gpio_irq_enable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 141 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 142 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
<> 144:ef7eb2e8f9f7 143 #else
<> 144:ef7eb2e8f9f7 144 NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 void gpio_irq_disable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 149 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 150 NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
<> 144:ef7eb2e8f9f7 151 #else
<> 144:ef7eb2e8f9f7 152 NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
<> 144:ef7eb2e8f9f7 153 #endif
<> 144:ef7eb2e8f9f7 154 }