mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * Copyright (c) 2015-2016 Nuvoton
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 #include "analogin_api.h"
AnnaBridge 172:7d866c31b3c5 18
AnnaBridge 172:7d866c31b3c5 19 void mbed_sdk_init(void)
AnnaBridge 172:7d866c31b3c5 20 {
AnnaBridge 172:7d866c31b3c5 21 // NOTE: Support singleton semantics to be called from other init functions
AnnaBridge 172:7d866c31b3c5 22 static int inited = 0;
AnnaBridge 172:7d866c31b3c5 23 if (inited) {
AnnaBridge 172:7d866c31b3c5 24 return;
AnnaBridge 172:7d866c31b3c5 25 }
AnnaBridge 172:7d866c31b3c5 26 inited = 1;
AnnaBridge 172:7d866c31b3c5 27
AnnaBridge 172:7d866c31b3c5 28 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 172:7d866c31b3c5 29 /* Init System Clock */
AnnaBridge 172:7d866c31b3c5 30 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 172:7d866c31b3c5 31 /* Unlock protected registers */
AnnaBridge 172:7d866c31b3c5 32 SYS_UnlockReg();
AnnaBridge 172:7d866c31b3c5 33
AnnaBridge 172:7d866c31b3c5 34 /* Enable HIRC clock (Internal RC 22.1184MHz) */
AnnaBridge 172:7d866c31b3c5 35 CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
AnnaBridge 172:7d866c31b3c5 36 /* Enable HXT clock (external XTAL 12MHz) */
AnnaBridge 172:7d866c31b3c5 37 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
AnnaBridge 172:7d866c31b3c5 38 /* Enable LIRC for lp_ticker */
AnnaBridge 172:7d866c31b3c5 39 CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
AnnaBridge 172:7d866c31b3c5 40 /* Enable LXT for RTC */
AnnaBridge 172:7d866c31b3c5 41 CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
AnnaBridge 172:7d866c31b3c5 42
AnnaBridge 172:7d866c31b3c5 43 /* Wait for HIRC clock ready */
AnnaBridge 172:7d866c31b3c5 44 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
AnnaBridge 172:7d866c31b3c5 45 /* Wait for HXT clock ready */
AnnaBridge 172:7d866c31b3c5 46 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
AnnaBridge 172:7d866c31b3c5 47 /* Wait for LIRC clock ready */
AnnaBridge 172:7d866c31b3c5 48 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
AnnaBridge 172:7d866c31b3c5 49 /* Wait for LXT clock ready */
AnnaBridge 172:7d866c31b3c5 50 CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
AnnaBridge 172:7d866c31b3c5 51
AnnaBridge 172:7d866c31b3c5 52 /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
AnnaBridge 172:7d866c31b3c5 53 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
AnnaBridge 172:7d866c31b3c5 54
AnnaBridge 172:7d866c31b3c5 55 /* Set core clock as 192000000 from PLL */
AnnaBridge 172:7d866c31b3c5 56 CLK_SetCoreClock(192000000);
AnnaBridge 172:7d866c31b3c5 57
AnnaBridge 172:7d866c31b3c5 58 /* Set PCLK0/PCLK1 to HCLK/2 */
AnnaBridge 172:7d866c31b3c5 59 CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); // PCLK divider set 2
AnnaBridge 172:7d866c31b3c5 60
AnnaBridge 172:7d866c31b3c5 61 #if DEVICE_ANALOGIN
AnnaBridge 172:7d866c31b3c5 62 /* Vref connect to internal */
AnnaBridge 172:7d866c31b3c5 63 SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V;
AnnaBridge 172:7d866c31b3c5 64 #endif
AnnaBridge 172:7d866c31b3c5 65
AnnaBridge 172:7d866c31b3c5 66 /* Update System Core Clock */
AnnaBridge 172:7d866c31b3c5 67 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
AnnaBridge 172:7d866c31b3c5 68 SystemCoreClockUpdate();
AnnaBridge 172:7d866c31b3c5 69
AnnaBridge 172:7d866c31b3c5 70 /* Lock protected registers */
AnnaBridge 172:7d866c31b3c5 71 SYS_LockReg();
AnnaBridge 172:7d866c31b3c5 72 }