mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "serial_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_SERIAL
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "cmsis.h"
<> 149:156823d33999 22 #include "mbed_error.h"
<> 149:156823d33999 23 #include "mbed_assert.h"
<> 149:156823d33999 24 #include "PeripheralPins.h"
<> 149:156823d33999 25 #include "nu_modutil.h"
<> 149:156823d33999 26 #include "nu_bitutil.h"
AnnaBridge 165:e614a9f1c9e2 27 #include <string.h>
AnnaBridge 188:bcfe06ba3d64 28 #include <stdbool.h>
<> 149:156823d33999 29
<> 149:156823d33999 30 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 31 #include "dma_api.h"
<> 149:156823d33999 32 #include "dma.h"
<> 149:156823d33999 33 #endif
<> 149:156823d33999 34
<> 149:156823d33999 35 struct nu_uart_var {
<> 151:5eaa88a5bcc7 36 uint32_t ref_cnt; // Reference count of the H/W module
<> 149:156823d33999 37 serial_t * obj;
<> 149:156823d33999 38 uint32_t fifo_size_tx;
<> 149:156823d33999 39 uint32_t fifo_size_rx;
<> 149:156823d33999 40 void (*vec)(void);
<> 149:156823d33999 41 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 42 void (*vec_async)(void);
<> 149:156823d33999 43 uint8_t pdma_perp_tx;
<> 149:156823d33999 44 uint8_t pdma_perp_rx;
<> 149:156823d33999 45 #endif
<> 149:156823d33999 46 };
<> 149:156823d33999 47
<> 149:156823d33999 48 static void uart0_vec(void);
<> 149:156823d33999 49 static void uart1_vec(void);
<> 149:156823d33999 50 static void uart2_vec(void);
<> 149:156823d33999 51 static void uart3_vec(void);
<> 149:156823d33999 52 static void uart_irq(serial_t *obj);
<> 149:156823d33999 53
<> 149:156823d33999 54 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 55 static void uart0_vec_async(void);
<> 149:156823d33999 56 static void uart1_vec_async(void);
<> 149:156823d33999 57 static void uart2_vec_async(void);
<> 149:156823d33999 58 static void uart3_vec_async(void);
<> 149:156823d33999 59 static void uart_irq_async(serial_t *obj);
<> 149:156823d33999 60
<> 149:156823d33999 61 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
<> 149:156823d33999 62 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
<> 149:156823d33999 63
<> 149:156823d33999 64 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
<> 149:156823d33999 65 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
AnnaBridge 165:e614a9f1c9e2 66 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
AnnaBridge 165:e614a9f1c9e2 67 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
<> 149:156823d33999 68 static int serial_write_async(serial_t *obj);
<> 149:156823d33999 69 static int serial_read_async(serial_t *obj);
<> 149:156823d33999 70
<> 149:156823d33999 71 static uint32_t serial_rx_event_check(serial_t *obj);
<> 149:156823d33999 72 static uint32_t serial_tx_event_check(serial_t *obj);
<> 149:156823d33999 73
<> 149:156823d33999 74 static int serial_is_tx_complete(serial_t *obj);
<> 149:156823d33999 75 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 149:156823d33999 76
<> 149:156823d33999 77 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
<> 149:156823d33999 78 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
<> 149:156823d33999 79 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
<> 149:156823d33999 80 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 149:156823d33999 81 static int serial_is_rx_complete(serial_t *obj);
<> 149:156823d33999 82
<> 149:156823d33999 83 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
<> 149:156823d33999 84 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
<> 149:156823d33999 85 #endif
<> 149:156823d33999 86
AnnaBridge 188:bcfe06ba3d64 87 bool serial_can_deep_sleep(void);
AnnaBridge 188:bcfe06ba3d64 88
<> 149:156823d33999 89 static struct nu_uart_var uart0_var = {
<> 151:5eaa88a5bcc7 90 .ref_cnt = 0,
<> 149:156823d33999 91 .obj = NULL,
<> 149:156823d33999 92 .fifo_size_tx = 16,
<> 149:156823d33999 93 .fifo_size_rx = 16,
<> 149:156823d33999 94 .vec = uart0_vec,
<> 149:156823d33999 95 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 96 .vec_async = uart0_vec_async,
<> 149:156823d33999 97 .pdma_perp_tx = PDMA_UART0_TX,
<> 149:156823d33999 98 .pdma_perp_rx = PDMA_UART0_RX
<> 149:156823d33999 99 #endif
<> 149:156823d33999 100 };
<> 149:156823d33999 101 static struct nu_uart_var uart1_var = {
<> 151:5eaa88a5bcc7 102 .ref_cnt = 0,
<> 149:156823d33999 103 .obj = NULL,
<> 149:156823d33999 104 .fifo_size_tx = 16,
<> 149:156823d33999 105 .fifo_size_rx = 16,
<> 149:156823d33999 106 .vec = uart1_vec,
<> 149:156823d33999 107 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 108 .vec_async = uart1_vec_async,
<> 149:156823d33999 109 .pdma_perp_tx = PDMA_UART1_TX,
<> 149:156823d33999 110 .pdma_perp_rx = PDMA_UART1_RX
<> 149:156823d33999 111 #endif
<> 149:156823d33999 112 };
<> 149:156823d33999 113 static struct nu_uart_var uart2_var = {
<> 151:5eaa88a5bcc7 114 .ref_cnt = 0,
<> 149:156823d33999 115 .obj = NULL,
<> 149:156823d33999 116 .fifo_size_tx = 16,
<> 149:156823d33999 117 .fifo_size_rx = 16,
<> 149:156823d33999 118 .vec = uart2_vec,
<> 149:156823d33999 119 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 120 .vec_async = uart2_vec_async,
<> 149:156823d33999 121 .pdma_perp_tx = PDMA_UART2_TX,
<> 149:156823d33999 122 .pdma_perp_rx = PDMA_UART2_RX
<> 149:156823d33999 123 #endif
<> 149:156823d33999 124 };
<> 149:156823d33999 125 static struct nu_uart_var uart3_var = {
<> 151:5eaa88a5bcc7 126 .ref_cnt = 0,
<> 149:156823d33999 127 .obj = NULL,
<> 149:156823d33999 128 .fifo_size_tx = 16,
<> 149:156823d33999 129 .fifo_size_rx = 16,
<> 149:156823d33999 130 .vec = uart3_vec,
<> 149:156823d33999 131 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 132 .vec_async = uart3_vec_async,
<> 149:156823d33999 133 .pdma_perp_tx = PDMA_UART3_TX,
<> 149:156823d33999 134 .pdma_perp_rx = PDMA_UART3_RX
<> 149:156823d33999 135 #endif
<> 149:156823d33999 136 };
<> 149:156823d33999 137
<> 149:156823d33999 138
<> 149:156823d33999 139 int stdio_uart_inited = 0;
<> 149:156823d33999 140 serial_t stdio_uart;
<> 149:156823d33999 141 static uint32_t uart_modinit_mask = 0;
<> 149:156823d33999 142
<> 149:156823d33999 143 static const struct nu_modinit_s uart_modinit_tab[] = {
<> 149:156823d33999 144 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
<> 149:156823d33999 145 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
<> 149:156823d33999 146 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
<> 149:156823d33999 147 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
<> 149:156823d33999 148
<> 149:156823d33999 149 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 149:156823d33999 150 };
<> 149:156823d33999 151
<> 149:156823d33999 152 extern void mbed_sdk_init(void);
<> 149:156823d33999 153
<> 149:156823d33999 154 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 149:156823d33999 155 {
<> 151:5eaa88a5bcc7 156 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
<> 149:156823d33999 157 mbed_sdk_init();
<> 149:156823d33999 158
<> 149:156823d33999 159 // Determine which UART_x the pins are used for
<> 149:156823d33999 160 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 149:156823d33999 161 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 149:156823d33999 162 // Get the peripheral name (UART_x) from the pins and assign it to the object
<> 149:156823d33999 163 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
<> 149:156823d33999 164 MBED_ASSERT((int)obj->serial.uart != NC);
<> 149:156823d33999 165
<> 149:156823d33999 166 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 167 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 168 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 169
<> 151:5eaa88a5bcc7 170 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 171
<> 151:5eaa88a5bcc7 172 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 173 // Reset this module
<> 151:5eaa88a5bcc7 174 SYS_ResetModule(modinit->rsetidx);
AnnaBridge 189:f392fc9709a3 175
<> 151:5eaa88a5bcc7 176 // Select IP clock source
<> 151:5eaa88a5bcc7 177 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 151:5eaa88a5bcc7 178 // Enable IP clock
<> 151:5eaa88a5bcc7 179 CLK_EnableModuleClock(modinit->clkidx);
<> 149:156823d33999 180
<> 151:5eaa88a5bcc7 181 pinmap_pinout(tx, PinMap_UART_TX);
<> 151:5eaa88a5bcc7 182 pinmap_pinout(rx, PinMap_UART_RX);
AnnaBridge 189:f392fc9709a3 183
AnnaBridge 189:f392fc9709a3 184 // Configure baudrate
AnnaBridge 189:f392fc9709a3 185 int baudrate = 9600;
AnnaBridge 189:f392fc9709a3 186 if (obj->serial.uart == STDIO_UART) {
AnnaBridge 189:f392fc9709a3 187 #if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
AnnaBridge 189:f392fc9709a3 188 baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE;
AnnaBridge 189:f392fc9709a3 189 #endif
AnnaBridge 189:f392fc9709a3 190 } else {
AnnaBridge 189:f392fc9709a3 191 #if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE
AnnaBridge 189:f392fc9709a3 192 baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE;
AnnaBridge 189:f392fc9709a3 193 #endif
AnnaBridge 189:f392fc9709a3 194 }
AnnaBridge 189:f392fc9709a3 195 serial_baud(obj, baudrate);
AnnaBridge 189:f392fc9709a3 196
AnnaBridge 189:f392fc9709a3 197 // Configure data bits, parity, and stop bits
AnnaBridge 189:f392fc9709a3 198 serial_format(obj, 8, ParityNone, 1);
<> 151:5eaa88a5bcc7 199 }
<> 151:5eaa88a5bcc7 200 var->ref_cnt ++;
AnnaBridge 189:f392fc9709a3 201
<> 151:5eaa88a5bcc7 202 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 203 obj->serial.irq_en = 0;
<> 149:156823d33999 204
<> 149:156823d33999 205 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 206 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
<> 149:156823d33999 207 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 149:156823d33999 208 obj->serial.event = 0;
<> 149:156823d33999 209 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 210 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 211 #endif
<> 149:156823d33999 212
AnnaBridge 189:f392fc9709a3 213 /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart)
AnnaBridge 189:f392fc9709a3 214 * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart)
AnnaBridge 189:f392fc9709a3 215 * calls in, we only need to set the 'stdio_uart_inited' flag. */
AnnaBridge 189:f392fc9709a3 216 if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) {
AnnaBridge 189:f392fc9709a3 217 MBED_ASSERT(obj->serial.uart == STDIO_UART);
<> 149:156823d33999 218 stdio_uart_inited = 1;
<> 149:156823d33999 219 }
AnnaBridge 189:f392fc9709a3 220
<> 151:5eaa88a5bcc7 221 if (var->ref_cnt) {
<> 151:5eaa88a5bcc7 222 // Mark this module to be inited.
<> 151:5eaa88a5bcc7 223 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 224 uart_modinit_mask |= 1 << i;
<> 151:5eaa88a5bcc7 225 }
<> 149:156823d33999 226 }
<> 149:156823d33999 227
<> 149:156823d33999 228 void serial_free(serial_t *obj)
<> 149:156823d33999 229 {
<> 149:156823d33999 230 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 231 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 232 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 233
<> 151:5eaa88a5bcc7 234 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 235
<> 151:5eaa88a5bcc7 236 var->ref_cnt --;
<> 151:5eaa88a5bcc7 237 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 238 #if DEVICE_SERIAL_ASYNCH
<> 151:5eaa88a5bcc7 239 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 240 dma_channel_free(obj->serial.dma_chn_id_tx);
<> 151:5eaa88a5bcc7 241 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 242 }
<> 151:5eaa88a5bcc7 243 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 244 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 151:5eaa88a5bcc7 245 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 246 }
<> 151:5eaa88a5bcc7 247 #endif
<> 151:5eaa88a5bcc7 248
<> 151:5eaa88a5bcc7 249 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
<> 149:156823d33999 250
<> 151:5eaa88a5bcc7 251 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 151:5eaa88a5bcc7 252 NVIC_DisableIRQ(modinit->irq_n);
<> 149:156823d33999 253
<> 151:5eaa88a5bcc7 254 // Disable IP clock
<> 151:5eaa88a5bcc7 255 CLK_DisableModuleClock(modinit->clkidx);
<> 151:5eaa88a5bcc7 256 }
<> 151:5eaa88a5bcc7 257
<> 151:5eaa88a5bcc7 258 if (var->obj == obj) {
<> 151:5eaa88a5bcc7 259 var->obj = NULL;
<> 151:5eaa88a5bcc7 260 }
AnnaBridge 189:f392fc9709a3 261
AnnaBridge 189:f392fc9709a3 262 /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */
AnnaBridge 189:f392fc9709a3 263 if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) {
AnnaBridge 189:f392fc9709a3 264 MBED_ASSERT(obj->serial.uart == STDIO_UART);
<> 149:156823d33999 265 stdio_uart_inited = 0;
<> 149:156823d33999 266 }
AnnaBridge 189:f392fc9709a3 267
<> 151:5eaa88a5bcc7 268 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 269 // Mark this module to be deinited.
<> 151:5eaa88a5bcc7 270 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 271 uart_modinit_mask &= ~(1 << i);
<> 151:5eaa88a5bcc7 272 }
<> 149:156823d33999 273 }
<> 149:156823d33999 274
<> 149:156823d33999 275 void serial_baud(serial_t *obj, int baudrate) {
<> 149:156823d33999 276 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 277 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 278
<> 149:156823d33999 279 obj->serial.baudrate = baudrate;
<> 149:156823d33999 280 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
<> 149:156823d33999 281 }
<> 149:156823d33999 282
<> 149:156823d33999 283 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 149:156823d33999 284 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 285 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 286
AnnaBridge 172:7d866c31b3c5 287 // Sanity check arguments
AnnaBridge 172:7d866c31b3c5 288 MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
AnnaBridge 172:7d866c31b3c5 289 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
AnnaBridge 172:7d866c31b3c5 290 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
AnnaBridge 172:7d866c31b3c5 291
<> 149:156823d33999 292 obj->serial.databits = data_bits;
<> 149:156823d33999 293 obj->serial.parity = parity;
<> 149:156823d33999 294 obj->serial.stopbits = stop_bits;
<> 149:156823d33999 295
<> 149:156823d33999 296 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
<> 149:156823d33999 297 (data_bits == 6) ? UART_WORD_LEN_6 :
<> 149:156823d33999 298 (data_bits == 7) ? UART_WORD_LEN_7 :
<> 149:156823d33999 299 UART_WORD_LEN_8;
<> 149:156823d33999 300 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
<> 149:156823d33999 301 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
<> 149:156823d33999 302 UART_PARITY_NONE;
<> 149:156823d33999 303 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
<> 149:156823d33999 304 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
<> 149:156823d33999 305 0, // Don't change baudrate
<> 149:156823d33999 306 databits_intern,
<> 149:156823d33999 307 parity_intern,
<> 149:156823d33999 308 stopbits_intern);
<> 149:156823d33999 309 }
<> 149:156823d33999 310
<> 149:156823d33999 311 #if DEVICE_SERIAL_FC
<> 149:156823d33999 312
<> 149:156823d33999 313 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 149:156823d33999 314 {
<> 149:156823d33999 315 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 316
AnnaBridge 189:f392fc9709a3 317 if (rxflow != NC) {
<> 149:156823d33999 318 // Check if RTS pin matches.
<> 149:156823d33999 319 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 149:156823d33999 320 MBED_ASSERT(uart_rts == obj->serial.uart);
<> 149:156823d33999 321 // Enable the pin for RTS function
<> 149:156823d33999 322 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 153:fa9ff456f731 323 // nRTS pin output is low level active
<> 153:fa9ff456f731 324 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
AnnaBridge 189:f392fc9709a3 325 // Configure RTS trigger level to 8 bytes
<> 149:156823d33999 326 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
AnnaBridge 189:f392fc9709a3 327
AnnaBridge 189:f392fc9709a3 328 if (type == FlowControlRTS || type == FlowControlRTSCTS) {
AnnaBridge 189:f392fc9709a3 329 // Enable RTS
AnnaBridge 189:f392fc9709a3 330 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
AnnaBridge 189:f392fc9709a3 331 } else {
AnnaBridge 189:f392fc9709a3 332 // Disable RTS
AnnaBridge 189:f392fc9709a3 333 uart_base->INTEN &= ~UART_INTEN_ATORTSEN_Msk;
AnnaBridge 189:f392fc9709a3 334 /* Drive nRTS pin output to low-active. Allow the peer to be able to send data
AnnaBridge 189:f392fc9709a3 335 * even though its CTS is still enabled. */
AnnaBridge 189:f392fc9709a3 336 uart_base->MODEM &= ~UART_MODEM_RTS_Msk;
AnnaBridge 189:f392fc9709a3 337 }
<> 149:156823d33999 338 }
AnnaBridge 189:f392fc9709a3 339
AnnaBridge 189:f392fc9709a3 340 /* If CTS is disabled, we don't need to configure CTS. But to be consistent with
AnnaBridge 189:f392fc9709a3 341 * RTS code above, we still configure CTS. */
AnnaBridge 189:f392fc9709a3 342 if (txflow != NC) {
<> 149:156823d33999 343 // Check if CTS pin matches.
<> 149:156823d33999 344 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 149:156823d33999 345 MBED_ASSERT(uart_cts == obj->serial.uart);
<> 149:156823d33999 346 // Enable the pin for CTS function
<> 149:156823d33999 347 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 153:fa9ff456f731 348 // nCTS pin input is low level active
<> 153:fa9ff456f731 349 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
AnnaBridge 189:f392fc9709a3 350
AnnaBridge 189:f392fc9709a3 351 if (type == FlowControlCTS || type == FlowControlRTSCTS) {
AnnaBridge 189:f392fc9709a3 352 // Enable CTS
AnnaBridge 189:f392fc9709a3 353 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
AnnaBridge 189:f392fc9709a3 354 } else {
AnnaBridge 189:f392fc9709a3 355 // Disable CTS
AnnaBridge 189:f392fc9709a3 356 uart_base->INTEN &= ~UART_INTEN_ATOCTSEN_Msk;
AnnaBridge 189:f392fc9709a3 357 }
<> 149:156823d33999 358 }
<> 149:156823d33999 359 }
<> 149:156823d33999 360
<> 149:156823d33999 361 #endif //DEVICE_SERIAL_FC
<> 149:156823d33999 362
<> 149:156823d33999 363 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 149:156823d33999 364 {
<> 149:156823d33999 365 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 366 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 367
<> 149:156823d33999 368 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 369 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 370 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 371
<> 149:156823d33999 372 obj->serial.irq_handler = (uint32_t) handler;
<> 149:156823d33999 373 obj->serial.irq_id = id;
<> 149:156823d33999 374
<> 149:156823d33999 375 // Restore sync-mode vector
<> 149:156823d33999 376 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
<> 149:156823d33999 377 }
<> 149:156823d33999 378
<> 149:156823d33999 379 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 149:156823d33999 380 {
AnnaBridge 165:e614a9f1c9e2 381 obj->serial.irq_en = enable;
AnnaBridge 165:e614a9f1c9e2 382 serial_enable_interrupt(obj, irq, enable);
<> 149:156823d33999 383 }
<> 149:156823d33999 384
<> 149:156823d33999 385 int serial_getc(serial_t *obj)
<> 149:156823d33999 386 {
AnnaBridge 165:e614a9f1c9e2 387 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 149:156823d33999 388 while (! serial_readable(obj));
<> 149:156823d33999 389 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 390
AnnaBridge 165:e614a9f1c9e2 391 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 392 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 149:156823d33999 393 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 394 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 395 }
<> 149:156823d33999 396
<> 149:156823d33999 397 return c;
<> 149:156823d33999 398 }
<> 149:156823d33999 399
<> 149:156823d33999 400 void serial_putc(serial_t *obj, int c)
<> 149:156823d33999 401 {
AnnaBridge 165:e614a9f1c9e2 402 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 149:156823d33999 403 while (! serial_writable(obj));
<> 149:156823d33999 404 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
<> 149:156823d33999 405
AnnaBridge 165:e614a9f1c9e2 406 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 407 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 149:156823d33999 408 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 409 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 410 }
<> 149:156823d33999 411 }
<> 149:156823d33999 412
<> 149:156823d33999 413 int serial_readable(serial_t *obj)
<> 149:156823d33999 414 {
<> 149:156823d33999 415 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 416 return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 417 }
<> 149:156823d33999 418
<> 149:156823d33999 419 int serial_writable(serial_t *obj)
<> 149:156823d33999 420 {
<> 149:156823d33999 421 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 422 }
<> 149:156823d33999 423
<> 149:156823d33999 424 void serial_pinout_tx(PinName tx)
<> 149:156823d33999 425 {
<> 149:156823d33999 426 pinmap_pinout(tx, PinMap_UART_TX);
<> 149:156823d33999 427 }
<> 149:156823d33999 428
<> 149:156823d33999 429 void serial_break_set(serial_t *obj)
<> 149:156823d33999 430 {
<> 149:156823d33999 431 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
<> 149:156823d33999 432 }
<> 149:156823d33999 433
<> 149:156823d33999 434 void serial_break_clear(serial_t *obj)
<> 149:156823d33999 435 {
<> 149:156823d33999 436 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
<> 149:156823d33999 437 }
<> 149:156823d33999 438
<> 149:156823d33999 439 static void uart0_vec(void)
<> 149:156823d33999 440 {
<> 149:156823d33999 441 uart_irq(uart0_var.obj);
<> 149:156823d33999 442 }
<> 149:156823d33999 443
<> 149:156823d33999 444 static void uart1_vec(void)
<> 149:156823d33999 445 {
<> 149:156823d33999 446 uart_irq(uart1_var.obj);
<> 149:156823d33999 447 }
<> 149:156823d33999 448
<> 149:156823d33999 449 static void uart2_vec(void)
<> 149:156823d33999 450 {
<> 149:156823d33999 451 uart_irq(uart2_var.obj);
<> 149:156823d33999 452 }
<> 149:156823d33999 453
<> 149:156823d33999 454 static void uart3_vec(void)
<> 149:156823d33999 455 {
<> 149:156823d33999 456 uart_irq(uart3_var.obj);
<> 149:156823d33999 457 }
<> 149:156823d33999 458
<> 149:156823d33999 459 static void uart_irq(serial_t *obj)
<> 149:156823d33999 460 {
<> 149:156823d33999 461 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 462
<> 149:156823d33999 463 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 149:156823d33999 464 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 149:156823d33999 465 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 466 if (obj->serial.irq_handler) {
<> 149:156823d33999 467 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
<> 149:156823d33999 468 }
<> 149:156823d33999 469 }
<> 149:156823d33999 470
<> 149:156823d33999 471 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 149:156823d33999 472 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 149:156823d33999 473 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 474 if (obj->serial.irq_handler) {
<> 149:156823d33999 475 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
<> 149:156823d33999 476 }
<> 149:156823d33999 477 }
<> 149:156823d33999 478
<> 149:156823d33999 479 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
<> 149:156823d33999 480 uart_base->INTSTS = uart_base->INTSTS;
<> 149:156823d33999 481 uart_base->FIFOSTS = uart_base->FIFOSTS;
<> 149:156823d33999 482 }
<> 149:156823d33999 483
<> 149:156823d33999 484
<> 149:156823d33999 485 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 486 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 487 {
<> 149:156823d33999 488 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
<> 149:156823d33999 489
<> 149:156823d33999 490 obj->serial.dma_usage_tx = hint;
<> 149:156823d33999 491 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
<> 149:156823d33999 492
<> 149:156823d33999 493 // UART IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 494 serial_tx_enable_event(obj, event, 1);
<> 149:156823d33999 495 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
<> 149:156823d33999 496 //UART_HAL_DisableTransmitter(obj->serial.address);
<> 149:156823d33999 497 //UART_HAL_FlushTxFifo(obj->serial.address);
<> 149:156823d33999 498 //UART_HAL_EnableTransmitter(obj->serial.address);
<> 149:156823d33999 499
<> 149:156823d33999 500 int n_word = 0;
<> 149:156823d33999 501 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 149:156823d33999 502 // Interrupt way
<> 149:156823d33999 503 n_word = serial_write_async(obj);
<> 149:156823d33999 504 serial_tx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 505 } else {
<> 149:156823d33999 506 // DMA way
<> 149:156823d33999 507 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 508 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 509 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 510
<> 161:2cc1468da177 511 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 512
<> 161:2cc1468da177 513 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
<> 149:156823d33999 514 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 515 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
<> 149:156823d33999 516 0, // Scatter-gather disabled
<> 149:156823d33999 517 0); // Scatter-gather descriptor address
<> 149:156823d33999 518 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 519 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 520 tx_length);
<> 149:156823d33999 521 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 522 (uint32_t) tx, // NOTE:
<> 149:156823d33999 523 // NUC472: End of source address
<> 149:156823d33999 524 // M451: Start of source address
<> 149:156823d33999 525 PDMA_SAR_INC, // Source address incremental
<> 161:2cc1468da177 526 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
<> 149:156823d33999 527 PDMA_DAR_FIX); // Destination address fixed
<> 149:156823d33999 528 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 529 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 530 0); // Burst size
<> 149:156823d33999 531 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 532 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 533 // Register DMA event handler
<> 149:156823d33999 534 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
<> 149:156823d33999 535 serial_tx_enable_interrupt(obj, handler, 1);
AnnaBridge 184:08ed48f1de7f 536 /* We needn't actually enable UART INT to go UART ISR -> handler.
AnnaBridge 184:08ed48f1de7f 537 * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
AnnaBridge 184:08ed48f1de7f 538 * with serial_tx/rx_enable_interrupt having set up this call path. */
AnnaBridge 184:08ed48f1de7f 539 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 540 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
<> 149:156823d33999 541 }
<> 149:156823d33999 542
<> 149:156823d33999 543 return n_word;
<> 149:156823d33999 544 }
<> 149:156823d33999 545
<> 149:156823d33999 546 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
<> 149:156823d33999 547 {
<> 149:156823d33999 548 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
<> 149:156823d33999 549
<> 149:156823d33999 550 obj->serial.dma_usage_rx = hint;
<> 149:156823d33999 551 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
<> 149:156823d33999 552 // DMA doesn't support char match, so fall back to IRQ if it is requested.
<> 149:156823d33999 553 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
<> 149:156823d33999 554 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 149:156823d33999 555 char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 149:156823d33999 556 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 149:156823d33999 557 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 149:156823d33999 558 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 559 }
<> 149:156823d33999 560
<> 149:156823d33999 561 // UART IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 562 serial_rx_enable_event(obj, event, 1);
<> 149:156823d33999 563 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
<> 149:156823d33999 564 serial_rx_set_char_match(obj, char_match);
<> 149:156823d33999 565 //UART_HAL_DisableReceiver(obj->serial.address);
<> 149:156823d33999 566 //UART_HAL_FlushRxFifo(obj->serial.address);
<> 149:156823d33999 567 //UART_HAL_EnableReceiver(obj->serial.address);
<> 149:156823d33999 568
<> 149:156823d33999 569 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 149:156823d33999 570 // Interrupt way
<> 149:156823d33999 571 serial_rx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 572 } else {
<> 149:156823d33999 573 // DMA way
<> 149:156823d33999 574 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 575 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 576 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 577
<> 161:2cc1468da177 578 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 579
<> 161:2cc1468da177 580 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
<> 149:156823d33999 581 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 582 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
<> 149:156823d33999 583 0, // Scatter-gather disabled
<> 149:156823d33999 584 0); // Scatter-gather descriptor address
<> 149:156823d33999 585 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 586 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 587 rx_length);
<> 149:156823d33999 588 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
<> 161:2cc1468da177 589 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
<> 149:156823d33999 590 PDMA_SAR_FIX, // Source address fixed
<> 149:156823d33999 591 (uint32_t) rx, // NOTE:
<> 149:156823d33999 592 // NUC472: End of destination address
<> 149:156823d33999 593 // M451: Start of destination address
<> 149:156823d33999 594 PDMA_DAR_INC); // Destination address incremental
<> 149:156823d33999 595 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 596 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 597 0); // Burst size
<> 149:156823d33999 598 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 599 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 600 // Register DMA event handler
<> 149:156823d33999 601 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
<> 149:156823d33999 602 serial_rx_enable_interrupt(obj, handler, 1);
AnnaBridge 184:08ed48f1de7f 603 /* We needn't actually enable UART INT to go UART ISR -> handler.
AnnaBridge 184:08ed48f1de7f 604 * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
AnnaBridge 184:08ed48f1de7f 605 * with serial_tx/rx_enable_interrupt having set up this call path. */
AnnaBridge 184:08ed48f1de7f 606 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 607 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
<> 149:156823d33999 608 }
<> 149:156823d33999 609 }
<> 149:156823d33999 610
<> 149:156823d33999 611 void serial_tx_abort_asynch(serial_t *obj)
<> 149:156823d33999 612 {
<> 149:156823d33999 613 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 614 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 615
<> 149:156823d33999 616 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 617 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 618
<> 149:156823d33999 619 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 620 PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
<> 149:156823d33999 621 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 149:156823d33999 622 //PDMA_STOP(obj->serial.dma_chn_id_tx);
<> 161:2cc1468da177 623 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
<> 149:156823d33999 624 }
<> 149:156823d33999 625 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
<> 149:156823d33999 626 }
<> 149:156823d33999 627
<> 149:156823d33999 628 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 629 serial_enable_interrupt(obj, TxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 630 serial_rollback_interrupt(obj, TxIrq);
<> 149:156823d33999 631 }
<> 149:156823d33999 632
<> 149:156823d33999 633 void serial_rx_abort_asynch(serial_t *obj)
<> 149:156823d33999 634 {
<> 149:156823d33999 635 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 636 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 637
<> 149:156823d33999 638 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 639 PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
<> 149:156823d33999 640 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 149:156823d33999 641 //PDMA_STOP(obj->serial.dma_chn_id_rx);
<> 161:2cc1468da177 642 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
<> 149:156823d33999 643 }
<> 149:156823d33999 644 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
<> 149:156823d33999 645 }
<> 149:156823d33999 646
<> 149:156823d33999 647 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 648 serial_enable_interrupt(obj, RxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 649 serial_rollback_interrupt(obj, RxIrq);
<> 149:156823d33999 650 }
<> 149:156823d33999 651
<> 149:156823d33999 652 uint8_t serial_tx_active(serial_t *obj)
<> 149:156823d33999 653 {
AnnaBridge 165:e614a9f1c9e2 654 // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 655 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 656 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 657 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 658
AnnaBridge 165:e614a9f1c9e2 659 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 660 return (obj->serial.vec == var->vec_async);
<> 149:156823d33999 661 }
<> 149:156823d33999 662
<> 149:156823d33999 663 uint8_t serial_rx_active(serial_t *obj)
<> 149:156823d33999 664 {
AnnaBridge 165:e614a9f1c9e2 665 // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 666 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 667 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 668 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 669
AnnaBridge 165:e614a9f1c9e2 670 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 671 return (obj->serial.vec == var->vec_async);
<> 149:156823d33999 672 }
<> 149:156823d33999 673
<> 149:156823d33999 674 int serial_irq_handler_asynch(serial_t *obj)
<> 149:156823d33999 675 {
<> 149:156823d33999 676 int event_rx = 0;
<> 149:156823d33999 677 int event_tx = 0;
<> 149:156823d33999 678
<> 151:5eaa88a5bcc7 679 // Necessary for both interrupt way and DMA way
<> 149:156823d33999 680 if (serial_is_irq_en(obj, RxIrq)) {
<> 149:156823d33999 681 event_rx = serial_rx_event_check(obj);
<> 149:156823d33999 682 if (event_rx) {
<> 149:156823d33999 683 serial_rx_abort_asynch(obj);
<> 149:156823d33999 684 }
<> 149:156823d33999 685 }
<> 149:156823d33999 686
<> 149:156823d33999 687 if (serial_is_irq_en(obj, TxIrq)) {
<> 149:156823d33999 688 event_tx = serial_tx_event_check(obj);
<> 149:156823d33999 689 if (event_tx) {
<> 149:156823d33999 690 serial_tx_abort_asynch(obj);
<> 149:156823d33999 691 }
<> 149:156823d33999 692 }
<> 149:156823d33999 693
<> 149:156823d33999 694 return (obj->serial.event & (event_rx | event_tx));
<> 149:156823d33999 695 }
<> 149:156823d33999 696
<> 149:156823d33999 697 static void uart0_vec_async(void)
<> 149:156823d33999 698 {
<> 149:156823d33999 699 uart_irq_async(uart0_var.obj);
<> 149:156823d33999 700 }
<> 149:156823d33999 701
<> 149:156823d33999 702 static void uart1_vec_async(void)
<> 149:156823d33999 703 {
<> 149:156823d33999 704 uart_irq_async(uart1_var.obj);
<> 149:156823d33999 705 }
<> 149:156823d33999 706
<> 149:156823d33999 707 static void uart2_vec_async(void)
<> 149:156823d33999 708 {
<> 149:156823d33999 709 uart_irq_async(uart2_var.obj);
<> 149:156823d33999 710 }
<> 149:156823d33999 711
<> 149:156823d33999 712 static void uart3_vec_async(void)
<> 149:156823d33999 713 {
<> 149:156823d33999 714 uart_irq_async(uart3_var.obj);
<> 149:156823d33999 715 }
<> 149:156823d33999 716
<> 149:156823d33999 717 static void uart_irq_async(serial_t *obj)
<> 149:156823d33999 718 {
<> 149:156823d33999 719 if (serial_is_irq_en(obj, RxIrq)) {
<> 149:156823d33999 720 (*obj->serial.irq_handler_rx_async)();
<> 149:156823d33999 721 }
<> 149:156823d33999 722 if (serial_is_irq_en(obj, TxIrq)) {
<> 149:156823d33999 723 (*obj->serial.irq_handler_tx_async)();
<> 149:156823d33999 724 }
<> 149:156823d33999 725 }
<> 149:156823d33999 726
<> 149:156823d33999 727 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
<> 149:156823d33999 728 {
<> 149:156823d33999 729 obj->char_match = char_match;
<> 149:156823d33999 730 obj->char_found = 0;
<> 149:156823d33999 731 }
<> 149:156823d33999 732
<> 149:156823d33999 733 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 149:156823d33999 734 {
<> 149:156823d33999 735 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
<> 149:156823d33999 736 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
<> 149:156823d33999 737
<> 149:156823d33999 738 //if (event & SERIAL_EVENT_TX_COMPLETE) {
<> 149:156823d33999 739 //}
<> 149:156823d33999 740 }
<> 149:156823d33999 741
<> 149:156823d33999 742 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 149:156823d33999 743 {
<> 149:156823d33999 744 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
<> 149:156823d33999 745 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
<> 149:156823d33999 746
<> 149:156823d33999 747 //if (event & SERIAL_EVENT_RX_COMPLETE) {
<> 149:156823d33999 748 //}
<> 149:156823d33999 749 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
<> 149:156823d33999 750 //}
<> 149:156823d33999 751 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
<> 149:156823d33999 752 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 149:156823d33999 753 }
<> 149:156823d33999 754 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
<> 149:156823d33999 755 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 149:156823d33999 756 }
<> 149:156823d33999 757 if (event & SERIAL_EVENT_RX_OVERFLOW) {
<> 149:156823d33999 758 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
<> 149:156823d33999 759 }
<> 149:156823d33999 760 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
<> 149:156823d33999 761 //}
<> 149:156823d33999 762 }
<> 149:156823d33999 763
<> 149:156823d33999 764 static int serial_is_tx_complete(serial_t *obj)
<> 149:156823d33999 765 {
<> 149:156823d33999 766 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
<> 149:156823d33999 767 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 768 // FIXME: Premature abort???
<> 149:156823d33999 769 return (obj->tx_buff.pos == obj->tx_buff.length);
<> 149:156823d33999 770 }
<> 149:156823d33999 771
<> 149:156823d33999 772 static int serial_is_rx_complete(serial_t *obj)
<> 149:156823d33999 773 {
<> 149:156823d33999 774 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 775 return (obj->rx_buff.pos == obj->rx_buff.length);
<> 149:156823d33999 776 }
<> 149:156823d33999 777
<> 149:156823d33999 778 static uint32_t serial_tx_event_check(serial_t *obj)
<> 149:156823d33999 779 {
<> 149:156823d33999 780 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 781
<> 149:156823d33999 782 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 149:156823d33999 783 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 149:156823d33999 784 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 785 }
<> 149:156823d33999 786
<> 149:156823d33999 787 uint32_t event = 0;
<> 149:156823d33999 788
<> 149:156823d33999 789 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 149:156823d33999 790 serial_write_async(obj);
<> 149:156823d33999 791 }
<> 149:156823d33999 792
<> 149:156823d33999 793 if (serial_is_tx_complete(obj)) {
<> 149:156823d33999 794 event |= SERIAL_EVENT_TX_COMPLETE;
<> 149:156823d33999 795 }
<> 149:156823d33999 796
<> 149:156823d33999 797 return event;
<> 149:156823d33999 798 }
<> 149:156823d33999 799
<> 149:156823d33999 800 static uint32_t serial_rx_event_check(serial_t *obj)
<> 149:156823d33999 801 {
<> 149:156823d33999 802 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 803
<> 149:156823d33999 804 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 149:156823d33999 805 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 149:156823d33999 806 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 807 }
<> 149:156823d33999 808
<> 149:156823d33999 809 uint32_t event = 0;
<> 149:156823d33999 810
<> 149:156823d33999 811 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
<> 149:156823d33999 812 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
<> 149:156823d33999 813 }
<> 149:156823d33999 814 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
<> 149:156823d33999 815 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
<> 149:156823d33999 816 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
<> 149:156823d33999 817 }
<> 149:156823d33999 818 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
<> 149:156823d33999 819 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
<> 149:156823d33999 820 event |= SERIAL_EVENT_RX_PARITY_ERROR;
<> 149:156823d33999 821 }
<> 149:156823d33999 822
<> 149:156823d33999 823 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
<> 149:156823d33999 824 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
<> 149:156823d33999 825 event |= SERIAL_EVENT_RX_OVERFLOW;
<> 149:156823d33999 826 }
<> 149:156823d33999 827
<> 149:156823d33999 828 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 149:156823d33999 829 serial_read_async(obj);
<> 149:156823d33999 830 }
<> 149:156823d33999 831
<> 149:156823d33999 832 if (serial_is_rx_complete(obj)) {
<> 149:156823d33999 833 event |= SERIAL_EVENT_RX_COMPLETE;
<> 149:156823d33999 834 }
<> 149:156823d33999 835 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
<> 149:156823d33999 836 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
<> 149:156823d33999 837 // FIXME: Timing to reset char_found?
<> 149:156823d33999 838 //obj->char_found = 0;
<> 149:156823d33999 839 }
<> 149:156823d33999 840
<> 149:156823d33999 841 return event;
<> 149:156823d33999 842 }
<> 149:156823d33999 843
<> 149:156823d33999 844 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 845 {
<> 149:156823d33999 846 serial_t *obj = (serial_t *) id;
<> 149:156823d33999 847
<> 149:156823d33999 848 // FIXME: Pass this error to caller
<> 149:156823d33999 849 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 850 }
<> 149:156823d33999 851 // Expect UART IRQ will catch this transfer done event
<> 149:156823d33999 852 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 853 obj->tx_buff.pos = obj->tx_buff.length;
<> 149:156823d33999 854 }
<> 149:156823d33999 855 // FIXME: Pass this error to caller
<> 149:156823d33999 856 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 857 }
<> 149:156823d33999 858
<> 149:156823d33999 859 uart_irq_async(obj);
<> 149:156823d33999 860 }
<> 149:156823d33999 861
<> 149:156823d33999 862 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 863 {
<> 149:156823d33999 864 serial_t *obj = (serial_t *) id;
<> 149:156823d33999 865
<> 149:156823d33999 866 // FIXME: Pass this error to caller
<> 149:156823d33999 867 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 868 }
<> 149:156823d33999 869 // Expect UART IRQ will catch this transfer done event
<> 149:156823d33999 870 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 871 obj->rx_buff.pos = obj->rx_buff.length;
<> 149:156823d33999 872 }
<> 149:156823d33999 873 // FIXME: Pass this error to caller
<> 149:156823d33999 874 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 875 }
<> 149:156823d33999 876
<> 149:156823d33999 877 uart_irq_async(obj);
<> 149:156823d33999 878 }
<> 149:156823d33999 879
<> 149:156823d33999 880 static int serial_write_async(serial_t *obj)
<> 149:156823d33999 881 {
<> 149:156823d33999 882 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 883 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 884 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 885
<> 149:156823d33999 886 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 887
<> 149:156823d33999 888 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
<> 149:156823d33999 889 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
<> 149:156823d33999 890 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
<> 149:156823d33999 891 tx_fifo_busy = tx_fifo_max;
<> 149:156823d33999 892 }
<> 149:156823d33999 893 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
<> 149:156823d33999 894 if (tx_fifo_free == 0) {
<> 149:156823d33999 895 // Simulate clear of the interrupt flag
<> 149:156823d33999 896 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 897 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 898 }
<> 149:156823d33999 899 return 0;
<> 149:156823d33999 900 }
<> 149:156823d33999 901
<> 149:156823d33999 902 uint32_t bytes_per_word = obj->tx_buff.width / 8;
<> 149:156823d33999 903
<> 149:156823d33999 904 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
<> 149:156823d33999 905 int n_words = 0;
<> 149:156823d33999 906 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
<> 149:156823d33999 907 switch (bytes_per_word) {
<> 149:156823d33999 908 case 4:
<> 149:156823d33999 909 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 910 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 911 case 2:
<> 149:156823d33999 912 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 913 case 1:
<> 149:156823d33999 914 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 915 }
<> 149:156823d33999 916
<> 149:156823d33999 917 n_words ++;
<> 149:156823d33999 918 tx_fifo_free -= bytes_per_word;
<> 149:156823d33999 919 obj->tx_buff.pos ++;
<> 149:156823d33999 920 }
<> 149:156823d33999 921
<> 149:156823d33999 922 if (n_words) {
<> 149:156823d33999 923 // Simulate clear of the interrupt flag
<> 149:156823d33999 924 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 925 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 926 }
<> 149:156823d33999 927 }
<> 149:156823d33999 928
<> 149:156823d33999 929 return n_words;
<> 149:156823d33999 930 }
<> 149:156823d33999 931
<> 149:156823d33999 932 static int serial_read_async(serial_t *obj)
<> 149:156823d33999 933 {
<> 149:156823d33999 934 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 935 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 936 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 937
<> 149:156823d33999 938 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
<> 149:156823d33999 939 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
<> 149:156823d33999 940 //if (rx_fifo_free == 0) {
<> 149:156823d33999 941 // return 0;
<> 149:156823d33999 942 //}
<> 149:156823d33999 943
<> 149:156823d33999 944 uint32_t bytes_per_word = obj->rx_buff.width / 8;
<> 149:156823d33999 945
<> 149:156823d33999 946 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
<> 149:156823d33999 947 int n_words = 0;
<> 149:156823d33999 948 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
<> 149:156823d33999 949 switch (bytes_per_word) {
<> 149:156823d33999 950 case 4:
<> 149:156823d33999 951 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 952 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 953 case 2:
<> 149:156823d33999 954 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 955 case 1:
<> 149:156823d33999 956 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 957 }
<> 149:156823d33999 958
<> 149:156823d33999 959 n_words ++;
<> 149:156823d33999 960 rx_fifo_busy -= bytes_per_word;
<> 149:156823d33999 961 obj->rx_buff.pos ++;
<> 149:156823d33999 962
<> 149:156823d33999 963 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 149:156823d33999 964 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 149:156823d33999 965 uint8_t *rx_cmp = rx;
<> 149:156823d33999 966 switch (bytes_per_word) {
<> 149:156823d33999 967 case 4:
<> 149:156823d33999 968 rx_cmp -= 2;
<> 149:156823d33999 969 case 2:
<> 149:156823d33999 970 rx_cmp --;
<> 149:156823d33999 971 case 1:
<> 149:156823d33999 972 rx_cmp --;
<> 149:156823d33999 973 }
<> 149:156823d33999 974 if (*rx_cmp == obj->char_match) {
<> 149:156823d33999 975 obj->char_found = 1;
<> 149:156823d33999 976 break;
<> 149:156823d33999 977 }
<> 149:156823d33999 978 }
<> 149:156823d33999 979 }
<> 149:156823d33999 980
<> 149:156823d33999 981 if (n_words) {
<> 149:156823d33999 982 // Simulate clear of the interrupt flag
<> 149:156823d33999 983 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 984 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 985 }
<> 149:156823d33999 986 }
<> 149:156823d33999 987
<> 149:156823d33999 988 return n_words;
<> 149:156823d33999 989 }
<> 149:156823d33999 990
<> 149:156823d33999 991 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
<> 149:156823d33999 992 {
<> 149:156823d33999 993 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 994 obj->tx_buff.length = length;
<> 149:156823d33999 995 obj->tx_buff.pos = 0;
<> 149:156823d33999 996 obj->tx_buff.width = width;
<> 149:156823d33999 997 }
<> 149:156823d33999 998
<> 149:156823d33999 999 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
<> 149:156823d33999 1000 {
<> 149:156823d33999 1001 obj->rx_buff.buffer = rx;
<> 149:156823d33999 1002 obj->rx_buff.length = length;
<> 149:156823d33999 1003 obj->rx_buff.pos = 0;
<> 149:156823d33999 1004 obj->rx_buff.width = width;
<> 149:156823d33999 1005 }
<> 149:156823d33999 1006
<> 149:156823d33999 1007 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 1008 {
<> 149:156823d33999 1009 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 1010 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1011 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 1012
<> 149:156823d33999 1013 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1014 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 1015 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1016 obj->serial.vec = var->vec_async;
<> 149:156823d33999 1017 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
AnnaBridge 165:e614a9f1c9e2 1018 serial_enable_interrupt(obj, TxIrq, enable);
<> 149:156823d33999 1019 }
<> 149:156823d33999 1020
<> 149:156823d33999 1021 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 1022 {
<> 149:156823d33999 1023 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 1024 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1025 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 1026
<> 149:156823d33999 1027 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1028 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 1029 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1030 obj->serial.vec = var->vec_async;
<> 149:156823d33999 1031 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
AnnaBridge 165:e614a9f1c9e2 1032 serial_enable_interrupt(obj, RxIrq, enable);
AnnaBridge 165:e614a9f1c9e2 1033 }
AnnaBridge 165:e614a9f1c9e2 1034
AnnaBridge 165:e614a9f1c9e2 1035 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
AnnaBridge 165:e614a9f1c9e2 1036 {
AnnaBridge 165:e614a9f1c9e2 1037 if (enable) {
AnnaBridge 165:e614a9f1c9e2 1038 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1039 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1040 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1041
AnnaBridge 165:e614a9f1c9e2 1042 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
AnnaBridge 165:e614a9f1c9e2 1043 NVIC_EnableIRQ(modinit->irq_n);
AnnaBridge 165:e614a9f1c9e2 1044
AnnaBridge 165:e614a9f1c9e2 1045 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1046 // Multiple serial S/W objects for single UART H/W module possibly.
AnnaBridge 165:e614a9f1c9e2 1047 // Bind serial S/W object to UART H/W module as interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1048 var->obj = obj;
AnnaBridge 165:e614a9f1c9e2 1049
AnnaBridge 165:e614a9f1c9e2 1050 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1051 // NOTE: Setting inten_msk first to avoid race condition
AnnaBridge 165:e614a9f1c9e2 1052 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1053 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1054 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1055 break;
AnnaBridge 165:e614a9f1c9e2 1056 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1057 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1058 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1059 break;
AnnaBridge 165:e614a9f1c9e2 1060 }
AnnaBridge 165:e614a9f1c9e2 1061 }
AnnaBridge 165:e614a9f1c9e2 1062 else { // disable
AnnaBridge 165:e614a9f1c9e2 1063 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1064 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1065 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1066 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1067 break;
AnnaBridge 165:e614a9f1c9e2 1068 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1069 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1070 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1071 break;
AnnaBridge 165:e614a9f1c9e2 1072 }
AnnaBridge 165:e614a9f1c9e2 1073 }
AnnaBridge 165:e614a9f1c9e2 1074 }
AnnaBridge 165:e614a9f1c9e2 1075
AnnaBridge 165:e614a9f1c9e2 1076 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
AnnaBridge 165:e614a9f1c9e2 1077 {
AnnaBridge 165:e614a9f1c9e2 1078 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1079 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1080 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1081
AnnaBridge 165:e614a9f1c9e2 1082 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1083
AnnaBridge 165:e614a9f1c9e2 1084 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 1085 serial_enable_interrupt(obj, irq, obj->serial.irq_en);
<> 149:156823d33999 1086 }
<> 149:156823d33999 1087
<> 149:156823d33999 1088 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
<> 149:156823d33999 1089 {
<> 149:156823d33999 1090 if (*dma_usage != DMA_USAGE_NEVER) {
<> 149:156823d33999 1091 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 1092 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
<> 149:156823d33999 1093 }
<> 149:156823d33999 1094 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 1095 *dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 1096 }
<> 149:156823d33999 1097 }
<> 149:156823d33999 1098 else {
<> 149:156823d33999 1099 dma_channel_free(*dma_ch);
<> 149:156823d33999 1100 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 1101 }
<> 149:156823d33999 1102 }
<> 149:156823d33999 1103
<> 149:156823d33999 1104 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
<> 149:156823d33999 1105 {
<> 149:156823d33999 1106 int inten_msk = 0;
<> 149:156823d33999 1107
<> 149:156823d33999 1108 switch (irq) {
<> 149:156823d33999 1109 case RxIrq:
<> 149:156823d33999 1110 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 149:156823d33999 1111 break;
<> 149:156823d33999 1112 case TxIrq:
<> 149:156823d33999 1113 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
<> 149:156823d33999 1114 break;
<> 149:156823d33999 1115 }
<> 149:156823d33999 1116
<> 149:156823d33999 1117 return !! inten_msk;
<> 149:156823d33999 1118 }
<> 149:156823d33999 1119
<> 149:156823d33999 1120 #endif // #if DEVICE_SERIAL_ASYNCH
AnnaBridge 188:bcfe06ba3d64 1121
AnnaBridge 188:bcfe06ba3d64 1122 bool serial_can_deep_sleep(void)
AnnaBridge 188:bcfe06ba3d64 1123 {
AnnaBridge 188:bcfe06ba3d64 1124 bool sleep_allowed = 1;
AnnaBridge 188:bcfe06ba3d64 1125 const struct nu_modinit_s *modinit = uart_modinit_tab;
AnnaBridge 188:bcfe06ba3d64 1126 while (modinit->var != NULL) {
AnnaBridge 188:bcfe06ba3d64 1127 struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
AnnaBridge 188:bcfe06ba3d64 1128 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
AnnaBridge 188:bcfe06ba3d64 1129 if (uart_var->ref_cnt > 0) {
AnnaBridge 188:bcfe06ba3d64 1130 if (!UART_IS_TX_EMPTY(uart_base)) {
AnnaBridge 188:bcfe06ba3d64 1131 sleep_allowed = 0;
AnnaBridge 188:bcfe06ba3d64 1132 break;
AnnaBridge 188:bcfe06ba3d64 1133 }
AnnaBridge 188:bcfe06ba3d64 1134 }
AnnaBridge 188:bcfe06ba3d64 1135 modinit++;
AnnaBridge 188:bcfe06ba3d64 1136 }
AnnaBridge 188:bcfe06ba3d64 1137 return sleep_allowed;
AnnaBridge 188:bcfe06ba3d64 1138 }
AnnaBridge 188:bcfe06ba3d64 1139
<> 149:156823d33999 1140 #endif // #if DEVICE_SERIAL