mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_NUVOTON/TARGET_M2351/spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 187:0387e8f68319
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 187:0387e8f68319 | 1 | /* mbed Microcontroller Library |
AnnaBridge | 187:0387e8f68319 | 2 | * Copyright (c) 2015-2016 Nuvoton |
AnnaBridge | 187:0387e8f68319 | 3 | * |
AnnaBridge | 187:0387e8f68319 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
AnnaBridge | 187:0387e8f68319 | 5 | * you may not use this file except in compliance with the License. |
AnnaBridge | 187:0387e8f68319 | 6 | * You may obtain a copy of the License at |
AnnaBridge | 187:0387e8f68319 | 7 | * |
AnnaBridge | 187:0387e8f68319 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 187:0387e8f68319 | 9 | * |
AnnaBridge | 187:0387e8f68319 | 10 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 187:0387e8f68319 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
AnnaBridge | 187:0387e8f68319 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 187:0387e8f68319 | 13 | * See the License for the specific language governing permissions and |
AnnaBridge | 187:0387e8f68319 | 14 | * limitations under the License. |
AnnaBridge | 187:0387e8f68319 | 15 | */ |
AnnaBridge | 187:0387e8f68319 | 16 | |
AnnaBridge | 187:0387e8f68319 | 17 | #include "spi_api.h" |
AnnaBridge | 187:0387e8f68319 | 18 | |
AnnaBridge | 187:0387e8f68319 | 19 | #if DEVICE_SPI |
AnnaBridge | 187:0387e8f68319 | 20 | |
AnnaBridge | 187:0387e8f68319 | 21 | #include "cmsis.h" |
AnnaBridge | 187:0387e8f68319 | 22 | #include "mbed_error.h" |
AnnaBridge | 187:0387e8f68319 | 23 | #include "pinmap.h" |
AnnaBridge | 187:0387e8f68319 | 24 | #include "PeripheralPins.h" |
AnnaBridge | 187:0387e8f68319 | 25 | #include "nu_modutil.h" |
AnnaBridge | 187:0387e8f68319 | 26 | #include "nu_miscutil.h" |
AnnaBridge | 187:0387e8f68319 | 27 | #include "nu_bitutil.h" |
AnnaBridge | 187:0387e8f68319 | 28 | |
AnnaBridge | 187:0387e8f68319 | 29 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 30 | #include "dma_api.h" |
AnnaBridge | 187:0387e8f68319 | 31 | #include "dma.h" |
AnnaBridge | 187:0387e8f68319 | 32 | #endif |
AnnaBridge | 187:0387e8f68319 | 33 | |
AnnaBridge | 187:0387e8f68319 | 34 | #define NU_SPI_FRAME_MIN 8 |
AnnaBridge | 187:0387e8f68319 | 35 | #define NU_SPI_FRAME_MAX 32 |
AnnaBridge | 187:0387e8f68319 | 36 | |
AnnaBridge | 187:0387e8f68319 | 37 | struct nu_spi_var { |
AnnaBridge | 187:0387e8f68319 | 38 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 39 | uint8_t pdma_perp_tx; |
AnnaBridge | 187:0387e8f68319 | 40 | uint8_t pdma_perp_rx; |
AnnaBridge | 187:0387e8f68319 | 41 | #endif |
AnnaBridge | 187:0387e8f68319 | 42 | }; |
AnnaBridge | 187:0387e8f68319 | 43 | |
AnnaBridge | 187:0387e8f68319 | 44 | static struct nu_spi_var spi0_var = { |
AnnaBridge | 187:0387e8f68319 | 45 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 46 | .pdma_perp_tx = PDMA_SPI0_TX, |
AnnaBridge | 187:0387e8f68319 | 47 | .pdma_perp_rx = PDMA_SPI0_RX |
AnnaBridge | 187:0387e8f68319 | 48 | #endif |
AnnaBridge | 187:0387e8f68319 | 49 | }; |
AnnaBridge | 187:0387e8f68319 | 50 | static struct nu_spi_var spi1_var = { |
AnnaBridge | 187:0387e8f68319 | 51 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 52 | .pdma_perp_tx = PDMA_SPI1_TX, |
AnnaBridge | 187:0387e8f68319 | 53 | .pdma_perp_rx = PDMA_SPI1_RX |
AnnaBridge | 187:0387e8f68319 | 54 | #endif |
AnnaBridge | 187:0387e8f68319 | 55 | }; |
AnnaBridge | 187:0387e8f68319 | 56 | static struct nu_spi_var spi2_var = { |
AnnaBridge | 187:0387e8f68319 | 57 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 58 | .pdma_perp_tx = PDMA_SPI2_TX, |
AnnaBridge | 187:0387e8f68319 | 59 | .pdma_perp_rx = PDMA_SPI2_RX |
AnnaBridge | 187:0387e8f68319 | 60 | #endif |
AnnaBridge | 187:0387e8f68319 | 61 | }; |
AnnaBridge | 187:0387e8f68319 | 62 | static struct nu_spi_var spi3_var = { |
AnnaBridge | 187:0387e8f68319 | 63 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 64 | .pdma_perp_tx = PDMA_SPI3_TX, |
AnnaBridge | 187:0387e8f68319 | 65 | .pdma_perp_rx = PDMA_SPI3_RX |
AnnaBridge | 187:0387e8f68319 | 66 | #endif |
AnnaBridge | 187:0387e8f68319 | 67 | }; |
AnnaBridge | 187:0387e8f68319 | 68 | static struct nu_spi_var spi5_var = { |
AnnaBridge | 187:0387e8f68319 | 69 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 70 | .pdma_perp_tx = PDMA_SPI5_TX, |
AnnaBridge | 187:0387e8f68319 | 71 | .pdma_perp_rx = PDMA_SPI5_RX |
AnnaBridge | 187:0387e8f68319 | 72 | #endif |
AnnaBridge | 187:0387e8f68319 | 73 | }; |
AnnaBridge | 187:0387e8f68319 | 74 | |
AnnaBridge | 187:0387e8f68319 | 75 | /* Synchronous version of SPI_ENABLE()/SPI_DISABLE() macros |
AnnaBridge | 187:0387e8f68319 | 76 | * |
AnnaBridge | 187:0387e8f68319 | 77 | * The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI |
AnnaBridge | 187:0387e8f68319 | 78 | * control logic is enabled/disabled, this bit indicates the real status of SPI controller. |
AnnaBridge | 187:0387e8f68319 | 79 | * |
AnnaBridge | 187:0387e8f68319 | 80 | * NOTE: All configurations shall be ready before calling SPI_ENABLE_SYNC(). |
AnnaBridge | 187:0387e8f68319 | 81 | * NOTE: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, |
AnnaBridge | 187:0387e8f68319 | 82 | * user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0 |
AnnaBridge | 187:0387e8f68319 | 83 | * (by SPI_DISABLE_SYNC here). |
AnnaBridge | 187:0387e8f68319 | 84 | */ |
AnnaBridge | 187:0387e8f68319 | 85 | __STATIC_INLINE void SPI_ENABLE_SYNC(SPI_T *spi_base) |
AnnaBridge | 187:0387e8f68319 | 86 | { |
AnnaBridge | 187:0387e8f68319 | 87 | if (! (spi_base->CTL & SPI_CTL_SPIEN_Msk)) { |
AnnaBridge | 187:0387e8f68319 | 88 | SPI_ENABLE(spi_base); |
AnnaBridge | 187:0387e8f68319 | 89 | } |
AnnaBridge | 187:0387e8f68319 | 90 | while (! (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk)); |
AnnaBridge | 187:0387e8f68319 | 91 | } |
AnnaBridge | 187:0387e8f68319 | 92 | __STATIC_INLINE void SPI_DISABLE_SYNC(SPI_T *spi_base) |
AnnaBridge | 187:0387e8f68319 | 93 | { |
AnnaBridge | 187:0387e8f68319 | 94 | if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { |
AnnaBridge | 187:0387e8f68319 | 95 | // NOTE: SPI H/W may get out of state without the busy check. |
AnnaBridge | 187:0387e8f68319 | 96 | while (SPI_IS_BUSY(spi_base)); |
AnnaBridge | 187:0387e8f68319 | 97 | |
AnnaBridge | 187:0387e8f68319 | 98 | SPI_DISABLE(spi_base); |
AnnaBridge | 187:0387e8f68319 | 99 | } |
AnnaBridge | 187:0387e8f68319 | 100 | while (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk); |
AnnaBridge | 187:0387e8f68319 | 101 | } |
AnnaBridge | 187:0387e8f68319 | 102 | |
AnnaBridge | 187:0387e8f68319 | 103 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 104 | static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable); |
AnnaBridge | 187:0387e8f68319 | 105 | static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable); |
AnnaBridge | 187:0387e8f68319 | 106 | static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit); |
AnnaBridge | 187:0387e8f68319 | 107 | static uint32_t spi_master_read_asynch(spi_t *obj); |
AnnaBridge | 187:0387e8f68319 | 108 | static uint32_t spi_event_check(spi_t *obj); |
AnnaBridge | 187:0387e8f68319 | 109 | static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable); |
AnnaBridge | 187:0387e8f68319 | 110 | static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); |
AnnaBridge | 187:0387e8f68319 | 111 | static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx); |
AnnaBridge | 187:0387e8f68319 | 112 | static uint8_t spi_get_data_width(spi_t *obj); |
AnnaBridge | 187:0387e8f68319 | 113 | static int spi_is_tx_complete(spi_t *obj); |
AnnaBridge | 187:0387e8f68319 | 114 | static int spi_is_rx_complete(spi_t *obj); |
AnnaBridge | 187:0387e8f68319 | 115 | static int spi_writeable(spi_t * obj); |
AnnaBridge | 187:0387e8f68319 | 116 | static int spi_readable(spi_t * obj); |
AnnaBridge | 187:0387e8f68319 | 117 | static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma); |
AnnaBridge | 187:0387e8f68319 | 118 | static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma); |
AnnaBridge | 187:0387e8f68319 | 119 | static uint32_t spi_fifo_depth(spi_t *obj); |
AnnaBridge | 187:0387e8f68319 | 120 | #endif |
AnnaBridge | 187:0387e8f68319 | 121 | |
AnnaBridge | 187:0387e8f68319 | 122 | static uint32_t spi_modinit_mask = 0; |
AnnaBridge | 187:0387e8f68319 | 123 | |
AnnaBridge | 187:0387e8f68319 | 124 | static const struct nu_modinit_s spi_modinit_tab[] = { |
AnnaBridge | 187:0387e8f68319 | 125 | {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var}, |
AnnaBridge | 187:0387e8f68319 | 126 | {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var}, |
AnnaBridge | 187:0387e8f68319 | 127 | {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK1, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var}, |
AnnaBridge | 187:0387e8f68319 | 128 | {SPI_3, SPI3_MODULE, CLK_CLKSEL2_SPI3SEL_PCLK0, MODULE_NoMsk, SPI3_RST, SPI3_IRQn, &spi3_var}, |
AnnaBridge | 187:0387e8f68319 | 129 | {SPI_5, SPI5_MODULE, CLK_CLKSEL2_SPI5SEL_PCLK1, MODULE_NoMsk, SPI5_RST, SPI5_IRQn, &spi5_var}, |
AnnaBridge | 187:0387e8f68319 | 130 | |
AnnaBridge | 187:0387e8f68319 | 131 | {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} |
AnnaBridge | 187:0387e8f68319 | 132 | }; |
AnnaBridge | 187:0387e8f68319 | 133 | |
AnnaBridge | 187:0387e8f68319 | 134 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) |
AnnaBridge | 187:0387e8f68319 | 135 | { |
AnnaBridge | 187:0387e8f68319 | 136 | // Determine which SPI_x the pins are used for |
AnnaBridge | 187:0387e8f68319 | 137 | uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
AnnaBridge | 187:0387e8f68319 | 138 | uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); |
AnnaBridge | 187:0387e8f68319 | 139 | uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
AnnaBridge | 187:0387e8f68319 | 140 | uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
AnnaBridge | 187:0387e8f68319 | 141 | uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); |
AnnaBridge | 187:0387e8f68319 | 142 | uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); |
AnnaBridge | 187:0387e8f68319 | 143 | obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl); |
AnnaBridge | 187:0387e8f68319 | 144 | MBED_ASSERT((int)obj->spi.spi != NC); |
AnnaBridge | 187:0387e8f68319 | 145 | |
AnnaBridge | 187:0387e8f68319 | 146 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 147 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 148 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 149 | |
AnnaBridge | 187:0387e8f68319 | 150 | /* Reset module |
AnnaBridge | 187:0387e8f68319 | 151 | * |
AnnaBridge | 187:0387e8f68319 | 152 | * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. |
AnnaBridge | 187:0387e8f68319 | 153 | */ |
AnnaBridge | 187:0387e8f68319 | 154 | SYS_ResetModule_S(modinit->rsetidx); |
AnnaBridge | 187:0387e8f68319 | 155 | |
AnnaBridge | 187:0387e8f68319 | 156 | /* Select IP clock source |
AnnaBridge | 187:0387e8f68319 | 157 | * |
AnnaBridge | 187:0387e8f68319 | 158 | * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. |
AnnaBridge | 187:0387e8f68319 | 159 | */ |
AnnaBridge | 187:0387e8f68319 | 160 | CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); |
AnnaBridge | 187:0387e8f68319 | 161 | |
AnnaBridge | 187:0387e8f68319 | 162 | /* Enable IP clock |
AnnaBridge | 187:0387e8f68319 | 163 | * |
AnnaBridge | 187:0387e8f68319 | 164 | * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. |
AnnaBridge | 187:0387e8f68319 | 165 | */ |
AnnaBridge | 187:0387e8f68319 | 166 | CLK_EnableModuleClock_S(modinit->clkidx); |
AnnaBridge | 187:0387e8f68319 | 167 | |
AnnaBridge | 187:0387e8f68319 | 168 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
AnnaBridge | 187:0387e8f68319 | 169 | pinmap_pinout(miso, PinMap_SPI_MISO); |
AnnaBridge | 187:0387e8f68319 | 170 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
AnnaBridge | 187:0387e8f68319 | 171 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
AnnaBridge | 187:0387e8f68319 | 172 | |
AnnaBridge | 187:0387e8f68319 | 173 | obj->spi.pin_mosi = mosi; |
AnnaBridge | 187:0387e8f68319 | 174 | obj->spi.pin_miso = miso; |
AnnaBridge | 187:0387e8f68319 | 175 | obj->spi.pin_sclk = sclk; |
AnnaBridge | 187:0387e8f68319 | 176 | obj->spi.pin_ssel = ssel; |
AnnaBridge | 187:0387e8f68319 | 177 | |
AnnaBridge | 187:0387e8f68319 | 178 | |
AnnaBridge | 187:0387e8f68319 | 179 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 180 | obj->spi.dma_usage = DMA_USAGE_NEVER; |
AnnaBridge | 187:0387e8f68319 | 181 | obj->spi.event = 0; |
AnnaBridge | 187:0387e8f68319 | 182 | obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 183 | obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 184 | |
AnnaBridge | 187:0387e8f68319 | 185 | /* NOTE: We use vector to judge if asynchronous transfer is on-going (spi_active). |
AnnaBridge | 187:0387e8f68319 | 186 | * At initial time, asynchronous transfer is not on-going and so vector must |
AnnaBridge | 187:0387e8f68319 | 187 | * be cleared to zero for correct judgement. */ |
AnnaBridge | 187:0387e8f68319 | 188 | NVIC_SetVector(modinit->irq_n, 0); |
AnnaBridge | 187:0387e8f68319 | 189 | #endif |
AnnaBridge | 187:0387e8f68319 | 190 | |
AnnaBridge | 187:0387e8f68319 | 191 | // Mark this module to be inited. |
AnnaBridge | 187:0387e8f68319 | 192 | int i = modinit - spi_modinit_tab; |
AnnaBridge | 187:0387e8f68319 | 193 | spi_modinit_mask |= 1 << i; |
AnnaBridge | 187:0387e8f68319 | 194 | } |
AnnaBridge | 187:0387e8f68319 | 195 | |
AnnaBridge | 187:0387e8f68319 | 196 | void spi_free(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 197 | { |
AnnaBridge | 187:0387e8f68319 | 198 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 199 | if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 200 | dma_channel_free(obj->spi.dma_chn_id_tx); |
AnnaBridge | 187:0387e8f68319 | 201 | obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 202 | } |
AnnaBridge | 187:0387e8f68319 | 203 | if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 204 | dma_channel_free(obj->spi.dma_chn_id_rx); |
AnnaBridge | 187:0387e8f68319 | 205 | obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 206 | } |
AnnaBridge | 187:0387e8f68319 | 207 | #endif |
AnnaBridge | 187:0387e8f68319 | 208 | |
AnnaBridge | 187:0387e8f68319 | 209 | SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi)); |
AnnaBridge | 187:0387e8f68319 | 210 | |
AnnaBridge | 187:0387e8f68319 | 211 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 212 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 213 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 214 | |
AnnaBridge | 187:0387e8f68319 | 215 | SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK)); |
AnnaBridge | 187:0387e8f68319 | 216 | NVIC_DisableIRQ(modinit->irq_n); |
AnnaBridge | 187:0387e8f68319 | 217 | |
AnnaBridge | 187:0387e8f68319 | 218 | /* Disable IP clock |
AnnaBridge | 187:0387e8f68319 | 219 | * |
AnnaBridge | 187:0387e8f68319 | 220 | * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. |
AnnaBridge | 187:0387e8f68319 | 221 | */ |
AnnaBridge | 187:0387e8f68319 | 222 | CLK_DisableModuleClock_S(modinit->clkidx); |
AnnaBridge | 187:0387e8f68319 | 223 | |
AnnaBridge | 187:0387e8f68319 | 224 | // Mark this module to be deinited. |
AnnaBridge | 187:0387e8f68319 | 225 | int i = modinit - spi_modinit_tab; |
AnnaBridge | 187:0387e8f68319 | 226 | spi_modinit_mask &= ~(1 << i); |
AnnaBridge | 187:0387e8f68319 | 227 | } |
AnnaBridge | 187:0387e8f68319 | 228 | |
AnnaBridge | 187:0387e8f68319 | 229 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
AnnaBridge | 187:0387e8f68319 | 230 | { |
AnnaBridge | 187:0387e8f68319 | 231 | MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX); |
AnnaBridge | 187:0387e8f68319 | 232 | |
AnnaBridge | 187:0387e8f68319 | 233 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 234 | |
AnnaBridge | 187:0387e8f68319 | 235 | SPI_DISABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 236 | |
AnnaBridge | 187:0387e8f68319 | 237 | SPI_Open(spi_base, |
AnnaBridge | 187:0387e8f68319 | 238 | slave ? SPI_SLAVE : SPI_MASTER, |
AnnaBridge | 187:0387e8f68319 | 239 | (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3, |
AnnaBridge | 187:0387e8f68319 | 240 | bits, |
AnnaBridge | 187:0387e8f68319 | 241 | SPI_GetBusClock(spi_base)); |
AnnaBridge | 187:0387e8f68319 | 242 | // NOTE: Hardcode to be MSB first. |
AnnaBridge | 187:0387e8f68319 | 243 | SPI_SET_MSB_FIRST(spi_base); |
AnnaBridge | 187:0387e8f68319 | 244 | |
AnnaBridge | 187:0387e8f68319 | 245 | if (! slave) { |
AnnaBridge | 187:0387e8f68319 | 246 | // Master |
AnnaBridge | 187:0387e8f68319 | 247 | if (obj->spi.pin_ssel != NC) { |
AnnaBridge | 187:0387e8f68319 | 248 | // Configure SS as low active. |
AnnaBridge | 187:0387e8f68319 | 249 | SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW); |
AnnaBridge | 187:0387e8f68319 | 250 | } else { |
AnnaBridge | 187:0387e8f68319 | 251 | SPI_DisableAutoSS(spi_base); |
AnnaBridge | 187:0387e8f68319 | 252 | } |
AnnaBridge | 187:0387e8f68319 | 253 | } else { |
AnnaBridge | 187:0387e8f68319 | 254 | // Slave |
AnnaBridge | 187:0387e8f68319 | 255 | // Configure SS as low active. |
AnnaBridge | 187:0387e8f68319 | 256 | spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk; |
AnnaBridge | 187:0387e8f68319 | 257 | } |
AnnaBridge | 187:0387e8f68319 | 258 | |
AnnaBridge | 187:0387e8f68319 | 259 | /* NOTE: M451's/M480's/M2351's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). |
AnnaBridge | 187:0387e8f68319 | 260 | * We cannot use SPI_CTL_SPIEN_Msk for judgement of spi_active(). |
AnnaBridge | 187:0387e8f68319 | 261 | * Judge with vector instead. */ |
AnnaBridge | 187:0387e8f68319 | 262 | } |
AnnaBridge | 187:0387e8f68319 | 263 | |
AnnaBridge | 187:0387e8f68319 | 264 | void spi_frequency(spi_t *obj, int hz) |
AnnaBridge | 187:0387e8f68319 | 265 | { |
AnnaBridge | 187:0387e8f68319 | 266 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 267 | |
AnnaBridge | 187:0387e8f68319 | 268 | SPI_DISABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 269 | |
AnnaBridge | 187:0387e8f68319 | 270 | SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz); |
AnnaBridge | 187:0387e8f68319 | 271 | } |
AnnaBridge | 187:0387e8f68319 | 272 | |
AnnaBridge | 187:0387e8f68319 | 273 | |
AnnaBridge | 187:0387e8f68319 | 274 | int spi_master_write(spi_t *obj, int value) |
AnnaBridge | 187:0387e8f68319 | 275 | { |
AnnaBridge | 187:0387e8f68319 | 276 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 277 | |
AnnaBridge | 187:0387e8f68319 | 278 | // NOTE: Data in receive FIFO can be read out via ICE. |
AnnaBridge | 187:0387e8f68319 | 279 | SPI_ENABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 280 | |
AnnaBridge | 187:0387e8f68319 | 281 | // Wait for tx buffer empty |
AnnaBridge | 187:0387e8f68319 | 282 | while(! spi_writeable(obj)); |
AnnaBridge | 187:0387e8f68319 | 283 | SPI_WRITE_TX(spi_base, value); |
AnnaBridge | 187:0387e8f68319 | 284 | |
AnnaBridge | 187:0387e8f68319 | 285 | // Wait for rx buffer full |
AnnaBridge | 187:0387e8f68319 | 286 | while (! spi_readable(obj)); |
AnnaBridge | 187:0387e8f68319 | 287 | int value2 = SPI_READ_RX(spi_base); |
AnnaBridge | 187:0387e8f68319 | 288 | |
AnnaBridge | 187:0387e8f68319 | 289 | /* We don't call SPI_DISABLE_SYNC here for performance. */ |
AnnaBridge | 187:0387e8f68319 | 290 | |
AnnaBridge | 187:0387e8f68319 | 291 | return value2; |
AnnaBridge | 187:0387e8f68319 | 292 | } |
AnnaBridge | 187:0387e8f68319 | 293 | |
AnnaBridge | 187:0387e8f68319 | 294 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, |
AnnaBridge | 187:0387e8f68319 | 295 | char *rx_buffer, int rx_length, char write_fill) { |
AnnaBridge | 187:0387e8f68319 | 296 | int total = (tx_length > rx_length) ? tx_length : rx_length; |
AnnaBridge | 187:0387e8f68319 | 297 | |
AnnaBridge | 187:0387e8f68319 | 298 | for (int i = 0; i < total; i++) { |
AnnaBridge | 187:0387e8f68319 | 299 | char out = (i < tx_length) ? tx_buffer[i] : write_fill; |
AnnaBridge | 187:0387e8f68319 | 300 | char in = spi_master_write(obj, out); |
AnnaBridge | 187:0387e8f68319 | 301 | if (i < rx_length) { |
AnnaBridge | 187:0387e8f68319 | 302 | rx_buffer[i] = in; |
AnnaBridge | 187:0387e8f68319 | 303 | } |
AnnaBridge | 187:0387e8f68319 | 304 | } |
AnnaBridge | 187:0387e8f68319 | 305 | |
AnnaBridge | 187:0387e8f68319 | 306 | return total; |
AnnaBridge | 187:0387e8f68319 | 307 | } |
AnnaBridge | 187:0387e8f68319 | 308 | |
AnnaBridge | 187:0387e8f68319 | 309 | #if DEVICE_SPISLAVE |
AnnaBridge | 187:0387e8f68319 | 310 | int spi_slave_receive(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 311 | { |
AnnaBridge | 187:0387e8f68319 | 312 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 313 | |
AnnaBridge | 187:0387e8f68319 | 314 | SPI_ENABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 315 | |
AnnaBridge | 187:0387e8f68319 | 316 | return spi_readable(obj); |
AnnaBridge | 187:0387e8f68319 | 317 | }; |
AnnaBridge | 187:0387e8f68319 | 318 | |
AnnaBridge | 187:0387e8f68319 | 319 | int spi_slave_read(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 320 | { |
AnnaBridge | 187:0387e8f68319 | 321 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 322 | |
AnnaBridge | 187:0387e8f68319 | 323 | SPI_ENABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 324 | |
AnnaBridge | 187:0387e8f68319 | 325 | // Wait for rx buffer full |
AnnaBridge | 187:0387e8f68319 | 326 | while (! spi_readable(obj)); |
AnnaBridge | 187:0387e8f68319 | 327 | int value = SPI_READ_RX(spi_base); |
AnnaBridge | 187:0387e8f68319 | 328 | return value; |
AnnaBridge | 187:0387e8f68319 | 329 | } |
AnnaBridge | 187:0387e8f68319 | 330 | |
AnnaBridge | 187:0387e8f68319 | 331 | void spi_slave_write(spi_t *obj, int value) |
AnnaBridge | 187:0387e8f68319 | 332 | { |
AnnaBridge | 187:0387e8f68319 | 333 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 334 | |
AnnaBridge | 187:0387e8f68319 | 335 | SPI_ENABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 336 | |
AnnaBridge | 187:0387e8f68319 | 337 | // Wait for tx buffer empty |
AnnaBridge | 187:0387e8f68319 | 338 | while(! spi_writeable(obj)); |
AnnaBridge | 187:0387e8f68319 | 339 | SPI_WRITE_TX(spi_base, value); |
AnnaBridge | 187:0387e8f68319 | 340 | } |
AnnaBridge | 187:0387e8f68319 | 341 | #endif |
AnnaBridge | 187:0387e8f68319 | 342 | |
AnnaBridge | 187:0387e8f68319 | 343 | #if DEVICE_SPI_ASYNCH |
AnnaBridge | 187:0387e8f68319 | 344 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) |
AnnaBridge | 187:0387e8f68319 | 345 | { |
AnnaBridge | 187:0387e8f68319 | 346 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 347 | SPI_SET_DATA_WIDTH(spi_base, bit_width); |
AnnaBridge | 187:0387e8f68319 | 348 | |
AnnaBridge | 187:0387e8f68319 | 349 | obj->spi.dma_usage = hint; |
AnnaBridge | 187:0387e8f68319 | 350 | spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx); |
AnnaBridge | 187:0387e8f68319 | 351 | uint32_t data_width = spi_get_data_width(obj); |
AnnaBridge | 187:0387e8f68319 | 352 | // Conditions to go DMA way: |
AnnaBridge | 187:0387e8f68319 | 353 | // (1) No DMA support for non-8 multiple data width. |
AnnaBridge | 187:0387e8f68319 | 354 | // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx. |
AnnaBridge | 187:0387e8f68319 | 355 | if ((data_width % 8) || |
AnnaBridge | 187:0387e8f68319 | 356 | (tx_length < rx_length)) { |
AnnaBridge | 187:0387e8f68319 | 357 | obj->spi.dma_usage = DMA_USAGE_NEVER; |
AnnaBridge | 187:0387e8f68319 | 358 | dma_channel_free(obj->spi.dma_chn_id_tx); |
AnnaBridge | 187:0387e8f68319 | 359 | obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 360 | dma_channel_free(obj->spi.dma_chn_id_rx); |
AnnaBridge | 187:0387e8f68319 | 361 | obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 362 | } |
AnnaBridge | 187:0387e8f68319 | 363 | |
AnnaBridge | 187:0387e8f68319 | 364 | // SPI IRQ is necessary for both interrupt way and DMA way |
AnnaBridge | 187:0387e8f68319 | 365 | spi_enable_event(obj, event, 1); |
AnnaBridge | 187:0387e8f68319 | 366 | spi_buffer_set(obj, tx, tx_length, rx, rx_length); |
AnnaBridge | 187:0387e8f68319 | 367 | |
AnnaBridge | 187:0387e8f68319 | 368 | SPI_ENABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 369 | |
AnnaBridge | 187:0387e8f68319 | 370 | if (obj->spi.dma_usage == DMA_USAGE_NEVER) { |
AnnaBridge | 187:0387e8f68319 | 371 | // Interrupt way |
AnnaBridge | 187:0387e8f68319 | 372 | spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2); |
AnnaBridge | 187:0387e8f68319 | 373 | spi_enable_vector_interrupt(obj, handler, 1); |
AnnaBridge | 187:0387e8f68319 | 374 | spi_master_enable_interrupt(obj, 1); |
AnnaBridge | 187:0387e8f68319 | 375 | } else { |
AnnaBridge | 187:0387e8f68319 | 376 | // DMA way |
AnnaBridge | 187:0387e8f68319 | 377 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 378 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 379 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 380 | |
AnnaBridge | 187:0387e8f68319 | 381 | PDMA_T *pdma_base = dma_modbase(); |
AnnaBridge | 187:0387e8f68319 | 382 | |
AnnaBridge | 187:0387e8f68319 | 383 | // Configure tx DMA |
AnnaBridge | 187:0387e8f68319 | 384 | pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel |
AnnaBridge | 187:0387e8f68319 | 385 | PDMA_SetTransferMode(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 386 | obj->spi.dma_chn_id_tx, |
AnnaBridge | 187:0387e8f68319 | 387 | ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA |
AnnaBridge | 187:0387e8f68319 | 388 | 0, // Scatter-gather disabled |
AnnaBridge | 187:0387e8f68319 | 389 | 0); // Scatter-gather descriptor address |
AnnaBridge | 187:0387e8f68319 | 390 | PDMA_SetTransferCnt(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 391 | obj->spi.dma_chn_id_tx, |
AnnaBridge | 187:0387e8f68319 | 392 | (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, |
AnnaBridge | 187:0387e8f68319 | 393 | tx_length); |
AnnaBridge | 187:0387e8f68319 | 394 | PDMA_SetTransferAddr(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 395 | obj->spi.dma_chn_id_tx, |
AnnaBridge | 187:0387e8f68319 | 396 | (uint32_t) tx, // NOTE: |
AnnaBridge | 187:0387e8f68319 | 397 | // NUC472: End of source address |
AnnaBridge | 187:0387e8f68319 | 398 | // M451/M480/M2351: Start of source address |
AnnaBridge | 187:0387e8f68319 | 399 | PDMA_SAR_INC, // Source address incremental |
AnnaBridge | 187:0387e8f68319 | 400 | (uint32_t) &spi_base->TX, // Destination address |
AnnaBridge | 187:0387e8f68319 | 401 | PDMA_DAR_FIX); // Destination address fixed |
AnnaBridge | 187:0387e8f68319 | 402 | PDMA_SetBurstType(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 403 | obj->spi.dma_chn_id_tx, |
AnnaBridge | 187:0387e8f68319 | 404 | PDMA_REQ_SINGLE, // Single mode |
AnnaBridge | 187:0387e8f68319 | 405 | 0); // Burst size |
AnnaBridge | 187:0387e8f68319 | 406 | PDMA_EnableInt(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 407 | obj->spi.dma_chn_id_tx, |
AnnaBridge | 187:0387e8f68319 | 408 | PDMA_INT_TRANS_DONE); // Interrupt type |
AnnaBridge | 187:0387e8f68319 | 409 | // Register DMA event handler |
AnnaBridge | 187:0387e8f68319 | 410 | dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); |
AnnaBridge | 187:0387e8f68319 | 411 | |
AnnaBridge | 187:0387e8f68319 | 412 | // Configure rx DMA |
AnnaBridge | 187:0387e8f68319 | 413 | pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel |
AnnaBridge | 187:0387e8f68319 | 414 | PDMA_SetTransferMode(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 415 | obj->spi.dma_chn_id_rx, |
AnnaBridge | 187:0387e8f68319 | 416 | ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA |
AnnaBridge | 187:0387e8f68319 | 417 | 0, // Scatter-gather disabled |
AnnaBridge | 187:0387e8f68319 | 418 | 0); // Scatter-gather descriptor address |
AnnaBridge | 187:0387e8f68319 | 419 | PDMA_SetTransferCnt(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 420 | obj->spi.dma_chn_id_rx, |
AnnaBridge | 187:0387e8f68319 | 421 | (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, |
AnnaBridge | 187:0387e8f68319 | 422 | rx_length); |
AnnaBridge | 187:0387e8f68319 | 423 | PDMA_SetTransferAddr(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 424 | obj->spi.dma_chn_id_rx, |
AnnaBridge | 187:0387e8f68319 | 425 | (uint32_t) &spi_base->RX, // Source address |
AnnaBridge | 187:0387e8f68319 | 426 | PDMA_SAR_FIX, // Source address fixed |
AnnaBridge | 187:0387e8f68319 | 427 | (uint32_t) rx, // NOTE: |
AnnaBridge | 187:0387e8f68319 | 428 | // NUC472: End of destination address |
AnnaBridge | 187:0387e8f68319 | 429 | // M451/M480/M2351: Start of destination address |
AnnaBridge | 187:0387e8f68319 | 430 | PDMA_DAR_INC); // Destination address incremental |
AnnaBridge | 187:0387e8f68319 | 431 | PDMA_SetBurstType(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 432 | obj->spi.dma_chn_id_rx, |
AnnaBridge | 187:0387e8f68319 | 433 | PDMA_REQ_SINGLE, // Single mode |
AnnaBridge | 187:0387e8f68319 | 434 | 0); // Burst size |
AnnaBridge | 187:0387e8f68319 | 435 | PDMA_EnableInt(pdma_base, |
AnnaBridge | 187:0387e8f68319 | 436 | obj->spi.dma_chn_id_rx, |
AnnaBridge | 187:0387e8f68319 | 437 | PDMA_INT_TRANS_DONE); // Interrupt type |
AnnaBridge | 187:0387e8f68319 | 438 | // Register DMA event handler |
AnnaBridge | 187:0387e8f68319 | 439 | dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); |
AnnaBridge | 187:0387e8f68319 | 440 | |
AnnaBridge | 187:0387e8f68319 | 441 | /* Start tx/rx DMA transfer |
AnnaBridge | 187:0387e8f68319 | 442 | * |
AnnaBridge | 187:0387e8f68319 | 443 | * If we have both PDMA and SPI interrupts enabled and PDMA priority is lower than SPI priority, |
AnnaBridge | 187:0387e8f68319 | 444 | * we would trap in SPI interrupt handler endlessly with the sequence: |
AnnaBridge | 187:0387e8f68319 | 445 | * |
AnnaBridge | 187:0387e8f68319 | 446 | * 1. PDMA TX transfer done interrupt occurs and is well handled. |
AnnaBridge | 187:0387e8f68319 | 447 | * 2. SPI RX FIFO threshold interrupt occurs. Trap here because PDMA RX transfer done interrupt doesn't get handled. |
AnnaBridge | 187:0387e8f68319 | 448 | * 3. PDMA RX transfer done interrupt occurs but it cannot be handled due to above. |
AnnaBridge | 187:0387e8f68319 | 449 | * |
AnnaBridge | 187:0387e8f68319 | 450 | * To fix it, we don't enable SPI TX/RX threshold interrupts but keep SPI vector handler set to be called |
AnnaBridge | 187:0387e8f68319 | 451 | * in PDMA TX/RX transfer done interrupt handlers (spi_dma_handler_tx/spi_dma_handler_rx). |
AnnaBridge | 187:0387e8f68319 | 452 | */ |
AnnaBridge | 187:0387e8f68319 | 453 | NVIC_SetVector(modinit->irq_n, handler); |
AnnaBridge | 187:0387e8f68319 | 454 | |
AnnaBridge | 187:0387e8f68319 | 455 | /* Order to enable PDMA TX/RX functions |
AnnaBridge | 187:0387e8f68319 | 456 | * |
AnnaBridge | 187:0387e8f68319 | 457 | * H/W spec: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are |
AnnaBridge | 187:0387e8f68319 | 458 | * enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable |
AnnaBridge | 187:0387e8f68319 | 459 | * TX PDMA function firstly or enable both functions simultaneously. |
AnnaBridge | 187:0387e8f68319 | 460 | * Per real test, it is safer to start RX PDMA first and then TX PDMA. Otherwise, receive FIFO is |
AnnaBridge | 187:0387e8f68319 | 461 | * subject to overflow by TX DMA. |
AnnaBridge | 187:0387e8f68319 | 462 | * |
AnnaBridge | 187:0387e8f68319 | 463 | * With the above conflicts, we enable PDMA TX/RX functions simultaneously. |
AnnaBridge | 187:0387e8f68319 | 464 | */ |
AnnaBridge | 187:0387e8f68319 | 465 | spi_base->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk); |
AnnaBridge | 187:0387e8f68319 | 466 | |
AnnaBridge | 187:0387e8f68319 | 467 | /* Don't enable SPI TX/RX threshold interrupts as commented above */ |
AnnaBridge | 187:0387e8f68319 | 468 | } |
AnnaBridge | 187:0387e8f68319 | 469 | } |
AnnaBridge | 187:0387e8f68319 | 470 | |
AnnaBridge | 187:0387e8f68319 | 471 | /** |
AnnaBridge | 187:0387e8f68319 | 472 | * Abort an SPI transfer |
AnnaBridge | 187:0387e8f68319 | 473 | * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing |
AnnaBridge | 187:0387e8f68319 | 474 | * transfers |
AnnaBridge | 187:0387e8f68319 | 475 | * @param[in] obj The SPI peripheral to stop |
AnnaBridge | 187:0387e8f68319 | 476 | */ |
AnnaBridge | 187:0387e8f68319 | 477 | void spi_abort_asynch(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 478 | { |
AnnaBridge | 187:0387e8f68319 | 479 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 480 | PDMA_T *pdma_base = dma_modbase(); |
AnnaBridge | 187:0387e8f68319 | 481 | |
AnnaBridge | 187:0387e8f68319 | 482 | if (obj->spi.dma_usage != DMA_USAGE_NEVER) { |
AnnaBridge | 187:0387e8f68319 | 483 | // Receive FIFO Overrun in case of tx length > rx length on DMA way |
AnnaBridge | 187:0387e8f68319 | 484 | if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { |
AnnaBridge | 187:0387e8f68319 | 485 | spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; |
AnnaBridge | 187:0387e8f68319 | 486 | } |
AnnaBridge | 187:0387e8f68319 | 487 | |
AnnaBridge | 187:0387e8f68319 | 488 | if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 489 | PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE); |
AnnaBridge | 187:0387e8f68319 | 490 | // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. |
AnnaBridge | 187:0387e8f68319 | 491 | pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); |
AnnaBridge | 187:0387e8f68319 | 492 | } |
AnnaBridge | 187:0387e8f68319 | 493 | SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); |
AnnaBridge | 187:0387e8f68319 | 494 | |
AnnaBridge | 187:0387e8f68319 | 495 | if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 496 | PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE); |
AnnaBridge | 187:0387e8f68319 | 497 | // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. |
AnnaBridge | 187:0387e8f68319 | 498 | pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); |
AnnaBridge | 187:0387e8f68319 | 499 | } |
AnnaBridge | 187:0387e8f68319 | 500 | SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); |
AnnaBridge | 187:0387e8f68319 | 501 | } |
AnnaBridge | 187:0387e8f68319 | 502 | |
AnnaBridge | 187:0387e8f68319 | 503 | // Necessary for both interrupt way and DMA way |
AnnaBridge | 187:0387e8f68319 | 504 | spi_enable_vector_interrupt(obj, 0, 0); |
AnnaBridge | 187:0387e8f68319 | 505 | spi_master_enable_interrupt(obj, 0); |
AnnaBridge | 187:0387e8f68319 | 506 | |
AnnaBridge | 187:0387e8f68319 | 507 | /* Necessary for accessing FIFOCTL below */ |
AnnaBridge | 187:0387e8f68319 | 508 | SPI_DISABLE_SYNC(spi_base); |
AnnaBridge | 187:0387e8f68319 | 509 | |
AnnaBridge | 187:0387e8f68319 | 510 | SPI_ClearRxFIFO(spi_base); |
AnnaBridge | 187:0387e8f68319 | 511 | SPI_ClearTxFIFO(spi_base); |
AnnaBridge | 187:0387e8f68319 | 512 | } |
AnnaBridge | 187:0387e8f68319 | 513 | |
AnnaBridge | 187:0387e8f68319 | 514 | /** |
AnnaBridge | 187:0387e8f68319 | 515 | * Handle the SPI interrupt |
AnnaBridge | 187:0387e8f68319 | 516 | * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way, |
AnnaBridge | 187:0387e8f68319 | 517 | * it is unlikely that the RX FIFO will overflow. |
AnnaBridge | 187:0387e8f68319 | 518 | * @param[in] obj The SPI peripheral that generated the interrupt |
AnnaBridge | 187:0387e8f68319 | 519 | * @return |
AnnaBridge | 187:0387e8f68319 | 520 | */ |
AnnaBridge | 187:0387e8f68319 | 521 | uint32_t spi_irq_handler_asynch(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 522 | { |
AnnaBridge | 187:0387e8f68319 | 523 | // Check for SPI events |
AnnaBridge | 187:0387e8f68319 | 524 | uint32_t event = spi_event_check(obj); |
AnnaBridge | 187:0387e8f68319 | 525 | if (event) { |
AnnaBridge | 187:0387e8f68319 | 526 | spi_abort_asynch(obj); |
AnnaBridge | 187:0387e8f68319 | 527 | } |
AnnaBridge | 187:0387e8f68319 | 528 | |
AnnaBridge | 187:0387e8f68319 | 529 | return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0); |
AnnaBridge | 187:0387e8f68319 | 530 | } |
AnnaBridge | 187:0387e8f68319 | 531 | |
AnnaBridge | 187:0387e8f68319 | 532 | uint8_t spi_active(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 533 | { |
AnnaBridge | 187:0387e8f68319 | 534 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 535 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 536 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 537 | |
AnnaBridge | 187:0387e8f68319 | 538 | /* Vector will be cleared when asynchronous transfer is finished or aborted. |
AnnaBridge | 187:0387e8f68319 | 539 | Use it to judge if asynchronous transfer is on-going. */ |
AnnaBridge | 187:0387e8f68319 | 540 | uint32_t vec = NVIC_GetVector(modinit->irq_n); |
AnnaBridge | 187:0387e8f68319 | 541 | return vec ? 1 : 0; |
AnnaBridge | 187:0387e8f68319 | 542 | } |
AnnaBridge | 187:0387e8f68319 | 543 | |
AnnaBridge | 187:0387e8f68319 | 544 | static int spi_writeable(spi_t * obj) |
AnnaBridge | 187:0387e8f68319 | 545 | { |
AnnaBridge | 187:0387e8f68319 | 546 | // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive |
AnnaBridge | 187:0387e8f68319 | 547 | return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))); |
AnnaBridge | 187:0387e8f68319 | 548 | } |
AnnaBridge | 187:0387e8f68319 | 549 | |
AnnaBridge | 187:0387e8f68319 | 550 | static int spi_readable(spi_t * obj) |
AnnaBridge | 187:0387e8f68319 | 551 | { |
AnnaBridge | 187:0387e8f68319 | 552 | return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))); |
AnnaBridge | 187:0387e8f68319 | 553 | } |
AnnaBridge | 187:0387e8f68319 | 554 | |
AnnaBridge | 187:0387e8f68319 | 555 | static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) |
AnnaBridge | 187:0387e8f68319 | 556 | { |
AnnaBridge | 187:0387e8f68319 | 557 | obj->spi.event &= ~SPI_EVENT_ALL; |
AnnaBridge | 187:0387e8f68319 | 558 | obj->spi.event |= (event & SPI_EVENT_ALL); |
AnnaBridge | 187:0387e8f68319 | 559 | if (event & SPI_EVENT_RX_OVERFLOW) { |
AnnaBridge | 187:0387e8f68319 | 560 | SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK); |
AnnaBridge | 187:0387e8f68319 | 561 | } |
AnnaBridge | 187:0387e8f68319 | 562 | } |
AnnaBridge | 187:0387e8f68319 | 563 | |
AnnaBridge | 187:0387e8f68319 | 564 | static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) |
AnnaBridge | 187:0387e8f68319 | 565 | { |
AnnaBridge | 187:0387e8f68319 | 566 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 567 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 568 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 569 | |
AnnaBridge | 187:0387e8f68319 | 570 | if (enable) { |
AnnaBridge | 187:0387e8f68319 | 571 | NVIC_SetVector(modinit->irq_n, handler); |
AnnaBridge | 187:0387e8f68319 | 572 | NVIC_EnableIRQ(modinit->irq_n); |
AnnaBridge | 187:0387e8f68319 | 573 | } else { |
AnnaBridge | 187:0387e8f68319 | 574 | NVIC_DisableIRQ(modinit->irq_n); |
AnnaBridge | 187:0387e8f68319 | 575 | NVIC_SetVector(modinit->irq_n, 0); |
AnnaBridge | 187:0387e8f68319 | 576 | } |
AnnaBridge | 187:0387e8f68319 | 577 | } |
AnnaBridge | 187:0387e8f68319 | 578 | |
AnnaBridge | 187:0387e8f68319 | 579 | static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable) |
AnnaBridge | 187:0387e8f68319 | 580 | { |
AnnaBridge | 187:0387e8f68319 | 581 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 582 | |
AnnaBridge | 187:0387e8f68319 | 583 | if (enable) { |
AnnaBridge | 187:0387e8f68319 | 584 | uint32_t fifo_depth = spi_fifo_depth(obj); |
AnnaBridge | 187:0387e8f68319 | 585 | SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2); |
AnnaBridge | 187:0387e8f68319 | 586 | // Enable tx/rx FIFO threshold interrupt |
AnnaBridge | 187:0387e8f68319 | 587 | SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); |
AnnaBridge | 187:0387e8f68319 | 588 | } else { |
AnnaBridge | 187:0387e8f68319 | 589 | SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); |
AnnaBridge | 187:0387e8f68319 | 590 | } |
AnnaBridge | 187:0387e8f68319 | 591 | } |
AnnaBridge | 187:0387e8f68319 | 592 | |
AnnaBridge | 187:0387e8f68319 | 593 | static uint32_t spi_event_check(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 594 | { |
AnnaBridge | 187:0387e8f68319 | 595 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 596 | uint32_t event = 0; |
AnnaBridge | 187:0387e8f68319 | 597 | |
AnnaBridge | 187:0387e8f68319 | 598 | if (obj->spi.dma_usage == DMA_USAGE_NEVER) { |
AnnaBridge | 187:0387e8f68319 | 599 | uint32_t n_rec = spi_master_read_asynch(obj); |
AnnaBridge | 187:0387e8f68319 | 600 | spi_master_write_asynch(obj, n_rec); |
AnnaBridge | 187:0387e8f68319 | 601 | } |
AnnaBridge | 187:0387e8f68319 | 602 | |
AnnaBridge | 187:0387e8f68319 | 603 | if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) { |
AnnaBridge | 187:0387e8f68319 | 604 | event |= SPI_EVENT_COMPLETE; |
AnnaBridge | 187:0387e8f68319 | 605 | } |
AnnaBridge | 187:0387e8f68319 | 606 | |
AnnaBridge | 187:0387e8f68319 | 607 | // Receive FIFO Overrun |
AnnaBridge | 187:0387e8f68319 | 608 | if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { |
AnnaBridge | 187:0387e8f68319 | 609 | spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; |
AnnaBridge | 187:0387e8f68319 | 610 | // In case of tx length > rx length on DMA way |
AnnaBridge | 187:0387e8f68319 | 611 | if (obj->spi.dma_usage == DMA_USAGE_NEVER) { |
AnnaBridge | 187:0387e8f68319 | 612 | event |= SPI_EVENT_RX_OVERFLOW; |
AnnaBridge | 187:0387e8f68319 | 613 | } |
AnnaBridge | 187:0387e8f68319 | 614 | } |
AnnaBridge | 187:0387e8f68319 | 615 | |
AnnaBridge | 187:0387e8f68319 | 616 | // Receive Time-Out |
AnnaBridge | 187:0387e8f68319 | 617 | if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) { |
AnnaBridge | 187:0387e8f68319 | 618 | spi_base->STATUS = SPI_STATUS_RXTOIF_Msk; |
AnnaBridge | 187:0387e8f68319 | 619 | // Not using this IF. Just clear it. |
AnnaBridge | 187:0387e8f68319 | 620 | } |
AnnaBridge | 187:0387e8f68319 | 621 | // Transmit FIFO Under-Run |
AnnaBridge | 187:0387e8f68319 | 622 | if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) { |
AnnaBridge | 187:0387e8f68319 | 623 | spi_base->STATUS = SPI_STATUS_TXUFIF_Msk; |
AnnaBridge | 187:0387e8f68319 | 624 | event |= SPI_EVENT_ERROR; |
AnnaBridge | 187:0387e8f68319 | 625 | } |
AnnaBridge | 187:0387e8f68319 | 626 | |
AnnaBridge | 187:0387e8f68319 | 627 | return event; |
AnnaBridge | 187:0387e8f68319 | 628 | } |
AnnaBridge | 187:0387e8f68319 | 629 | |
AnnaBridge | 187:0387e8f68319 | 630 | /** |
AnnaBridge | 187:0387e8f68319 | 631 | * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full |
AnnaBridge | 187:0387e8f68319 | 632 | * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed. |
AnnaBridge | 187:0387e8f68319 | 633 | * @param[in] obj The SPI object on which to operate |
AnnaBridge | 187:0387e8f68319 | 634 | * @param[in] tx_limit The maximum number of words to send |
AnnaBridge | 187:0387e8f68319 | 635 | * @return The number of SPI words that have been transfered |
AnnaBridge | 187:0387e8f68319 | 636 | */ |
AnnaBridge | 187:0387e8f68319 | 637 | static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) |
AnnaBridge | 187:0387e8f68319 | 638 | { |
AnnaBridge | 187:0387e8f68319 | 639 | uint32_t n_words = 0; |
AnnaBridge | 187:0387e8f68319 | 640 | uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; |
AnnaBridge | 187:0387e8f68319 | 641 | uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; |
AnnaBridge | 187:0387e8f68319 | 642 | uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn); |
AnnaBridge | 187:0387e8f68319 | 643 | max_tx = NU_MIN(max_tx, tx_limit); |
AnnaBridge | 187:0387e8f68319 | 644 | uint8_t data_width = spi_get_data_width(obj); |
AnnaBridge | 187:0387e8f68319 | 645 | uint8_t bytes_per_word = (data_width + 7) / 8; |
AnnaBridge | 187:0387e8f68319 | 646 | uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; |
AnnaBridge | 187:0387e8f68319 | 647 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 648 | |
AnnaBridge | 187:0387e8f68319 | 649 | while ((n_words < max_tx) && spi_writeable(obj)) { |
AnnaBridge | 187:0387e8f68319 | 650 | if (spi_is_tx_complete(obj)) { |
AnnaBridge | 187:0387e8f68319 | 651 | // Transmit dummy as transmit buffer is empty |
AnnaBridge | 187:0387e8f68319 | 652 | SPI_WRITE_TX(spi_base, 0); |
AnnaBridge | 187:0387e8f68319 | 653 | } else { |
AnnaBridge | 187:0387e8f68319 | 654 | switch (bytes_per_word) { |
AnnaBridge | 187:0387e8f68319 | 655 | case 4: |
AnnaBridge | 187:0387e8f68319 | 656 | SPI_WRITE_TX(spi_base, nu_get32_le(tx)); |
AnnaBridge | 187:0387e8f68319 | 657 | tx += 4; |
AnnaBridge | 187:0387e8f68319 | 658 | break; |
AnnaBridge | 187:0387e8f68319 | 659 | case 2: |
AnnaBridge | 187:0387e8f68319 | 660 | SPI_WRITE_TX(spi_base, nu_get16_le(tx)); |
AnnaBridge | 187:0387e8f68319 | 661 | tx += 2; |
AnnaBridge | 187:0387e8f68319 | 662 | break; |
AnnaBridge | 187:0387e8f68319 | 663 | case 1: |
AnnaBridge | 187:0387e8f68319 | 664 | SPI_WRITE_TX(spi_base, *((uint8_t *) tx)); |
AnnaBridge | 187:0387e8f68319 | 665 | tx += 1; |
AnnaBridge | 187:0387e8f68319 | 666 | break; |
AnnaBridge | 187:0387e8f68319 | 667 | } |
AnnaBridge | 187:0387e8f68319 | 668 | |
AnnaBridge | 187:0387e8f68319 | 669 | obj->tx_buff.pos ++; |
AnnaBridge | 187:0387e8f68319 | 670 | } |
AnnaBridge | 187:0387e8f68319 | 671 | n_words ++; |
AnnaBridge | 187:0387e8f68319 | 672 | } |
AnnaBridge | 187:0387e8f68319 | 673 | |
AnnaBridge | 187:0387e8f68319 | 674 | //Return the number of words that have been sent |
AnnaBridge | 187:0387e8f68319 | 675 | return n_words; |
AnnaBridge | 187:0387e8f68319 | 676 | } |
AnnaBridge | 187:0387e8f68319 | 677 | |
AnnaBridge | 187:0387e8f68319 | 678 | /** |
AnnaBridge | 187:0387e8f68319 | 679 | * Read SPI words out of the RX FIFO |
AnnaBridge | 187:0387e8f68319 | 680 | * Continues reading words out of the RX FIFO until the following condition is met: |
AnnaBridge | 187:0387e8f68319 | 681 | * o There are no more words in the FIFO |
AnnaBridge | 187:0387e8f68319 | 682 | * OR BOTH OF: |
AnnaBridge | 187:0387e8f68319 | 683 | * o At least as many words as the TX buffer have been received |
AnnaBridge | 187:0387e8f68319 | 684 | * o At least as many words as the RX buffer have been received |
AnnaBridge | 187:0387e8f68319 | 685 | * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size |
AnnaBridge | 187:0387e8f68319 | 686 | * @param[in] obj The SPI object on which to operate |
AnnaBridge | 187:0387e8f68319 | 687 | * @return Returns the number of words extracted from the RX FIFO |
AnnaBridge | 187:0387e8f68319 | 688 | */ |
AnnaBridge | 187:0387e8f68319 | 689 | static uint32_t spi_master_read_asynch(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 690 | { |
AnnaBridge | 187:0387e8f68319 | 691 | uint32_t n_words = 0; |
AnnaBridge | 187:0387e8f68319 | 692 | uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; |
AnnaBridge | 187:0387e8f68319 | 693 | uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; |
AnnaBridge | 187:0387e8f68319 | 694 | uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn); |
AnnaBridge | 187:0387e8f68319 | 695 | uint8_t data_width = spi_get_data_width(obj); |
AnnaBridge | 187:0387e8f68319 | 696 | uint8_t bytes_per_word = (data_width + 7) / 8; |
AnnaBridge | 187:0387e8f68319 | 697 | uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; |
AnnaBridge | 187:0387e8f68319 | 698 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 699 | |
AnnaBridge | 187:0387e8f68319 | 700 | while ((n_words < max_rx) && spi_readable(obj)) { |
AnnaBridge | 187:0387e8f68319 | 701 | if (spi_is_rx_complete(obj)) { |
AnnaBridge | 187:0387e8f68319 | 702 | // Disregard as receive buffer is full |
AnnaBridge | 187:0387e8f68319 | 703 | SPI_READ_RX(spi_base); |
AnnaBridge | 187:0387e8f68319 | 704 | } else { |
AnnaBridge | 187:0387e8f68319 | 705 | switch (bytes_per_word) { |
AnnaBridge | 187:0387e8f68319 | 706 | case 4: { |
AnnaBridge | 187:0387e8f68319 | 707 | uint32_t val = SPI_READ_RX(spi_base); |
AnnaBridge | 187:0387e8f68319 | 708 | nu_set32_le(rx, val); |
AnnaBridge | 187:0387e8f68319 | 709 | rx += 4; |
AnnaBridge | 187:0387e8f68319 | 710 | break; |
AnnaBridge | 187:0387e8f68319 | 711 | } |
AnnaBridge | 187:0387e8f68319 | 712 | case 2: { |
AnnaBridge | 187:0387e8f68319 | 713 | uint16_t val = SPI_READ_RX(spi_base); |
AnnaBridge | 187:0387e8f68319 | 714 | nu_set16_le(rx, val); |
AnnaBridge | 187:0387e8f68319 | 715 | rx += 2; |
AnnaBridge | 187:0387e8f68319 | 716 | break; |
AnnaBridge | 187:0387e8f68319 | 717 | } |
AnnaBridge | 187:0387e8f68319 | 718 | case 1: |
AnnaBridge | 187:0387e8f68319 | 719 | *rx ++ = SPI_READ_RX(spi_base); |
AnnaBridge | 187:0387e8f68319 | 720 | break; |
AnnaBridge | 187:0387e8f68319 | 721 | } |
AnnaBridge | 187:0387e8f68319 | 722 | |
AnnaBridge | 187:0387e8f68319 | 723 | obj->rx_buff.pos ++; |
AnnaBridge | 187:0387e8f68319 | 724 | } |
AnnaBridge | 187:0387e8f68319 | 725 | n_words ++; |
AnnaBridge | 187:0387e8f68319 | 726 | } |
AnnaBridge | 187:0387e8f68319 | 727 | |
AnnaBridge | 187:0387e8f68319 | 728 | // Return the number of words received |
AnnaBridge | 187:0387e8f68319 | 729 | return n_words; |
AnnaBridge | 187:0387e8f68319 | 730 | } |
AnnaBridge | 187:0387e8f68319 | 731 | |
AnnaBridge | 187:0387e8f68319 | 732 | static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) |
AnnaBridge | 187:0387e8f68319 | 733 | { |
AnnaBridge | 187:0387e8f68319 | 734 | obj->tx_buff.buffer = (void *) tx; |
AnnaBridge | 187:0387e8f68319 | 735 | obj->tx_buff.length = tx_length; |
AnnaBridge | 187:0387e8f68319 | 736 | obj->tx_buff.pos = 0; |
AnnaBridge | 187:0387e8f68319 | 737 | obj->tx_buff.width = spi_get_data_width(obj); |
AnnaBridge | 187:0387e8f68319 | 738 | obj->rx_buff.buffer = rx; |
AnnaBridge | 187:0387e8f68319 | 739 | obj->rx_buff.length = rx_length; |
AnnaBridge | 187:0387e8f68319 | 740 | obj->rx_buff.pos = 0; |
AnnaBridge | 187:0387e8f68319 | 741 | obj->rx_buff.width = spi_get_data_width(obj); |
AnnaBridge | 187:0387e8f68319 | 742 | } |
AnnaBridge | 187:0387e8f68319 | 743 | |
AnnaBridge | 187:0387e8f68319 | 744 | static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx) |
AnnaBridge | 187:0387e8f68319 | 745 | { |
AnnaBridge | 187:0387e8f68319 | 746 | if (*dma_usage != DMA_USAGE_NEVER) { |
AnnaBridge | 187:0387e8f68319 | 747 | if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 748 | *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE); |
AnnaBridge | 187:0387e8f68319 | 749 | } |
AnnaBridge | 187:0387e8f68319 | 750 | if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 751 | *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE); |
AnnaBridge | 187:0387e8f68319 | 752 | } |
AnnaBridge | 187:0387e8f68319 | 753 | |
AnnaBridge | 187:0387e8f68319 | 754 | if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { |
AnnaBridge | 187:0387e8f68319 | 755 | *dma_usage = DMA_USAGE_NEVER; |
AnnaBridge | 187:0387e8f68319 | 756 | } |
AnnaBridge | 187:0387e8f68319 | 757 | } |
AnnaBridge | 187:0387e8f68319 | 758 | |
AnnaBridge | 187:0387e8f68319 | 759 | if (*dma_usage == DMA_USAGE_NEVER) { |
AnnaBridge | 187:0387e8f68319 | 760 | dma_channel_free(*dma_ch_tx); |
AnnaBridge | 187:0387e8f68319 | 761 | *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 762 | dma_channel_free(*dma_ch_rx); |
AnnaBridge | 187:0387e8f68319 | 763 | *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS; |
AnnaBridge | 187:0387e8f68319 | 764 | } |
AnnaBridge | 187:0387e8f68319 | 765 | } |
AnnaBridge | 187:0387e8f68319 | 766 | |
AnnaBridge | 187:0387e8f68319 | 767 | static uint8_t spi_get_data_width(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 768 | { |
AnnaBridge | 187:0387e8f68319 | 769 | SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 770 | |
AnnaBridge | 187:0387e8f68319 | 771 | uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos); |
AnnaBridge | 187:0387e8f68319 | 772 | if (data_width == 0) { |
AnnaBridge | 187:0387e8f68319 | 773 | data_width = 32; |
AnnaBridge | 187:0387e8f68319 | 774 | } |
AnnaBridge | 187:0387e8f68319 | 775 | |
AnnaBridge | 187:0387e8f68319 | 776 | return data_width; |
AnnaBridge | 187:0387e8f68319 | 777 | } |
AnnaBridge | 187:0387e8f68319 | 778 | |
AnnaBridge | 187:0387e8f68319 | 779 | static int spi_is_tx_complete(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 780 | { |
AnnaBridge | 187:0387e8f68319 | 781 | return (obj->tx_buff.pos == obj->tx_buff.length); |
AnnaBridge | 187:0387e8f68319 | 782 | } |
AnnaBridge | 187:0387e8f68319 | 783 | |
AnnaBridge | 187:0387e8f68319 | 784 | static int spi_is_rx_complete(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 785 | { |
AnnaBridge | 187:0387e8f68319 | 786 | return (obj->rx_buff.pos == obj->rx_buff.length); |
AnnaBridge | 187:0387e8f68319 | 787 | } |
AnnaBridge | 187:0387e8f68319 | 788 | |
AnnaBridge | 187:0387e8f68319 | 789 | static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma) |
AnnaBridge | 187:0387e8f68319 | 790 | { |
AnnaBridge | 187:0387e8f68319 | 791 | spi_t *obj = (spi_t *) id; |
AnnaBridge | 187:0387e8f68319 | 792 | |
AnnaBridge | 187:0387e8f68319 | 793 | // FIXME: Pass this error to caller |
AnnaBridge | 187:0387e8f68319 | 794 | if (event_dma & DMA_EVENT_ABORT) { |
AnnaBridge | 187:0387e8f68319 | 795 | } |
AnnaBridge | 187:0387e8f68319 | 796 | // Expect SPI IRQ will catch this transfer done event |
AnnaBridge | 187:0387e8f68319 | 797 | if (event_dma & DMA_EVENT_TRANSFER_DONE) { |
AnnaBridge | 187:0387e8f68319 | 798 | obj->tx_buff.pos = obj->tx_buff.length; |
AnnaBridge | 187:0387e8f68319 | 799 | } |
AnnaBridge | 187:0387e8f68319 | 800 | // FIXME: Pass this error to caller |
AnnaBridge | 187:0387e8f68319 | 801 | if (event_dma & DMA_EVENT_TIMEOUT) { |
AnnaBridge | 187:0387e8f68319 | 802 | } |
AnnaBridge | 187:0387e8f68319 | 803 | |
AnnaBridge | 187:0387e8f68319 | 804 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 805 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 806 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 807 | |
AnnaBridge | 187:0387e8f68319 | 808 | void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); |
AnnaBridge | 187:0387e8f68319 | 809 | vec(); |
AnnaBridge | 187:0387e8f68319 | 810 | } |
AnnaBridge | 187:0387e8f68319 | 811 | |
AnnaBridge | 187:0387e8f68319 | 812 | static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma) |
AnnaBridge | 187:0387e8f68319 | 813 | { |
AnnaBridge | 187:0387e8f68319 | 814 | spi_t *obj = (spi_t *) id; |
AnnaBridge | 187:0387e8f68319 | 815 | |
AnnaBridge | 187:0387e8f68319 | 816 | // FIXME: Pass this error to caller |
AnnaBridge | 187:0387e8f68319 | 817 | if (event_dma & DMA_EVENT_ABORT) { |
AnnaBridge | 187:0387e8f68319 | 818 | } |
AnnaBridge | 187:0387e8f68319 | 819 | // Expect SPI IRQ will catch this transfer done event |
AnnaBridge | 187:0387e8f68319 | 820 | if (event_dma & DMA_EVENT_TRANSFER_DONE) { |
AnnaBridge | 187:0387e8f68319 | 821 | obj->rx_buff.pos = obj->rx_buff.length; |
AnnaBridge | 187:0387e8f68319 | 822 | } |
AnnaBridge | 187:0387e8f68319 | 823 | // FIXME: Pass this error to caller |
AnnaBridge | 187:0387e8f68319 | 824 | if (event_dma & DMA_EVENT_TIMEOUT) { |
AnnaBridge | 187:0387e8f68319 | 825 | } |
AnnaBridge | 187:0387e8f68319 | 826 | |
AnnaBridge | 187:0387e8f68319 | 827 | const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); |
AnnaBridge | 187:0387e8f68319 | 828 | MBED_ASSERT(modinit != NULL); |
AnnaBridge | 187:0387e8f68319 | 829 | MBED_ASSERT(modinit->modname == (int) obj->spi.spi); |
AnnaBridge | 187:0387e8f68319 | 830 | |
AnnaBridge | 187:0387e8f68319 | 831 | void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); |
AnnaBridge | 187:0387e8f68319 | 832 | vec(); |
AnnaBridge | 187:0387e8f68319 | 833 | } |
AnnaBridge | 187:0387e8f68319 | 834 | |
AnnaBridge | 187:0387e8f68319 | 835 | /** Return FIFO depth of the SPI peripheral |
AnnaBridge | 187:0387e8f68319 | 836 | * |
AnnaBridge | 187:0387e8f68319 | 837 | * @details |
AnnaBridge | 187:0387e8f68319 | 838 | * M2351 |
AnnaBridge | 187:0387e8f68319 | 839 | * SPI0/1/2/3 8 if data width <=16; 4 otherwise |
AnnaBridge | 187:0387e8f68319 | 840 | */ |
AnnaBridge | 187:0387e8f68319 | 841 | static uint32_t spi_fifo_depth(spi_t *obj) |
AnnaBridge | 187:0387e8f68319 | 842 | { |
AnnaBridge | 187:0387e8f68319 | 843 | return (spi_get_data_width(obj) <= 16) ? 8 : 4; |
AnnaBridge | 187:0387e8f68319 | 844 | } |
AnnaBridge | 187:0387e8f68319 | 845 | |
AnnaBridge | 187:0387e8f68319 | 846 | #endif |
AnnaBridge | 187:0387e8f68319 | 847 | |
AnnaBridge | 187:0387e8f68319 | 848 | #endif |