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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_M/core_sc000.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /**************************************************************************//**
Anna Bridge 180:96ed750bd169 2 * @file core_sc000.h
Anna Bridge 180:96ed750bd169 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 188:bcfe06ba3d64 4 * @version V5.0.5
AnnaBridge 188:bcfe06ba3d64 5 * @date 28. May 2018
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 186:707f6e361f3e 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #if defined ( __ICCARM__ )
Anna Bridge 186:707f6e361f3e 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 186:707f6e361f3e 27 #elif defined (__clang__)
Anna Bridge 180:96ed750bd169 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 180:96ed750bd169 29 #endif
Anna Bridge 180:96ed750bd169 30
Anna Bridge 180:96ed750bd169 31 #ifndef __CORE_SC000_H_GENERIC
Anna Bridge 180:96ed750bd169 32 #define __CORE_SC000_H_GENERIC
Anna Bridge 180:96ed750bd169 33
Anna Bridge 180:96ed750bd169 34 #include <stdint.h>
Anna Bridge 180:96ed750bd169 35
Anna Bridge 180:96ed750bd169 36 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 37 extern "C" {
Anna Bridge 180:96ed750bd169 38 #endif
Anna Bridge 180:96ed750bd169 39
Anna Bridge 180:96ed750bd169 40 /**
Anna Bridge 180:96ed750bd169 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 180:96ed750bd169 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 180:96ed750bd169 43
Anna Bridge 180:96ed750bd169 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 180:96ed750bd169 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 180:96ed750bd169 46
Anna Bridge 180:96ed750bd169 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 180:96ed750bd169 48 Unions are used for effective representation of core registers.
Anna Bridge 180:96ed750bd169 49
Anna Bridge 180:96ed750bd169 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 180:96ed750bd169 51 Function-like macros are used to allow more efficient code.
Anna Bridge 180:96ed750bd169 52 */
Anna Bridge 180:96ed750bd169 53
Anna Bridge 180:96ed750bd169 54
Anna Bridge 180:96ed750bd169 55 /*******************************************************************************
Anna Bridge 180:96ed750bd169 56 * CMSIS definitions
Anna Bridge 180:96ed750bd169 57 ******************************************************************************/
Anna Bridge 180:96ed750bd169 58 /**
Anna Bridge 180:96ed750bd169 59 \ingroup SC000
Anna Bridge 180:96ed750bd169 60 @{
Anna Bridge 180:96ed750bd169 61 */
Anna Bridge 180:96ed750bd169 62
Anna Bridge 180:96ed750bd169 63 #include "cmsis_version.h"
Anna Bridge 180:96ed750bd169 64
Anna Bridge 180:96ed750bd169 65 /* CMSIS SC000 definitions */
Anna Bridge 180:96ed750bd169 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 180:96ed750bd169 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 180:96ed750bd169 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 180:96ed750bd169 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 180:96ed750bd169 70
Anna Bridge 180:96ed750bd169 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
Anna Bridge 180:96ed750bd169 72
Anna Bridge 180:96ed750bd169 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 180:96ed750bd169 74 This core does not support an FPU at all
Anna Bridge 180:96ed750bd169 75 */
Anna Bridge 180:96ed750bd169 76 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 77
Anna Bridge 180:96ed750bd169 78 #if defined ( __CC_ARM )
Anna Bridge 180:96ed750bd169 79 #if defined __TARGET_FPU_VFP
Anna Bridge 180:96ed750bd169 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 81 #endif
Anna Bridge 180:96ed750bd169 82
Anna Bridge 180:96ed750bd169 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 189:f392fc9709a3 84 #if defined __ARM_FP
Anna Bridge 180:96ed750bd169 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 86 #endif
Anna Bridge 180:96ed750bd169 87
Anna Bridge 180:96ed750bd169 88 #elif defined ( __GNUC__ )
Anna Bridge 180:96ed750bd169 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 180:96ed750bd169 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 91 #endif
Anna Bridge 180:96ed750bd169 92
Anna Bridge 180:96ed750bd169 93 #elif defined ( __ICCARM__ )
Anna Bridge 180:96ed750bd169 94 #if defined __ARMVFP__
Anna Bridge 180:96ed750bd169 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 96 #endif
Anna Bridge 180:96ed750bd169 97
Anna Bridge 180:96ed750bd169 98 #elif defined ( __TI_ARM__ )
Anna Bridge 180:96ed750bd169 99 #if defined __TI_VFP_SUPPORT__
Anna Bridge 180:96ed750bd169 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 101 #endif
Anna Bridge 180:96ed750bd169 102
Anna Bridge 180:96ed750bd169 103 #elif defined ( __TASKING__ )
Anna Bridge 180:96ed750bd169 104 #if defined __FPU_VFP__
Anna Bridge 180:96ed750bd169 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 106 #endif
Anna Bridge 180:96ed750bd169 107
Anna Bridge 180:96ed750bd169 108 #elif defined ( __CSMC__ )
Anna Bridge 180:96ed750bd169 109 #if ( __CSMC__ & 0x400U)
Anna Bridge 180:96ed750bd169 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 111 #endif
Anna Bridge 180:96ed750bd169 112
Anna Bridge 180:96ed750bd169 113 #endif
Anna Bridge 180:96ed750bd169 114
Anna Bridge 180:96ed750bd169 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 180:96ed750bd169 116
Anna Bridge 180:96ed750bd169 117
Anna Bridge 180:96ed750bd169 118 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 119 }
Anna Bridge 180:96ed750bd169 120 #endif
Anna Bridge 180:96ed750bd169 121
Anna Bridge 180:96ed750bd169 122 #endif /* __CORE_SC000_H_GENERIC */
Anna Bridge 180:96ed750bd169 123
Anna Bridge 180:96ed750bd169 124 #ifndef __CMSIS_GENERIC
Anna Bridge 180:96ed750bd169 125
Anna Bridge 180:96ed750bd169 126 #ifndef __CORE_SC000_H_DEPENDANT
Anna Bridge 180:96ed750bd169 127 #define __CORE_SC000_H_DEPENDANT
Anna Bridge 180:96ed750bd169 128
Anna Bridge 180:96ed750bd169 129 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 130 extern "C" {
Anna Bridge 180:96ed750bd169 131 #endif
Anna Bridge 180:96ed750bd169 132
Anna Bridge 180:96ed750bd169 133 /* check device defines and use defaults */
Anna Bridge 180:96ed750bd169 134 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 180:96ed750bd169 135 #ifndef __SC000_REV
Anna Bridge 180:96ed750bd169 136 #define __SC000_REV 0x0000U
Anna Bridge 180:96ed750bd169 137 #warning "__SC000_REV not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 138 #endif
Anna Bridge 180:96ed750bd169 139
Anna Bridge 180:96ed750bd169 140 #ifndef __MPU_PRESENT
Anna Bridge 180:96ed750bd169 141 #define __MPU_PRESENT 0U
Anna Bridge 180:96ed750bd169 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 143 #endif
Anna Bridge 180:96ed750bd169 144
Anna Bridge 180:96ed750bd169 145 #ifndef __NVIC_PRIO_BITS
Anna Bridge 180:96ed750bd169 146 #define __NVIC_PRIO_BITS 2U
Anna Bridge 180:96ed750bd169 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 148 #endif
Anna Bridge 180:96ed750bd169 149
Anna Bridge 180:96ed750bd169 150 #ifndef __Vendor_SysTickConfig
Anna Bridge 180:96ed750bd169 151 #define __Vendor_SysTickConfig 0U
Anna Bridge 180:96ed750bd169 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 153 #endif
Anna Bridge 180:96ed750bd169 154 #endif
Anna Bridge 180:96ed750bd169 155
Anna Bridge 180:96ed750bd169 156 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 180:96ed750bd169 157 /**
Anna Bridge 180:96ed750bd169 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 180:96ed750bd169 159
Anna Bridge 180:96ed750bd169 160 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 180:96ed750bd169 161 \li to specify the access to peripheral variables.
Anna Bridge 180:96ed750bd169 162 \li for automatic generation of peripheral register debug information.
Anna Bridge 180:96ed750bd169 163 */
Anna Bridge 180:96ed750bd169 164 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 165 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 166 #else
Anna Bridge 180:96ed750bd169 167 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 168 #endif
Anna Bridge 180:96ed750bd169 169 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 180:96ed750bd169 170 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 180:96ed750bd169 171
Anna Bridge 180:96ed750bd169 172 /* following defines should be used for structure members */
Anna Bridge 180:96ed750bd169 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 180:96ed750bd169 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 180:96ed750bd169 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 180:96ed750bd169 176
Anna Bridge 180:96ed750bd169 177 /*@} end of group SC000 */
Anna Bridge 180:96ed750bd169 178
Anna Bridge 180:96ed750bd169 179
Anna Bridge 180:96ed750bd169 180
Anna Bridge 180:96ed750bd169 181 /*******************************************************************************
Anna Bridge 180:96ed750bd169 182 * Register Abstraction
Anna Bridge 180:96ed750bd169 183 Core Register contain:
Anna Bridge 180:96ed750bd169 184 - Core Register
Anna Bridge 180:96ed750bd169 185 - Core NVIC Register
Anna Bridge 180:96ed750bd169 186 - Core SCB Register
Anna Bridge 180:96ed750bd169 187 - Core SysTick Register
Anna Bridge 180:96ed750bd169 188 - Core MPU Register
Anna Bridge 180:96ed750bd169 189 ******************************************************************************/
Anna Bridge 180:96ed750bd169 190 /**
Anna Bridge 180:96ed750bd169 191 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 180:96ed750bd169 192 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 180:96ed750bd169 193 */
Anna Bridge 180:96ed750bd169 194
Anna Bridge 180:96ed750bd169 195 /**
Anna Bridge 180:96ed750bd169 196 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 197 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 180:96ed750bd169 198 \brief Core Register type definitions.
Anna Bridge 180:96ed750bd169 199 @{
Anna Bridge 180:96ed750bd169 200 */
Anna Bridge 180:96ed750bd169 201
Anna Bridge 180:96ed750bd169 202 /**
Anna Bridge 180:96ed750bd169 203 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 180:96ed750bd169 204 */
Anna Bridge 180:96ed750bd169 205 typedef union
Anna Bridge 180:96ed750bd169 206 {
Anna Bridge 180:96ed750bd169 207 struct
Anna Bridge 180:96ed750bd169 208 {
Anna Bridge 180:96ed750bd169 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 180:96ed750bd169 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 214 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 215 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 216 } APSR_Type;
Anna Bridge 180:96ed750bd169 217
Anna Bridge 180:96ed750bd169 218 /* APSR Register Definitions */
Anna Bridge 180:96ed750bd169 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 180:96ed750bd169 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 180:96ed750bd169 221
Anna Bridge 180:96ed750bd169 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 180:96ed750bd169 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 180:96ed750bd169 224
Anna Bridge 180:96ed750bd169 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 180:96ed750bd169 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 180:96ed750bd169 227
Anna Bridge 180:96ed750bd169 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 180:96ed750bd169 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 180:96ed750bd169 230
Anna Bridge 180:96ed750bd169 231
Anna Bridge 180:96ed750bd169 232 /**
Anna Bridge 180:96ed750bd169 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 180:96ed750bd169 234 */
Anna Bridge 180:96ed750bd169 235 typedef union
Anna Bridge 180:96ed750bd169 236 {
Anna Bridge 180:96ed750bd169 237 struct
Anna Bridge 180:96ed750bd169 238 {
Anna Bridge 180:96ed750bd169 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 180:96ed750bd169 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 180:96ed750bd169 241 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 242 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 243 } IPSR_Type;
Anna Bridge 180:96ed750bd169 244
Anna Bridge 180:96ed750bd169 245 /* IPSR Register Definitions */
Anna Bridge 180:96ed750bd169 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 180:96ed750bd169 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 180:96ed750bd169 248
Anna Bridge 180:96ed750bd169 249
Anna Bridge 180:96ed750bd169 250 /**
Anna Bridge 180:96ed750bd169 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 180:96ed750bd169 252 */
Anna Bridge 180:96ed750bd169 253 typedef union
Anna Bridge 180:96ed750bd169 254 {
Anna Bridge 180:96ed750bd169 255 struct
Anna Bridge 180:96ed750bd169 256 {
Anna Bridge 180:96ed750bd169 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 180:96ed750bd169 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 180:96ed750bd169 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 180:96ed750bd169 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 180:96ed750bd169 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 265 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 266 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 267 } xPSR_Type;
Anna Bridge 180:96ed750bd169 268
Anna Bridge 180:96ed750bd169 269 /* xPSR Register Definitions */
Anna Bridge 180:96ed750bd169 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 180:96ed750bd169 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 180:96ed750bd169 272
Anna Bridge 180:96ed750bd169 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 180:96ed750bd169 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 180:96ed750bd169 275
Anna Bridge 180:96ed750bd169 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 180:96ed750bd169 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 180:96ed750bd169 278
Anna Bridge 180:96ed750bd169 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 180:96ed750bd169 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 180:96ed750bd169 281
Anna Bridge 180:96ed750bd169 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 180:96ed750bd169 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 180:96ed750bd169 284
Anna Bridge 180:96ed750bd169 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 180:96ed750bd169 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 180:96ed750bd169 287
Anna Bridge 180:96ed750bd169 288
Anna Bridge 180:96ed750bd169 289 /**
Anna Bridge 180:96ed750bd169 290 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 180:96ed750bd169 291 */
Anna Bridge 180:96ed750bd169 292 typedef union
Anna Bridge 180:96ed750bd169 293 {
Anna Bridge 180:96ed750bd169 294 struct
Anna Bridge 180:96ed750bd169 295 {
Anna Bridge 180:96ed750bd169 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Anna Bridge 180:96ed750bd169 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Anna Bridge 180:96ed750bd169 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 180:96ed750bd169 299 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 300 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 301 } CONTROL_Type;
Anna Bridge 180:96ed750bd169 302
Anna Bridge 180:96ed750bd169 303 /* CONTROL Register Definitions */
Anna Bridge 180:96ed750bd169 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 180:96ed750bd169 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 180:96ed750bd169 306
Anna Bridge 180:96ed750bd169 307 /*@} end of group CMSIS_CORE */
Anna Bridge 180:96ed750bd169 308
Anna Bridge 180:96ed750bd169 309
Anna Bridge 180:96ed750bd169 310 /**
Anna Bridge 180:96ed750bd169 311 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 180:96ed750bd169 313 \brief Type definitions for the NVIC Registers
Anna Bridge 180:96ed750bd169 314 @{
Anna Bridge 180:96ed750bd169 315 */
Anna Bridge 180:96ed750bd169 316
Anna Bridge 180:96ed750bd169 317 /**
Anna Bridge 180:96ed750bd169 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 180:96ed750bd169 319 */
Anna Bridge 180:96ed750bd169 320 typedef struct
Anna Bridge 180:96ed750bd169 321 {
Anna Bridge 180:96ed750bd169 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 180:96ed750bd169 323 uint32_t RESERVED0[31U];
Anna Bridge 180:96ed750bd169 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 180:96ed750bd169 325 uint32_t RSERVED1[31U];
Anna Bridge 180:96ed750bd169 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 180:96ed750bd169 327 uint32_t RESERVED2[31U];
Anna Bridge 180:96ed750bd169 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 180:96ed750bd169 329 uint32_t RESERVED3[31U];
Anna Bridge 180:96ed750bd169 330 uint32_t RESERVED4[64U];
Anna Bridge 180:96ed750bd169 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 180:96ed750bd169 332 } NVIC_Type;
Anna Bridge 180:96ed750bd169 333
Anna Bridge 180:96ed750bd169 334 /*@} end of group CMSIS_NVIC */
Anna Bridge 180:96ed750bd169 335
Anna Bridge 180:96ed750bd169 336
Anna Bridge 180:96ed750bd169 337 /**
Anna Bridge 180:96ed750bd169 338 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 339 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 180:96ed750bd169 340 \brief Type definitions for the System Control Block Registers
Anna Bridge 180:96ed750bd169 341 @{
Anna Bridge 180:96ed750bd169 342 */
Anna Bridge 180:96ed750bd169 343
Anna Bridge 180:96ed750bd169 344 /**
Anna Bridge 180:96ed750bd169 345 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 180:96ed750bd169 346 */
Anna Bridge 180:96ed750bd169 347 typedef struct
Anna Bridge 180:96ed750bd169 348 {
Anna Bridge 180:96ed750bd169 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 180:96ed750bd169 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 180:96ed750bd169 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 180:96ed750bd169 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 180:96ed750bd169 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 180:96ed750bd169 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 180:96ed750bd169 355 uint32_t RESERVED0[1U];
Anna Bridge 180:96ed750bd169 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 180:96ed750bd169 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 180:96ed750bd169 358 uint32_t RESERVED1[154U];
Anna Bridge 180:96ed750bd169 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Anna Bridge 180:96ed750bd169 360 } SCB_Type;
Anna Bridge 180:96ed750bd169 361
Anna Bridge 180:96ed750bd169 362 /* SCB CPUID Register Definitions */
Anna Bridge 180:96ed750bd169 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 180:96ed750bd169 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 180:96ed750bd169 365
Anna Bridge 180:96ed750bd169 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 180:96ed750bd169 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 180:96ed750bd169 368
Anna Bridge 180:96ed750bd169 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 180:96ed750bd169 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 180:96ed750bd169 371
Anna Bridge 180:96ed750bd169 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 180:96ed750bd169 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 180:96ed750bd169 374
Anna Bridge 180:96ed750bd169 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 180:96ed750bd169 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 180:96ed750bd169 377
Anna Bridge 180:96ed750bd169 378 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 180:96ed750bd169 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 180:96ed750bd169 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 180:96ed750bd169 381
Anna Bridge 180:96ed750bd169 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 180:96ed750bd169 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 180:96ed750bd169 384
Anna Bridge 180:96ed750bd169 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 180:96ed750bd169 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 180:96ed750bd169 387
Anna Bridge 180:96ed750bd169 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 180:96ed750bd169 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 180:96ed750bd169 390
Anna Bridge 180:96ed750bd169 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 180:96ed750bd169 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 180:96ed750bd169 393
Anna Bridge 180:96ed750bd169 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 180:96ed750bd169 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 180:96ed750bd169 396
Anna Bridge 180:96ed750bd169 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 180:96ed750bd169 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 180:96ed750bd169 399
Anna Bridge 180:96ed750bd169 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 180:96ed750bd169 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 180:96ed750bd169 402
Anna Bridge 180:96ed750bd169 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 180:96ed750bd169 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 180:96ed750bd169 405
Anna Bridge 180:96ed750bd169 406 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 180:96ed750bd169 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 180:96ed750bd169 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 180:96ed750bd169 409
Anna Bridge 180:96ed750bd169 410 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 180:96ed750bd169 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 180:96ed750bd169 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 180:96ed750bd169 413
Anna Bridge 180:96ed750bd169 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 180:96ed750bd169 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 180:96ed750bd169 416
Anna Bridge 180:96ed750bd169 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 180:96ed750bd169 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 180:96ed750bd169 419
Anna Bridge 180:96ed750bd169 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 180:96ed750bd169 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 180:96ed750bd169 422
Anna Bridge 180:96ed750bd169 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 180:96ed750bd169 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 180:96ed750bd169 425
Anna Bridge 180:96ed750bd169 426 /* SCB System Control Register Definitions */
Anna Bridge 180:96ed750bd169 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 180:96ed750bd169 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 180:96ed750bd169 429
Anna Bridge 180:96ed750bd169 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 180:96ed750bd169 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 180:96ed750bd169 432
Anna Bridge 180:96ed750bd169 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 180:96ed750bd169 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 180:96ed750bd169 435
Anna Bridge 180:96ed750bd169 436 /* SCB Configuration Control Register Definitions */
Anna Bridge 180:96ed750bd169 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Anna Bridge 180:96ed750bd169 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 180:96ed750bd169 439
Anna Bridge 180:96ed750bd169 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 180:96ed750bd169 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 180:96ed750bd169 442
Anna Bridge 180:96ed750bd169 443 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 180:96ed750bd169 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 180:96ed750bd169 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 180:96ed750bd169 446
Anna Bridge 180:96ed750bd169 447 /*@} end of group CMSIS_SCB */
Anna Bridge 180:96ed750bd169 448
Anna Bridge 180:96ed750bd169 449
Anna Bridge 180:96ed750bd169 450 /**
Anna Bridge 180:96ed750bd169 451 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge 180:96ed750bd169 453 \brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge 180:96ed750bd169 454 @{
Anna Bridge 180:96ed750bd169 455 */
Anna Bridge 180:96ed750bd169 456
Anna Bridge 180:96ed750bd169 457 /**
Anna Bridge 180:96ed750bd169 458 \brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge 180:96ed750bd169 459 */
Anna Bridge 180:96ed750bd169 460 typedef struct
Anna Bridge 180:96ed750bd169 461 {
Anna Bridge 180:96ed750bd169 462 uint32_t RESERVED0[2U];
Anna Bridge 180:96ed750bd169 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Anna Bridge 180:96ed750bd169 464 } SCnSCB_Type;
Anna Bridge 180:96ed750bd169 465
Anna Bridge 180:96ed750bd169 466 /* Auxiliary Control Register Definitions */
Anna Bridge 180:96ed750bd169 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Anna Bridge 180:96ed750bd169 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Anna Bridge 180:96ed750bd169 469
Anna Bridge 180:96ed750bd169 470 /*@} end of group CMSIS_SCnotSCB */
Anna Bridge 180:96ed750bd169 471
Anna Bridge 180:96ed750bd169 472
Anna Bridge 180:96ed750bd169 473 /**
Anna Bridge 180:96ed750bd169 474 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 180:96ed750bd169 476 \brief Type definitions for the System Timer Registers.
Anna Bridge 180:96ed750bd169 477 @{
Anna Bridge 180:96ed750bd169 478 */
Anna Bridge 180:96ed750bd169 479
Anna Bridge 180:96ed750bd169 480 /**
Anna Bridge 180:96ed750bd169 481 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 180:96ed750bd169 482 */
Anna Bridge 180:96ed750bd169 483 typedef struct
Anna Bridge 180:96ed750bd169 484 {
Anna Bridge 180:96ed750bd169 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 180:96ed750bd169 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 180:96ed750bd169 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 180:96ed750bd169 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 180:96ed750bd169 489 } SysTick_Type;
Anna Bridge 180:96ed750bd169 490
Anna Bridge 180:96ed750bd169 491 /* SysTick Control / Status Register Definitions */
Anna Bridge 180:96ed750bd169 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 180:96ed750bd169 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 180:96ed750bd169 494
Anna Bridge 180:96ed750bd169 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 180:96ed750bd169 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 180:96ed750bd169 497
Anna Bridge 180:96ed750bd169 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 180:96ed750bd169 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 180:96ed750bd169 500
Anna Bridge 180:96ed750bd169 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 503
Anna Bridge 180:96ed750bd169 504 /* SysTick Reload Register Definitions */
Anna Bridge 180:96ed750bd169 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 180:96ed750bd169 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 180:96ed750bd169 507
Anna Bridge 180:96ed750bd169 508 /* SysTick Current Register Definitions */
Anna Bridge 180:96ed750bd169 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 180:96ed750bd169 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 180:96ed750bd169 511
Anna Bridge 180:96ed750bd169 512 /* SysTick Calibration Register Definitions */
Anna Bridge 180:96ed750bd169 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 180:96ed750bd169 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 180:96ed750bd169 515
Anna Bridge 180:96ed750bd169 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 180:96ed750bd169 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 180:96ed750bd169 518
Anna Bridge 180:96ed750bd169 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 180:96ed750bd169 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 180:96ed750bd169 521
Anna Bridge 180:96ed750bd169 522 /*@} end of group CMSIS_SysTick */
Anna Bridge 180:96ed750bd169 523
Anna Bridge 180:96ed750bd169 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 525 /**
Anna Bridge 180:96ed750bd169 526 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 180:96ed750bd169 528 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 180:96ed750bd169 529 @{
Anna Bridge 180:96ed750bd169 530 */
Anna Bridge 180:96ed750bd169 531
Anna Bridge 180:96ed750bd169 532 /**
Anna Bridge 180:96ed750bd169 533 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 180:96ed750bd169 534 */
Anna Bridge 180:96ed750bd169 535 typedef struct
Anna Bridge 180:96ed750bd169 536 {
Anna Bridge 180:96ed750bd169 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 180:96ed750bd169 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 180:96ed750bd169 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Anna Bridge 180:96ed750bd169 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 180:96ed750bd169 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 180:96ed750bd169 542 } MPU_Type;
Anna Bridge 180:96ed750bd169 543
Anna Bridge 180:96ed750bd169 544 /* MPU Type Register Definitions */
Anna Bridge 180:96ed750bd169 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 180:96ed750bd169 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 180:96ed750bd169 547
Anna Bridge 180:96ed750bd169 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 180:96ed750bd169 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 180:96ed750bd169 550
Anna Bridge 180:96ed750bd169 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 180:96ed750bd169 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 180:96ed750bd169 553
Anna Bridge 180:96ed750bd169 554 /* MPU Control Register Definitions */
Anna Bridge 180:96ed750bd169 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 180:96ed750bd169 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 180:96ed750bd169 557
Anna Bridge 180:96ed750bd169 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 180:96ed750bd169 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 180:96ed750bd169 560
Anna Bridge 180:96ed750bd169 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 563
Anna Bridge 180:96ed750bd169 564 /* MPU Region Number Register Definitions */
Anna Bridge 180:96ed750bd169 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 180:96ed750bd169 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 180:96ed750bd169 567
Anna Bridge 180:96ed750bd169 568 /* MPU Region Base Address Register Definitions */
Anna Bridge 180:96ed750bd169 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Anna Bridge 180:96ed750bd169 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 180:96ed750bd169 571
Anna Bridge 180:96ed750bd169 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Anna Bridge 180:96ed750bd169 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 180:96ed750bd169 574
Anna Bridge 180:96ed750bd169 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Anna Bridge 180:96ed750bd169 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 180:96ed750bd169 577
Anna Bridge 180:96ed750bd169 578 /* MPU Region Attribute and Size Register Definitions */
Anna Bridge 180:96ed750bd169 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 180:96ed750bd169 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 180:96ed750bd169 581
Anna Bridge 180:96ed750bd169 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 180:96ed750bd169 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 180:96ed750bd169 584
Anna Bridge 180:96ed750bd169 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 180:96ed750bd169 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 180:96ed750bd169 587
Anna Bridge 180:96ed750bd169 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 180:96ed750bd169 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 180:96ed750bd169 590
Anna Bridge 180:96ed750bd169 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 180:96ed750bd169 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 180:96ed750bd169 593
Anna Bridge 180:96ed750bd169 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 180:96ed750bd169 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 180:96ed750bd169 596
Anna Bridge 180:96ed750bd169 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 180:96ed750bd169 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 180:96ed750bd169 599
Anna Bridge 180:96ed750bd169 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 180:96ed750bd169 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 180:96ed750bd169 602
Anna Bridge 180:96ed750bd169 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Anna Bridge 180:96ed750bd169 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 180:96ed750bd169 605
Anna Bridge 180:96ed750bd169 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Anna Bridge 180:96ed750bd169 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 180:96ed750bd169 608
Anna Bridge 180:96ed750bd169 609 /*@} end of group CMSIS_MPU */
Anna Bridge 180:96ed750bd169 610 #endif
Anna Bridge 180:96ed750bd169 611
Anna Bridge 180:96ed750bd169 612
Anna Bridge 180:96ed750bd169 613 /**
Anna Bridge 180:96ed750bd169 614 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 180:96ed750bd169 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Anna Bridge 180:96ed750bd169 617 Therefore they are not covered by the SC000 header file.
Anna Bridge 180:96ed750bd169 618 @{
Anna Bridge 180:96ed750bd169 619 */
Anna Bridge 180:96ed750bd169 620 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 180:96ed750bd169 621
Anna Bridge 180:96ed750bd169 622
Anna Bridge 180:96ed750bd169 623 /**
Anna Bridge 180:96ed750bd169 624 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 625 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 180:96ed750bd169 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 180:96ed750bd169 627 @{
Anna Bridge 180:96ed750bd169 628 */
Anna Bridge 180:96ed750bd169 629
Anna Bridge 180:96ed750bd169 630 /**
Anna Bridge 180:96ed750bd169 631 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 180:96ed750bd169 632 \param[in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 634 \return Masked and shifted value.
Anna Bridge 180:96ed750bd169 635 */
Anna Bridge 180:96ed750bd169 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 180:96ed750bd169 637
Anna Bridge 180:96ed750bd169 638 /**
Anna Bridge 180:96ed750bd169 639 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 180:96ed750bd169 640 \param[in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 642 \return Masked and shifted bit field value.
Anna Bridge 180:96ed750bd169 643 */
Anna Bridge 180:96ed750bd169 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 180:96ed750bd169 645
Anna Bridge 180:96ed750bd169 646 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 180:96ed750bd169 647
Anna Bridge 180:96ed750bd169 648
Anna Bridge 180:96ed750bd169 649 /**
Anna Bridge 180:96ed750bd169 650 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 651 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 180:96ed750bd169 652 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 180:96ed750bd169 653 @{
Anna Bridge 180:96ed750bd169 654 */
Anna Bridge 180:96ed750bd169 655
Anna Bridge 180:96ed750bd169 656 /* Memory mapping of Core Hardware */
Anna Bridge 180:96ed750bd169 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 180:96ed750bd169 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 180:96ed750bd169 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 180:96ed750bd169 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 180:96ed750bd169 661
Anna Bridge 180:96ed750bd169 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Anna Bridge 180:96ed750bd169 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 180:96ed750bd169 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 180:96ed750bd169 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 180:96ed750bd169 666
Anna Bridge 180:96ed750bd169 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 180:96ed750bd169 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 180:96ed750bd169 670 #endif
Anna Bridge 180:96ed750bd169 671
Anna Bridge 180:96ed750bd169 672 /*@} */
Anna Bridge 180:96ed750bd169 673
Anna Bridge 180:96ed750bd169 674
Anna Bridge 180:96ed750bd169 675
Anna Bridge 180:96ed750bd169 676 /*******************************************************************************
Anna Bridge 180:96ed750bd169 677 * Hardware Abstraction Layer
Anna Bridge 180:96ed750bd169 678 Core Function Interface contains:
Anna Bridge 180:96ed750bd169 679 - Core NVIC Functions
Anna Bridge 180:96ed750bd169 680 - Core SysTick Functions
Anna Bridge 180:96ed750bd169 681 - Core Register Access Functions
Anna Bridge 180:96ed750bd169 682 ******************************************************************************/
Anna Bridge 180:96ed750bd169 683 /**
Anna Bridge 180:96ed750bd169 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 180:96ed750bd169 685 */
Anna Bridge 180:96ed750bd169 686
Anna Bridge 180:96ed750bd169 687
Anna Bridge 180:96ed750bd169 688
Anna Bridge 180:96ed750bd169 689 /* ########################## NVIC functions #################################### */
Anna Bridge 180:96ed750bd169 690 /**
Anna Bridge 180:96ed750bd169 691 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 180:96ed750bd169 693 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 180:96ed750bd169 694 @{
Anna Bridge 180:96ed750bd169 695 */
Anna Bridge 180:96ed750bd169 696
Anna Bridge 180:96ed750bd169 697 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 180:96ed750bd169 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 180:96ed750bd169 700 #endif
Anna Bridge 180:96ed750bd169 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 702 #else
Anna Bridge 180:96ed750bd169 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
Anna Bridge 180:96ed750bd169 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
Anna Bridge 180:96ed750bd169 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 180:96ed750bd169 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 180:96ed750bd169 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 180:96ed750bd169 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 180:96ed750bd169 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 180:96ed750bd169 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 180:96ed750bd169 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
Anna Bridge 180:96ed750bd169 712 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 180:96ed750bd169 713 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 180:96ed750bd169 714 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 180:96ed750bd169 715 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 180:96ed750bd169 716
Anna Bridge 180:96ed750bd169 717 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 180:96ed750bd169 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 180:96ed750bd169 720 #endif
Anna Bridge 180:96ed750bd169 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 722 #else
Anna Bridge 180:96ed750bd169 723 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 180:96ed750bd169 724 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 180:96ed750bd169 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 180:96ed750bd169 726
Anna Bridge 180:96ed750bd169 727 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 180:96ed750bd169 728
Anna Bridge 180:96ed750bd169 729
AnnaBridge 188:bcfe06ba3d64 730 /* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge 188:bcfe06ba3d64 731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge 188:bcfe06ba3d64 732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge 188:bcfe06ba3d64 733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge 188:bcfe06ba3d64 734
AnnaBridge 188:bcfe06ba3d64 735
Anna Bridge 186:707f6e361f3e 736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
Anna Bridge 180:96ed750bd169 737 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 180:96ed750bd169 738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 180:96ed750bd169 739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 180:96ed750bd169 740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 180:96ed750bd169 741
Anna Bridge 180:96ed750bd169 742
Anna Bridge 180:96ed750bd169 743 /**
Anna Bridge 180:96ed750bd169 744 \brief Enable Interrupt
Anna Bridge 180:96ed750bd169 745 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 746 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 747 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 748 */
Anna Bridge 180:96ed750bd169 749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 750 {
Anna Bridge 180:96ed750bd169 751 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 752 {
Anna Bridge 186:707f6e361f3e 753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 754 }
Anna Bridge 180:96ed750bd169 755 }
Anna Bridge 180:96ed750bd169 756
Anna Bridge 180:96ed750bd169 757
Anna Bridge 180:96ed750bd169 758 /**
Anna Bridge 180:96ed750bd169 759 \brief Get Interrupt Enable status
Anna Bridge 180:96ed750bd169 760 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 761 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 762 \return 0 Interrupt is not enabled.
Anna Bridge 180:96ed750bd169 763 \return 1 Interrupt is enabled.
Anna Bridge 180:96ed750bd169 764 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 765 */
Anna Bridge 180:96ed750bd169 766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 767 {
Anna Bridge 180:96ed750bd169 768 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 769 {
Anna Bridge 186:707f6e361f3e 770 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 771 }
Anna Bridge 180:96ed750bd169 772 else
Anna Bridge 180:96ed750bd169 773 {
Anna Bridge 180:96ed750bd169 774 return(0U);
Anna Bridge 180:96ed750bd169 775 }
Anna Bridge 180:96ed750bd169 776 }
Anna Bridge 180:96ed750bd169 777
Anna Bridge 180:96ed750bd169 778
Anna Bridge 180:96ed750bd169 779 /**
Anna Bridge 180:96ed750bd169 780 \brief Disable Interrupt
Anna Bridge 180:96ed750bd169 781 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 782 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 783 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 784 */
Anna Bridge 180:96ed750bd169 785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 786 {
Anna Bridge 180:96ed750bd169 787 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 788 {
Anna Bridge 186:707f6e361f3e 789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 790 __DSB();
Anna Bridge 180:96ed750bd169 791 __ISB();
Anna Bridge 180:96ed750bd169 792 }
Anna Bridge 180:96ed750bd169 793 }
Anna Bridge 180:96ed750bd169 794
Anna Bridge 180:96ed750bd169 795
Anna Bridge 180:96ed750bd169 796 /**
Anna Bridge 180:96ed750bd169 797 \brief Get Pending Interrupt
Anna Bridge 180:96ed750bd169 798 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 180:96ed750bd169 799 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 800 \return 0 Interrupt status is not pending.
Anna Bridge 180:96ed750bd169 801 \return 1 Interrupt status is pending.
Anna Bridge 180:96ed750bd169 802 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 803 */
Anna Bridge 180:96ed750bd169 804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 805 {
Anna Bridge 180:96ed750bd169 806 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 807 {
Anna Bridge 186:707f6e361f3e 808 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 809 }
Anna Bridge 180:96ed750bd169 810 else
Anna Bridge 180:96ed750bd169 811 {
Anna Bridge 180:96ed750bd169 812 return(0U);
Anna Bridge 180:96ed750bd169 813 }
Anna Bridge 180:96ed750bd169 814 }
Anna Bridge 180:96ed750bd169 815
Anna Bridge 180:96ed750bd169 816
Anna Bridge 180:96ed750bd169 817 /**
Anna Bridge 180:96ed750bd169 818 \brief Set Pending Interrupt
Anna Bridge 180:96ed750bd169 819 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 180:96ed750bd169 820 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 821 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 822 */
Anna Bridge 180:96ed750bd169 823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 824 {
Anna Bridge 180:96ed750bd169 825 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 826 {
Anna Bridge 186:707f6e361f3e 827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 828 }
Anna Bridge 180:96ed750bd169 829 }
Anna Bridge 180:96ed750bd169 830
Anna Bridge 180:96ed750bd169 831
Anna Bridge 180:96ed750bd169 832 /**
Anna Bridge 180:96ed750bd169 833 \brief Clear Pending Interrupt
Anna Bridge 180:96ed750bd169 834 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 180:96ed750bd169 835 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 836 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 837 */
Anna Bridge 180:96ed750bd169 838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 839 {
Anna Bridge 180:96ed750bd169 840 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 841 {
Anna Bridge 186:707f6e361f3e 842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 843 }
Anna Bridge 180:96ed750bd169 844 }
Anna Bridge 180:96ed750bd169 845
Anna Bridge 180:96ed750bd169 846
Anna Bridge 180:96ed750bd169 847 /**
Anna Bridge 180:96ed750bd169 848 \brief Set Interrupt Priority
Anna Bridge 180:96ed750bd169 849 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 180:96ed750bd169 850 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 851 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 852 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 853 \param [in] priority Priority to set.
Anna Bridge 180:96ed750bd169 854 \note The priority cannot be set for every processor exception.
Anna Bridge 180:96ed750bd169 855 */
Anna Bridge 180:96ed750bd169 856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 180:96ed750bd169 857 {
Anna Bridge 180:96ed750bd169 858 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 859 {
Anna Bridge 180:96ed750bd169 860 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 861 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 862 }
Anna Bridge 180:96ed750bd169 863 else
Anna Bridge 180:96ed750bd169 864 {
Anna Bridge 180:96ed750bd169 865 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 866 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 867 }
Anna Bridge 180:96ed750bd169 868 }
Anna Bridge 180:96ed750bd169 869
Anna Bridge 180:96ed750bd169 870
Anna Bridge 180:96ed750bd169 871 /**
Anna Bridge 180:96ed750bd169 872 \brief Get Interrupt Priority
Anna Bridge 180:96ed750bd169 873 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 180:96ed750bd169 874 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 875 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 876 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 877 \return Interrupt Priority.
Anna Bridge 180:96ed750bd169 878 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 180:96ed750bd169 879 */
Anna Bridge 180:96ed750bd169 880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 881 {
Anna Bridge 180:96ed750bd169 882
Anna Bridge 180:96ed750bd169 883 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 884 {
Anna Bridge 180:96ed750bd169 885 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 886 }
Anna Bridge 180:96ed750bd169 887 else
Anna Bridge 180:96ed750bd169 888 {
Anna Bridge 180:96ed750bd169 889 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 890 }
Anna Bridge 180:96ed750bd169 891 }
Anna Bridge 180:96ed750bd169 892
Anna Bridge 180:96ed750bd169 893
Anna Bridge 180:96ed750bd169 894 /**
Anna Bridge 180:96ed750bd169 895 \brief Set Interrupt Vector
Anna Bridge 180:96ed750bd169 896 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 180:96ed750bd169 897 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 898 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 899 VTOR must been relocated to SRAM before.
Anna Bridge 180:96ed750bd169 900 \param [in] IRQn Interrupt number
Anna Bridge 180:96ed750bd169 901 \param [in] vector Address of interrupt handler function
Anna Bridge 180:96ed750bd169 902 */
Anna Bridge 180:96ed750bd169 903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 180:96ed750bd169 904 {
Anna Bridge 180:96ed750bd169 905 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 180:96ed750bd169 906 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 180:96ed750bd169 907 }
Anna Bridge 180:96ed750bd169 908
Anna Bridge 180:96ed750bd169 909
Anna Bridge 180:96ed750bd169 910 /**
Anna Bridge 180:96ed750bd169 911 \brief Get Interrupt Vector
Anna Bridge 180:96ed750bd169 912 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 180:96ed750bd169 913 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 914 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 915 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 916 \return Address of interrupt handler function
Anna Bridge 180:96ed750bd169 917 */
Anna Bridge 180:96ed750bd169 918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 919 {
Anna Bridge 180:96ed750bd169 920 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 180:96ed750bd169 921 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 180:96ed750bd169 922 }
Anna Bridge 180:96ed750bd169 923
Anna Bridge 180:96ed750bd169 924
Anna Bridge 180:96ed750bd169 925 /**
Anna Bridge 180:96ed750bd169 926 \brief System Reset
Anna Bridge 180:96ed750bd169 927 \details Initiates a system reset request to reset the MCU.
Anna Bridge 180:96ed750bd169 928 */
AnnaBridge 188:bcfe06ba3d64 929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 180:96ed750bd169 930 {
Anna Bridge 180:96ed750bd169 931 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 180:96ed750bd169 932 buffered write are completed before reset */
Anna Bridge 180:96ed750bd169 933 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 180:96ed750bd169 934 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 180:96ed750bd169 935 __DSB(); /* Ensure completion of memory access */
Anna Bridge 180:96ed750bd169 936
Anna Bridge 180:96ed750bd169 937 for(;;) /* wait until reset */
Anna Bridge 180:96ed750bd169 938 {
Anna Bridge 180:96ed750bd169 939 __NOP();
Anna Bridge 180:96ed750bd169 940 }
Anna Bridge 180:96ed750bd169 941 }
Anna Bridge 180:96ed750bd169 942
Anna Bridge 180:96ed750bd169 943 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 180:96ed750bd169 944
Anna Bridge 180:96ed750bd169 945
Anna Bridge 180:96ed750bd169 946 /* ########################## FPU functions #################################### */
Anna Bridge 180:96ed750bd169 947 /**
Anna Bridge 180:96ed750bd169 948 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 949 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 180:96ed750bd169 950 \brief Function that provides FPU type.
Anna Bridge 180:96ed750bd169 951 @{
Anna Bridge 180:96ed750bd169 952 */
Anna Bridge 180:96ed750bd169 953
Anna Bridge 180:96ed750bd169 954 /**
Anna Bridge 180:96ed750bd169 955 \brief get FPU type
Anna Bridge 180:96ed750bd169 956 \details returns the FPU type
Anna Bridge 180:96ed750bd169 957 \returns
Anna Bridge 180:96ed750bd169 958 - \b 0: No FPU
Anna Bridge 180:96ed750bd169 959 - \b 1: Single precision FPU
Anna Bridge 180:96ed750bd169 960 - \b 2: Double + Single precision FPU
Anna Bridge 180:96ed750bd169 961 */
Anna Bridge 180:96ed750bd169 962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 180:96ed750bd169 963 {
Anna Bridge 180:96ed750bd169 964 return 0U; /* No FPU */
Anna Bridge 180:96ed750bd169 965 }
Anna Bridge 180:96ed750bd169 966
Anna Bridge 180:96ed750bd169 967
Anna Bridge 180:96ed750bd169 968 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 180:96ed750bd169 969
Anna Bridge 180:96ed750bd169 970
Anna Bridge 180:96ed750bd169 971
Anna Bridge 180:96ed750bd169 972 /* ################################## SysTick function ############################################ */
Anna Bridge 180:96ed750bd169 973 /**
Anna Bridge 180:96ed750bd169 974 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 975 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 180:96ed750bd169 976 \brief Functions that configure the System.
Anna Bridge 180:96ed750bd169 977 @{
Anna Bridge 180:96ed750bd169 978 */
Anna Bridge 180:96ed750bd169 979
Anna Bridge 180:96ed750bd169 980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 180:96ed750bd169 981
Anna Bridge 180:96ed750bd169 982 /**
Anna Bridge 180:96ed750bd169 983 \brief System Tick Configuration
Anna Bridge 180:96ed750bd169 984 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 180:96ed750bd169 985 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 180:96ed750bd169 986 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 180:96ed750bd169 987 \return 0 Function succeeded.
Anna Bridge 180:96ed750bd169 988 \return 1 Function failed.
Anna Bridge 180:96ed750bd169 989 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 180:96ed750bd169 990 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 180:96ed750bd169 991 must contain a vendor-specific implementation of this function.
Anna Bridge 180:96ed750bd169 992 */
Anna Bridge 180:96ed750bd169 993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 180:96ed750bd169 994 {
Anna Bridge 180:96ed750bd169 995 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 180:96ed750bd169 996 {
Anna Bridge 180:96ed750bd169 997 return (1UL); /* Reload value impossible */
Anna Bridge 180:96ed750bd169 998 }
Anna Bridge 180:96ed750bd169 999
Anna Bridge 180:96ed750bd169 1000 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 180:96ed750bd169 1001 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 180:96ed750bd169 1002 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 180:96ed750bd169 1003 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 180:96ed750bd169 1004 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 180:96ed750bd169 1005 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 180:96ed750bd169 1006 return (0UL); /* Function successful */
Anna Bridge 180:96ed750bd169 1007 }
Anna Bridge 180:96ed750bd169 1008
Anna Bridge 180:96ed750bd169 1009 #endif
Anna Bridge 180:96ed750bd169 1010
Anna Bridge 180:96ed750bd169 1011 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 180:96ed750bd169 1012
Anna Bridge 180:96ed750bd169 1013
Anna Bridge 180:96ed750bd169 1014
Anna Bridge 180:96ed750bd169 1015
Anna Bridge 180:96ed750bd169 1016 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 1017 }
Anna Bridge 180:96ed750bd169 1018 #endif
Anna Bridge 180:96ed750bd169 1019
Anna Bridge 180:96ed750bd169 1020 #endif /* __CORE_SC000_H_DEPENDANT */
Anna Bridge 180:96ed750bd169 1021
Anna Bridge 180:96ed750bd169 1022 #endif /* __CMSIS_GENERIC */