mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_M/core_cm7.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 188:bcfe06ba3d64

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
Anna Bridge	180:96ed750bd169	1	/************************************************************************//
Anna Bridge	180:96ed750bd169	2	* @file core_cm7.h
Anna Bridge	180:96ed750bd169	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
AnnaBridge	188:bcfe06ba3d64	4	* @version V5.0.8
AnnaBridge	188:bcfe06ba3d64	5	* @date 04. June 2018
Anna Bridge	180:96ed750bd169	6	******************************************************************************/
Anna Bridge	180:96ed750bd169	7	/*
AnnaBridge	188:bcfe06ba3d64	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge	180:96ed750bd169	9	*
Anna Bridge	180:96ed750bd169	10	* SPDX-License-Identifier: Apache-2.0
Anna Bridge	180:96ed750bd169	11	*
Anna Bridge	180:96ed750bd169	12	* Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge	180:96ed750bd169	13	* not use this file except in compliance with the License.
Anna Bridge	180:96ed750bd169	14	* You may obtain a copy of the License at
Anna Bridge	180:96ed750bd169	15	*
Anna Bridge	180:96ed750bd169	16	* www.apache.org/licenses/LICENSE-2.0
Anna Bridge	180:96ed750bd169	17	*
Anna Bridge	180:96ed750bd169	18	* Unless required by applicable law or agreed to in writing, software
Anna Bridge	180:96ed750bd169	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge	180:96ed750bd169	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge	180:96ed750bd169	21	* See the License for the specific language governing permissions and
Anna Bridge	180:96ed750bd169	22	* limitations under the License.
Anna Bridge	180:96ed750bd169	23	*/
Anna Bridge	180:96ed750bd169	24
Anna Bridge	180:96ed750bd169	25	#if defined ( __ICCARM__ )
Anna Bridge	186:707f6e361f3e	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	186:707f6e361f3e	27	#elif defined (__clang__)
Anna Bridge	180:96ed750bd169	28	#pragma clang system_header /* treat file as system include file */
Anna Bridge	180:96ed750bd169	29	#endif
Anna Bridge	180:96ed750bd169	30
Anna Bridge	180:96ed750bd169	31	#ifndef __CORE_CM7_H_GENERIC
Anna Bridge	180:96ed750bd169	32	#define __CORE_CM7_H_GENERIC
Anna Bridge	180:96ed750bd169	33
Anna Bridge	180:96ed750bd169	34	#include <stdint.h>
Anna Bridge	180:96ed750bd169	35
Anna Bridge	180:96ed750bd169	36	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	37	extern "C" {
Anna Bridge	180:96ed750bd169	38	#endif
Anna Bridge	180:96ed750bd169	39
Anna Bridge	180:96ed750bd169	40	/**
Anna Bridge	180:96ed750bd169	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge	180:96ed750bd169	42	CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge	180:96ed750bd169	43
Anna Bridge	180:96ed750bd169	44	\li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge	180:96ed750bd169	45	Function definitions in header files are used to allow 'inlining'.
Anna Bridge	180:96ed750bd169	46
Anna Bridge	180:96ed750bd169	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge	180:96ed750bd169	48	Unions are used for effective representation of core registers.
Anna Bridge	180:96ed750bd169	49
Anna Bridge	180:96ed750bd169	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge	180:96ed750bd169	51	Function-like macros are used to allow more efficient code.
Anna Bridge	180:96ed750bd169	52	*/
Anna Bridge	180:96ed750bd169	53
Anna Bridge	180:96ed750bd169	54
Anna Bridge	180:96ed750bd169	55	/*******************************************************************************
Anna Bridge	180:96ed750bd169	56	* CMSIS definitions
Anna Bridge	180:96ed750bd169	57	******************************************************************************/
Anna Bridge	180:96ed750bd169	58	/**
Anna Bridge	180:96ed750bd169	59	\ingroup Cortex_M7
Anna Bridge	180:96ed750bd169	60	@{
Anna Bridge	180:96ed750bd169	61	*/
Anna Bridge	180:96ed750bd169	62
Anna Bridge	180:96ed750bd169	63	#include "cmsis_version.h"
Anna Bridge	180:96ed750bd169	64
AnnaBridge	188:bcfe06ba3d64	65	/* CMSIS CM7 definitions */
Anna Bridge	180:96ed750bd169	66	#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	180:96ed750bd169	67	#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
Anna Bridge	180:96ed750bd169	68	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	180:96ed750bd169	69	__CM7_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
Anna Bridge	180:96ed750bd169	70
Anna Bridge	180:96ed750bd169	71	#define __CORTEX_M (7U) /!< Cortex-M Core /
Anna Bridge	180:96ed750bd169	72
Anna Bridge	180:96ed750bd169	73	/** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge	180:96ed750bd169	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Anna Bridge	180:96ed750bd169	75	*/
Anna Bridge	180:96ed750bd169	76	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	77	#if defined __TARGET_FPU_VFP
Anna Bridge	180:96ed750bd169	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	79	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	80	#else
Anna Bridge	180:96ed750bd169	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	82	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	83	#endif
Anna Bridge	180:96ed750bd169	84	#else
Anna Bridge	180:96ed750bd169	85	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	86	#endif
Anna Bridge	180:96ed750bd169	87
Anna Bridge	180:96ed750bd169	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	189:f392fc9709a3	89	#if defined __ARM_FP
Anna Bridge	180:96ed750bd169	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	91	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	92	#else
Anna Bridge	180:96ed750bd169	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	94	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	95	#endif
Anna Bridge	180:96ed750bd169	96	#else
Anna Bridge	180:96ed750bd169	97	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	98	#endif
Anna Bridge	180:96ed750bd169	99
Anna Bridge	180:96ed750bd169	100	#elif defined ( __GNUC__ )
Anna Bridge	180:96ed750bd169	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge	180:96ed750bd169	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	103	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	104	#else
Anna Bridge	180:96ed750bd169	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	106	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	107	#endif
Anna Bridge	180:96ed750bd169	108	#else
Anna Bridge	180:96ed750bd169	109	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	110	#endif
Anna Bridge	180:96ed750bd169	111
Anna Bridge	180:96ed750bd169	112	#elif defined ( __ICCARM__ )
Anna Bridge	180:96ed750bd169	113	#if defined __ARMVFP__
Anna Bridge	180:96ed750bd169	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	115	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	116	#else
Anna Bridge	180:96ed750bd169	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	118	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	119	#endif
Anna Bridge	180:96ed750bd169	120	#else
Anna Bridge	180:96ed750bd169	121	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	122	#endif
Anna Bridge	180:96ed750bd169	123
Anna Bridge	180:96ed750bd169	124	#elif defined ( __TI_ARM__ )
Anna Bridge	180:96ed750bd169	125	#if defined __TI_VFP_SUPPORT__
Anna Bridge	180:96ed750bd169	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	127	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	128	#else
Anna Bridge	180:96ed750bd169	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	130	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	131	#endif
Anna Bridge	180:96ed750bd169	132	#else
Anna Bridge	180:96ed750bd169	133	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	134	#endif
Anna Bridge	180:96ed750bd169	135
Anna Bridge	180:96ed750bd169	136	#elif defined ( __TASKING__ )
Anna Bridge	180:96ed750bd169	137	#if defined __FPU_VFP__
Anna Bridge	180:96ed750bd169	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	139	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	140	#else
Anna Bridge	180:96ed750bd169	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	142	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	143	#endif
Anna Bridge	180:96ed750bd169	144	#else
Anna Bridge	180:96ed750bd169	145	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	146	#endif
Anna Bridge	180:96ed750bd169	147
Anna Bridge	180:96ed750bd169	148	#elif defined ( __CSMC__ )
Anna Bridge	180:96ed750bd169	149	#if ( __CSMC__ & 0x400U)
Anna Bridge	180:96ed750bd169	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	151	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	152	#else
Anna Bridge	180:96ed750bd169	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	154	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	155	#endif
Anna Bridge	180:96ed750bd169	156	#else
Anna Bridge	180:96ed750bd169	157	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	158	#endif
Anna Bridge	180:96ed750bd169	159
Anna Bridge	180:96ed750bd169	160	#endif
Anna Bridge	180:96ed750bd169	161
Anna Bridge	180:96ed750bd169	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge	180:96ed750bd169	163
Anna Bridge	180:96ed750bd169	164
Anna Bridge	180:96ed750bd169	165	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	166	}
Anna Bridge	180:96ed750bd169	167	#endif
Anna Bridge	180:96ed750bd169	168
Anna Bridge	180:96ed750bd169	169	#endif /* __CORE_CM7_H_GENERIC */
Anna Bridge	180:96ed750bd169	170
Anna Bridge	180:96ed750bd169	171	#ifndef __CMSIS_GENERIC
Anna Bridge	180:96ed750bd169	172
Anna Bridge	180:96ed750bd169	173	#ifndef __CORE_CM7_H_DEPENDANT
Anna Bridge	180:96ed750bd169	174	#define __CORE_CM7_H_DEPENDANT
Anna Bridge	180:96ed750bd169	175
Anna Bridge	180:96ed750bd169	176	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	177	extern "C" {
Anna Bridge	180:96ed750bd169	178	#endif
Anna Bridge	180:96ed750bd169	179
Anna Bridge	180:96ed750bd169	180	/* check device defines and use defaults */
Anna Bridge	180:96ed750bd169	181	#if defined __CHECK_DEVICE_DEFINES
Anna Bridge	180:96ed750bd169	182	#ifndef __CM7_REV
Anna Bridge	180:96ed750bd169	183	#define __CM7_REV 0x0000U
Anna Bridge	180:96ed750bd169	184	#warning "__CM7_REV not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	185	#endif
Anna Bridge	180:96ed750bd169	186
Anna Bridge	180:96ed750bd169	187	#ifndef __FPU_PRESENT
Anna Bridge	180:96ed750bd169	188	#define __FPU_PRESENT 0U
Anna Bridge	180:96ed750bd169	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	190	#endif
Anna Bridge	180:96ed750bd169	191
Anna Bridge	180:96ed750bd169	192	#ifndef __MPU_PRESENT
Anna Bridge	180:96ed750bd169	193	#define __MPU_PRESENT 0U
Anna Bridge	180:96ed750bd169	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	195	#endif
Anna Bridge	180:96ed750bd169	196
Anna Bridge	180:96ed750bd169	197	#ifndef __ICACHE_PRESENT
Anna Bridge	180:96ed750bd169	198	#define __ICACHE_PRESENT 0U
Anna Bridge	180:96ed750bd169	199	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	200	#endif
Anna Bridge	180:96ed750bd169	201
Anna Bridge	180:96ed750bd169	202	#ifndef __DCACHE_PRESENT
Anna Bridge	180:96ed750bd169	203	#define __DCACHE_PRESENT 0U
Anna Bridge	180:96ed750bd169	204	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	205	#endif
Anna Bridge	180:96ed750bd169	206
Anna Bridge	180:96ed750bd169	207	#ifndef __DTCM_PRESENT
Anna Bridge	180:96ed750bd169	208	#define __DTCM_PRESENT 0U
Anna Bridge	180:96ed750bd169	209	#warning "__DTCM_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	210	#endif
Anna Bridge	180:96ed750bd169	211
Anna Bridge	180:96ed750bd169	212	#ifndef __NVIC_PRIO_BITS
Anna Bridge	180:96ed750bd169	213	#define __NVIC_PRIO_BITS 3U
Anna Bridge	180:96ed750bd169	214	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	215	#endif
Anna Bridge	180:96ed750bd169	216
Anna Bridge	180:96ed750bd169	217	#ifndef __Vendor_SysTickConfig
Anna Bridge	180:96ed750bd169	218	#define __Vendor_SysTickConfig 0U
Anna Bridge	180:96ed750bd169	219	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	220	#endif
Anna Bridge	180:96ed750bd169	221	#endif
Anna Bridge	180:96ed750bd169	222
Anna Bridge	180:96ed750bd169	223	/* IO definitions (access restrictions to peripheral registers) */
Anna Bridge	180:96ed750bd169	224	/**
Anna Bridge	180:96ed750bd169	225	\defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge	180:96ed750bd169	226
Anna Bridge	180:96ed750bd169	227	<strong>IO Type Qualifiers</strong> are used
Anna Bridge	180:96ed750bd169	228	\li to specify the access to peripheral variables.
Anna Bridge	180:96ed750bd169	229	\li for automatic generation of peripheral register debug information.
Anna Bridge	180:96ed750bd169	230	*/
Anna Bridge	180:96ed750bd169	231	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	232	#define __I volatile /!< Defines 'read only' permissions /
Anna Bridge	180:96ed750bd169	233	#else
Anna Bridge	180:96ed750bd169	234	#define __I volatile const /!< Defines 'read only' permissions /
Anna Bridge	180:96ed750bd169	235	#endif
Anna Bridge	180:96ed750bd169	236	#define __O volatile /!< Defines 'write only' permissions /
Anna Bridge	180:96ed750bd169	237	#define __IO volatile /!< Defines 'read / write' permissions /
Anna Bridge	180:96ed750bd169	238
Anna Bridge	180:96ed750bd169	239	/* following defines should be used for structure members */
Anna Bridge	180:96ed750bd169	240	#define __IM volatile const /! Defines 'read only' structure member permissions /
Anna Bridge	180:96ed750bd169	241	#define __OM volatile /! Defines 'write only' structure member permissions /
Anna Bridge	180:96ed750bd169	242	#define __IOM volatile /! Defines 'read / write' structure member permissions /
Anna Bridge	180:96ed750bd169	243
Anna Bridge	180:96ed750bd169	244	/@} end of group Cortex_M7 /
Anna Bridge	180:96ed750bd169	245
Anna Bridge	180:96ed750bd169	246
Anna Bridge	180:96ed750bd169	247
Anna Bridge	180:96ed750bd169	248	/*******************************************************************************
Anna Bridge	180:96ed750bd169	249	* Register Abstraction
Anna Bridge	180:96ed750bd169	250	Core Register contain:
Anna Bridge	180:96ed750bd169	251	- Core Register
Anna Bridge	180:96ed750bd169	252	- Core NVIC Register
Anna Bridge	180:96ed750bd169	253	- Core SCB Register
Anna Bridge	180:96ed750bd169	254	- Core SysTick Register
Anna Bridge	180:96ed750bd169	255	- Core Debug Register
Anna Bridge	180:96ed750bd169	256	- Core MPU Register
Anna Bridge	180:96ed750bd169	257	- Core FPU Register
Anna Bridge	180:96ed750bd169	258	******************************************************************************/
Anna Bridge	180:96ed750bd169	259	/**
Anna Bridge	180:96ed750bd169	260	\defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge	180:96ed750bd169	261	\brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge	180:96ed750bd169	262	*/
Anna Bridge	180:96ed750bd169	263
Anna Bridge	180:96ed750bd169	264	/**
Anna Bridge	180:96ed750bd169	265	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	266	\defgroup CMSIS_CORE Status and Control Registers
Anna Bridge	180:96ed750bd169	267	\brief Core Register type definitions.
Anna Bridge	180:96ed750bd169	268	@{
Anna Bridge	180:96ed750bd169	269	*/
Anna Bridge	180:96ed750bd169	270
Anna Bridge	180:96ed750bd169	271	/**
Anna Bridge	180:96ed750bd169	272	\brief Union type to access the Application Program Status Register (APSR).
Anna Bridge	180:96ed750bd169	273	*/
Anna Bridge	180:96ed750bd169	274	typedef union
Anna Bridge	180:96ed750bd169	275	{
Anna Bridge	180:96ed750bd169	276	struct
Anna Bridge	180:96ed750bd169	277	{
Anna Bridge	180:96ed750bd169	278	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Anna Bridge	180:96ed750bd169	279	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	180:96ed750bd169	280	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Anna Bridge	180:96ed750bd169	281	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	180:96ed750bd169	282	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	180:96ed750bd169	283	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	180:96ed750bd169	284	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	180:96ed750bd169	285	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	180:96ed750bd169	286	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	287	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	288	} APSR_Type;
Anna Bridge	180:96ed750bd169	289
Anna Bridge	180:96ed750bd169	290	/* APSR Register Definitions */
Anna Bridge	180:96ed750bd169	291	#define APSR_N_Pos 31U /!< APSR: N Position /
Anna Bridge	180:96ed750bd169	292	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Anna Bridge	180:96ed750bd169	293
Anna Bridge	180:96ed750bd169	294	#define APSR_Z_Pos 30U /!< APSR: Z Position /
Anna Bridge	180:96ed750bd169	295	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Anna Bridge	180:96ed750bd169	296
Anna Bridge	180:96ed750bd169	297	#define APSR_C_Pos 29U /!< APSR: C Position /
Anna Bridge	180:96ed750bd169	298	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Anna Bridge	180:96ed750bd169	299
Anna Bridge	180:96ed750bd169	300	#define APSR_V_Pos 28U /!< APSR: V Position /
Anna Bridge	180:96ed750bd169	301	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Anna Bridge	180:96ed750bd169	302
Anna Bridge	180:96ed750bd169	303	#define APSR_Q_Pos 27U /!< APSR: Q Position /
Anna Bridge	180:96ed750bd169	304	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Anna Bridge	180:96ed750bd169	305
Anna Bridge	180:96ed750bd169	306	#define APSR_GE_Pos 16U /!< APSR: GE Position /
Anna Bridge	180:96ed750bd169	307	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Anna Bridge	180:96ed750bd169	308
Anna Bridge	180:96ed750bd169	309
Anna Bridge	180:96ed750bd169	310	/**
Anna Bridge	180:96ed750bd169	311	\brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge	180:96ed750bd169	312	*/
Anna Bridge	180:96ed750bd169	313	typedef union
Anna Bridge	180:96ed750bd169	314	{
Anna Bridge	180:96ed750bd169	315	struct
Anna Bridge	180:96ed750bd169	316	{
Anna Bridge	180:96ed750bd169	317	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	180:96ed750bd169	318	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Anna Bridge	180:96ed750bd169	319	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	320	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	321	} IPSR_Type;
Anna Bridge	180:96ed750bd169	322
Anna Bridge	180:96ed750bd169	323	/* IPSR Register Definitions */
Anna Bridge	180:96ed750bd169	324	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
Anna Bridge	180:96ed750bd169	325	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Anna Bridge	180:96ed750bd169	326
Anna Bridge	180:96ed750bd169	327
Anna Bridge	180:96ed750bd169	328	/**
Anna Bridge	180:96ed750bd169	329	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge	180:96ed750bd169	330	*/
Anna Bridge	180:96ed750bd169	331	typedef union
Anna Bridge	180:96ed750bd169	332	{
Anna Bridge	180:96ed750bd169	333	struct
Anna Bridge	180:96ed750bd169	334	{
Anna Bridge	180:96ed750bd169	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	180:96ed750bd169	336	uint32_t _reserved0:1; /!< bit: 9 Reserved /
Anna Bridge	180:96ed750bd169	337	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
Anna Bridge	180:96ed750bd169	338	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	180:96ed750bd169	339	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Anna Bridge	180:96ed750bd169	340	uint32_t T:1; /!< bit: 24 Thumb bit /
Anna Bridge	180:96ed750bd169	341	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
Anna Bridge	180:96ed750bd169	342	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	180:96ed750bd169	343	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	180:96ed750bd169	344	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	180:96ed750bd169	345	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	180:96ed750bd169	346	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	180:96ed750bd169	347	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	348	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	349	} xPSR_Type;
Anna Bridge	180:96ed750bd169	350
Anna Bridge	180:96ed750bd169	351	/* xPSR Register Definitions */
Anna Bridge	180:96ed750bd169	352	#define xPSR_N_Pos 31U /!< xPSR: N Position /
Anna Bridge	180:96ed750bd169	353	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Anna Bridge	180:96ed750bd169	354
Anna Bridge	180:96ed750bd169	355	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
Anna Bridge	180:96ed750bd169	356	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Anna Bridge	180:96ed750bd169	357
Anna Bridge	180:96ed750bd169	358	#define xPSR_C_Pos 29U /!< xPSR: C Position /
Anna Bridge	180:96ed750bd169	359	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Anna Bridge	180:96ed750bd169	360
Anna Bridge	180:96ed750bd169	361	#define xPSR_V_Pos 28U /!< xPSR: V Position /
Anna Bridge	180:96ed750bd169	362	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Anna Bridge	180:96ed750bd169	363
Anna Bridge	180:96ed750bd169	364	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
Anna Bridge	180:96ed750bd169	365	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Anna Bridge	180:96ed750bd169	366
Anna Bridge	180:96ed750bd169	367	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
Anna Bridge	180:96ed750bd169	368	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
Anna Bridge	180:96ed750bd169	369
Anna Bridge	180:96ed750bd169	370	#define xPSR_T_Pos 24U /!< xPSR: T Position /
Anna Bridge	180:96ed750bd169	371	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Anna Bridge	180:96ed750bd169	372
Anna Bridge	180:96ed750bd169	373	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
Anna Bridge	180:96ed750bd169	374	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Anna Bridge	180:96ed750bd169	375
Anna Bridge	180:96ed750bd169	376	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
Anna Bridge	180:96ed750bd169	377	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
Anna Bridge	180:96ed750bd169	378
Anna Bridge	180:96ed750bd169	379	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
Anna Bridge	180:96ed750bd169	380	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Anna Bridge	180:96ed750bd169	381
Anna Bridge	180:96ed750bd169	382
Anna Bridge	180:96ed750bd169	383	/**
Anna Bridge	180:96ed750bd169	384	\brief Union type to access the Control Registers (CONTROL).
Anna Bridge	180:96ed750bd169	385	*/
Anna Bridge	180:96ed750bd169	386	typedef union
Anna Bridge	180:96ed750bd169	387	{
Anna Bridge	180:96ed750bd169	388	struct
Anna Bridge	180:96ed750bd169	389	{
Anna Bridge	180:96ed750bd169	390	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Anna Bridge	180:96ed750bd169	391	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Anna Bridge	180:96ed750bd169	392	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Anna Bridge	180:96ed750bd169	393	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Anna Bridge	180:96ed750bd169	394	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	395	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	396	} CONTROL_Type;
Anna Bridge	180:96ed750bd169	397
Anna Bridge	180:96ed750bd169	398	/* CONTROL Register Definitions */
Anna Bridge	180:96ed750bd169	399	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
Anna Bridge	180:96ed750bd169	400	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Anna Bridge	180:96ed750bd169	401
Anna Bridge	180:96ed750bd169	402	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
Anna Bridge	180:96ed750bd169	403	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Anna Bridge	180:96ed750bd169	404
Anna Bridge	180:96ed750bd169	405	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
Anna Bridge	180:96ed750bd169	406	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Anna Bridge	180:96ed750bd169	407
Anna Bridge	180:96ed750bd169	408	/@} end of group CMSIS_CORE /
Anna Bridge	180:96ed750bd169	409
Anna Bridge	180:96ed750bd169	410
Anna Bridge	180:96ed750bd169	411	/**
Anna Bridge	180:96ed750bd169	412	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	413	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge	180:96ed750bd169	414	\brief Type definitions for the NVIC Registers
Anna Bridge	180:96ed750bd169	415	@{
Anna Bridge	180:96ed750bd169	416	*/
Anna Bridge	180:96ed750bd169	417
Anna Bridge	180:96ed750bd169	418	/**
Anna Bridge	180:96ed750bd169	419	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge	180:96ed750bd169	420	*/
Anna Bridge	180:96ed750bd169	421	typedef struct
Anna Bridge	180:96ed750bd169	422	{
Anna Bridge	180:96ed750bd169	423	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Anna Bridge	180:96ed750bd169	424	uint32_t RESERVED0[24U];
Anna Bridge	180:96ed750bd169	425	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Anna Bridge	180:96ed750bd169	426	uint32_t RSERVED1[24U];
Anna Bridge	180:96ed750bd169	427	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Anna Bridge	180:96ed750bd169	428	uint32_t RESERVED2[24U];
Anna Bridge	180:96ed750bd169	429	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Anna Bridge	180:96ed750bd169	430	uint32_t RESERVED3[24U];
Anna Bridge	180:96ed750bd169	431	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Anna Bridge	180:96ed750bd169	432	uint32_t RESERVED4[56U];
Anna Bridge	180:96ed750bd169	433	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Anna Bridge	180:96ed750bd169	434	uint32_t RESERVED5[644U];
Anna Bridge	180:96ed750bd169	435	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Anna Bridge	180:96ed750bd169	436	} NVIC_Type;
Anna Bridge	180:96ed750bd169	437
Anna Bridge	180:96ed750bd169	438	/* Software Triggered Interrupt Register Definitions */
Anna Bridge	180:96ed750bd169	439	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
Anna Bridge	180:96ed750bd169	440	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Anna Bridge	180:96ed750bd169	441
Anna Bridge	180:96ed750bd169	442	/@} end of group CMSIS_NVIC /
Anna Bridge	180:96ed750bd169	443
Anna Bridge	180:96ed750bd169	444
Anna Bridge	180:96ed750bd169	445	/**
Anna Bridge	180:96ed750bd169	446	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	447	\defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge	180:96ed750bd169	448	\brief Type definitions for the System Control Block Registers
Anna Bridge	180:96ed750bd169	449	@{
Anna Bridge	180:96ed750bd169	450	*/
Anna Bridge	180:96ed750bd169	451
Anna Bridge	180:96ed750bd169	452	/**
Anna Bridge	180:96ed750bd169	453	\brief Structure type to access the System Control Block (SCB).
Anna Bridge	180:96ed750bd169	454	*/
Anna Bridge	180:96ed750bd169	455	typedef struct
Anna Bridge	180:96ed750bd169	456	{
Anna Bridge	180:96ed750bd169	457	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Anna Bridge	180:96ed750bd169	458	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Anna Bridge	180:96ed750bd169	459	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Anna Bridge	180:96ed750bd169	460	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Anna Bridge	180:96ed750bd169	461	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Anna Bridge	180:96ed750bd169	462	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Anna Bridge	180:96ed750bd169	463	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Anna Bridge	180:96ed750bd169	464	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Anna Bridge	180:96ed750bd169	465	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Anna Bridge	180:96ed750bd169	466	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Anna Bridge	180:96ed750bd169	467	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Anna Bridge	180:96ed750bd169	468	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Anna Bridge	180:96ed750bd169	469	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Anna Bridge	180:96ed750bd169	470	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Anna Bridge	180:96ed750bd169	471	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Anna Bridge	180:96ed750bd169	472	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Anna Bridge	180:96ed750bd169	473	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Anna Bridge	180:96ed750bd169	474	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Anna Bridge	180:96ed750bd169	475	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Anna Bridge	180:96ed750bd169	476	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	477	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Anna Bridge	180:96ed750bd169	478	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Anna Bridge	180:96ed750bd169	479	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Anna Bridge	180:96ed750bd169	480	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Anna Bridge	180:96ed750bd169	481	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Anna Bridge	180:96ed750bd169	482	uint32_t RESERVED3[93U];
Anna Bridge	180:96ed750bd169	483	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Anna Bridge	180:96ed750bd169	484	uint32_t RESERVED4[15U];
Anna Bridge	180:96ed750bd169	485	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Anna Bridge	180:96ed750bd169	486	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	180:96ed750bd169	487	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
Anna Bridge	180:96ed750bd169	488	uint32_t RESERVED5[1U];
Anna Bridge	180:96ed750bd169	489	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Anna Bridge	180:96ed750bd169	490	uint32_t RESERVED6[1U];
Anna Bridge	180:96ed750bd169	491	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Anna Bridge	180:96ed750bd169	492	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Anna Bridge	180:96ed750bd169	493	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Anna Bridge	180:96ed750bd169	494	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Anna Bridge	180:96ed750bd169	495	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Anna Bridge	180:96ed750bd169	496	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Anna Bridge	180:96ed750bd169	497	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Anna Bridge	180:96ed750bd169	498	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Anna Bridge	180:96ed750bd169	499	uint32_t RESERVED7[6U];
Anna Bridge	180:96ed750bd169	500	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Anna Bridge	180:96ed750bd169	501	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Anna Bridge	180:96ed750bd169	502	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Anna Bridge	180:96ed750bd169	503	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Anna Bridge	180:96ed750bd169	504	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Anna Bridge	180:96ed750bd169	505	uint32_t RESERVED8[1U];
Anna Bridge	180:96ed750bd169	506	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Anna Bridge	180:96ed750bd169	507	} SCB_Type;
Anna Bridge	180:96ed750bd169	508
Anna Bridge	180:96ed750bd169	509	/* SCB CPUID Register Definitions */
Anna Bridge	180:96ed750bd169	510	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
Anna Bridge	180:96ed750bd169	511	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Anna Bridge	180:96ed750bd169	512
Anna Bridge	180:96ed750bd169	513	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
Anna Bridge	180:96ed750bd169	514	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Anna Bridge	180:96ed750bd169	515
Anna Bridge	180:96ed750bd169	516	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
Anna Bridge	180:96ed750bd169	517	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Anna Bridge	180:96ed750bd169	518
Anna Bridge	180:96ed750bd169	519	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
Anna Bridge	180:96ed750bd169	520	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Anna Bridge	180:96ed750bd169	521
Anna Bridge	180:96ed750bd169	522	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
Anna Bridge	180:96ed750bd169	523	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Anna Bridge	180:96ed750bd169	524
Anna Bridge	180:96ed750bd169	525	/* SCB Interrupt Control State Register Definitions */
Anna Bridge	180:96ed750bd169	526	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
Anna Bridge	180:96ed750bd169	527	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Anna Bridge	180:96ed750bd169	528
Anna Bridge	180:96ed750bd169	529	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
Anna Bridge	180:96ed750bd169	530	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Anna Bridge	180:96ed750bd169	531
Anna Bridge	180:96ed750bd169	532	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
Anna Bridge	180:96ed750bd169	533	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Anna Bridge	180:96ed750bd169	534
Anna Bridge	180:96ed750bd169	535	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
Anna Bridge	180:96ed750bd169	536	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Anna Bridge	180:96ed750bd169	537
Anna Bridge	180:96ed750bd169	538	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
Anna Bridge	180:96ed750bd169	539	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Anna Bridge	180:96ed750bd169	540
Anna Bridge	180:96ed750bd169	541	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
Anna Bridge	180:96ed750bd169	542	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Anna Bridge	180:96ed750bd169	543
Anna Bridge	180:96ed750bd169	544	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
Anna Bridge	180:96ed750bd169	545	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Anna Bridge	180:96ed750bd169	546
Anna Bridge	180:96ed750bd169	547	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
Anna Bridge	180:96ed750bd169	548	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Anna Bridge	180:96ed750bd169	549
Anna Bridge	180:96ed750bd169	550	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
Anna Bridge	180:96ed750bd169	551	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Anna Bridge	180:96ed750bd169	552
Anna Bridge	180:96ed750bd169	553	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
Anna Bridge	180:96ed750bd169	554	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Anna Bridge	180:96ed750bd169	555
Anna Bridge	180:96ed750bd169	556	/* SCB Vector Table Offset Register Definitions */
Anna Bridge	180:96ed750bd169	557	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Anna Bridge	180:96ed750bd169	558	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Anna Bridge	180:96ed750bd169	559
Anna Bridge	180:96ed750bd169	560	/* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge	180:96ed750bd169	561	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
Anna Bridge	180:96ed750bd169	562	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Anna Bridge	180:96ed750bd169	563
Anna Bridge	180:96ed750bd169	564	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
Anna Bridge	180:96ed750bd169	565	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Anna Bridge	180:96ed750bd169	566
Anna Bridge	180:96ed750bd169	567	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
Anna Bridge	180:96ed750bd169	568	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Anna Bridge	180:96ed750bd169	569
Anna Bridge	180:96ed750bd169	570	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
Anna Bridge	180:96ed750bd169	571	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Anna Bridge	180:96ed750bd169	572
Anna Bridge	180:96ed750bd169	573	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
Anna Bridge	180:96ed750bd169	574	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Anna Bridge	180:96ed750bd169	575
Anna Bridge	180:96ed750bd169	576	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
Anna Bridge	180:96ed750bd169	577	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Anna Bridge	180:96ed750bd169	578
Anna Bridge	180:96ed750bd169	579	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
Anna Bridge	180:96ed750bd169	580	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Anna Bridge	180:96ed750bd169	581
Anna Bridge	180:96ed750bd169	582	/* SCB System Control Register Definitions */
Anna Bridge	180:96ed750bd169	583	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
Anna Bridge	180:96ed750bd169	584	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Anna Bridge	180:96ed750bd169	585
Anna Bridge	180:96ed750bd169	586	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
Anna Bridge	180:96ed750bd169	587	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Anna Bridge	180:96ed750bd169	588
Anna Bridge	180:96ed750bd169	589	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
Anna Bridge	180:96ed750bd169	590	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Anna Bridge	180:96ed750bd169	591
Anna Bridge	180:96ed750bd169	592	/* SCB Configuration Control Register Definitions */
Anna Bridge	180:96ed750bd169	593	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
Anna Bridge	180:96ed750bd169	594	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
Anna Bridge	180:96ed750bd169	595
Anna Bridge	180:96ed750bd169	596	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
Anna Bridge	180:96ed750bd169	597	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
Anna Bridge	180:96ed750bd169	598
Anna Bridge	180:96ed750bd169	599	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
Anna Bridge	180:96ed750bd169	600	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
Anna Bridge	180:96ed750bd169	601
Anna Bridge	180:96ed750bd169	602	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
Anna Bridge	180:96ed750bd169	603	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Anna Bridge	180:96ed750bd169	604
Anna Bridge	180:96ed750bd169	605	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
Anna Bridge	180:96ed750bd169	606	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Anna Bridge	180:96ed750bd169	607
Anna Bridge	180:96ed750bd169	608	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
Anna Bridge	180:96ed750bd169	609	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Anna Bridge	180:96ed750bd169	610
Anna Bridge	180:96ed750bd169	611	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
Anna Bridge	180:96ed750bd169	612	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Anna Bridge	180:96ed750bd169	613
Anna Bridge	180:96ed750bd169	614	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
Anna Bridge	180:96ed750bd169	615	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Anna Bridge	180:96ed750bd169	616
Anna Bridge	180:96ed750bd169	617	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
Anna Bridge	180:96ed750bd169	618	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Anna Bridge	180:96ed750bd169	619
Anna Bridge	180:96ed750bd169	620	/* SCB System Handler Control and State Register Definitions */
Anna Bridge	180:96ed750bd169	621	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
Anna Bridge	180:96ed750bd169	622	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Anna Bridge	180:96ed750bd169	623
Anna Bridge	180:96ed750bd169	624	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
Anna Bridge	180:96ed750bd169	625	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Anna Bridge	180:96ed750bd169	626
Anna Bridge	180:96ed750bd169	627	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
Anna Bridge	180:96ed750bd169	628	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Anna Bridge	180:96ed750bd169	629
Anna Bridge	180:96ed750bd169	630	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
Anna Bridge	180:96ed750bd169	631	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Anna Bridge	180:96ed750bd169	632
Anna Bridge	180:96ed750bd169	633	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	634	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	635
Anna Bridge	180:96ed750bd169	636	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	637	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	638
Anna Bridge	180:96ed750bd169	639	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	640	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	641
Anna Bridge	180:96ed750bd169	642	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
Anna Bridge	180:96ed750bd169	643	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Anna Bridge	180:96ed750bd169	644
Anna Bridge	180:96ed750bd169	645	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
Anna Bridge	180:96ed750bd169	646	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Anna Bridge	180:96ed750bd169	647
Anna Bridge	180:96ed750bd169	648	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
Anna Bridge	180:96ed750bd169	649	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Anna Bridge	180:96ed750bd169	650
Anna Bridge	180:96ed750bd169	651	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
Anna Bridge	180:96ed750bd169	652	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Anna Bridge	180:96ed750bd169	653
Anna Bridge	180:96ed750bd169	654	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
Anna Bridge	180:96ed750bd169	655	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Anna Bridge	180:96ed750bd169	656
Anna Bridge	180:96ed750bd169	657	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
Anna Bridge	180:96ed750bd169	658	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Anna Bridge	180:96ed750bd169	659
Anna Bridge	180:96ed750bd169	660	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
Anna Bridge	180:96ed750bd169	661	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Anna Bridge	180:96ed750bd169	662
Anna Bridge	180:96ed750bd169	663	/* SCB Configurable Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	664	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
Anna Bridge	180:96ed750bd169	665	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	666
Anna Bridge	180:96ed750bd169	667	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
Anna Bridge	180:96ed750bd169	668	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	669
Anna Bridge	180:96ed750bd169	670	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
Anna Bridge	180:96ed750bd169	671	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	672
Anna Bridge	180:96ed750bd169	673	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	674	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
Anna Bridge	180:96ed750bd169	675	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
Anna Bridge	180:96ed750bd169	676
Anna Bridge	180:96ed750bd169	677	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
Anna Bridge	180:96ed750bd169	678	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
Anna Bridge	180:96ed750bd169	679
Anna Bridge	180:96ed750bd169	680	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
Anna Bridge	180:96ed750bd169	681	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
Anna Bridge	180:96ed750bd169	682
Anna Bridge	180:96ed750bd169	683	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
Anna Bridge	180:96ed750bd169	684	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
Anna Bridge	180:96ed750bd169	685
Anna Bridge	180:96ed750bd169	686	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
Anna Bridge	180:96ed750bd169	687	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
Anna Bridge	180:96ed750bd169	688
Anna Bridge	180:96ed750bd169	689	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
Anna Bridge	180:96ed750bd169	690	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
Anna Bridge	180:96ed750bd169	691
Anna Bridge	180:96ed750bd169	692	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	693	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
Anna Bridge	180:96ed750bd169	694	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
Anna Bridge	180:96ed750bd169	695
Anna Bridge	180:96ed750bd169	696	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
Anna Bridge	180:96ed750bd169	697	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
Anna Bridge	180:96ed750bd169	698
Anna Bridge	180:96ed750bd169	699	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
Anna Bridge	180:96ed750bd169	700	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
Anna Bridge	180:96ed750bd169	701
Anna Bridge	180:96ed750bd169	702	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
Anna Bridge	180:96ed750bd169	703	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
Anna Bridge	180:96ed750bd169	704
Anna Bridge	180:96ed750bd169	705	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
Anna Bridge	180:96ed750bd169	706	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
Anna Bridge	180:96ed750bd169	707
Anna Bridge	180:96ed750bd169	708	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
Anna Bridge	180:96ed750bd169	709	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
Anna Bridge	180:96ed750bd169	710
Anna Bridge	180:96ed750bd169	711	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
Anna Bridge	180:96ed750bd169	712	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
Anna Bridge	180:96ed750bd169	713
Anna Bridge	180:96ed750bd169	714	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	715	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
Anna Bridge	180:96ed750bd169	716	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
Anna Bridge	180:96ed750bd169	717
Anna Bridge	180:96ed750bd169	718	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
Anna Bridge	180:96ed750bd169	719	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
Anna Bridge	180:96ed750bd169	720
Anna Bridge	180:96ed750bd169	721	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
Anna Bridge	180:96ed750bd169	722	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
Anna Bridge	180:96ed750bd169	723
Anna Bridge	180:96ed750bd169	724	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
Anna Bridge	180:96ed750bd169	725	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
Anna Bridge	180:96ed750bd169	726
Anna Bridge	180:96ed750bd169	727	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
Anna Bridge	180:96ed750bd169	728	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
Anna Bridge	180:96ed750bd169	729
Anna Bridge	180:96ed750bd169	730	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
Anna Bridge	180:96ed750bd169	731	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
Anna Bridge	180:96ed750bd169	732
Anna Bridge	180:96ed750bd169	733	/* SCB Hard Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	734	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
Anna Bridge	180:96ed750bd169	735	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Anna Bridge	180:96ed750bd169	736
Anna Bridge	180:96ed750bd169	737	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
Anna Bridge	180:96ed750bd169	738	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Anna Bridge	180:96ed750bd169	739
Anna Bridge	180:96ed750bd169	740	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
Anna Bridge	180:96ed750bd169	741	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Anna Bridge	180:96ed750bd169	742
Anna Bridge	180:96ed750bd169	743	/* SCB Debug Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	744	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
Anna Bridge	180:96ed750bd169	745	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Anna Bridge	180:96ed750bd169	746
Anna Bridge	180:96ed750bd169	747	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
Anna Bridge	180:96ed750bd169	748	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Anna Bridge	180:96ed750bd169	749
Anna Bridge	180:96ed750bd169	750	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
Anna Bridge	180:96ed750bd169	751	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Anna Bridge	180:96ed750bd169	752
Anna Bridge	180:96ed750bd169	753	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
Anna Bridge	180:96ed750bd169	754	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Anna Bridge	180:96ed750bd169	755
Anna Bridge	180:96ed750bd169	756	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
Anna Bridge	180:96ed750bd169	757	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Anna Bridge	180:96ed750bd169	758
Anna Bridge	180:96ed750bd169	759	/* SCB Cache Level ID Register Definitions */
Anna Bridge	180:96ed750bd169	760	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
Anna Bridge	180:96ed750bd169	761	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Anna Bridge	180:96ed750bd169	762
Anna Bridge	180:96ed750bd169	763	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
Anna Bridge	180:96ed750bd169	764	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
Anna Bridge	180:96ed750bd169	765
Anna Bridge	180:96ed750bd169	766	/* SCB Cache Type Register Definitions */
Anna Bridge	180:96ed750bd169	767	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
Anna Bridge	180:96ed750bd169	768	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Anna Bridge	180:96ed750bd169	769
Anna Bridge	180:96ed750bd169	770	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
Anna Bridge	180:96ed750bd169	771	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Anna Bridge	180:96ed750bd169	772
Anna Bridge	180:96ed750bd169	773	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
Anna Bridge	180:96ed750bd169	774	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Anna Bridge	180:96ed750bd169	775
Anna Bridge	180:96ed750bd169	776	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
Anna Bridge	180:96ed750bd169	777	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Anna Bridge	180:96ed750bd169	778
Anna Bridge	180:96ed750bd169	779	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
Anna Bridge	180:96ed750bd169	780	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Anna Bridge	180:96ed750bd169	781
Anna Bridge	180:96ed750bd169	782	/* SCB Cache Size ID Register Definitions */
Anna Bridge	180:96ed750bd169	783	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
Anna Bridge	180:96ed750bd169	784	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Anna Bridge	180:96ed750bd169	785
Anna Bridge	180:96ed750bd169	786	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
Anna Bridge	180:96ed750bd169	787	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Anna Bridge	180:96ed750bd169	788
Anna Bridge	180:96ed750bd169	789	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
Anna Bridge	180:96ed750bd169	790	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Anna Bridge	180:96ed750bd169	791
Anna Bridge	180:96ed750bd169	792	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
Anna Bridge	180:96ed750bd169	793	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Anna Bridge	180:96ed750bd169	794
Anna Bridge	180:96ed750bd169	795	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
Anna Bridge	180:96ed750bd169	796	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Anna Bridge	180:96ed750bd169	797
Anna Bridge	180:96ed750bd169	798	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
Anna Bridge	180:96ed750bd169	799	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Anna Bridge	180:96ed750bd169	800
Anna Bridge	180:96ed750bd169	801	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
Anna Bridge	180:96ed750bd169	802	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Anna Bridge	180:96ed750bd169	803
Anna Bridge	180:96ed750bd169	804	/* SCB Cache Size Selection Register Definitions */
Anna Bridge	180:96ed750bd169	805	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
Anna Bridge	180:96ed750bd169	806	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Anna Bridge	180:96ed750bd169	807
Anna Bridge	180:96ed750bd169	808	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
Anna Bridge	180:96ed750bd169	809	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Anna Bridge	180:96ed750bd169	810
Anna Bridge	180:96ed750bd169	811	/* SCB Software Triggered Interrupt Register Definitions */
Anna Bridge	180:96ed750bd169	812	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
Anna Bridge	180:96ed750bd169	813	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Anna Bridge	180:96ed750bd169	814
Anna Bridge	180:96ed750bd169	815	/* SCB D-Cache Invalidate by Set-way Register Definitions */
Anna Bridge	180:96ed750bd169	816	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
Anna Bridge	180:96ed750bd169	817	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
Anna Bridge	180:96ed750bd169	818
Anna Bridge	180:96ed750bd169	819	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
Anna Bridge	180:96ed750bd169	820	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
Anna Bridge	180:96ed750bd169	821
Anna Bridge	180:96ed750bd169	822	/* SCB D-Cache Clean by Set-way Register Definitions */
Anna Bridge	180:96ed750bd169	823	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
Anna Bridge	180:96ed750bd169	824	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
Anna Bridge	180:96ed750bd169	825
Anna Bridge	180:96ed750bd169	826	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
Anna Bridge	180:96ed750bd169	827	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
Anna Bridge	180:96ed750bd169	828
Anna Bridge	180:96ed750bd169	829	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
Anna Bridge	180:96ed750bd169	830	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
Anna Bridge	180:96ed750bd169	831	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
Anna Bridge	180:96ed750bd169	832
Anna Bridge	180:96ed750bd169	833	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
Anna Bridge	180:96ed750bd169	834	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
Anna Bridge	180:96ed750bd169	835
Anna Bridge	180:96ed750bd169	836	/* Instruction Tightly-Coupled Memory Control Register Definitions */
Anna Bridge	180:96ed750bd169	837	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
Anna Bridge	180:96ed750bd169	838	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Anna Bridge	180:96ed750bd169	839
Anna Bridge	180:96ed750bd169	840	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
Anna Bridge	180:96ed750bd169	841	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Anna Bridge	180:96ed750bd169	842
Anna Bridge	180:96ed750bd169	843	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
Anna Bridge	180:96ed750bd169	844	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Anna Bridge	180:96ed750bd169	845
Anna Bridge	180:96ed750bd169	846	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
Anna Bridge	180:96ed750bd169	847	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Anna Bridge	180:96ed750bd169	848
Anna Bridge	180:96ed750bd169	849	/* Data Tightly-Coupled Memory Control Register Definitions */
Anna Bridge	180:96ed750bd169	850	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
Anna Bridge	180:96ed750bd169	851	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Anna Bridge	180:96ed750bd169	852
Anna Bridge	180:96ed750bd169	853	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
Anna Bridge	180:96ed750bd169	854	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Anna Bridge	180:96ed750bd169	855
Anna Bridge	180:96ed750bd169	856	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
Anna Bridge	180:96ed750bd169	857	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Anna Bridge	180:96ed750bd169	858
Anna Bridge	180:96ed750bd169	859	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
Anna Bridge	180:96ed750bd169	860	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Anna Bridge	180:96ed750bd169	861
Anna Bridge	180:96ed750bd169	862	/* AHBP Control Register Definitions */
Anna Bridge	180:96ed750bd169	863	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
Anna Bridge	180:96ed750bd169	864	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Anna Bridge	180:96ed750bd169	865
Anna Bridge	180:96ed750bd169	866	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
Anna Bridge	180:96ed750bd169	867	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Anna Bridge	180:96ed750bd169	868
Anna Bridge	180:96ed750bd169	869	/* L1 Cache Control Register Definitions */
Anna Bridge	180:96ed750bd169	870	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
Anna Bridge	180:96ed750bd169	871	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Anna Bridge	180:96ed750bd169	872
Anna Bridge	180:96ed750bd169	873	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
Anna Bridge	180:96ed750bd169	874	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Anna Bridge	180:96ed750bd169	875
Anna Bridge	180:96ed750bd169	876	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
Anna Bridge	180:96ed750bd169	877	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Anna Bridge	180:96ed750bd169	878
Anna Bridge	180:96ed750bd169	879	/* AHBS Control Register Definitions */
Anna Bridge	180:96ed750bd169	880	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
Anna Bridge	180:96ed750bd169	881	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Anna Bridge	180:96ed750bd169	882
Anna Bridge	180:96ed750bd169	883	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
Anna Bridge	180:96ed750bd169	884	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Anna Bridge	180:96ed750bd169	885
Anna Bridge	180:96ed750bd169	886	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
Anna Bridge	180:96ed750bd169	887	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Anna Bridge	180:96ed750bd169	888
Anna Bridge	180:96ed750bd169	889	/* Auxiliary Bus Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	890	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
Anna Bridge	180:96ed750bd169	891	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Anna Bridge	180:96ed750bd169	892
Anna Bridge	180:96ed750bd169	893	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
Anna Bridge	180:96ed750bd169	894	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Anna Bridge	180:96ed750bd169	895
Anna Bridge	180:96ed750bd169	896	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
Anna Bridge	180:96ed750bd169	897	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Anna Bridge	180:96ed750bd169	898
Anna Bridge	180:96ed750bd169	899	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
Anna Bridge	180:96ed750bd169	900	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Anna Bridge	180:96ed750bd169	901
Anna Bridge	180:96ed750bd169	902	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
Anna Bridge	180:96ed750bd169	903	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Anna Bridge	180:96ed750bd169	904
Anna Bridge	180:96ed750bd169	905	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
Anna Bridge	180:96ed750bd169	906	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Anna Bridge	180:96ed750bd169	907
Anna Bridge	180:96ed750bd169	908	/@} end of group CMSIS_SCB /
Anna Bridge	180:96ed750bd169	909
Anna Bridge	180:96ed750bd169	910
Anna Bridge	180:96ed750bd169	911	/**
Anna Bridge	180:96ed750bd169	912	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	913	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge	180:96ed750bd169	914	\brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge	180:96ed750bd169	915	@{
Anna Bridge	180:96ed750bd169	916	*/
Anna Bridge	180:96ed750bd169	917
Anna Bridge	180:96ed750bd169	918	/**
Anna Bridge	180:96ed750bd169	919	\brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge	180:96ed750bd169	920	*/
Anna Bridge	180:96ed750bd169	921	typedef struct
Anna Bridge	180:96ed750bd169	922	{
Anna Bridge	180:96ed750bd169	923	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	924	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Anna Bridge	180:96ed750bd169	925	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Anna Bridge	180:96ed750bd169	926	} SCnSCB_Type;
Anna Bridge	180:96ed750bd169	927
Anna Bridge	180:96ed750bd169	928	/* Interrupt Controller Type Register Definitions */
Anna Bridge	180:96ed750bd169	929	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
Anna Bridge	180:96ed750bd169	930	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Anna Bridge	180:96ed750bd169	931
Anna Bridge	180:96ed750bd169	932	/* Auxiliary Control Register Definitions */
Anna Bridge	180:96ed750bd169	933	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
Anna Bridge	180:96ed750bd169	934	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
Anna Bridge	180:96ed750bd169	935
Anna Bridge	180:96ed750bd169	936	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
Anna Bridge	180:96ed750bd169	937	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
Anna Bridge	180:96ed750bd169	938
Anna Bridge	180:96ed750bd169	939	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
Anna Bridge	180:96ed750bd169	940	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
Anna Bridge	180:96ed750bd169	941
Anna Bridge	180:96ed750bd169	942	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
Anna Bridge	180:96ed750bd169	943	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Anna Bridge	180:96ed750bd169	944
Anna Bridge	180:96ed750bd169	945	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
Anna Bridge	180:96ed750bd169	946	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Anna Bridge	180:96ed750bd169	947
Anna Bridge	180:96ed750bd169	948	/@} end of group CMSIS_SCnotSCB /
Anna Bridge	180:96ed750bd169	949
Anna Bridge	180:96ed750bd169	950
Anna Bridge	180:96ed750bd169	951	/**
Anna Bridge	180:96ed750bd169	952	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	953	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge	180:96ed750bd169	954	\brief Type definitions for the System Timer Registers.
Anna Bridge	180:96ed750bd169	955	@{
Anna Bridge	180:96ed750bd169	956	*/
Anna Bridge	180:96ed750bd169	957
Anna Bridge	180:96ed750bd169	958	/**
Anna Bridge	180:96ed750bd169	959	\brief Structure type to access the System Timer (SysTick).
Anna Bridge	180:96ed750bd169	960	*/
Anna Bridge	180:96ed750bd169	961	typedef struct
Anna Bridge	180:96ed750bd169	962	{
Anna Bridge	180:96ed750bd169	963	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Anna Bridge	180:96ed750bd169	964	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Anna Bridge	180:96ed750bd169	965	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Anna Bridge	180:96ed750bd169	966	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Anna Bridge	180:96ed750bd169	967	} SysTick_Type;
Anna Bridge	180:96ed750bd169	968
Anna Bridge	180:96ed750bd169	969	/* SysTick Control / Status Register Definitions */
Anna Bridge	180:96ed750bd169	970	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
Anna Bridge	180:96ed750bd169	971	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Anna Bridge	180:96ed750bd169	972
Anna Bridge	180:96ed750bd169	973	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
Anna Bridge	180:96ed750bd169	974	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Anna Bridge	180:96ed750bd169	975
Anna Bridge	180:96ed750bd169	976	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
Anna Bridge	180:96ed750bd169	977	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Anna Bridge	180:96ed750bd169	978
Anna Bridge	180:96ed750bd169	979	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	980	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	981
Anna Bridge	180:96ed750bd169	982	/* SysTick Reload Register Definitions */
Anna Bridge	180:96ed750bd169	983	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
Anna Bridge	180:96ed750bd169	984	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Anna Bridge	180:96ed750bd169	985
Anna Bridge	180:96ed750bd169	986	/* SysTick Current Register Definitions */
Anna Bridge	180:96ed750bd169	987	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
Anna Bridge	180:96ed750bd169	988	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Anna Bridge	180:96ed750bd169	989
Anna Bridge	180:96ed750bd169	990	/* SysTick Calibration Register Definitions */
Anna Bridge	180:96ed750bd169	991	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
Anna Bridge	180:96ed750bd169	992	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Anna Bridge	180:96ed750bd169	993
Anna Bridge	180:96ed750bd169	994	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
Anna Bridge	180:96ed750bd169	995	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Anna Bridge	180:96ed750bd169	996
Anna Bridge	180:96ed750bd169	997	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
Anna Bridge	180:96ed750bd169	998	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Anna Bridge	180:96ed750bd169	999
Anna Bridge	180:96ed750bd169	1000	/@} end of group CMSIS_SysTick /
Anna Bridge	180:96ed750bd169	1001
Anna Bridge	180:96ed750bd169	1002
Anna Bridge	180:96ed750bd169	1003	/**
Anna Bridge	180:96ed750bd169	1004	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1005	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge	180:96ed750bd169	1006	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge	180:96ed750bd169	1007	@{
Anna Bridge	180:96ed750bd169	1008	*/
Anna Bridge	180:96ed750bd169	1009
Anna Bridge	180:96ed750bd169	1010	/**
Anna Bridge	180:96ed750bd169	1011	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge	180:96ed750bd169	1012	*/
Anna Bridge	180:96ed750bd169	1013	typedef struct
Anna Bridge	180:96ed750bd169	1014	{
Anna Bridge	180:96ed750bd169	1015	__OM union
Anna Bridge	180:96ed750bd169	1016	{
Anna Bridge	180:96ed750bd169	1017	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Anna Bridge	180:96ed750bd169	1018	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Anna Bridge	180:96ed750bd169	1019	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Anna Bridge	180:96ed750bd169	1020	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Anna Bridge	180:96ed750bd169	1021	uint32_t RESERVED0[864U];
Anna Bridge	180:96ed750bd169	1022	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Anna Bridge	180:96ed750bd169	1023	uint32_t RESERVED1[15U];
Anna Bridge	180:96ed750bd169	1024	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Anna Bridge	180:96ed750bd169	1025	uint32_t RESERVED2[15U];
Anna Bridge	180:96ed750bd169	1026	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Anna Bridge	180:96ed750bd169	1027	uint32_t RESERVED3[29U];
Anna Bridge	180:96ed750bd169	1028	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Anna Bridge	180:96ed750bd169	1029	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Anna Bridge	180:96ed750bd169	1030	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Anna Bridge	180:96ed750bd169	1031	uint32_t RESERVED4[43U];
Anna Bridge	180:96ed750bd169	1032	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Anna Bridge	180:96ed750bd169	1033	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Anna Bridge	180:96ed750bd169	1034	uint32_t RESERVED5[6U];
Anna Bridge	180:96ed750bd169	1035	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Anna Bridge	180:96ed750bd169	1036	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Anna Bridge	180:96ed750bd169	1037	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Anna Bridge	180:96ed750bd169	1038	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Anna Bridge	180:96ed750bd169	1039	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Anna Bridge	180:96ed750bd169	1040	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Anna Bridge	180:96ed750bd169	1041	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Anna Bridge	180:96ed750bd169	1042	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Anna Bridge	180:96ed750bd169	1043	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Anna Bridge	180:96ed750bd169	1044	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Anna Bridge	180:96ed750bd169	1045	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Anna Bridge	180:96ed750bd169	1046	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Anna Bridge	180:96ed750bd169	1047	} ITM_Type;
Anna Bridge	180:96ed750bd169	1048
Anna Bridge	180:96ed750bd169	1049	/* ITM Trace Privilege Register Definitions */
Anna Bridge	180:96ed750bd169	1050	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	186:707f6e361f3e	1051	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Anna Bridge	180:96ed750bd169	1052
Anna Bridge	180:96ed750bd169	1053	/* ITM Trace Control Register Definitions */
Anna Bridge	180:96ed750bd169	1054	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
Anna Bridge	180:96ed750bd169	1055	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Anna Bridge	180:96ed750bd169	1056
Anna Bridge	180:96ed750bd169	1057	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
Anna Bridge	180:96ed750bd169	1058	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Anna Bridge	180:96ed750bd169	1059
Anna Bridge	180:96ed750bd169	1060	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
Anna Bridge	180:96ed750bd169	1061	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Anna Bridge	180:96ed750bd169	1062
Anna Bridge	180:96ed750bd169	1063	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
Anna Bridge	180:96ed750bd169	1064	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Anna Bridge	180:96ed750bd169	1065
Anna Bridge	180:96ed750bd169	1066	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
Anna Bridge	180:96ed750bd169	1067	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Anna Bridge	180:96ed750bd169	1068
Anna Bridge	180:96ed750bd169	1069	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
Anna Bridge	180:96ed750bd169	1070	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Anna Bridge	180:96ed750bd169	1071
Anna Bridge	180:96ed750bd169	1072	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
Anna Bridge	180:96ed750bd169	1073	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Anna Bridge	180:96ed750bd169	1074
Anna Bridge	180:96ed750bd169	1075	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
Anna Bridge	180:96ed750bd169	1076	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Anna Bridge	180:96ed750bd169	1077
Anna Bridge	180:96ed750bd169	1078	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
Anna Bridge	180:96ed750bd169	1079	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Anna Bridge	180:96ed750bd169	1080
Anna Bridge	180:96ed750bd169	1081	/* ITM Integration Write Register Definitions */
Anna Bridge	180:96ed750bd169	1082	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
Anna Bridge	180:96ed750bd169	1083	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Anna Bridge	180:96ed750bd169	1084
Anna Bridge	180:96ed750bd169	1085	/* ITM Integration Read Register Definitions */
Anna Bridge	180:96ed750bd169	1086	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
Anna Bridge	180:96ed750bd169	1087	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Anna Bridge	180:96ed750bd169	1088
Anna Bridge	180:96ed750bd169	1089	/* ITM Integration Mode Control Register Definitions */
Anna Bridge	180:96ed750bd169	1090	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
Anna Bridge	180:96ed750bd169	1091	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Anna Bridge	180:96ed750bd169	1092
Anna Bridge	180:96ed750bd169	1093	/* ITM Lock Status Register Definitions */
Anna Bridge	180:96ed750bd169	1094	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
Anna Bridge	180:96ed750bd169	1095	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Anna Bridge	180:96ed750bd169	1096
Anna Bridge	180:96ed750bd169	1097	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
Anna Bridge	180:96ed750bd169	1098	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Anna Bridge	180:96ed750bd169	1099
Anna Bridge	180:96ed750bd169	1100	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
Anna Bridge	180:96ed750bd169	1101	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Anna Bridge	180:96ed750bd169	1102
Anna Bridge	180:96ed750bd169	1103	/@}/ /* end of group CMSIS_ITM */
Anna Bridge	180:96ed750bd169	1104
Anna Bridge	180:96ed750bd169	1105
Anna Bridge	180:96ed750bd169	1106	/**
Anna Bridge	180:96ed750bd169	1107	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1108	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge	180:96ed750bd169	1109	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge	180:96ed750bd169	1110	@{
Anna Bridge	180:96ed750bd169	1111	*/
Anna Bridge	180:96ed750bd169	1112
Anna Bridge	180:96ed750bd169	1113	/**
Anna Bridge	180:96ed750bd169	1114	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge	180:96ed750bd169	1115	*/
Anna Bridge	180:96ed750bd169	1116	typedef struct
Anna Bridge	180:96ed750bd169	1117	{
Anna Bridge	180:96ed750bd169	1118	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Anna Bridge	180:96ed750bd169	1119	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Anna Bridge	180:96ed750bd169	1120	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Anna Bridge	180:96ed750bd169	1121	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Anna Bridge	180:96ed750bd169	1122	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Anna Bridge	180:96ed750bd169	1123	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Anna Bridge	180:96ed750bd169	1124	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Anna Bridge	180:96ed750bd169	1125	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Anna Bridge	180:96ed750bd169	1126	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Anna Bridge	180:96ed750bd169	1127	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Anna Bridge	180:96ed750bd169	1128	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Anna Bridge	180:96ed750bd169	1129	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	1130	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Anna Bridge	180:96ed750bd169	1131	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Anna Bridge	180:96ed750bd169	1132	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Anna Bridge	180:96ed750bd169	1133	uint32_t RESERVED1[1U];
Anna Bridge	180:96ed750bd169	1134	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Anna Bridge	180:96ed750bd169	1135	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Anna Bridge	180:96ed750bd169	1136	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Anna Bridge	180:96ed750bd169	1137	uint32_t RESERVED2[1U];
Anna Bridge	180:96ed750bd169	1138	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Anna Bridge	180:96ed750bd169	1139	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Anna Bridge	180:96ed750bd169	1140	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Anna Bridge	180:96ed750bd169	1141	uint32_t RESERVED3[981U];
Anna Bridge	180:96ed750bd169	1142	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
Anna Bridge	180:96ed750bd169	1143	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Anna Bridge	180:96ed750bd169	1144	} DWT_Type;
Anna Bridge	180:96ed750bd169	1145
Anna Bridge	180:96ed750bd169	1146	/* DWT Control Register Definitions */
Anna Bridge	180:96ed750bd169	1147	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
Anna Bridge	180:96ed750bd169	1148	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Anna Bridge	180:96ed750bd169	1149
Anna Bridge	180:96ed750bd169	1150	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
Anna Bridge	180:96ed750bd169	1151	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Anna Bridge	180:96ed750bd169	1152
Anna Bridge	180:96ed750bd169	1153	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
Anna Bridge	180:96ed750bd169	1154	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Anna Bridge	180:96ed750bd169	1155
Anna Bridge	180:96ed750bd169	1156	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
Anna Bridge	180:96ed750bd169	1157	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Anna Bridge	180:96ed750bd169	1158
Anna Bridge	180:96ed750bd169	1159	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
Anna Bridge	180:96ed750bd169	1160	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Anna Bridge	180:96ed750bd169	1161
Anna Bridge	180:96ed750bd169	1162	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
Anna Bridge	180:96ed750bd169	1163	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Anna Bridge	180:96ed750bd169	1164
Anna Bridge	180:96ed750bd169	1165	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
Anna Bridge	180:96ed750bd169	1166	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Anna Bridge	180:96ed750bd169	1167
Anna Bridge	180:96ed750bd169	1168	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
Anna Bridge	180:96ed750bd169	1169	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Anna Bridge	180:96ed750bd169	1170
Anna Bridge	180:96ed750bd169	1171	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
Anna Bridge	180:96ed750bd169	1172	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Anna Bridge	180:96ed750bd169	1173
Anna Bridge	180:96ed750bd169	1174	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
Anna Bridge	180:96ed750bd169	1175	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Anna Bridge	180:96ed750bd169	1176
Anna Bridge	180:96ed750bd169	1177	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
Anna Bridge	180:96ed750bd169	1178	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Anna Bridge	180:96ed750bd169	1179
Anna Bridge	180:96ed750bd169	1180	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
Anna Bridge	180:96ed750bd169	1181	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Anna Bridge	180:96ed750bd169	1182
Anna Bridge	180:96ed750bd169	1183	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
Anna Bridge	180:96ed750bd169	1184	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Anna Bridge	180:96ed750bd169	1185
Anna Bridge	180:96ed750bd169	1186	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
Anna Bridge	180:96ed750bd169	1187	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Anna Bridge	180:96ed750bd169	1188
Anna Bridge	180:96ed750bd169	1189	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
Anna Bridge	180:96ed750bd169	1190	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Anna Bridge	180:96ed750bd169	1191
Anna Bridge	180:96ed750bd169	1192	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
Anna Bridge	180:96ed750bd169	1193	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Anna Bridge	180:96ed750bd169	1194
Anna Bridge	180:96ed750bd169	1195	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
Anna Bridge	180:96ed750bd169	1196	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Anna Bridge	180:96ed750bd169	1197
Anna Bridge	180:96ed750bd169	1198	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
Anna Bridge	180:96ed750bd169	1199	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Anna Bridge	180:96ed750bd169	1200
Anna Bridge	180:96ed750bd169	1201	/* DWT CPI Count Register Definitions */
Anna Bridge	180:96ed750bd169	1202	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
Anna Bridge	180:96ed750bd169	1203	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Anna Bridge	180:96ed750bd169	1204
Anna Bridge	180:96ed750bd169	1205	/* DWT Exception Overhead Count Register Definitions */
Anna Bridge	180:96ed750bd169	1206	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
Anna Bridge	180:96ed750bd169	1207	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Anna Bridge	180:96ed750bd169	1208
Anna Bridge	180:96ed750bd169	1209	/* DWT Sleep Count Register Definitions */
Anna Bridge	180:96ed750bd169	1210	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
Anna Bridge	180:96ed750bd169	1211	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Anna Bridge	180:96ed750bd169	1212
Anna Bridge	180:96ed750bd169	1213	/* DWT LSU Count Register Definitions */
Anna Bridge	180:96ed750bd169	1214	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
Anna Bridge	180:96ed750bd169	1215	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Anna Bridge	180:96ed750bd169	1216
Anna Bridge	180:96ed750bd169	1217	/* DWT Folded-instruction Count Register Definitions */
Anna Bridge	180:96ed750bd169	1218	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
Anna Bridge	180:96ed750bd169	1219	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Anna Bridge	180:96ed750bd169	1220
Anna Bridge	180:96ed750bd169	1221	/* DWT Comparator Mask Register Definitions */
Anna Bridge	180:96ed750bd169	1222	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
Anna Bridge	180:96ed750bd169	1223	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Anna Bridge	180:96ed750bd169	1224
Anna Bridge	180:96ed750bd169	1225	/* DWT Comparator Function Register Definitions */
Anna Bridge	180:96ed750bd169	1226	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
Anna Bridge	180:96ed750bd169	1227	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Anna Bridge	180:96ed750bd169	1228
Anna Bridge	180:96ed750bd169	1229	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
Anna Bridge	180:96ed750bd169	1230	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Anna Bridge	180:96ed750bd169	1231
Anna Bridge	180:96ed750bd169	1232	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
Anna Bridge	180:96ed750bd169	1233	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Anna Bridge	180:96ed750bd169	1234
Anna Bridge	180:96ed750bd169	1235	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
Anna Bridge	180:96ed750bd169	1236	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Anna Bridge	180:96ed750bd169	1237
Anna Bridge	180:96ed750bd169	1238	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
Anna Bridge	180:96ed750bd169	1239	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Anna Bridge	180:96ed750bd169	1240
Anna Bridge	180:96ed750bd169	1241	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
Anna Bridge	180:96ed750bd169	1242	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Anna Bridge	180:96ed750bd169	1243
Anna Bridge	180:96ed750bd169	1244	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
Anna Bridge	180:96ed750bd169	1245	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Anna Bridge	180:96ed750bd169	1246
Anna Bridge	180:96ed750bd169	1247	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
Anna Bridge	180:96ed750bd169	1248	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Anna Bridge	180:96ed750bd169	1249
Anna Bridge	180:96ed750bd169	1250	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
Anna Bridge	180:96ed750bd169	1251	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Anna Bridge	180:96ed750bd169	1252
Anna Bridge	180:96ed750bd169	1253	/@}/ /* end of group CMSIS_DWT */
Anna Bridge	180:96ed750bd169	1254
Anna Bridge	180:96ed750bd169	1255
Anna Bridge	180:96ed750bd169	1256	/**
Anna Bridge	180:96ed750bd169	1257	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1258	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge	180:96ed750bd169	1259	\brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge	180:96ed750bd169	1260	@{
Anna Bridge	180:96ed750bd169	1261	*/
Anna Bridge	180:96ed750bd169	1262
Anna Bridge	180:96ed750bd169	1263	/**
Anna Bridge	180:96ed750bd169	1264	\brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge	180:96ed750bd169	1265	*/
Anna Bridge	180:96ed750bd169	1266	typedef struct
Anna Bridge	180:96ed750bd169	1267	{
AnnaBridge	188:bcfe06ba3d64	1268	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Anna Bridge	180:96ed750bd169	1269	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Anna Bridge	180:96ed750bd169	1270	uint32_t RESERVED0[2U];
Anna Bridge	180:96ed750bd169	1271	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Anna Bridge	180:96ed750bd169	1272	uint32_t RESERVED1[55U];
Anna Bridge	180:96ed750bd169	1273	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Anna Bridge	180:96ed750bd169	1274	uint32_t RESERVED2[131U];
Anna Bridge	180:96ed750bd169	1275	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Anna Bridge	180:96ed750bd169	1276	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Anna Bridge	180:96ed750bd169	1277	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Anna Bridge	180:96ed750bd169	1278	uint32_t RESERVED3[759U];
AnnaBridge	188:bcfe06ba3d64	1279	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
Anna Bridge	180:96ed750bd169	1280	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Anna Bridge	180:96ed750bd169	1281	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Anna Bridge	180:96ed750bd169	1282	uint32_t RESERVED4[1U];
Anna Bridge	180:96ed750bd169	1283	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Anna Bridge	180:96ed750bd169	1284	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Anna Bridge	180:96ed750bd169	1285	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Anna Bridge	180:96ed750bd169	1286	uint32_t RESERVED5[39U];
Anna Bridge	180:96ed750bd169	1287	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Anna Bridge	180:96ed750bd169	1288	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Anna Bridge	180:96ed750bd169	1289	uint32_t RESERVED7[8U];
Anna Bridge	180:96ed750bd169	1290	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Anna Bridge	180:96ed750bd169	1291	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Anna Bridge	180:96ed750bd169	1292	} TPI_Type;
Anna Bridge	180:96ed750bd169	1293
Anna Bridge	180:96ed750bd169	1294	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1295	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	188:bcfe06ba3d64	1296	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Anna Bridge	180:96ed750bd169	1297
Anna Bridge	180:96ed750bd169	1298	/* TPI Selected Pin Protocol Register Definitions */
Anna Bridge	180:96ed750bd169	1299	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
Anna Bridge	180:96ed750bd169	1300	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Anna Bridge	180:96ed750bd169	1301
Anna Bridge	180:96ed750bd169	1302	/* TPI Formatter and Flush Status Register Definitions */
Anna Bridge	180:96ed750bd169	1303	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
Anna Bridge	180:96ed750bd169	1304	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Anna Bridge	180:96ed750bd169	1305
Anna Bridge	180:96ed750bd169	1306	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
Anna Bridge	180:96ed750bd169	1307	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Anna Bridge	180:96ed750bd169	1308
Anna Bridge	180:96ed750bd169	1309	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
Anna Bridge	180:96ed750bd169	1310	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Anna Bridge	180:96ed750bd169	1311
Anna Bridge	180:96ed750bd169	1312	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
Anna Bridge	180:96ed750bd169	1313	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Anna Bridge	180:96ed750bd169	1314
Anna Bridge	180:96ed750bd169	1315	/* TPI Formatter and Flush Control Register Definitions */
Anna Bridge	180:96ed750bd169	1316	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
Anna Bridge	180:96ed750bd169	1317	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Anna Bridge	180:96ed750bd169	1318
Anna Bridge	180:96ed750bd169	1319	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
Anna Bridge	180:96ed750bd169	1320	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Anna Bridge	180:96ed750bd169	1321
Anna Bridge	180:96ed750bd169	1322	/* TPI TRIGGER Register Definitions */
Anna Bridge	180:96ed750bd169	1323	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
Anna Bridge	180:96ed750bd169	1324	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Anna Bridge	180:96ed750bd169	1325
Anna Bridge	180:96ed750bd169	1326	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge	180:96ed750bd169	1327	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1328	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1329
Anna Bridge	180:96ed750bd169	1330	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
Anna Bridge	180:96ed750bd169	1331	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1332
Anna Bridge	180:96ed750bd169	1333	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1334	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1335
Anna Bridge	180:96ed750bd169	1336	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
Anna Bridge	180:96ed750bd169	1337	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1338
Anna Bridge	180:96ed750bd169	1339	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
Anna Bridge	180:96ed750bd169	1340	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Anna Bridge	180:96ed750bd169	1341
Anna Bridge	180:96ed750bd169	1342	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
Anna Bridge	180:96ed750bd169	1343	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Anna Bridge	180:96ed750bd169	1344
Anna Bridge	180:96ed750bd169	1345	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
Anna Bridge	180:96ed750bd169	1346	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Anna Bridge	180:96ed750bd169	1347
Anna Bridge	180:96ed750bd169	1348	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1349	#define TPI_ITATBCTR2_ATREADY2_Pos 0U /!< TPI ITATBCTR2: ATREADY2 Position /
AnnaBridge	188:bcfe06ba3d64	1350	#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/) /!< TPI ITATBCTR2: ATREADY2 Mask /
AnnaBridge	188:bcfe06ba3d64	1351
AnnaBridge	188:bcfe06ba3d64	1352	#define TPI_ITATBCTR2_ATREADY1_Pos 0U /!< TPI ITATBCTR2: ATREADY1 Position /
AnnaBridge	188:bcfe06ba3d64	1353	#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/) /!< TPI ITATBCTR2: ATREADY1 Mask /
Anna Bridge	180:96ed750bd169	1354
Anna Bridge	180:96ed750bd169	1355	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge	180:96ed750bd169	1356	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1357	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1358
Anna Bridge	180:96ed750bd169	1359	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
Anna Bridge	180:96ed750bd169	1360	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1361
Anna Bridge	180:96ed750bd169	1362	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1363	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1364
Anna Bridge	180:96ed750bd169	1365	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
Anna Bridge	180:96ed750bd169	1366	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1367
Anna Bridge	180:96ed750bd169	1368	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
Anna Bridge	180:96ed750bd169	1369	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Anna Bridge	180:96ed750bd169	1370
Anna Bridge	180:96ed750bd169	1371	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
Anna Bridge	180:96ed750bd169	1372	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Anna Bridge	180:96ed750bd169	1373
Anna Bridge	180:96ed750bd169	1374	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
Anna Bridge	180:96ed750bd169	1375	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Anna Bridge	180:96ed750bd169	1376
Anna Bridge	180:96ed750bd169	1377	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1378	#define TPI_ITATBCTR0_ATREADY2_Pos 0U /!< TPI ITATBCTR0: ATREADY2 Position /
AnnaBridge	188:bcfe06ba3d64	1379	#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/) /!< TPI ITATBCTR0: ATREADY2 Mask /
AnnaBridge	188:bcfe06ba3d64	1380
AnnaBridge	188:bcfe06ba3d64	1381	#define TPI_ITATBCTR0_ATREADY1_Pos 0U /!< TPI ITATBCTR0: ATREADY1 Position /
AnnaBridge	188:bcfe06ba3d64	1382	#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/) /!< TPI ITATBCTR0: ATREADY1 Mask /
Anna Bridge	180:96ed750bd169	1383
Anna Bridge	180:96ed750bd169	1384	/* TPI Integration Mode Control Register Definitions */
Anna Bridge	180:96ed750bd169	1385	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	188:bcfe06ba3d64	1386	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Anna Bridge	180:96ed750bd169	1387
Anna Bridge	180:96ed750bd169	1388	/* TPI DEVID Register Definitions */
Anna Bridge	180:96ed750bd169	1389	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
Anna Bridge	180:96ed750bd169	1390	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Anna Bridge	180:96ed750bd169	1391
Anna Bridge	180:96ed750bd169	1392	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
Anna Bridge	180:96ed750bd169	1393	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Anna Bridge	180:96ed750bd169	1394
Anna Bridge	180:96ed750bd169	1395	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
Anna Bridge	180:96ed750bd169	1396	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Anna Bridge	180:96ed750bd169	1397
Anna Bridge	180:96ed750bd169	1398	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
Anna Bridge	180:96ed750bd169	1399	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Anna Bridge	180:96ed750bd169	1400
Anna Bridge	180:96ed750bd169	1401	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
Anna Bridge	180:96ed750bd169	1402	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Anna Bridge	180:96ed750bd169	1403
Anna Bridge	180:96ed750bd169	1404	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
Anna Bridge	180:96ed750bd169	1405	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Anna Bridge	180:96ed750bd169	1406
Anna Bridge	180:96ed750bd169	1407	/* TPI DEVTYPE Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1408	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	188:bcfe06ba3d64	1409	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	188:bcfe06ba3d64	1410
AnnaBridge	188:bcfe06ba3d64	1411	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
Anna Bridge	180:96ed750bd169	1412	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Anna Bridge	180:96ed750bd169	1413
Anna Bridge	180:96ed750bd169	1414	/@}/ /* end of group CMSIS_TPI */
Anna Bridge	180:96ed750bd169	1415
Anna Bridge	180:96ed750bd169	1416
Anna Bridge	180:96ed750bd169	1417	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1418	/**
Anna Bridge	180:96ed750bd169	1419	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1420	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge	180:96ed750bd169	1421	\brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge	180:96ed750bd169	1422	@{
Anna Bridge	180:96ed750bd169	1423	*/
Anna Bridge	180:96ed750bd169	1424
Anna Bridge	180:96ed750bd169	1425	/**
Anna Bridge	180:96ed750bd169	1426	\brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge	180:96ed750bd169	1427	*/
Anna Bridge	180:96ed750bd169	1428	typedef struct
Anna Bridge	180:96ed750bd169	1429	{
Anna Bridge	180:96ed750bd169	1430	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Anna Bridge	180:96ed750bd169	1431	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Anna Bridge	180:96ed750bd169	1432	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Anna Bridge	180:96ed750bd169	1433	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Anna Bridge	180:96ed750bd169	1434	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1435	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Anna Bridge	180:96ed750bd169	1436	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1437	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Anna Bridge	180:96ed750bd169	1438	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1439	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Anna Bridge	180:96ed750bd169	1440	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1441	} MPU_Type;
Anna Bridge	180:96ed750bd169	1442
Anna Bridge	180:96ed750bd169	1443	#define MPU_TYPE_RALIASES 4U
Anna Bridge	180:96ed750bd169	1444
Anna Bridge	180:96ed750bd169	1445	/* MPU Type Register Definitions */
Anna Bridge	180:96ed750bd169	1446	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
Anna Bridge	180:96ed750bd169	1447	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Anna Bridge	180:96ed750bd169	1448
Anna Bridge	180:96ed750bd169	1449	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
Anna Bridge	180:96ed750bd169	1450	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Anna Bridge	180:96ed750bd169	1451
Anna Bridge	180:96ed750bd169	1452	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
Anna Bridge	180:96ed750bd169	1453	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Anna Bridge	180:96ed750bd169	1454
Anna Bridge	180:96ed750bd169	1455	/* MPU Control Register Definitions */
Anna Bridge	180:96ed750bd169	1456	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
Anna Bridge	180:96ed750bd169	1457	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Anna Bridge	180:96ed750bd169	1458
Anna Bridge	180:96ed750bd169	1459	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
Anna Bridge	180:96ed750bd169	1460	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Anna Bridge	180:96ed750bd169	1461
Anna Bridge	180:96ed750bd169	1462	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	1463	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	1464
Anna Bridge	180:96ed750bd169	1465	/* MPU Region Number Register Definitions */
Anna Bridge	180:96ed750bd169	1466	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
Anna Bridge	180:96ed750bd169	1467	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Anna Bridge	180:96ed750bd169	1468
Anna Bridge	180:96ed750bd169	1469	/* MPU Region Base Address Register Definitions */
Anna Bridge	180:96ed750bd169	1470	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
Anna Bridge	180:96ed750bd169	1471	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Anna Bridge	180:96ed750bd169	1472
Anna Bridge	180:96ed750bd169	1473	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
Anna Bridge	180:96ed750bd169	1474	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Anna Bridge	180:96ed750bd169	1475
Anna Bridge	180:96ed750bd169	1476	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
Anna Bridge	180:96ed750bd169	1477	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Anna Bridge	180:96ed750bd169	1478
Anna Bridge	180:96ed750bd169	1479	/* MPU Region Attribute and Size Register Definitions */
Anna Bridge	180:96ed750bd169	1480	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
Anna Bridge	180:96ed750bd169	1481	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Anna Bridge	180:96ed750bd169	1482
Anna Bridge	180:96ed750bd169	1483	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
Anna Bridge	180:96ed750bd169	1484	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Anna Bridge	180:96ed750bd169	1485
Anna Bridge	180:96ed750bd169	1486	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
Anna Bridge	180:96ed750bd169	1487	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Anna Bridge	180:96ed750bd169	1488
Anna Bridge	180:96ed750bd169	1489	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
Anna Bridge	180:96ed750bd169	1490	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Anna Bridge	180:96ed750bd169	1491
Anna Bridge	180:96ed750bd169	1492	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
Anna Bridge	180:96ed750bd169	1493	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Anna Bridge	180:96ed750bd169	1494
Anna Bridge	180:96ed750bd169	1495	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
Anna Bridge	180:96ed750bd169	1496	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Anna Bridge	180:96ed750bd169	1497
Anna Bridge	180:96ed750bd169	1498	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
Anna Bridge	180:96ed750bd169	1499	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Anna Bridge	180:96ed750bd169	1500
Anna Bridge	180:96ed750bd169	1501	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
Anna Bridge	180:96ed750bd169	1502	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Anna Bridge	180:96ed750bd169	1503
Anna Bridge	180:96ed750bd169	1504	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
Anna Bridge	180:96ed750bd169	1505	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Anna Bridge	180:96ed750bd169	1506
Anna Bridge	180:96ed750bd169	1507	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
Anna Bridge	180:96ed750bd169	1508	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Anna Bridge	180:96ed750bd169	1509
Anna Bridge	180:96ed750bd169	1510	/@} end of group CMSIS_MPU /
Anna Bridge	180:96ed750bd169	1511	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
Anna Bridge	180:96ed750bd169	1512
Anna Bridge	180:96ed750bd169	1513
Anna Bridge	180:96ed750bd169	1514	/**
Anna Bridge	180:96ed750bd169	1515	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1516	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Anna Bridge	180:96ed750bd169	1517	\brief Type definitions for the Floating Point Unit (FPU)
Anna Bridge	180:96ed750bd169	1518	@{
Anna Bridge	180:96ed750bd169	1519	*/
Anna Bridge	180:96ed750bd169	1520
Anna Bridge	180:96ed750bd169	1521	/**
Anna Bridge	180:96ed750bd169	1522	\brief Structure type to access the Floating Point Unit (FPU).
Anna Bridge	180:96ed750bd169	1523	*/
Anna Bridge	180:96ed750bd169	1524	typedef struct
Anna Bridge	180:96ed750bd169	1525	{
Anna Bridge	180:96ed750bd169	1526	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	1527	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Anna Bridge	180:96ed750bd169	1528	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Anna Bridge	180:96ed750bd169	1529	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Anna Bridge	180:96ed750bd169	1530	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Anna Bridge	180:96ed750bd169	1531	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Anna Bridge	180:96ed750bd169	1532	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
Anna Bridge	180:96ed750bd169	1533	} FPU_Type;
Anna Bridge	180:96ed750bd169	1534
Anna Bridge	180:96ed750bd169	1535	/* Floating-Point Context Control Register Definitions */
Anna Bridge	180:96ed750bd169	1536	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
Anna Bridge	180:96ed750bd169	1537	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Anna Bridge	180:96ed750bd169	1538
Anna Bridge	180:96ed750bd169	1539	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
Anna Bridge	180:96ed750bd169	1540	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Anna Bridge	180:96ed750bd169	1541
Anna Bridge	180:96ed750bd169	1542	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
Anna Bridge	180:96ed750bd169	1543	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Anna Bridge	180:96ed750bd169	1544
Anna Bridge	180:96ed750bd169	1545	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
Anna Bridge	180:96ed750bd169	1546	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Anna Bridge	180:96ed750bd169	1547
Anna Bridge	180:96ed750bd169	1548	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
Anna Bridge	180:96ed750bd169	1549	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Anna Bridge	180:96ed750bd169	1550
Anna Bridge	180:96ed750bd169	1551	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
Anna Bridge	180:96ed750bd169	1552	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Anna Bridge	180:96ed750bd169	1553
Anna Bridge	180:96ed750bd169	1554	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
Anna Bridge	180:96ed750bd169	1555	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Anna Bridge	180:96ed750bd169	1556
Anna Bridge	180:96ed750bd169	1557	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
Anna Bridge	180:96ed750bd169	1558	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Anna Bridge	180:96ed750bd169	1559
Anna Bridge	180:96ed750bd169	1560	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
Anna Bridge	180:96ed750bd169	1561	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Anna Bridge	180:96ed750bd169	1562
Anna Bridge	180:96ed750bd169	1563	/* Floating-Point Context Address Register Definitions */
Anna Bridge	180:96ed750bd169	1564	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
Anna Bridge	180:96ed750bd169	1565	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Anna Bridge	180:96ed750bd169	1566
Anna Bridge	180:96ed750bd169	1567	/* Floating-Point Default Status Control Register Definitions */
Anna Bridge	180:96ed750bd169	1568	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
Anna Bridge	180:96ed750bd169	1569	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Anna Bridge	180:96ed750bd169	1570
Anna Bridge	180:96ed750bd169	1571	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
Anna Bridge	180:96ed750bd169	1572	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Anna Bridge	180:96ed750bd169	1573
Anna Bridge	180:96ed750bd169	1574	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
Anna Bridge	180:96ed750bd169	1575	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Anna Bridge	180:96ed750bd169	1576
Anna Bridge	180:96ed750bd169	1577	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
Anna Bridge	180:96ed750bd169	1578	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Anna Bridge	180:96ed750bd169	1579
Anna Bridge	180:96ed750bd169	1580	/* Media and FP Feature Register 0 Definitions */
Anna Bridge	180:96ed750bd169	1581	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
Anna Bridge	180:96ed750bd169	1582	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Anna Bridge	180:96ed750bd169	1583
Anna Bridge	180:96ed750bd169	1584	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
Anna Bridge	180:96ed750bd169	1585	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Anna Bridge	180:96ed750bd169	1586
Anna Bridge	180:96ed750bd169	1587	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
Anna Bridge	180:96ed750bd169	1588	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Anna Bridge	180:96ed750bd169	1589
Anna Bridge	180:96ed750bd169	1590	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
Anna Bridge	180:96ed750bd169	1591	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Anna Bridge	180:96ed750bd169	1592
Anna Bridge	180:96ed750bd169	1593	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
Anna Bridge	180:96ed750bd169	1594	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Anna Bridge	180:96ed750bd169	1595
Anna Bridge	180:96ed750bd169	1596	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
Anna Bridge	180:96ed750bd169	1597	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Anna Bridge	180:96ed750bd169	1598
Anna Bridge	180:96ed750bd169	1599	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
Anna Bridge	180:96ed750bd169	1600	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Anna Bridge	180:96ed750bd169	1601
Anna Bridge	180:96ed750bd169	1602	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
Anna Bridge	180:96ed750bd169	1603	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Anna Bridge	180:96ed750bd169	1604
Anna Bridge	180:96ed750bd169	1605	/* Media and FP Feature Register 1 Definitions */
Anna Bridge	180:96ed750bd169	1606	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
Anna Bridge	180:96ed750bd169	1607	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Anna Bridge	180:96ed750bd169	1608
Anna Bridge	180:96ed750bd169	1609	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
Anna Bridge	180:96ed750bd169	1610	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Anna Bridge	180:96ed750bd169	1611
Anna Bridge	180:96ed750bd169	1612	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
Anna Bridge	180:96ed750bd169	1613	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Anna Bridge	180:96ed750bd169	1614
Anna Bridge	180:96ed750bd169	1615	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
Anna Bridge	180:96ed750bd169	1616	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Anna Bridge	180:96ed750bd169	1617
Anna Bridge	180:96ed750bd169	1618	/* Media and FP Feature Register 2 Definitions */
Anna Bridge	180:96ed750bd169	1619
Anna Bridge	180:96ed750bd169	1620	/@} end of group CMSIS_FPU /
Anna Bridge	180:96ed750bd169	1621
Anna Bridge	180:96ed750bd169	1622
Anna Bridge	180:96ed750bd169	1623	/**
Anna Bridge	180:96ed750bd169	1624	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1625	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge	180:96ed750bd169	1626	\brief Type definitions for the Core Debug Registers
Anna Bridge	180:96ed750bd169	1627	@{
Anna Bridge	180:96ed750bd169	1628	*/
Anna Bridge	180:96ed750bd169	1629
Anna Bridge	180:96ed750bd169	1630	/**
Anna Bridge	180:96ed750bd169	1631	\brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge	180:96ed750bd169	1632	*/
Anna Bridge	180:96ed750bd169	1633	typedef struct
Anna Bridge	180:96ed750bd169	1634	{
Anna Bridge	180:96ed750bd169	1635	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Anna Bridge	180:96ed750bd169	1636	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Anna Bridge	180:96ed750bd169	1637	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Anna Bridge	180:96ed750bd169	1638	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Anna Bridge	180:96ed750bd169	1639	} CoreDebug_Type;
Anna Bridge	180:96ed750bd169	1640
Anna Bridge	180:96ed750bd169	1641	/* Debug Halting Control and Status Register Definitions */
Anna Bridge	180:96ed750bd169	1642	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
Anna Bridge	180:96ed750bd169	1643	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Anna Bridge	180:96ed750bd169	1644
Anna Bridge	180:96ed750bd169	1645	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
Anna Bridge	180:96ed750bd169	1646	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Anna Bridge	180:96ed750bd169	1647
Anna Bridge	180:96ed750bd169	1648	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Anna Bridge	180:96ed750bd169	1649	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Anna Bridge	180:96ed750bd169	1650
Anna Bridge	180:96ed750bd169	1651	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
Anna Bridge	180:96ed750bd169	1652	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Anna Bridge	180:96ed750bd169	1653
Anna Bridge	180:96ed750bd169	1654	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
Anna Bridge	180:96ed750bd169	1655	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Anna Bridge	180:96ed750bd169	1656
Anna Bridge	180:96ed750bd169	1657	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
Anna Bridge	180:96ed750bd169	1658	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Anna Bridge	180:96ed750bd169	1659
Anna Bridge	180:96ed750bd169	1660	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
Anna Bridge	180:96ed750bd169	1661	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Anna Bridge	180:96ed750bd169	1662
Anna Bridge	180:96ed750bd169	1663	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Anna Bridge	180:96ed750bd169	1664	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Anna Bridge	180:96ed750bd169	1665
Anna Bridge	180:96ed750bd169	1666	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
Anna Bridge	180:96ed750bd169	1667	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Anna Bridge	180:96ed750bd169	1668
Anna Bridge	180:96ed750bd169	1669	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
Anna Bridge	180:96ed750bd169	1670	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Anna Bridge	180:96ed750bd169	1671
Anna Bridge	180:96ed750bd169	1672	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
Anna Bridge	180:96ed750bd169	1673	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Anna Bridge	180:96ed750bd169	1674
Anna Bridge	180:96ed750bd169	1675	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
Anna Bridge	180:96ed750bd169	1676	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Anna Bridge	180:96ed750bd169	1677
Anna Bridge	180:96ed750bd169	1678	/* Debug Core Register Selector Register Definitions */
Anna Bridge	180:96ed750bd169	1679	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
Anna Bridge	180:96ed750bd169	1680	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Anna Bridge	180:96ed750bd169	1681
Anna Bridge	180:96ed750bd169	1682	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
Anna Bridge	180:96ed750bd169	1683	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Anna Bridge	180:96ed750bd169	1684
Anna Bridge	180:96ed750bd169	1685	/* Debug Exception and Monitor Control Register Definitions */
Anna Bridge	180:96ed750bd169	1686	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
Anna Bridge	180:96ed750bd169	1687	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Anna Bridge	180:96ed750bd169	1688
Anna Bridge	180:96ed750bd169	1689	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
Anna Bridge	180:96ed750bd169	1690	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Anna Bridge	180:96ed750bd169	1691
Anna Bridge	180:96ed750bd169	1692	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
Anna Bridge	180:96ed750bd169	1693	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Anna Bridge	180:96ed750bd169	1694
Anna Bridge	180:96ed750bd169	1695	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
Anna Bridge	180:96ed750bd169	1696	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Anna Bridge	180:96ed750bd169	1697
Anna Bridge	180:96ed750bd169	1698	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
Anna Bridge	180:96ed750bd169	1699	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Anna Bridge	180:96ed750bd169	1700
Anna Bridge	180:96ed750bd169	1701	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
Anna Bridge	180:96ed750bd169	1702	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Anna Bridge	180:96ed750bd169	1703
Anna Bridge	180:96ed750bd169	1704	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
Anna Bridge	180:96ed750bd169	1705	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Anna Bridge	180:96ed750bd169	1706
Anna Bridge	180:96ed750bd169	1707	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
Anna Bridge	180:96ed750bd169	1708	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Anna Bridge	180:96ed750bd169	1709
Anna Bridge	180:96ed750bd169	1710	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
Anna Bridge	180:96ed750bd169	1711	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Anna Bridge	180:96ed750bd169	1712
Anna Bridge	180:96ed750bd169	1713	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
Anna Bridge	180:96ed750bd169	1714	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Anna Bridge	180:96ed750bd169	1715
Anna Bridge	180:96ed750bd169	1716	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
Anna Bridge	180:96ed750bd169	1717	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Anna Bridge	180:96ed750bd169	1718
Anna Bridge	180:96ed750bd169	1719	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
Anna Bridge	180:96ed750bd169	1720	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Anna Bridge	180:96ed750bd169	1721
Anna Bridge	180:96ed750bd169	1722	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
Anna Bridge	180:96ed750bd169	1723	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Anna Bridge	180:96ed750bd169	1724
Anna Bridge	180:96ed750bd169	1725	/@} end of group CMSIS_CoreDebug /
Anna Bridge	180:96ed750bd169	1726
Anna Bridge	180:96ed750bd169	1727
Anna Bridge	180:96ed750bd169	1728	/**
Anna Bridge	180:96ed750bd169	1729	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1730	\defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge	180:96ed750bd169	1731	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge	180:96ed750bd169	1732	@{
Anna Bridge	180:96ed750bd169	1733	*/
Anna Bridge	180:96ed750bd169	1734
Anna Bridge	180:96ed750bd169	1735	/**
Anna Bridge	180:96ed750bd169	1736	\brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge	180:96ed750bd169	1737	\param[in] field Name of the register bit field.
Anna Bridge	180:96ed750bd169	1738	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge	180:96ed750bd169	1739	\return Masked and shifted value.
Anna Bridge	180:96ed750bd169	1740	*/
Anna Bridge	180:96ed750bd169	1741	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge	180:96ed750bd169	1742
Anna Bridge	180:96ed750bd169	1743	/**
Anna Bridge	180:96ed750bd169	1744	\brief Mask and shift a register value to extract a bit filed value.
Anna Bridge	180:96ed750bd169	1745	\param[in] field Name of the register bit field.
Anna Bridge	180:96ed750bd169	1746	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge	180:96ed750bd169	1747	\return Masked and shifted bit field value.
Anna Bridge	180:96ed750bd169	1748	*/
Anna Bridge	180:96ed750bd169	1749	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge	180:96ed750bd169	1750
Anna Bridge	180:96ed750bd169	1751	/@} end of group CMSIS_core_bitfield /
Anna Bridge	180:96ed750bd169	1752
Anna Bridge	180:96ed750bd169	1753
Anna Bridge	180:96ed750bd169	1754	/**
Anna Bridge	180:96ed750bd169	1755	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1756	\defgroup CMSIS_core_base Core Definitions
Anna Bridge	180:96ed750bd169	1757	\brief Definitions for base addresses, unions, and structures.
Anna Bridge	180:96ed750bd169	1758	@{
Anna Bridge	180:96ed750bd169	1759	*/
Anna Bridge	180:96ed750bd169	1760
Anna Bridge	180:96ed750bd169	1761	/* Memory mapping of Core Hardware */
Anna Bridge	180:96ed750bd169	1762	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Anna Bridge	180:96ed750bd169	1763	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Anna Bridge	180:96ed750bd169	1764	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Anna Bridge	180:96ed750bd169	1765	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Anna Bridge	180:96ed750bd169	1766	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Anna Bridge	180:96ed750bd169	1767	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Anna Bridge	180:96ed750bd169	1768	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Anna Bridge	180:96ed750bd169	1769	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Anna Bridge	180:96ed750bd169	1770
Anna Bridge	180:96ed750bd169	1771	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Anna Bridge	180:96ed750bd169	1772	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Anna Bridge	180:96ed750bd169	1773	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Anna Bridge	180:96ed750bd169	1774	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Anna Bridge	180:96ed750bd169	1775	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Anna Bridge	180:96ed750bd169	1776	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Anna Bridge	180:96ed750bd169	1777	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Anna Bridge	180:96ed750bd169	1778	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Anna Bridge	180:96ed750bd169	1779
Anna Bridge	180:96ed750bd169	1780	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1781	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Anna Bridge	180:96ed750bd169	1782	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Anna Bridge	180:96ed750bd169	1783	#endif
Anna Bridge	180:96ed750bd169	1784
Anna Bridge	180:96ed750bd169	1785	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Anna Bridge	180:96ed750bd169	1786	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Anna Bridge	180:96ed750bd169	1787
Anna Bridge	180:96ed750bd169	1788	/@} /
Anna Bridge	180:96ed750bd169	1789
Anna Bridge	180:96ed750bd169	1790
Anna Bridge	180:96ed750bd169	1791
Anna Bridge	180:96ed750bd169	1792	/*******************************************************************************
Anna Bridge	180:96ed750bd169	1793	* Hardware Abstraction Layer
Anna Bridge	180:96ed750bd169	1794	Core Function Interface contains:
Anna Bridge	180:96ed750bd169	1795	- Core NVIC Functions
Anna Bridge	180:96ed750bd169	1796	- Core SysTick Functions
Anna Bridge	180:96ed750bd169	1797	- Core Debug Functions
Anna Bridge	180:96ed750bd169	1798	- Core Register Access Functions
Anna Bridge	180:96ed750bd169	1799	******************************************************************************/
Anna Bridge	180:96ed750bd169	1800	/**
Anna Bridge	180:96ed750bd169	1801	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge	180:96ed750bd169	1802	*/
Anna Bridge	180:96ed750bd169	1803
Anna Bridge	180:96ed750bd169	1804
Anna Bridge	180:96ed750bd169	1805
Anna Bridge	180:96ed750bd169	1806	/* ########################## NVIC functions #################################### */
Anna Bridge	180:96ed750bd169	1807	/**
Anna Bridge	180:96ed750bd169	1808	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	1809	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge	180:96ed750bd169	1810	\brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge	180:96ed750bd169	1811	@{
Anna Bridge	180:96ed750bd169	1812	*/
Anna Bridge	180:96ed750bd169	1813
Anna Bridge	180:96ed750bd169	1814	#ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge	180:96ed750bd169	1815	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1816	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge	180:96ed750bd169	1817	#endif
Anna Bridge	180:96ed750bd169	1818	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1819	#else
Anna Bridge	180:96ed750bd169	1820	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge	180:96ed750bd169	1821	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge	180:96ed750bd169	1822	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge	180:96ed750bd169	1823	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge	180:96ed750bd169	1824	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge	180:96ed750bd169	1825	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge	180:96ed750bd169	1826	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge	180:96ed750bd169	1827	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge	180:96ed750bd169	1828	#define NVIC_GetActive __NVIC_GetActive
Anna Bridge	180:96ed750bd169	1829	#define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge	180:96ed750bd169	1830	#define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge	180:96ed750bd169	1831	#define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge	180:96ed750bd169	1832	#endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge	180:96ed750bd169	1833
Anna Bridge	180:96ed750bd169	1834	#ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge	180:96ed750bd169	1835	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1836	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge	180:96ed750bd169	1837	#endif
Anna Bridge	180:96ed750bd169	1838	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1839	#else
Anna Bridge	180:96ed750bd169	1840	#define NVIC_SetVector __NVIC_SetVector
Anna Bridge	180:96ed750bd169	1841	#define NVIC_GetVector __NVIC_GetVector
Anna Bridge	180:96ed750bd169	1842	#endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge	180:96ed750bd169	1843
Anna Bridge	180:96ed750bd169	1844	#define NVIC_USER_IRQ_OFFSET 16
Anna Bridge	180:96ed750bd169	1845
Anna Bridge	180:96ed750bd169	1846
AnnaBridge	188:bcfe06ba3d64	1847	/* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge	188:bcfe06ba3d64	1848	#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge	188:bcfe06ba3d64	1849	#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge	188:bcfe06ba3d64	1850	#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge	188:bcfe06ba3d64	1851	#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
AnnaBridge	188:bcfe06ba3d64	1852	#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
AnnaBridge	188:bcfe06ba3d64	1853	#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
AnnaBridge	188:bcfe06ba3d64	1854
Anna Bridge	180:96ed750bd169	1855
Anna Bridge	180:96ed750bd169	1856	/**
Anna Bridge	180:96ed750bd169	1857	\brief Set Priority Grouping
Anna Bridge	180:96ed750bd169	1858	\details Sets the priority grouping field using the required unlock sequence.
Anna Bridge	180:96ed750bd169	1859	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	180:96ed750bd169	1860	Only values from 0..7 are used.
Anna Bridge	180:96ed750bd169	1861	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	1862	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	1863	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	180:96ed750bd169	1864	*/
Anna Bridge	180:96ed750bd169	1865	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge	180:96ed750bd169	1866	{
Anna Bridge	180:96ed750bd169	1867	uint32_t reg_value;
Anna Bridge	180:96ed750bd169	1868	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	1869
Anna Bridge	180:96ed750bd169	1870	reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge	180:96ed750bd169	1871	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	180:96ed750bd169	1872	reg_value = (reg_value \|
Anna Bridge	180:96ed750bd169	1873	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	186:707f6e361f3e	1874	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
Anna Bridge	180:96ed750bd169	1875	SCB->AIRCR = reg_value;
Anna Bridge	180:96ed750bd169	1876	}
Anna Bridge	180:96ed750bd169	1877
Anna Bridge	180:96ed750bd169	1878
Anna Bridge	180:96ed750bd169	1879	/**
Anna Bridge	180:96ed750bd169	1880	\brief Get Priority Grouping
Anna Bridge	180:96ed750bd169	1881	\details Reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge	180:96ed750bd169	1882	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	180:96ed750bd169	1883	*/
Anna Bridge	180:96ed750bd169	1884	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge	180:96ed750bd169	1885	{
Anna Bridge	180:96ed750bd169	1886	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	180:96ed750bd169	1887	}
Anna Bridge	180:96ed750bd169	1888
Anna Bridge	180:96ed750bd169	1889
Anna Bridge	180:96ed750bd169	1890	/**
Anna Bridge	180:96ed750bd169	1891	\brief Enable Interrupt
Anna Bridge	180:96ed750bd169	1892	\details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	1893	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1894	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1895	*/
Anna Bridge	180:96ed750bd169	1896	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1897	{
Anna Bridge	180:96ed750bd169	1898	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1899	{
Anna Bridge	186:707f6e361f3e	1900	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1901	}
Anna Bridge	180:96ed750bd169	1902	}
Anna Bridge	180:96ed750bd169	1903
Anna Bridge	180:96ed750bd169	1904
Anna Bridge	180:96ed750bd169	1905	/**
Anna Bridge	180:96ed750bd169	1906	\brief Get Interrupt Enable status
Anna Bridge	180:96ed750bd169	1907	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	1908	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1909	\return 0 Interrupt is not enabled.
Anna Bridge	180:96ed750bd169	1910	\return 1 Interrupt is enabled.
Anna Bridge	180:96ed750bd169	1911	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1912	*/
Anna Bridge	180:96ed750bd169	1913	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1914	{
Anna Bridge	180:96ed750bd169	1915	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1916	{
Anna Bridge	186:707f6e361f3e	1917	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	1918	}
Anna Bridge	180:96ed750bd169	1919	else
Anna Bridge	180:96ed750bd169	1920	{
Anna Bridge	180:96ed750bd169	1921	return(0U);
Anna Bridge	180:96ed750bd169	1922	}
Anna Bridge	180:96ed750bd169	1923	}
Anna Bridge	180:96ed750bd169	1924
Anna Bridge	180:96ed750bd169	1925
Anna Bridge	180:96ed750bd169	1926	/**
Anna Bridge	180:96ed750bd169	1927	\brief Disable Interrupt
Anna Bridge	180:96ed750bd169	1928	\details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	1929	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1930	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1931	*/
Anna Bridge	180:96ed750bd169	1932	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1933	{
Anna Bridge	180:96ed750bd169	1934	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1935	{
Anna Bridge	186:707f6e361f3e	1936	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1937	__DSB();
Anna Bridge	180:96ed750bd169	1938	__ISB();
Anna Bridge	180:96ed750bd169	1939	}
Anna Bridge	180:96ed750bd169	1940	}
Anna Bridge	180:96ed750bd169	1941
Anna Bridge	180:96ed750bd169	1942
Anna Bridge	180:96ed750bd169	1943	/**
Anna Bridge	180:96ed750bd169	1944	\brief Get Pending Interrupt
Anna Bridge	180:96ed750bd169	1945	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge	180:96ed750bd169	1946	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1947	\return 0 Interrupt status is not pending.
Anna Bridge	180:96ed750bd169	1948	\return 1 Interrupt status is pending.
Anna Bridge	180:96ed750bd169	1949	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1950	*/
Anna Bridge	180:96ed750bd169	1951	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1952	{
Anna Bridge	180:96ed750bd169	1953	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1954	{
Anna Bridge	186:707f6e361f3e	1955	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	1956	}
Anna Bridge	180:96ed750bd169	1957	else
Anna Bridge	180:96ed750bd169	1958	{
Anna Bridge	180:96ed750bd169	1959	return(0U);
Anna Bridge	180:96ed750bd169	1960	}
Anna Bridge	180:96ed750bd169	1961	}
Anna Bridge	180:96ed750bd169	1962
Anna Bridge	180:96ed750bd169	1963
Anna Bridge	180:96ed750bd169	1964	/**
Anna Bridge	180:96ed750bd169	1965	\brief Set Pending Interrupt
Anna Bridge	180:96ed750bd169	1966	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	180:96ed750bd169	1967	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1968	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1969	*/
Anna Bridge	180:96ed750bd169	1970	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1971	{
Anna Bridge	180:96ed750bd169	1972	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1973	{
Anna Bridge	186:707f6e361f3e	1974	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1975	}
Anna Bridge	180:96ed750bd169	1976	}
Anna Bridge	180:96ed750bd169	1977
Anna Bridge	180:96ed750bd169	1978
Anna Bridge	180:96ed750bd169	1979	/**
Anna Bridge	180:96ed750bd169	1980	\brief Clear Pending Interrupt
Anna Bridge	180:96ed750bd169	1981	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	180:96ed750bd169	1982	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1983	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1984	*/
Anna Bridge	180:96ed750bd169	1985	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1986	{
Anna Bridge	180:96ed750bd169	1987	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1988	{
Anna Bridge	186:707f6e361f3e	1989	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1990	}
Anna Bridge	180:96ed750bd169	1991	}
Anna Bridge	180:96ed750bd169	1992
Anna Bridge	180:96ed750bd169	1993
Anna Bridge	180:96ed750bd169	1994	/**
Anna Bridge	180:96ed750bd169	1995	\brief Get Active Interrupt
Anna Bridge	180:96ed750bd169	1996	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	1997	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1998	\return 0 Interrupt status is not active.
Anna Bridge	180:96ed750bd169	1999	\return 1 Interrupt status is active.
Anna Bridge	180:96ed750bd169	2000	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2001	*/
Anna Bridge	180:96ed750bd169	2002	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2003	{
Anna Bridge	180:96ed750bd169	2004	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2005	{
Anna Bridge	186:707f6e361f3e	2006	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2007	}
Anna Bridge	180:96ed750bd169	2008	else
Anna Bridge	180:96ed750bd169	2009	{
Anna Bridge	180:96ed750bd169	2010	return(0U);
Anna Bridge	180:96ed750bd169	2011	}
Anna Bridge	180:96ed750bd169	2012	}
Anna Bridge	180:96ed750bd169	2013
Anna Bridge	180:96ed750bd169	2014
Anna Bridge	180:96ed750bd169	2015	/**
Anna Bridge	180:96ed750bd169	2016	\brief Set Interrupt Priority
Anna Bridge	180:96ed750bd169	2017	\details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge	180:96ed750bd169	2018	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2019	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2020	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2021	\param [in] priority Priority to set.
Anna Bridge	180:96ed750bd169	2022	\note The priority cannot be set for every processor exception.
Anna Bridge	180:96ed750bd169	2023	*/
Anna Bridge	180:96ed750bd169	2024	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	180:96ed750bd169	2025	{
Anna Bridge	180:96ed750bd169	2026	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2027	{
Anna Bridge	186:707f6e361f3e	2028	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	2029	}
Anna Bridge	180:96ed750bd169	2030	else
Anna Bridge	180:96ed750bd169	2031	{
Anna Bridge	186:707f6e361f3e	2032	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	2033	}
Anna Bridge	180:96ed750bd169	2034	}
Anna Bridge	180:96ed750bd169	2035
Anna Bridge	180:96ed750bd169	2036
Anna Bridge	180:96ed750bd169	2037	/**
Anna Bridge	180:96ed750bd169	2038	\brief Get Interrupt Priority
Anna Bridge	180:96ed750bd169	2039	\details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge	180:96ed750bd169	2040	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2041	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2042	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2043	\return Interrupt Priority.
Anna Bridge	180:96ed750bd169	2044	Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge	180:96ed750bd169	2045	*/
Anna Bridge	180:96ed750bd169	2046	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2047	{
Anna Bridge	180:96ed750bd169	2048
Anna Bridge	180:96ed750bd169	2049	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2050	{
Anna Bridge	186:707f6e361f3e	2051	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	2052	}
Anna Bridge	180:96ed750bd169	2053	else
Anna Bridge	180:96ed750bd169	2054	{
Anna Bridge	186:707f6e361f3e	2055	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	2056	}
Anna Bridge	180:96ed750bd169	2057	}
Anna Bridge	180:96ed750bd169	2058
Anna Bridge	180:96ed750bd169	2059
Anna Bridge	180:96ed750bd169	2060	/**
Anna Bridge	180:96ed750bd169	2061	\brief Encode Priority
Anna Bridge	180:96ed750bd169	2062	\details Encodes the priority for an interrupt with the given priority group,
Anna Bridge	180:96ed750bd169	2063	preemptive priority value, and subpriority value.
Anna Bridge	180:96ed750bd169	2064	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	2065	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	2066	\param [in] PriorityGroup Used priority group.
Anna Bridge	180:96ed750bd169	2067	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	180:96ed750bd169	2068	\param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge	180:96ed750bd169	2069	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge	180:96ed750bd169	2070	*/
Anna Bridge	180:96ed750bd169	2071	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge	180:96ed750bd169	2072	{
Anna Bridge	180:96ed750bd169	2073	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	2074	uint32_t PreemptPriorityBits;
Anna Bridge	180:96ed750bd169	2075	uint32_t SubPriorityBits;
Anna Bridge	180:96ed750bd169	2076
Anna Bridge	180:96ed750bd169	2077	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	180:96ed750bd169	2078	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	180:96ed750bd169	2079
Anna Bridge	180:96ed750bd169	2080	return (
Anna Bridge	180:96ed750bd169	2081	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Anna Bridge	180:96ed750bd169	2082	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge	180:96ed750bd169	2083	);
Anna Bridge	180:96ed750bd169	2084	}
Anna Bridge	180:96ed750bd169	2085
Anna Bridge	180:96ed750bd169	2086
Anna Bridge	180:96ed750bd169	2087	/**
Anna Bridge	180:96ed750bd169	2088	\brief Decode Priority
Anna Bridge	180:96ed750bd169	2089	\details Decodes an interrupt priority value with a given priority group to
Anna Bridge	180:96ed750bd169	2090	preemptive priority value and subpriority value.
Anna Bridge	180:96ed750bd169	2091	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	2092	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	2093	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge	180:96ed750bd169	2094	\param [in] PriorityGroup Used priority group.
Anna Bridge	180:96ed750bd169	2095	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	180:96ed750bd169	2096	\param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge	180:96ed750bd169	2097	*/
Anna Bridge	180:96ed750bd169	2098	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Anna Bridge	180:96ed750bd169	2099	{
Anna Bridge	180:96ed750bd169	2100	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	2101	uint32_t PreemptPriorityBits;
Anna Bridge	180:96ed750bd169	2102	uint32_t SubPriorityBits;
Anna Bridge	180:96ed750bd169	2103
Anna Bridge	180:96ed750bd169	2104	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	180:96ed750bd169	2105	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	180:96ed750bd169	2106
Anna Bridge	180:96ed750bd169	2107	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge	180:96ed750bd169	2108	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge	180:96ed750bd169	2109	}
Anna Bridge	180:96ed750bd169	2110
Anna Bridge	180:96ed750bd169	2111
Anna Bridge	180:96ed750bd169	2112	/**
Anna Bridge	180:96ed750bd169	2113	\brief Set Interrupt Vector
Anna Bridge	180:96ed750bd169	2114	\details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge	180:96ed750bd169	2115	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2116	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2117	VTOR must been relocated to SRAM before.
Anna Bridge	180:96ed750bd169	2118	\param [in] IRQn Interrupt number
Anna Bridge	180:96ed750bd169	2119	\param [in] vector Address of interrupt handler function
Anna Bridge	180:96ed750bd169	2120	*/
Anna Bridge	180:96ed750bd169	2121	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge	180:96ed750bd169	2122	{
Anna Bridge	180:96ed750bd169	2123	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	180:96ed750bd169	2124	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge	180:96ed750bd169	2125	}
Anna Bridge	180:96ed750bd169	2126
Anna Bridge	180:96ed750bd169	2127
Anna Bridge	180:96ed750bd169	2128	/**
Anna Bridge	180:96ed750bd169	2129	\brief Get Interrupt Vector
Anna Bridge	180:96ed750bd169	2130	\details Reads an interrupt vector from interrupt vector table.
Anna Bridge	180:96ed750bd169	2131	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2132	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2133	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2134	\return Address of interrupt handler function
Anna Bridge	180:96ed750bd169	2135	*/
Anna Bridge	180:96ed750bd169	2136	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2137	{
Anna Bridge	180:96ed750bd169	2138	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	180:96ed750bd169	2139	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge	180:96ed750bd169	2140	}
Anna Bridge	180:96ed750bd169	2141
Anna Bridge	180:96ed750bd169	2142
Anna Bridge	180:96ed750bd169	2143	/**
Anna Bridge	180:96ed750bd169	2144	\brief System Reset
Anna Bridge	180:96ed750bd169	2145	\details Initiates a system reset request to reset the MCU.
Anna Bridge	180:96ed750bd169	2146	*/
AnnaBridge	188:bcfe06ba3d64	2147	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge	180:96ed750bd169	2148	{
Anna Bridge	180:96ed750bd169	2149	__DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge	180:96ed750bd169	2150	buffered write are completed before reset */
Anna Bridge	180:96ed750bd169	2151	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	180:96ed750bd169	2152	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Anna Bridge	180:96ed750bd169	2153	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge	180:96ed750bd169	2154	__DSB(); /* Ensure completion of memory access */
Anna Bridge	180:96ed750bd169	2155
Anna Bridge	180:96ed750bd169	2156	for(;;) /* wait until reset */
Anna Bridge	180:96ed750bd169	2157	{
Anna Bridge	180:96ed750bd169	2158	__NOP();
Anna Bridge	180:96ed750bd169	2159	}
Anna Bridge	180:96ed750bd169	2160	}
Anna Bridge	180:96ed750bd169	2161
Anna Bridge	180:96ed750bd169	2162	/@} end of CMSIS_Core_NVICFunctions /
Anna Bridge	180:96ed750bd169	2163
Anna Bridge	180:96ed750bd169	2164	/* ########################## MPU functions #################################### */
Anna Bridge	180:96ed750bd169	2165
Anna Bridge	180:96ed750bd169	2166	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2167
Anna Bridge	180:96ed750bd169	2168	#include "mpu_armv7.h"
Anna Bridge	180:96ed750bd169	2169
Anna Bridge	180:96ed750bd169	2170	#endif
Anna Bridge	180:96ed750bd169	2171
Anna Bridge	180:96ed750bd169	2172	/* ########################## FPU functions #################################### */
Anna Bridge	180:96ed750bd169	2173	/**
Anna Bridge	180:96ed750bd169	2174	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2175	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge	180:96ed750bd169	2176	\brief Function that provides FPU type.
Anna Bridge	180:96ed750bd169	2177	@{
Anna Bridge	180:96ed750bd169	2178	*/
Anna Bridge	180:96ed750bd169	2179
Anna Bridge	180:96ed750bd169	2180	/**
Anna Bridge	180:96ed750bd169	2181	\brief get FPU type
Anna Bridge	180:96ed750bd169	2182	\details returns the FPU type
Anna Bridge	180:96ed750bd169	2183	\returns
Anna Bridge	180:96ed750bd169	2184	- \b 0: No FPU
Anna Bridge	180:96ed750bd169	2185	- \b 1: Single precision FPU
Anna Bridge	180:96ed750bd169	2186	- \b 2: Double + Single precision FPU
Anna Bridge	180:96ed750bd169	2187	*/
Anna Bridge	180:96ed750bd169	2188	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge	180:96ed750bd169	2189	{
Anna Bridge	180:96ed750bd169	2190	uint32_t mvfr0;
Anna Bridge	180:96ed750bd169	2191
Anna Bridge	180:96ed750bd169	2192	mvfr0 = SCB->MVFR0;
Anna Bridge	180:96ed750bd169	2193	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
Anna Bridge	180:96ed750bd169	2194	{
Anna Bridge	180:96ed750bd169	2195	return 2U; /* Double + Single precision FPU */
Anna Bridge	180:96ed750bd169	2196	}
Anna Bridge	180:96ed750bd169	2197	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
Anna Bridge	180:96ed750bd169	2198	{
Anna Bridge	180:96ed750bd169	2199	return 1U; /* Single precision FPU */
Anna Bridge	180:96ed750bd169	2200	}
Anna Bridge	180:96ed750bd169	2201	else
Anna Bridge	180:96ed750bd169	2202	{
Anna Bridge	180:96ed750bd169	2203	return 0U; /* No FPU */
Anna Bridge	180:96ed750bd169	2204	}
Anna Bridge	180:96ed750bd169	2205	}
Anna Bridge	180:96ed750bd169	2206
Anna Bridge	180:96ed750bd169	2207
Anna Bridge	180:96ed750bd169	2208	/@} end of CMSIS_Core_FpuFunctions /
Anna Bridge	180:96ed750bd169	2209
Anna Bridge	180:96ed750bd169	2210
Anna Bridge	180:96ed750bd169	2211
Anna Bridge	180:96ed750bd169	2212	/* ########################## Cache functions #################################### */
Anna Bridge	180:96ed750bd169	2213	/**
Anna Bridge	180:96ed750bd169	2214	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2215	\defgroup CMSIS_Core_CacheFunctions Cache Functions
Anna Bridge	180:96ed750bd169	2216	\brief Functions that configure Instruction and Data cache.
Anna Bridge	180:96ed750bd169	2217	@{
Anna Bridge	180:96ed750bd169	2218	*/
Anna Bridge	180:96ed750bd169	2219
Anna Bridge	180:96ed750bd169	2220	/* Cache Size ID Register Macros */
Anna Bridge	180:96ed750bd169	2221	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Anna Bridge	180:96ed750bd169	2222	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Anna Bridge	180:96ed750bd169	2223
Anna Bridge	180:96ed750bd169	2224
Anna Bridge	180:96ed750bd169	2225	/**
Anna Bridge	180:96ed750bd169	2226	\brief Enable I-Cache
Anna Bridge	180:96ed750bd169	2227	\details Turns on I-Cache
Anna Bridge	180:96ed750bd169	2228	*/
Anna Bridge	180:96ed750bd169	2229	__STATIC_INLINE void SCB_EnableICache (void)
Anna Bridge	180:96ed750bd169	2230	{
Anna Bridge	180:96ed750bd169	2231	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2232	__DSB();
Anna Bridge	180:96ed750bd169	2233	__ISB();
Anna Bridge	180:96ed750bd169	2234	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
Anna Bridge	180:96ed750bd169	2235	__DSB();
Anna Bridge	180:96ed750bd169	2236	__ISB();
Anna Bridge	180:96ed750bd169	2237	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
Anna Bridge	180:96ed750bd169	2238	__DSB();
Anna Bridge	180:96ed750bd169	2239	__ISB();
Anna Bridge	180:96ed750bd169	2240	#endif
Anna Bridge	180:96ed750bd169	2241	}
Anna Bridge	180:96ed750bd169	2242
Anna Bridge	180:96ed750bd169	2243
Anna Bridge	180:96ed750bd169	2244	/**
Anna Bridge	180:96ed750bd169	2245	\brief Disable I-Cache
Anna Bridge	180:96ed750bd169	2246	\details Turns off I-Cache
Anna Bridge	180:96ed750bd169	2247	*/
Anna Bridge	180:96ed750bd169	2248	__STATIC_INLINE void SCB_DisableICache (void)
Anna Bridge	180:96ed750bd169	2249	{
Anna Bridge	180:96ed750bd169	2250	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2251	__DSB();
Anna Bridge	180:96ed750bd169	2252	__ISB();
Anna Bridge	180:96ed750bd169	2253	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
Anna Bridge	180:96ed750bd169	2254	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
Anna Bridge	180:96ed750bd169	2255	__DSB();
Anna Bridge	180:96ed750bd169	2256	__ISB();
Anna Bridge	180:96ed750bd169	2257	#endif
Anna Bridge	180:96ed750bd169	2258	}
Anna Bridge	180:96ed750bd169	2259
Anna Bridge	180:96ed750bd169	2260
Anna Bridge	180:96ed750bd169	2261	/**
Anna Bridge	180:96ed750bd169	2262	\brief Invalidate I-Cache
Anna Bridge	180:96ed750bd169	2263	\details Invalidates I-Cache
Anna Bridge	180:96ed750bd169	2264	*/
Anna Bridge	180:96ed750bd169	2265	__STATIC_INLINE void SCB_InvalidateICache (void)
Anna Bridge	180:96ed750bd169	2266	{
Anna Bridge	180:96ed750bd169	2267	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2268	__DSB();
Anna Bridge	180:96ed750bd169	2269	__ISB();
Anna Bridge	180:96ed750bd169	2270	SCB->ICIALLU = 0UL;
Anna Bridge	180:96ed750bd169	2271	__DSB();
Anna Bridge	180:96ed750bd169	2272	__ISB();
Anna Bridge	180:96ed750bd169	2273	#endif
Anna Bridge	180:96ed750bd169	2274	}
Anna Bridge	180:96ed750bd169	2275
Anna Bridge	180:96ed750bd169	2276
Anna Bridge	180:96ed750bd169	2277	/**
Anna Bridge	180:96ed750bd169	2278	\brief Enable D-Cache
Anna Bridge	180:96ed750bd169	2279	\details Turns on D-Cache
Anna Bridge	180:96ed750bd169	2280	*/
Anna Bridge	180:96ed750bd169	2281	__STATIC_INLINE void SCB_EnableDCache (void)
Anna Bridge	180:96ed750bd169	2282	{
Anna Bridge	180:96ed750bd169	2283	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2284	uint32_t ccsidr;
Anna Bridge	180:96ed750bd169	2285	uint32_t sets;
Anna Bridge	180:96ed750bd169	2286	uint32_t ways;
Anna Bridge	180:96ed750bd169	2287
Anna Bridge	180:96ed750bd169	2288	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
Anna Bridge	180:96ed750bd169	2289	__DSB();
Anna Bridge	180:96ed750bd169	2290
Anna Bridge	180:96ed750bd169	2291	ccsidr = SCB->CCSIDR;
Anna Bridge	180:96ed750bd169	2292
Anna Bridge	180:96ed750bd169	2293	/* invalidate D-Cache */
Anna Bridge	180:96ed750bd169	2294	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Anna Bridge	180:96ed750bd169	2295	do {
Anna Bridge	180:96ed750bd169	2296	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Anna Bridge	180:96ed750bd169	2297	do {
Anna Bridge	180:96ed750bd169	2298	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
Anna Bridge	180:96ed750bd169	2299	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
Anna Bridge	180:96ed750bd169	2300	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	2301	__schedule_barrier();
Anna Bridge	180:96ed750bd169	2302	#endif
Anna Bridge	180:96ed750bd169	2303	} while (ways-- != 0U);
Anna Bridge	180:96ed750bd169	2304	} while(sets-- != 0U);
Anna Bridge	180:96ed750bd169	2305	__DSB();
Anna Bridge	180:96ed750bd169	2306
Anna Bridge	180:96ed750bd169	2307	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
Anna Bridge	180:96ed750bd169	2308
Anna Bridge	180:96ed750bd169	2309	__DSB();
Anna Bridge	180:96ed750bd169	2310	__ISB();
Anna Bridge	180:96ed750bd169	2311	#endif
Anna Bridge	180:96ed750bd169	2312	}
Anna Bridge	180:96ed750bd169	2313
Anna Bridge	180:96ed750bd169	2314
Anna Bridge	180:96ed750bd169	2315	/**
Anna Bridge	180:96ed750bd169	2316	\brief Disable D-Cache
Anna Bridge	180:96ed750bd169	2317	\details Turns off D-Cache
Anna Bridge	180:96ed750bd169	2318	*/
Anna Bridge	180:96ed750bd169	2319	__STATIC_INLINE void SCB_DisableDCache (void)
Anna Bridge	180:96ed750bd169	2320	{
Anna Bridge	180:96ed750bd169	2321	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	188:bcfe06ba3d64	2322	uint32_t ccsidr;
AnnaBridge	188:bcfe06ba3d64	2323	uint32_t sets;
AnnaBridge	188:bcfe06ba3d64	2324	uint32_t ways;
Anna Bridge	180:96ed750bd169	2325
Anna Bridge	180:96ed750bd169	2326	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
Anna Bridge	180:96ed750bd169	2327	__DSB();
Anna Bridge	180:96ed750bd169	2328
Anna Bridge	180:96ed750bd169	2329	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
Anna Bridge	180:96ed750bd169	2330	__DSB();
Anna Bridge	180:96ed750bd169	2331
Anna Bridge	180:96ed750bd169	2332	ccsidr = SCB->CCSIDR;
Anna Bridge	180:96ed750bd169	2333
Anna Bridge	180:96ed750bd169	2334	/* clean & invalidate D-Cache */
Anna Bridge	180:96ed750bd169	2335	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Anna Bridge	180:96ed750bd169	2336	do {
Anna Bridge	180:96ed750bd169	2337	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Anna Bridge	180:96ed750bd169	2338	do {
Anna Bridge	180:96ed750bd169	2339	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
Anna Bridge	180:96ed750bd169	2340	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
Anna Bridge	180:96ed750bd169	2341	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	2342	__schedule_barrier();
Anna Bridge	180:96ed750bd169	2343	#endif
Anna Bridge	180:96ed750bd169	2344	} while (ways-- != 0U);
Anna Bridge	180:96ed750bd169	2345	} while(sets-- != 0U);
Anna Bridge	180:96ed750bd169	2346
Anna Bridge	180:96ed750bd169	2347	__DSB();
Anna Bridge	180:96ed750bd169	2348	__ISB();
Anna Bridge	180:96ed750bd169	2349	#endif
Anna Bridge	180:96ed750bd169	2350	}
Anna Bridge	180:96ed750bd169	2351
Anna Bridge	180:96ed750bd169	2352
Anna Bridge	180:96ed750bd169	2353	/**
Anna Bridge	180:96ed750bd169	2354	\brief Invalidate D-Cache
Anna Bridge	180:96ed750bd169	2355	\details Invalidates D-Cache
Anna Bridge	180:96ed750bd169	2356	*/
Anna Bridge	180:96ed750bd169	2357	__STATIC_INLINE void SCB_InvalidateDCache (void)
Anna Bridge	180:96ed750bd169	2358	{
Anna Bridge	180:96ed750bd169	2359	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2360	uint32_t ccsidr;
Anna Bridge	180:96ed750bd169	2361	uint32_t sets;
Anna Bridge	180:96ed750bd169	2362	uint32_t ways;
Anna Bridge	180:96ed750bd169	2363
Anna Bridge	180:96ed750bd169	2364	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
Anna Bridge	180:96ed750bd169	2365	__DSB();
Anna Bridge	180:96ed750bd169	2366
Anna Bridge	180:96ed750bd169	2367	ccsidr = SCB->CCSIDR;
Anna Bridge	180:96ed750bd169	2368
Anna Bridge	180:96ed750bd169	2369	/* invalidate D-Cache */
Anna Bridge	180:96ed750bd169	2370	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Anna Bridge	180:96ed750bd169	2371	do {
Anna Bridge	180:96ed750bd169	2372	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Anna Bridge	180:96ed750bd169	2373	do {
Anna Bridge	180:96ed750bd169	2374	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
Anna Bridge	180:96ed750bd169	2375	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
Anna Bridge	180:96ed750bd169	2376	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	2377	__schedule_barrier();
Anna Bridge	180:96ed750bd169	2378	#endif
Anna Bridge	180:96ed750bd169	2379	} while (ways-- != 0U);
Anna Bridge	180:96ed750bd169	2380	} while(sets-- != 0U);
Anna Bridge	180:96ed750bd169	2381
Anna Bridge	180:96ed750bd169	2382	__DSB();
Anna Bridge	180:96ed750bd169	2383	__ISB();
Anna Bridge	180:96ed750bd169	2384	#endif
Anna Bridge	180:96ed750bd169	2385	}
Anna Bridge	180:96ed750bd169	2386
Anna Bridge	180:96ed750bd169	2387
Anna Bridge	180:96ed750bd169	2388	/**
Anna Bridge	180:96ed750bd169	2389	\brief Clean D-Cache
Anna Bridge	180:96ed750bd169	2390	\details Cleans D-Cache
Anna Bridge	180:96ed750bd169	2391	*/
Anna Bridge	180:96ed750bd169	2392	__STATIC_INLINE void SCB_CleanDCache (void)
Anna Bridge	180:96ed750bd169	2393	{
Anna Bridge	180:96ed750bd169	2394	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2395	uint32_t ccsidr;
Anna Bridge	180:96ed750bd169	2396	uint32_t sets;
Anna Bridge	180:96ed750bd169	2397	uint32_t ways;
Anna Bridge	180:96ed750bd169	2398
Anna Bridge	180:96ed750bd169	2399	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
Anna Bridge	180:96ed750bd169	2400	__DSB();
Anna Bridge	180:96ed750bd169	2401
Anna Bridge	180:96ed750bd169	2402	ccsidr = SCB->CCSIDR;
Anna Bridge	180:96ed750bd169	2403
Anna Bridge	180:96ed750bd169	2404	/* clean D-Cache */
Anna Bridge	180:96ed750bd169	2405	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Anna Bridge	180:96ed750bd169	2406	do {
Anna Bridge	180:96ed750bd169	2407	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Anna Bridge	180:96ed750bd169	2408	do {
Anna Bridge	180:96ed750bd169	2409	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
Anna Bridge	180:96ed750bd169	2410	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
Anna Bridge	180:96ed750bd169	2411	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	2412	__schedule_barrier();
Anna Bridge	180:96ed750bd169	2413	#endif
Anna Bridge	180:96ed750bd169	2414	} while (ways-- != 0U);
Anna Bridge	180:96ed750bd169	2415	} while(sets-- != 0U);
Anna Bridge	180:96ed750bd169	2416
Anna Bridge	180:96ed750bd169	2417	__DSB();
Anna Bridge	180:96ed750bd169	2418	__ISB();
Anna Bridge	180:96ed750bd169	2419	#endif
Anna Bridge	180:96ed750bd169	2420	}
Anna Bridge	180:96ed750bd169	2421
Anna Bridge	180:96ed750bd169	2422
Anna Bridge	180:96ed750bd169	2423	/**
Anna Bridge	180:96ed750bd169	2424	\brief Clean & Invalidate D-Cache
Anna Bridge	180:96ed750bd169	2425	\details Cleans and Invalidates D-Cache
Anna Bridge	180:96ed750bd169	2426	*/
Anna Bridge	180:96ed750bd169	2427	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Anna Bridge	180:96ed750bd169	2428	{
Anna Bridge	180:96ed750bd169	2429	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2430	uint32_t ccsidr;
Anna Bridge	180:96ed750bd169	2431	uint32_t sets;
Anna Bridge	180:96ed750bd169	2432	uint32_t ways;
Anna Bridge	180:96ed750bd169	2433
Anna Bridge	180:96ed750bd169	2434	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
Anna Bridge	180:96ed750bd169	2435	__DSB();
Anna Bridge	180:96ed750bd169	2436
Anna Bridge	180:96ed750bd169	2437	ccsidr = SCB->CCSIDR;
Anna Bridge	180:96ed750bd169	2438
Anna Bridge	180:96ed750bd169	2439	/* clean & invalidate D-Cache */
Anna Bridge	180:96ed750bd169	2440	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Anna Bridge	180:96ed750bd169	2441	do {
Anna Bridge	180:96ed750bd169	2442	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Anna Bridge	180:96ed750bd169	2443	do {
Anna Bridge	180:96ed750bd169	2444	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
Anna Bridge	180:96ed750bd169	2445	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
Anna Bridge	180:96ed750bd169	2446	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	2447	__schedule_barrier();
Anna Bridge	180:96ed750bd169	2448	#endif
Anna Bridge	180:96ed750bd169	2449	} while (ways-- != 0U);
Anna Bridge	180:96ed750bd169	2450	} while(sets-- != 0U);
Anna Bridge	180:96ed750bd169	2451
Anna Bridge	180:96ed750bd169	2452	__DSB();
Anna Bridge	180:96ed750bd169	2453	__ISB();
Anna Bridge	180:96ed750bd169	2454	#endif
Anna Bridge	180:96ed750bd169	2455	}
Anna Bridge	180:96ed750bd169	2456
Anna Bridge	180:96ed750bd169	2457
Anna Bridge	180:96ed750bd169	2458	/**
Anna Bridge	180:96ed750bd169	2459	\brief D-Cache Invalidate by address
Anna Bridge	180:96ed750bd169	2460	\details Invalidates D-Cache for the given address
Anna Bridge	180:96ed750bd169	2461	\param[in] addr address (aligned to 32-byte boundary)
Anna Bridge	180:96ed750bd169	2462	\param[in] dsize size of memory block (in number of bytes)
Anna Bridge	180:96ed750bd169	2463	*/
Anna Bridge	180:96ed750bd169	2464	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Anna Bridge	180:96ed750bd169	2465	{
Anna Bridge	180:96ed750bd169	2466	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2467	int32_t op_size = dsize;
Anna Bridge	180:96ed750bd169	2468	uint32_t op_addr = (uint32_t)addr;
Anna Bridge	180:96ed750bd169	2469	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
Anna Bridge	180:96ed750bd169	2470
Anna Bridge	180:96ed750bd169	2471	__DSB();
Anna Bridge	180:96ed750bd169	2472
Anna Bridge	180:96ed750bd169	2473	while (op_size > 0) {
Anna Bridge	180:96ed750bd169	2474	SCB->DCIMVAC = op_addr;
Anna Bridge	180:96ed750bd169	2475	op_addr += (uint32_t)linesize;
Anna Bridge	180:96ed750bd169	2476	op_size -= linesize;
Anna Bridge	180:96ed750bd169	2477	}
Anna Bridge	180:96ed750bd169	2478
Anna Bridge	180:96ed750bd169	2479	__DSB();
Anna Bridge	180:96ed750bd169	2480	__ISB();
Anna Bridge	180:96ed750bd169	2481	#endif
Anna Bridge	180:96ed750bd169	2482	}
Anna Bridge	180:96ed750bd169	2483
Anna Bridge	180:96ed750bd169	2484
Anna Bridge	180:96ed750bd169	2485	/**
Anna Bridge	180:96ed750bd169	2486	\brief D-Cache Clean by address
Anna Bridge	180:96ed750bd169	2487	\details Cleans D-Cache for the given address
Anna Bridge	180:96ed750bd169	2488	\param[in] addr address (aligned to 32-byte boundary)
Anna Bridge	180:96ed750bd169	2489	\param[in] dsize size of memory block (in number of bytes)
Anna Bridge	180:96ed750bd169	2490	*/
Anna Bridge	180:96ed750bd169	2491	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Anna Bridge	180:96ed750bd169	2492	{
Anna Bridge	180:96ed750bd169	2493	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2494	int32_t op_size = dsize;
Anna Bridge	180:96ed750bd169	2495	uint32_t op_addr = (uint32_t) addr;
Anna Bridge	180:96ed750bd169	2496	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
Anna Bridge	180:96ed750bd169	2497
Anna Bridge	180:96ed750bd169	2498	__DSB();
Anna Bridge	180:96ed750bd169	2499
Anna Bridge	180:96ed750bd169	2500	while (op_size > 0) {
Anna Bridge	180:96ed750bd169	2501	SCB->DCCMVAC = op_addr;
Anna Bridge	180:96ed750bd169	2502	op_addr += (uint32_t)linesize;
Anna Bridge	180:96ed750bd169	2503	op_size -= linesize;
Anna Bridge	180:96ed750bd169	2504	}
Anna Bridge	180:96ed750bd169	2505
Anna Bridge	180:96ed750bd169	2506	__DSB();
Anna Bridge	180:96ed750bd169	2507	__ISB();
Anna Bridge	180:96ed750bd169	2508	#endif
Anna Bridge	180:96ed750bd169	2509	}
Anna Bridge	180:96ed750bd169	2510
Anna Bridge	180:96ed750bd169	2511
Anna Bridge	180:96ed750bd169	2512	/**
Anna Bridge	180:96ed750bd169	2513	\brief D-Cache Clean and Invalidate by address
Anna Bridge	180:96ed750bd169	2514	\details Cleans and invalidates D_Cache for the given address
Anna Bridge	180:96ed750bd169	2515	\param[in] addr address (aligned to 32-byte boundary)
Anna Bridge	180:96ed750bd169	2516	\param[in] dsize size of memory block (in number of bytes)
Anna Bridge	180:96ed750bd169	2517	*/
Anna Bridge	180:96ed750bd169	2518	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Anna Bridge	180:96ed750bd169	2519	{
Anna Bridge	180:96ed750bd169	2520	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2521	int32_t op_size = dsize;
Anna Bridge	180:96ed750bd169	2522	uint32_t op_addr = (uint32_t) addr;
Anna Bridge	180:96ed750bd169	2523	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
Anna Bridge	180:96ed750bd169	2524
Anna Bridge	180:96ed750bd169	2525	__DSB();
Anna Bridge	180:96ed750bd169	2526
Anna Bridge	180:96ed750bd169	2527	while (op_size > 0) {
Anna Bridge	180:96ed750bd169	2528	SCB->DCCIMVAC = op_addr;
Anna Bridge	180:96ed750bd169	2529	op_addr += (uint32_t)linesize;
Anna Bridge	180:96ed750bd169	2530	op_size -= linesize;
Anna Bridge	180:96ed750bd169	2531	}
Anna Bridge	180:96ed750bd169	2532
Anna Bridge	180:96ed750bd169	2533	__DSB();
Anna Bridge	180:96ed750bd169	2534	__ISB();
Anna Bridge	180:96ed750bd169	2535	#endif
Anna Bridge	180:96ed750bd169	2536	}
Anna Bridge	180:96ed750bd169	2537
Anna Bridge	180:96ed750bd169	2538
Anna Bridge	180:96ed750bd169	2539	/@} end of CMSIS_Core_CacheFunctions /
Anna Bridge	180:96ed750bd169	2540
Anna Bridge	180:96ed750bd169	2541
Anna Bridge	180:96ed750bd169	2542
Anna Bridge	180:96ed750bd169	2543	/* ################################## SysTick function ############################################ */
Anna Bridge	180:96ed750bd169	2544	/**
Anna Bridge	180:96ed750bd169	2545	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2546	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge	180:96ed750bd169	2547	\brief Functions that configure the System.
Anna Bridge	180:96ed750bd169	2548	@{
Anna Bridge	180:96ed750bd169	2549	*/
Anna Bridge	180:96ed750bd169	2550
Anna Bridge	180:96ed750bd169	2551	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge	180:96ed750bd169	2552
Anna Bridge	180:96ed750bd169	2553	/**
Anna Bridge	180:96ed750bd169	2554	\brief System Tick Configuration
Anna Bridge	180:96ed750bd169	2555	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge	180:96ed750bd169	2556	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	180:96ed750bd169	2557	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	180:96ed750bd169	2558	\return 0 Function succeeded.
Anna Bridge	180:96ed750bd169	2559	\return 1 Function failed.
Anna Bridge	180:96ed750bd169	2560	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	180:96ed750bd169	2561	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	180:96ed750bd169	2562	must contain a vendor-specific implementation of this function.
Anna Bridge	180:96ed750bd169	2563	*/
Anna Bridge	180:96ed750bd169	2564	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge	180:96ed750bd169	2565	{
Anna Bridge	180:96ed750bd169	2566	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge	180:96ed750bd169	2567	{
Anna Bridge	180:96ed750bd169	2568	return (1UL); /* Reload value impossible */
Anna Bridge	180:96ed750bd169	2569	}
Anna Bridge	180:96ed750bd169	2570
Anna Bridge	180:96ed750bd169	2571	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	180:96ed750bd169	2572	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	180:96ed750bd169	2573	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	180:96ed750bd169	2574	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	180:96ed750bd169	2575	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	180:96ed750bd169	2576	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	180:96ed750bd169	2577	return (0UL); /* Function successful */
Anna Bridge	180:96ed750bd169	2578	}
Anna Bridge	180:96ed750bd169	2579
Anna Bridge	180:96ed750bd169	2580	#endif
Anna Bridge	180:96ed750bd169	2581
Anna Bridge	180:96ed750bd169	2582	/@} end of CMSIS_Core_SysTickFunctions /
Anna Bridge	180:96ed750bd169	2583
Anna Bridge	180:96ed750bd169	2584
Anna Bridge	180:96ed750bd169	2585
Anna Bridge	180:96ed750bd169	2586	/* ##################################### Debug In/Output function ########################################### */
Anna Bridge	180:96ed750bd169	2587	/**
Anna Bridge	180:96ed750bd169	2588	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2589	\defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge	180:96ed750bd169	2590	\brief Functions that access the ITM debug interface.
Anna Bridge	180:96ed750bd169	2591	@{
Anna Bridge	180:96ed750bd169	2592	*/
Anna Bridge	180:96ed750bd169	2593
Anna Bridge	180:96ed750bd169	2594	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Anna Bridge	180:96ed750bd169	2595	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Anna Bridge	180:96ed750bd169	2596
Anna Bridge	180:96ed750bd169	2597
Anna Bridge	180:96ed750bd169	2598	/**
Anna Bridge	180:96ed750bd169	2599	\brief ITM Send Character
Anna Bridge	180:96ed750bd169	2600	\details Transmits a character via the ITM channel 0, and
Anna Bridge	180:96ed750bd169	2601	\li Just returns when no debugger is connected that has booked the output.
Anna Bridge	180:96ed750bd169	2602	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge	180:96ed750bd169	2603	\param [in] ch Character to transmit.
Anna Bridge	180:96ed750bd169	2604	\returns Character to transmit.
Anna Bridge	180:96ed750bd169	2605	*/
Anna Bridge	180:96ed750bd169	2606	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge	180:96ed750bd169	2607	{
Anna Bridge	180:96ed750bd169	2608	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge	180:96ed750bd169	2609	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge	180:96ed750bd169	2610	{
Anna Bridge	180:96ed750bd169	2611	while (ITM->PORT[0U].u32 == 0UL)
Anna Bridge	180:96ed750bd169	2612	{
Anna Bridge	180:96ed750bd169	2613	__NOP();
Anna Bridge	180:96ed750bd169	2614	}
Anna Bridge	180:96ed750bd169	2615	ITM->PORT[0U].u8 = (uint8_t)ch;
Anna Bridge	180:96ed750bd169	2616	}
Anna Bridge	180:96ed750bd169	2617	return (ch);
Anna Bridge	180:96ed750bd169	2618	}
Anna Bridge	180:96ed750bd169	2619
Anna Bridge	180:96ed750bd169	2620
Anna Bridge	180:96ed750bd169	2621	/**
Anna Bridge	180:96ed750bd169	2622	\brief ITM Receive Character
Anna Bridge	180:96ed750bd169	2623	\details Inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge	180:96ed750bd169	2624	\return Received character.
Anna Bridge	180:96ed750bd169	2625	\return -1 No character pending.
Anna Bridge	180:96ed750bd169	2626	*/
Anna Bridge	180:96ed750bd169	2627	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
Anna Bridge	180:96ed750bd169	2628	{
Anna Bridge	180:96ed750bd169	2629	int32_t ch = -1; /* no character available */
Anna Bridge	180:96ed750bd169	2630
Anna Bridge	180:96ed750bd169	2631	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Anna Bridge	180:96ed750bd169	2632	{
Anna Bridge	180:96ed750bd169	2633	ch = ITM_RxBuffer;
Anna Bridge	180:96ed750bd169	2634	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge	180:96ed750bd169	2635	}
Anna Bridge	180:96ed750bd169	2636
Anna Bridge	180:96ed750bd169	2637	return (ch);
Anna Bridge	180:96ed750bd169	2638	}
Anna Bridge	180:96ed750bd169	2639
Anna Bridge	180:96ed750bd169	2640
Anna Bridge	180:96ed750bd169	2641	/**
Anna Bridge	180:96ed750bd169	2642	\brief ITM Check Character
Anna Bridge	180:96ed750bd169	2643	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge	180:96ed750bd169	2644	\return 0 No character available.
Anna Bridge	180:96ed750bd169	2645	\return 1 Character available.
Anna Bridge	180:96ed750bd169	2646	*/
Anna Bridge	180:96ed750bd169	2647	__STATIC_INLINE int32_t ITM_CheckChar (void)
Anna Bridge	180:96ed750bd169	2648	{
Anna Bridge	180:96ed750bd169	2649
Anna Bridge	180:96ed750bd169	2650	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Anna Bridge	180:96ed750bd169	2651	{
Anna Bridge	180:96ed750bd169	2652	return (0); /* no character available */
Anna Bridge	180:96ed750bd169	2653	}
Anna Bridge	180:96ed750bd169	2654	else
Anna Bridge	180:96ed750bd169	2655	{
Anna Bridge	180:96ed750bd169	2656	return (1); /* character available */
Anna Bridge	180:96ed750bd169	2657	}
Anna Bridge	180:96ed750bd169	2658	}
Anna Bridge	180:96ed750bd169	2659
Anna Bridge	180:96ed750bd169	2660	/@} end of CMSIS_core_DebugFunctions /
Anna Bridge	180:96ed750bd169	2661
Anna Bridge	180:96ed750bd169	2662
Anna Bridge	180:96ed750bd169	2663
Anna Bridge	180:96ed750bd169	2664
Anna Bridge	180:96ed750bd169	2665	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	2666	}
Anna Bridge	180:96ed750bd169	2667	#endif
Anna Bridge	180:96ed750bd169	2668
Anna Bridge	180:96ed750bd169	2669	#endif /* __CORE_CM7_H_DEPENDANT */
Anna Bridge	180:96ed750bd169	2670
Anna Bridge	180:96ed750bd169	2671	#endif /* __CMSIS_GENERIC */