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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_M/core_cm3.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 188:bcfe06ba3d64

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
Anna Bridge	180:96ed750bd169	1	/************************************************************************//
Anna Bridge	180:96ed750bd169	2	* @file core_cm3.h
Anna Bridge	180:96ed750bd169	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
AnnaBridge	188:bcfe06ba3d64	4	* @version V5.0.8
AnnaBridge	188:bcfe06ba3d64	5	* @date 04. June 2018
Anna Bridge	180:96ed750bd169	6	******************************************************************************/
Anna Bridge	180:96ed750bd169	7	/*
AnnaBridge	188:bcfe06ba3d64	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge	180:96ed750bd169	9	*
Anna Bridge	180:96ed750bd169	10	* SPDX-License-Identifier: Apache-2.0
Anna Bridge	180:96ed750bd169	11	*
Anna Bridge	180:96ed750bd169	12	* Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge	180:96ed750bd169	13	* not use this file except in compliance with the License.
Anna Bridge	180:96ed750bd169	14	* You may obtain a copy of the License at
Anna Bridge	180:96ed750bd169	15	*
Anna Bridge	180:96ed750bd169	16	* www.apache.org/licenses/LICENSE-2.0
Anna Bridge	180:96ed750bd169	17	*
Anna Bridge	180:96ed750bd169	18	* Unless required by applicable law or agreed to in writing, software
Anna Bridge	180:96ed750bd169	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge	180:96ed750bd169	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge	180:96ed750bd169	21	* See the License for the specific language governing permissions and
Anna Bridge	180:96ed750bd169	22	* limitations under the License.
Anna Bridge	180:96ed750bd169	23	*/
Anna Bridge	180:96ed750bd169	24
Anna Bridge	180:96ed750bd169	25	#if defined ( __ICCARM__ )
Anna Bridge	186:707f6e361f3e	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	186:707f6e361f3e	27	#elif defined (__clang__)
Anna Bridge	180:96ed750bd169	28	#pragma clang system_header /* treat file as system include file */
Anna Bridge	180:96ed750bd169	29	#endif
Anna Bridge	180:96ed750bd169	30
Anna Bridge	180:96ed750bd169	31	#ifndef __CORE_CM3_H_GENERIC
Anna Bridge	180:96ed750bd169	32	#define __CORE_CM3_H_GENERIC
Anna Bridge	180:96ed750bd169	33
Anna Bridge	180:96ed750bd169	34	#include <stdint.h>
Anna Bridge	180:96ed750bd169	35
Anna Bridge	180:96ed750bd169	36	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	37	extern "C" {
Anna Bridge	180:96ed750bd169	38	#endif
Anna Bridge	180:96ed750bd169	39
Anna Bridge	180:96ed750bd169	40	/**
Anna Bridge	180:96ed750bd169	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge	180:96ed750bd169	42	CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge	180:96ed750bd169	43
Anna Bridge	180:96ed750bd169	44	\li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge	180:96ed750bd169	45	Function definitions in header files are used to allow 'inlining'.
Anna Bridge	180:96ed750bd169	46
Anna Bridge	180:96ed750bd169	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge	180:96ed750bd169	48	Unions are used for effective representation of core registers.
Anna Bridge	180:96ed750bd169	49
Anna Bridge	180:96ed750bd169	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge	180:96ed750bd169	51	Function-like macros are used to allow more efficient code.
Anna Bridge	180:96ed750bd169	52	*/
Anna Bridge	180:96ed750bd169	53
Anna Bridge	180:96ed750bd169	54
Anna Bridge	180:96ed750bd169	55	/*******************************************************************************
Anna Bridge	180:96ed750bd169	56	* CMSIS definitions
Anna Bridge	180:96ed750bd169	57	******************************************************************************/
Anna Bridge	180:96ed750bd169	58	/**
Anna Bridge	180:96ed750bd169	59	\ingroup Cortex_M3
Anna Bridge	180:96ed750bd169	60	@{
Anna Bridge	180:96ed750bd169	61	*/
Anna Bridge	180:96ed750bd169	62
Anna Bridge	180:96ed750bd169	63	#include "cmsis_version.h"
AnnaBridge	188:bcfe06ba3d64	64
Anna Bridge	180:96ed750bd169	65	/* CMSIS CM3 definitions */
Anna Bridge	180:96ed750bd169	66	#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	180:96ed750bd169	67	#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
Anna Bridge	180:96ed750bd169	68	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	180:96ed750bd169	69	__CM3_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
Anna Bridge	180:96ed750bd169	70
Anna Bridge	180:96ed750bd169	71	#define __CORTEX_M (3U) /!< Cortex-M Core /
Anna Bridge	180:96ed750bd169	72
Anna Bridge	180:96ed750bd169	73	/** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge	180:96ed750bd169	74	This core does not support an FPU at all
Anna Bridge	180:96ed750bd169	75	*/
Anna Bridge	180:96ed750bd169	76	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	77
Anna Bridge	180:96ed750bd169	78	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	79	#if defined __TARGET_FPU_VFP
Anna Bridge	180:96ed750bd169	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	81	#endif
Anna Bridge	180:96ed750bd169	82
Anna Bridge	180:96ed750bd169	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	189:f392fc9709a3	84	#if defined __ARM_FP
Anna Bridge	180:96ed750bd169	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	86	#endif
Anna Bridge	180:96ed750bd169	87
Anna Bridge	180:96ed750bd169	88	#elif defined ( __GNUC__ )
Anna Bridge	180:96ed750bd169	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge	180:96ed750bd169	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	91	#endif
Anna Bridge	180:96ed750bd169	92
Anna Bridge	180:96ed750bd169	93	#elif defined ( __ICCARM__ )
Anna Bridge	180:96ed750bd169	94	#if defined __ARMVFP__
Anna Bridge	180:96ed750bd169	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	96	#endif
Anna Bridge	180:96ed750bd169	97
Anna Bridge	180:96ed750bd169	98	#elif defined ( __TI_ARM__ )
Anna Bridge	180:96ed750bd169	99	#if defined __TI_VFP_SUPPORT__
Anna Bridge	180:96ed750bd169	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	101	#endif
Anna Bridge	180:96ed750bd169	102
Anna Bridge	180:96ed750bd169	103	#elif defined ( __TASKING__ )
Anna Bridge	180:96ed750bd169	104	#if defined __FPU_VFP__
Anna Bridge	180:96ed750bd169	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	106	#endif
Anna Bridge	180:96ed750bd169	107
Anna Bridge	180:96ed750bd169	108	#elif defined ( __CSMC__ )
Anna Bridge	180:96ed750bd169	109	#if ( __CSMC__ & 0x400U)
Anna Bridge	180:96ed750bd169	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	111	#endif
Anna Bridge	180:96ed750bd169	112
Anna Bridge	180:96ed750bd169	113	#endif
Anna Bridge	180:96ed750bd169	114
Anna Bridge	180:96ed750bd169	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge	180:96ed750bd169	116
Anna Bridge	180:96ed750bd169	117
Anna Bridge	180:96ed750bd169	118	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	119	}
Anna Bridge	180:96ed750bd169	120	#endif
Anna Bridge	180:96ed750bd169	121
Anna Bridge	180:96ed750bd169	122	#endif /* __CORE_CM3_H_GENERIC */
Anna Bridge	180:96ed750bd169	123
Anna Bridge	180:96ed750bd169	124	#ifndef __CMSIS_GENERIC
Anna Bridge	180:96ed750bd169	125
Anna Bridge	180:96ed750bd169	126	#ifndef __CORE_CM3_H_DEPENDANT
Anna Bridge	180:96ed750bd169	127	#define __CORE_CM3_H_DEPENDANT
Anna Bridge	180:96ed750bd169	128
Anna Bridge	180:96ed750bd169	129	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	130	extern "C" {
Anna Bridge	180:96ed750bd169	131	#endif
Anna Bridge	180:96ed750bd169	132
Anna Bridge	180:96ed750bd169	133	/* check device defines and use defaults */
Anna Bridge	180:96ed750bd169	134	#if defined __CHECK_DEVICE_DEFINES
Anna Bridge	180:96ed750bd169	135	#ifndef __CM3_REV
Anna Bridge	180:96ed750bd169	136	#define __CM3_REV 0x0200U
Anna Bridge	180:96ed750bd169	137	#warning "__CM3_REV not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	138	#endif
Anna Bridge	180:96ed750bd169	139
Anna Bridge	180:96ed750bd169	140	#ifndef __MPU_PRESENT
Anna Bridge	180:96ed750bd169	141	#define __MPU_PRESENT 0U
Anna Bridge	180:96ed750bd169	142	#warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	143	#endif
Anna Bridge	180:96ed750bd169	144
Anna Bridge	180:96ed750bd169	145	#ifndef __NVIC_PRIO_BITS
Anna Bridge	180:96ed750bd169	146	#define __NVIC_PRIO_BITS 3U
Anna Bridge	180:96ed750bd169	147	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	148	#endif
Anna Bridge	180:96ed750bd169	149
Anna Bridge	180:96ed750bd169	150	#ifndef __Vendor_SysTickConfig
Anna Bridge	180:96ed750bd169	151	#define __Vendor_SysTickConfig 0U
Anna Bridge	180:96ed750bd169	152	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	153	#endif
Anna Bridge	180:96ed750bd169	154	#endif
Anna Bridge	180:96ed750bd169	155
Anna Bridge	180:96ed750bd169	156	/* IO definitions (access restrictions to peripheral registers) */
Anna Bridge	180:96ed750bd169	157	/**
Anna Bridge	180:96ed750bd169	158	\defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge	180:96ed750bd169	159
Anna Bridge	180:96ed750bd169	160	<strong>IO Type Qualifiers</strong> are used
Anna Bridge	180:96ed750bd169	161	\li to specify the access to peripheral variables.
Anna Bridge	180:96ed750bd169	162	\li for automatic generation of peripheral register debug information.
Anna Bridge	180:96ed750bd169	163	*/
Anna Bridge	180:96ed750bd169	164	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	165	#define __I volatile /!< Defines 'read only' permissions /
Anna Bridge	180:96ed750bd169	166	#else
Anna Bridge	180:96ed750bd169	167	#define __I volatile const /!< Defines 'read only' permissions /
Anna Bridge	180:96ed750bd169	168	#endif
Anna Bridge	180:96ed750bd169	169	#define __O volatile /!< Defines 'write only' permissions /
Anna Bridge	180:96ed750bd169	170	#define __IO volatile /!< Defines 'read / write' permissions /
Anna Bridge	180:96ed750bd169	171
Anna Bridge	180:96ed750bd169	172	/* following defines should be used for structure members */
Anna Bridge	180:96ed750bd169	173	#define __IM volatile const /! Defines 'read only' structure member permissions /
Anna Bridge	180:96ed750bd169	174	#define __OM volatile /! Defines 'write only' structure member permissions /
Anna Bridge	180:96ed750bd169	175	#define __IOM volatile /! Defines 'read / write' structure member permissions /
Anna Bridge	180:96ed750bd169	176
Anna Bridge	180:96ed750bd169	177	/@} end of group Cortex_M3 /
Anna Bridge	180:96ed750bd169	178
Anna Bridge	180:96ed750bd169	179
Anna Bridge	180:96ed750bd169	180
Anna Bridge	180:96ed750bd169	181	/*******************************************************************************
Anna Bridge	180:96ed750bd169	182	* Register Abstraction
Anna Bridge	180:96ed750bd169	183	Core Register contain:
Anna Bridge	180:96ed750bd169	184	- Core Register
Anna Bridge	180:96ed750bd169	185	- Core NVIC Register
Anna Bridge	180:96ed750bd169	186	- Core SCB Register
Anna Bridge	180:96ed750bd169	187	- Core SysTick Register
Anna Bridge	180:96ed750bd169	188	- Core Debug Register
Anna Bridge	180:96ed750bd169	189	- Core MPU Register
Anna Bridge	180:96ed750bd169	190	******************************************************************************/
Anna Bridge	180:96ed750bd169	191	/**
Anna Bridge	180:96ed750bd169	192	\defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge	180:96ed750bd169	193	\brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge	180:96ed750bd169	194	*/
Anna Bridge	180:96ed750bd169	195
Anna Bridge	180:96ed750bd169	196	/**
Anna Bridge	180:96ed750bd169	197	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	198	\defgroup CMSIS_CORE Status and Control Registers
Anna Bridge	180:96ed750bd169	199	\brief Core Register type definitions.
Anna Bridge	180:96ed750bd169	200	@{
Anna Bridge	180:96ed750bd169	201	*/
Anna Bridge	180:96ed750bd169	202
Anna Bridge	180:96ed750bd169	203	/**
Anna Bridge	180:96ed750bd169	204	\brief Union type to access the Application Program Status Register (APSR).
Anna Bridge	180:96ed750bd169	205	*/
Anna Bridge	180:96ed750bd169	206	typedef union
Anna Bridge	180:96ed750bd169	207	{
Anna Bridge	180:96ed750bd169	208	struct
Anna Bridge	180:96ed750bd169	209	{
Anna Bridge	180:96ed750bd169	210	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Anna Bridge	180:96ed750bd169	211	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	180:96ed750bd169	212	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	180:96ed750bd169	213	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	180:96ed750bd169	214	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	180:96ed750bd169	215	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	180:96ed750bd169	216	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	217	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	218	} APSR_Type;
Anna Bridge	180:96ed750bd169	219
Anna Bridge	180:96ed750bd169	220	/* APSR Register Definitions */
Anna Bridge	180:96ed750bd169	221	#define APSR_N_Pos 31U /!< APSR: N Position /
Anna Bridge	180:96ed750bd169	222	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Anna Bridge	180:96ed750bd169	223
Anna Bridge	180:96ed750bd169	224	#define APSR_Z_Pos 30U /!< APSR: Z Position /
Anna Bridge	180:96ed750bd169	225	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Anna Bridge	180:96ed750bd169	226
Anna Bridge	180:96ed750bd169	227	#define APSR_C_Pos 29U /!< APSR: C Position /
Anna Bridge	180:96ed750bd169	228	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Anna Bridge	180:96ed750bd169	229
Anna Bridge	180:96ed750bd169	230	#define APSR_V_Pos 28U /!< APSR: V Position /
Anna Bridge	180:96ed750bd169	231	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Anna Bridge	180:96ed750bd169	232
Anna Bridge	180:96ed750bd169	233	#define APSR_Q_Pos 27U /!< APSR: Q Position /
Anna Bridge	180:96ed750bd169	234	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Anna Bridge	180:96ed750bd169	235
Anna Bridge	180:96ed750bd169	236
Anna Bridge	180:96ed750bd169	237	/**
Anna Bridge	180:96ed750bd169	238	\brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge	180:96ed750bd169	239	*/
Anna Bridge	180:96ed750bd169	240	typedef union
Anna Bridge	180:96ed750bd169	241	{
Anna Bridge	180:96ed750bd169	242	struct
Anna Bridge	180:96ed750bd169	243	{
Anna Bridge	180:96ed750bd169	244	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	180:96ed750bd169	245	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Anna Bridge	180:96ed750bd169	246	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	247	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	248	} IPSR_Type;
Anna Bridge	180:96ed750bd169	249
Anna Bridge	180:96ed750bd169	250	/* IPSR Register Definitions */
Anna Bridge	180:96ed750bd169	251	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
Anna Bridge	180:96ed750bd169	252	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Anna Bridge	180:96ed750bd169	253
Anna Bridge	180:96ed750bd169	254
Anna Bridge	180:96ed750bd169	255	/**
Anna Bridge	180:96ed750bd169	256	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge	180:96ed750bd169	257	*/
Anna Bridge	180:96ed750bd169	258	typedef union
Anna Bridge	180:96ed750bd169	259	{
Anna Bridge	180:96ed750bd169	260	struct
Anna Bridge	180:96ed750bd169	261	{
Anna Bridge	180:96ed750bd169	262	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	180:96ed750bd169	263	uint32_t _reserved0:1; /!< bit: 9 Reserved /
Anna Bridge	180:96ed750bd169	264	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
Anna Bridge	180:96ed750bd169	265	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
Anna Bridge	180:96ed750bd169	266	uint32_t T:1; /!< bit: 24 Thumb bit /
Anna Bridge	180:96ed750bd169	267	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
Anna Bridge	180:96ed750bd169	268	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	180:96ed750bd169	269	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	180:96ed750bd169	270	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	180:96ed750bd169	271	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	180:96ed750bd169	272	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	180:96ed750bd169	273	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	274	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	275	} xPSR_Type;
Anna Bridge	180:96ed750bd169	276
Anna Bridge	180:96ed750bd169	277	/* xPSR Register Definitions */
Anna Bridge	180:96ed750bd169	278	#define xPSR_N_Pos 31U /!< xPSR: N Position /
Anna Bridge	180:96ed750bd169	279	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Anna Bridge	180:96ed750bd169	280
Anna Bridge	180:96ed750bd169	281	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
Anna Bridge	180:96ed750bd169	282	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Anna Bridge	180:96ed750bd169	283
Anna Bridge	180:96ed750bd169	284	#define xPSR_C_Pos 29U /!< xPSR: C Position /
Anna Bridge	180:96ed750bd169	285	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Anna Bridge	180:96ed750bd169	286
Anna Bridge	180:96ed750bd169	287	#define xPSR_V_Pos 28U /!< xPSR: V Position /
Anna Bridge	180:96ed750bd169	288	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Anna Bridge	180:96ed750bd169	289
Anna Bridge	180:96ed750bd169	290	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
Anna Bridge	180:96ed750bd169	291	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Anna Bridge	180:96ed750bd169	292
Anna Bridge	180:96ed750bd169	293	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
Anna Bridge	180:96ed750bd169	294	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
Anna Bridge	180:96ed750bd169	295
Anna Bridge	180:96ed750bd169	296	#define xPSR_T_Pos 24U /!< xPSR: T Position /
Anna Bridge	180:96ed750bd169	297	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Anna Bridge	180:96ed750bd169	298
Anna Bridge	180:96ed750bd169	299	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
Anna Bridge	180:96ed750bd169	300	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
Anna Bridge	180:96ed750bd169	301
Anna Bridge	180:96ed750bd169	302	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
Anna Bridge	180:96ed750bd169	303	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Anna Bridge	180:96ed750bd169	304
Anna Bridge	180:96ed750bd169	305
Anna Bridge	180:96ed750bd169	306	/**
Anna Bridge	180:96ed750bd169	307	\brief Union type to access the Control Registers (CONTROL).
Anna Bridge	180:96ed750bd169	308	*/
Anna Bridge	180:96ed750bd169	309	typedef union
Anna Bridge	180:96ed750bd169	310	{
Anna Bridge	180:96ed750bd169	311	struct
Anna Bridge	180:96ed750bd169	312	{
Anna Bridge	180:96ed750bd169	313	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Anna Bridge	180:96ed750bd169	314	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Anna Bridge	180:96ed750bd169	315	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
Anna Bridge	180:96ed750bd169	316	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	317	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	318	} CONTROL_Type;
Anna Bridge	180:96ed750bd169	319
Anna Bridge	180:96ed750bd169	320	/* CONTROL Register Definitions */
Anna Bridge	180:96ed750bd169	321	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
Anna Bridge	180:96ed750bd169	322	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Anna Bridge	180:96ed750bd169	323
Anna Bridge	180:96ed750bd169	324	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
Anna Bridge	180:96ed750bd169	325	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Anna Bridge	180:96ed750bd169	326
Anna Bridge	180:96ed750bd169	327	/@} end of group CMSIS_CORE /
Anna Bridge	180:96ed750bd169	328
Anna Bridge	180:96ed750bd169	329
Anna Bridge	180:96ed750bd169	330	/**
Anna Bridge	180:96ed750bd169	331	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	332	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge	180:96ed750bd169	333	\brief Type definitions for the NVIC Registers
Anna Bridge	180:96ed750bd169	334	@{
Anna Bridge	180:96ed750bd169	335	*/
Anna Bridge	180:96ed750bd169	336
Anna Bridge	180:96ed750bd169	337	/**
Anna Bridge	180:96ed750bd169	338	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge	180:96ed750bd169	339	*/
Anna Bridge	180:96ed750bd169	340	typedef struct
Anna Bridge	180:96ed750bd169	341	{
Anna Bridge	180:96ed750bd169	342	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Anna Bridge	180:96ed750bd169	343	uint32_t RESERVED0[24U];
Anna Bridge	180:96ed750bd169	344	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Anna Bridge	180:96ed750bd169	345	uint32_t RSERVED1[24U];
Anna Bridge	180:96ed750bd169	346	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Anna Bridge	180:96ed750bd169	347	uint32_t RESERVED2[24U];
Anna Bridge	180:96ed750bd169	348	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Anna Bridge	180:96ed750bd169	349	uint32_t RESERVED3[24U];
Anna Bridge	180:96ed750bd169	350	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Anna Bridge	180:96ed750bd169	351	uint32_t RESERVED4[56U];
Anna Bridge	180:96ed750bd169	352	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Anna Bridge	180:96ed750bd169	353	uint32_t RESERVED5[644U];
Anna Bridge	180:96ed750bd169	354	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Anna Bridge	180:96ed750bd169	355	} NVIC_Type;
Anna Bridge	180:96ed750bd169	356
Anna Bridge	180:96ed750bd169	357	/* Software Triggered Interrupt Register Definitions */
Anna Bridge	180:96ed750bd169	358	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
Anna Bridge	180:96ed750bd169	359	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Anna Bridge	180:96ed750bd169	360
Anna Bridge	180:96ed750bd169	361	/@} end of group CMSIS_NVIC /
Anna Bridge	180:96ed750bd169	362
Anna Bridge	180:96ed750bd169	363
Anna Bridge	180:96ed750bd169	364	/**
Anna Bridge	180:96ed750bd169	365	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	366	\defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge	180:96ed750bd169	367	\brief Type definitions for the System Control Block Registers
Anna Bridge	180:96ed750bd169	368	@{
Anna Bridge	180:96ed750bd169	369	*/
Anna Bridge	180:96ed750bd169	370
Anna Bridge	180:96ed750bd169	371	/**
Anna Bridge	180:96ed750bd169	372	\brief Structure type to access the System Control Block (SCB).
Anna Bridge	180:96ed750bd169	373	*/
Anna Bridge	180:96ed750bd169	374	typedef struct
Anna Bridge	180:96ed750bd169	375	{
Anna Bridge	180:96ed750bd169	376	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Anna Bridge	180:96ed750bd169	377	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Anna Bridge	180:96ed750bd169	378	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Anna Bridge	180:96ed750bd169	379	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Anna Bridge	180:96ed750bd169	380	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Anna Bridge	180:96ed750bd169	381	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Anna Bridge	180:96ed750bd169	382	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Anna Bridge	180:96ed750bd169	383	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Anna Bridge	180:96ed750bd169	384	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Anna Bridge	180:96ed750bd169	385	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Anna Bridge	180:96ed750bd169	386	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Anna Bridge	180:96ed750bd169	387	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Anna Bridge	180:96ed750bd169	388	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Anna Bridge	180:96ed750bd169	389	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Anna Bridge	180:96ed750bd169	390	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Anna Bridge	180:96ed750bd169	391	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Anna Bridge	180:96ed750bd169	392	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Anna Bridge	180:96ed750bd169	393	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Anna Bridge	180:96ed750bd169	394	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Anna Bridge	180:96ed750bd169	395	uint32_t RESERVED0[5U];
Anna Bridge	180:96ed750bd169	396	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Anna Bridge	180:96ed750bd169	397	} SCB_Type;
Anna Bridge	180:96ed750bd169	398
Anna Bridge	180:96ed750bd169	399	/* SCB CPUID Register Definitions */
Anna Bridge	180:96ed750bd169	400	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
Anna Bridge	180:96ed750bd169	401	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Anna Bridge	180:96ed750bd169	402
Anna Bridge	180:96ed750bd169	403	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
Anna Bridge	180:96ed750bd169	404	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Anna Bridge	180:96ed750bd169	405
Anna Bridge	180:96ed750bd169	406	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
Anna Bridge	180:96ed750bd169	407	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Anna Bridge	180:96ed750bd169	408
Anna Bridge	180:96ed750bd169	409	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
Anna Bridge	180:96ed750bd169	410	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Anna Bridge	180:96ed750bd169	411
Anna Bridge	180:96ed750bd169	412	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
Anna Bridge	180:96ed750bd169	413	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Anna Bridge	180:96ed750bd169	414
Anna Bridge	180:96ed750bd169	415	/* SCB Interrupt Control State Register Definitions */
Anna Bridge	180:96ed750bd169	416	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
Anna Bridge	180:96ed750bd169	417	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Anna Bridge	180:96ed750bd169	418
Anna Bridge	180:96ed750bd169	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
Anna Bridge	180:96ed750bd169	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Anna Bridge	180:96ed750bd169	421
Anna Bridge	180:96ed750bd169	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
Anna Bridge	180:96ed750bd169	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Anna Bridge	180:96ed750bd169	424
Anna Bridge	180:96ed750bd169	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
Anna Bridge	180:96ed750bd169	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Anna Bridge	180:96ed750bd169	427
Anna Bridge	180:96ed750bd169	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
Anna Bridge	180:96ed750bd169	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Anna Bridge	180:96ed750bd169	430
Anna Bridge	180:96ed750bd169	431	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
Anna Bridge	180:96ed750bd169	432	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Anna Bridge	180:96ed750bd169	433
Anna Bridge	180:96ed750bd169	434	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
Anna Bridge	180:96ed750bd169	435	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Anna Bridge	180:96ed750bd169	436
Anna Bridge	180:96ed750bd169	437	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
Anna Bridge	180:96ed750bd169	438	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Anna Bridge	180:96ed750bd169	439
Anna Bridge	180:96ed750bd169	440	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
Anna Bridge	180:96ed750bd169	441	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Anna Bridge	180:96ed750bd169	442
Anna Bridge	180:96ed750bd169	443	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
Anna Bridge	180:96ed750bd169	444	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Anna Bridge	180:96ed750bd169	445
Anna Bridge	180:96ed750bd169	446	/* SCB Vector Table Offset Register Definitions */
Anna Bridge	180:96ed750bd169	447	#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
Anna Bridge	180:96ed750bd169	448	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
Anna Bridge	180:96ed750bd169	449	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
Anna Bridge	180:96ed750bd169	450
Anna Bridge	180:96ed750bd169	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Anna Bridge	180:96ed750bd169	452	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Anna Bridge	180:96ed750bd169	453	#else
Anna Bridge	180:96ed750bd169	454	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Anna Bridge	180:96ed750bd169	455	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Anna Bridge	180:96ed750bd169	456	#endif
Anna Bridge	180:96ed750bd169	457
Anna Bridge	180:96ed750bd169	458	/* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge	180:96ed750bd169	459	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
Anna Bridge	180:96ed750bd169	460	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Anna Bridge	180:96ed750bd169	461
Anna Bridge	180:96ed750bd169	462	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
Anna Bridge	180:96ed750bd169	463	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Anna Bridge	180:96ed750bd169	464
Anna Bridge	180:96ed750bd169	465	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
Anna Bridge	180:96ed750bd169	466	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Anna Bridge	180:96ed750bd169	467
Anna Bridge	180:96ed750bd169	468	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
Anna Bridge	180:96ed750bd169	469	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Anna Bridge	180:96ed750bd169	470
Anna Bridge	180:96ed750bd169	471	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
Anna Bridge	180:96ed750bd169	472	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Anna Bridge	180:96ed750bd169	473
Anna Bridge	180:96ed750bd169	474	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
Anna Bridge	180:96ed750bd169	475	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Anna Bridge	180:96ed750bd169	476
Anna Bridge	180:96ed750bd169	477	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
Anna Bridge	180:96ed750bd169	478	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Anna Bridge	180:96ed750bd169	479
Anna Bridge	180:96ed750bd169	480	/* SCB System Control Register Definitions */
Anna Bridge	180:96ed750bd169	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
Anna Bridge	180:96ed750bd169	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Anna Bridge	180:96ed750bd169	483
Anna Bridge	180:96ed750bd169	484	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
Anna Bridge	180:96ed750bd169	485	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Anna Bridge	180:96ed750bd169	486
Anna Bridge	180:96ed750bd169	487	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
Anna Bridge	180:96ed750bd169	488	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Anna Bridge	180:96ed750bd169	489
Anna Bridge	180:96ed750bd169	490	/* SCB Configuration Control Register Definitions */
Anna Bridge	180:96ed750bd169	491	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
Anna Bridge	180:96ed750bd169	492	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Anna Bridge	180:96ed750bd169	493
Anna Bridge	180:96ed750bd169	494	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
Anna Bridge	180:96ed750bd169	495	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Anna Bridge	180:96ed750bd169	496
Anna Bridge	180:96ed750bd169	497	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
Anna Bridge	180:96ed750bd169	498	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Anna Bridge	180:96ed750bd169	499
Anna Bridge	180:96ed750bd169	500	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
Anna Bridge	180:96ed750bd169	501	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Anna Bridge	180:96ed750bd169	502
Anna Bridge	180:96ed750bd169	503	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
Anna Bridge	180:96ed750bd169	504	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Anna Bridge	180:96ed750bd169	505
Anna Bridge	180:96ed750bd169	506	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
Anna Bridge	180:96ed750bd169	507	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Anna Bridge	180:96ed750bd169	508
Anna Bridge	180:96ed750bd169	509	/* SCB System Handler Control and State Register Definitions */
Anna Bridge	180:96ed750bd169	510	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
Anna Bridge	180:96ed750bd169	511	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Anna Bridge	180:96ed750bd169	512
Anna Bridge	180:96ed750bd169	513	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
Anna Bridge	180:96ed750bd169	514	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Anna Bridge	180:96ed750bd169	515
Anna Bridge	180:96ed750bd169	516	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
Anna Bridge	180:96ed750bd169	517	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Anna Bridge	180:96ed750bd169	518
Anna Bridge	180:96ed750bd169	519	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
Anna Bridge	180:96ed750bd169	520	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Anna Bridge	180:96ed750bd169	521
Anna Bridge	180:96ed750bd169	522	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	523	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	524
Anna Bridge	180:96ed750bd169	525	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	526	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	527
Anna Bridge	180:96ed750bd169	528	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	529	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	530
Anna Bridge	180:96ed750bd169	531	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
Anna Bridge	180:96ed750bd169	532	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Anna Bridge	180:96ed750bd169	533
Anna Bridge	180:96ed750bd169	534	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
Anna Bridge	180:96ed750bd169	535	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Anna Bridge	180:96ed750bd169	536
Anna Bridge	180:96ed750bd169	537	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
Anna Bridge	180:96ed750bd169	538	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Anna Bridge	180:96ed750bd169	539
Anna Bridge	180:96ed750bd169	540	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
Anna Bridge	180:96ed750bd169	541	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Anna Bridge	180:96ed750bd169	542
Anna Bridge	180:96ed750bd169	543	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
Anna Bridge	180:96ed750bd169	544	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Anna Bridge	180:96ed750bd169	545
Anna Bridge	180:96ed750bd169	546	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
Anna Bridge	180:96ed750bd169	547	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Anna Bridge	180:96ed750bd169	548
Anna Bridge	180:96ed750bd169	549	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
Anna Bridge	180:96ed750bd169	550	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Anna Bridge	180:96ed750bd169	551
Anna Bridge	180:96ed750bd169	552	/* SCB Configurable Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	553	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
Anna Bridge	180:96ed750bd169	554	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	555
Anna Bridge	180:96ed750bd169	556	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
Anna Bridge	180:96ed750bd169	557	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	558
Anna Bridge	180:96ed750bd169	559	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
Anna Bridge	180:96ed750bd169	560	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	561
Anna Bridge	180:96ed750bd169	562	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	563	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
Anna Bridge	180:96ed750bd169	564	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
Anna Bridge	180:96ed750bd169	565
Anna Bridge	180:96ed750bd169	566	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
Anna Bridge	180:96ed750bd169	567	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
Anna Bridge	180:96ed750bd169	568
Anna Bridge	180:96ed750bd169	569	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
Anna Bridge	180:96ed750bd169	570	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
Anna Bridge	180:96ed750bd169	571
Anna Bridge	180:96ed750bd169	572	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
Anna Bridge	180:96ed750bd169	573	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
Anna Bridge	180:96ed750bd169	574
Anna Bridge	180:96ed750bd169	575	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
Anna Bridge	180:96ed750bd169	576	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
Anna Bridge	180:96ed750bd169	577
Anna Bridge	180:96ed750bd169	578	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	579	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
Anna Bridge	180:96ed750bd169	580	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
Anna Bridge	180:96ed750bd169	581
Anna Bridge	180:96ed750bd169	582	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
Anna Bridge	180:96ed750bd169	583	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
Anna Bridge	180:96ed750bd169	584
Anna Bridge	180:96ed750bd169	585	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
Anna Bridge	180:96ed750bd169	586	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
Anna Bridge	180:96ed750bd169	587
Anna Bridge	180:96ed750bd169	588	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
Anna Bridge	180:96ed750bd169	589	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
Anna Bridge	180:96ed750bd169	590
Anna Bridge	180:96ed750bd169	591	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
Anna Bridge	180:96ed750bd169	592	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
Anna Bridge	180:96ed750bd169	593
Anna Bridge	180:96ed750bd169	594	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
Anna Bridge	180:96ed750bd169	595	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
Anna Bridge	180:96ed750bd169	596
Anna Bridge	180:96ed750bd169	597	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	598	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
Anna Bridge	180:96ed750bd169	599	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
Anna Bridge	180:96ed750bd169	600
Anna Bridge	180:96ed750bd169	601	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
Anna Bridge	180:96ed750bd169	602	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
Anna Bridge	180:96ed750bd169	603
Anna Bridge	180:96ed750bd169	604	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
Anna Bridge	180:96ed750bd169	605	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
Anna Bridge	180:96ed750bd169	606
Anna Bridge	180:96ed750bd169	607	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
Anna Bridge	180:96ed750bd169	608	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
Anna Bridge	180:96ed750bd169	609
Anna Bridge	180:96ed750bd169	610	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
Anna Bridge	180:96ed750bd169	611	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
Anna Bridge	180:96ed750bd169	612
Anna Bridge	180:96ed750bd169	613	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
Anna Bridge	180:96ed750bd169	614	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
Anna Bridge	180:96ed750bd169	615
Anna Bridge	180:96ed750bd169	616	/* SCB Hard Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	617	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
Anna Bridge	180:96ed750bd169	618	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Anna Bridge	180:96ed750bd169	619
Anna Bridge	180:96ed750bd169	620	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
Anna Bridge	180:96ed750bd169	621	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Anna Bridge	180:96ed750bd169	622
Anna Bridge	180:96ed750bd169	623	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
Anna Bridge	180:96ed750bd169	624	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Anna Bridge	180:96ed750bd169	625
Anna Bridge	180:96ed750bd169	626	/* SCB Debug Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	627	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
Anna Bridge	180:96ed750bd169	628	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Anna Bridge	180:96ed750bd169	629
Anna Bridge	180:96ed750bd169	630	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
Anna Bridge	180:96ed750bd169	631	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Anna Bridge	180:96ed750bd169	632
Anna Bridge	180:96ed750bd169	633	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
Anna Bridge	180:96ed750bd169	634	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Anna Bridge	180:96ed750bd169	635
Anna Bridge	180:96ed750bd169	636	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
Anna Bridge	180:96ed750bd169	637	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Anna Bridge	180:96ed750bd169	638
Anna Bridge	180:96ed750bd169	639	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
Anna Bridge	180:96ed750bd169	640	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Anna Bridge	180:96ed750bd169	641
Anna Bridge	180:96ed750bd169	642	/@} end of group CMSIS_SCB /
Anna Bridge	180:96ed750bd169	643
Anna Bridge	180:96ed750bd169	644
Anna Bridge	180:96ed750bd169	645	/**
Anna Bridge	180:96ed750bd169	646	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	647	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge	180:96ed750bd169	648	\brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge	180:96ed750bd169	649	@{
Anna Bridge	180:96ed750bd169	650	*/
Anna Bridge	180:96ed750bd169	651
Anna Bridge	180:96ed750bd169	652	/**
Anna Bridge	180:96ed750bd169	653	\brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge	180:96ed750bd169	654	*/
Anna Bridge	180:96ed750bd169	655	typedef struct
Anna Bridge	180:96ed750bd169	656	{
Anna Bridge	180:96ed750bd169	657	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	658	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Anna Bridge	180:96ed750bd169	659	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
Anna Bridge	180:96ed750bd169	660	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Anna Bridge	180:96ed750bd169	661	#else
Anna Bridge	180:96ed750bd169	662	uint32_t RESERVED1[1U];
Anna Bridge	180:96ed750bd169	663	#endif
Anna Bridge	180:96ed750bd169	664	} SCnSCB_Type;
Anna Bridge	180:96ed750bd169	665
Anna Bridge	180:96ed750bd169	666	/* Interrupt Controller Type Register Definitions */
Anna Bridge	180:96ed750bd169	667	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
Anna Bridge	180:96ed750bd169	668	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Anna Bridge	180:96ed750bd169	669
Anna Bridge	180:96ed750bd169	670	/* Auxiliary Control Register Definitions */
AnnaBridge	189:f392fc9709a3	671	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
Anna Bridge	180:96ed750bd169	672	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
Anna Bridge	180:96ed750bd169	673	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Anna Bridge	180:96ed750bd169	674
Anna Bridge	180:96ed750bd169	675	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
Anna Bridge	180:96ed750bd169	676	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Anna Bridge	180:96ed750bd169	677
Anna Bridge	180:96ed750bd169	678	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
Anna Bridge	180:96ed750bd169	679	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	189:f392fc9709a3	680	#endif
Anna Bridge	180:96ed750bd169	681
Anna Bridge	180:96ed750bd169	682	/@} end of group CMSIS_SCnotSCB /
Anna Bridge	180:96ed750bd169	683
Anna Bridge	180:96ed750bd169	684
Anna Bridge	180:96ed750bd169	685	/**
Anna Bridge	180:96ed750bd169	686	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	687	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge	180:96ed750bd169	688	\brief Type definitions for the System Timer Registers.
Anna Bridge	180:96ed750bd169	689	@{
Anna Bridge	180:96ed750bd169	690	*/
Anna Bridge	180:96ed750bd169	691
Anna Bridge	180:96ed750bd169	692	/**
Anna Bridge	180:96ed750bd169	693	\brief Structure type to access the System Timer (SysTick).
Anna Bridge	180:96ed750bd169	694	*/
Anna Bridge	180:96ed750bd169	695	typedef struct
Anna Bridge	180:96ed750bd169	696	{
Anna Bridge	180:96ed750bd169	697	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Anna Bridge	180:96ed750bd169	698	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Anna Bridge	180:96ed750bd169	699	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Anna Bridge	180:96ed750bd169	700	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Anna Bridge	180:96ed750bd169	701	} SysTick_Type;
Anna Bridge	180:96ed750bd169	702
Anna Bridge	180:96ed750bd169	703	/* SysTick Control / Status Register Definitions */
Anna Bridge	180:96ed750bd169	704	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
Anna Bridge	180:96ed750bd169	705	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Anna Bridge	180:96ed750bd169	706
Anna Bridge	180:96ed750bd169	707	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
Anna Bridge	180:96ed750bd169	708	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Anna Bridge	180:96ed750bd169	709
Anna Bridge	180:96ed750bd169	710	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
Anna Bridge	180:96ed750bd169	711	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Anna Bridge	180:96ed750bd169	712
Anna Bridge	180:96ed750bd169	713	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	714	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	715
Anna Bridge	180:96ed750bd169	716	/* SysTick Reload Register Definitions */
Anna Bridge	180:96ed750bd169	717	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
Anna Bridge	180:96ed750bd169	718	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Anna Bridge	180:96ed750bd169	719
Anna Bridge	180:96ed750bd169	720	/* SysTick Current Register Definitions */
Anna Bridge	180:96ed750bd169	721	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
Anna Bridge	180:96ed750bd169	722	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Anna Bridge	180:96ed750bd169	723
Anna Bridge	180:96ed750bd169	724	/* SysTick Calibration Register Definitions */
Anna Bridge	180:96ed750bd169	725	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
Anna Bridge	180:96ed750bd169	726	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Anna Bridge	180:96ed750bd169	727
Anna Bridge	180:96ed750bd169	728	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
Anna Bridge	180:96ed750bd169	729	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Anna Bridge	180:96ed750bd169	730
Anna Bridge	180:96ed750bd169	731	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
Anna Bridge	180:96ed750bd169	732	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Anna Bridge	180:96ed750bd169	733
Anna Bridge	180:96ed750bd169	734	/@} end of group CMSIS_SysTick /
Anna Bridge	180:96ed750bd169	735
Anna Bridge	180:96ed750bd169	736
Anna Bridge	180:96ed750bd169	737	/**
Anna Bridge	180:96ed750bd169	738	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	739	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge	180:96ed750bd169	740	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge	180:96ed750bd169	741	@{
Anna Bridge	180:96ed750bd169	742	*/
Anna Bridge	180:96ed750bd169	743
Anna Bridge	180:96ed750bd169	744	/**
Anna Bridge	180:96ed750bd169	745	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge	180:96ed750bd169	746	*/
Anna Bridge	180:96ed750bd169	747	typedef struct
Anna Bridge	180:96ed750bd169	748	{
Anna Bridge	180:96ed750bd169	749	__OM union
Anna Bridge	180:96ed750bd169	750	{
Anna Bridge	180:96ed750bd169	751	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Anna Bridge	180:96ed750bd169	752	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Anna Bridge	180:96ed750bd169	753	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Anna Bridge	180:96ed750bd169	754	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Anna Bridge	180:96ed750bd169	755	uint32_t RESERVED0[864U];
Anna Bridge	180:96ed750bd169	756	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Anna Bridge	180:96ed750bd169	757	uint32_t RESERVED1[15U];
Anna Bridge	180:96ed750bd169	758	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Anna Bridge	180:96ed750bd169	759	uint32_t RESERVED2[15U];
Anna Bridge	180:96ed750bd169	760	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Anna Bridge	180:96ed750bd169	761	uint32_t RESERVED3[29U];
Anna Bridge	180:96ed750bd169	762	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Anna Bridge	180:96ed750bd169	763	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Anna Bridge	180:96ed750bd169	764	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Anna Bridge	180:96ed750bd169	765	uint32_t RESERVED4[43U];
Anna Bridge	180:96ed750bd169	766	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Anna Bridge	180:96ed750bd169	767	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Anna Bridge	180:96ed750bd169	768	uint32_t RESERVED5[6U];
Anna Bridge	180:96ed750bd169	769	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Anna Bridge	180:96ed750bd169	770	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Anna Bridge	180:96ed750bd169	771	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Anna Bridge	180:96ed750bd169	772	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Anna Bridge	180:96ed750bd169	773	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Anna Bridge	180:96ed750bd169	774	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Anna Bridge	180:96ed750bd169	775	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Anna Bridge	180:96ed750bd169	776	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Anna Bridge	180:96ed750bd169	777	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Anna Bridge	180:96ed750bd169	778	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Anna Bridge	180:96ed750bd169	779	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Anna Bridge	180:96ed750bd169	780	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Anna Bridge	180:96ed750bd169	781	} ITM_Type;
Anna Bridge	180:96ed750bd169	782
Anna Bridge	180:96ed750bd169	783	/* ITM Trace Privilege Register Definitions */
Anna Bridge	180:96ed750bd169	784	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	186:707f6e361f3e	785	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Anna Bridge	180:96ed750bd169	786
Anna Bridge	180:96ed750bd169	787	/* ITM Trace Control Register Definitions */
Anna Bridge	180:96ed750bd169	788	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
Anna Bridge	180:96ed750bd169	789	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Anna Bridge	180:96ed750bd169	790
Anna Bridge	180:96ed750bd169	791	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
Anna Bridge	180:96ed750bd169	792	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Anna Bridge	180:96ed750bd169	793
Anna Bridge	180:96ed750bd169	794	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
Anna Bridge	180:96ed750bd169	795	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Anna Bridge	180:96ed750bd169	796
Anna Bridge	180:96ed750bd169	797	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
Anna Bridge	180:96ed750bd169	798	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Anna Bridge	180:96ed750bd169	799
Anna Bridge	180:96ed750bd169	800	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
Anna Bridge	180:96ed750bd169	801	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Anna Bridge	180:96ed750bd169	802
Anna Bridge	180:96ed750bd169	803	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
Anna Bridge	180:96ed750bd169	804	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Anna Bridge	180:96ed750bd169	805
Anna Bridge	180:96ed750bd169	806	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
Anna Bridge	180:96ed750bd169	807	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Anna Bridge	180:96ed750bd169	808
Anna Bridge	180:96ed750bd169	809	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
Anna Bridge	180:96ed750bd169	810	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Anna Bridge	180:96ed750bd169	811
Anna Bridge	180:96ed750bd169	812	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
Anna Bridge	180:96ed750bd169	813	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Anna Bridge	180:96ed750bd169	814
Anna Bridge	180:96ed750bd169	815	/* ITM Integration Write Register Definitions */
Anna Bridge	180:96ed750bd169	816	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
Anna Bridge	180:96ed750bd169	817	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Anna Bridge	180:96ed750bd169	818
Anna Bridge	180:96ed750bd169	819	/* ITM Integration Read Register Definitions */
Anna Bridge	180:96ed750bd169	820	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
Anna Bridge	180:96ed750bd169	821	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Anna Bridge	180:96ed750bd169	822
Anna Bridge	180:96ed750bd169	823	/* ITM Integration Mode Control Register Definitions */
Anna Bridge	180:96ed750bd169	824	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
Anna Bridge	180:96ed750bd169	825	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Anna Bridge	180:96ed750bd169	826
Anna Bridge	180:96ed750bd169	827	/* ITM Lock Status Register Definitions */
Anna Bridge	180:96ed750bd169	828	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
Anna Bridge	180:96ed750bd169	829	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Anna Bridge	180:96ed750bd169	830
Anna Bridge	180:96ed750bd169	831	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
Anna Bridge	180:96ed750bd169	832	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Anna Bridge	180:96ed750bd169	833
Anna Bridge	180:96ed750bd169	834	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
Anna Bridge	180:96ed750bd169	835	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Anna Bridge	180:96ed750bd169	836
Anna Bridge	180:96ed750bd169	837	/@}/ /* end of group CMSIS_ITM */
Anna Bridge	180:96ed750bd169	838
Anna Bridge	180:96ed750bd169	839
Anna Bridge	180:96ed750bd169	840	/**
Anna Bridge	180:96ed750bd169	841	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	842	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge	180:96ed750bd169	843	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge	180:96ed750bd169	844	@{
Anna Bridge	180:96ed750bd169	845	*/
Anna Bridge	180:96ed750bd169	846
Anna Bridge	180:96ed750bd169	847	/**
Anna Bridge	180:96ed750bd169	848	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge	180:96ed750bd169	849	*/
Anna Bridge	180:96ed750bd169	850	typedef struct
Anna Bridge	180:96ed750bd169	851	{
Anna Bridge	180:96ed750bd169	852	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Anna Bridge	180:96ed750bd169	853	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Anna Bridge	180:96ed750bd169	854	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Anna Bridge	180:96ed750bd169	855	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Anna Bridge	180:96ed750bd169	856	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Anna Bridge	180:96ed750bd169	857	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Anna Bridge	180:96ed750bd169	858	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Anna Bridge	180:96ed750bd169	859	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Anna Bridge	180:96ed750bd169	860	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Anna Bridge	180:96ed750bd169	861	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Anna Bridge	180:96ed750bd169	862	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Anna Bridge	180:96ed750bd169	863	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	864	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Anna Bridge	180:96ed750bd169	865	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Anna Bridge	180:96ed750bd169	866	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Anna Bridge	180:96ed750bd169	867	uint32_t RESERVED1[1U];
Anna Bridge	180:96ed750bd169	868	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Anna Bridge	180:96ed750bd169	869	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Anna Bridge	180:96ed750bd169	870	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Anna Bridge	180:96ed750bd169	871	uint32_t RESERVED2[1U];
Anna Bridge	180:96ed750bd169	872	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Anna Bridge	180:96ed750bd169	873	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Anna Bridge	180:96ed750bd169	874	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Anna Bridge	180:96ed750bd169	875	} DWT_Type;
Anna Bridge	180:96ed750bd169	876
Anna Bridge	180:96ed750bd169	877	/* DWT Control Register Definitions */
Anna Bridge	180:96ed750bd169	878	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
Anna Bridge	180:96ed750bd169	879	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Anna Bridge	180:96ed750bd169	880
Anna Bridge	180:96ed750bd169	881	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
Anna Bridge	180:96ed750bd169	882	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Anna Bridge	180:96ed750bd169	883
Anna Bridge	180:96ed750bd169	884	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
Anna Bridge	180:96ed750bd169	885	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Anna Bridge	180:96ed750bd169	886
Anna Bridge	180:96ed750bd169	887	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
Anna Bridge	180:96ed750bd169	888	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Anna Bridge	180:96ed750bd169	889
Anna Bridge	180:96ed750bd169	890	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
Anna Bridge	180:96ed750bd169	891	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Anna Bridge	180:96ed750bd169	892
Anna Bridge	180:96ed750bd169	893	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
Anna Bridge	180:96ed750bd169	894	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Anna Bridge	180:96ed750bd169	895
Anna Bridge	180:96ed750bd169	896	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
Anna Bridge	180:96ed750bd169	897	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Anna Bridge	180:96ed750bd169	898
Anna Bridge	180:96ed750bd169	899	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
Anna Bridge	180:96ed750bd169	900	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Anna Bridge	180:96ed750bd169	901
Anna Bridge	180:96ed750bd169	902	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
Anna Bridge	180:96ed750bd169	903	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Anna Bridge	180:96ed750bd169	904
Anna Bridge	180:96ed750bd169	905	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
Anna Bridge	180:96ed750bd169	906	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Anna Bridge	180:96ed750bd169	907
Anna Bridge	180:96ed750bd169	908	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
Anna Bridge	180:96ed750bd169	909	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Anna Bridge	180:96ed750bd169	910
Anna Bridge	180:96ed750bd169	911	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
Anna Bridge	180:96ed750bd169	912	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Anna Bridge	180:96ed750bd169	913
Anna Bridge	180:96ed750bd169	914	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
Anna Bridge	180:96ed750bd169	915	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Anna Bridge	180:96ed750bd169	916
Anna Bridge	180:96ed750bd169	917	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
Anna Bridge	180:96ed750bd169	918	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Anna Bridge	180:96ed750bd169	919
Anna Bridge	180:96ed750bd169	920	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
Anna Bridge	180:96ed750bd169	921	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Anna Bridge	180:96ed750bd169	922
Anna Bridge	180:96ed750bd169	923	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
Anna Bridge	180:96ed750bd169	924	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Anna Bridge	180:96ed750bd169	925
Anna Bridge	180:96ed750bd169	926	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
Anna Bridge	180:96ed750bd169	927	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Anna Bridge	180:96ed750bd169	928
Anna Bridge	180:96ed750bd169	929	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
Anna Bridge	180:96ed750bd169	930	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Anna Bridge	180:96ed750bd169	931
Anna Bridge	180:96ed750bd169	932	/* DWT CPI Count Register Definitions */
Anna Bridge	180:96ed750bd169	933	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
Anna Bridge	180:96ed750bd169	934	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Anna Bridge	180:96ed750bd169	935
Anna Bridge	180:96ed750bd169	936	/* DWT Exception Overhead Count Register Definitions */
Anna Bridge	180:96ed750bd169	937	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
Anna Bridge	180:96ed750bd169	938	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Anna Bridge	180:96ed750bd169	939
Anna Bridge	180:96ed750bd169	940	/* DWT Sleep Count Register Definitions */
Anna Bridge	180:96ed750bd169	941	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
Anna Bridge	180:96ed750bd169	942	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Anna Bridge	180:96ed750bd169	943
Anna Bridge	180:96ed750bd169	944	/* DWT LSU Count Register Definitions */
Anna Bridge	180:96ed750bd169	945	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
Anna Bridge	180:96ed750bd169	946	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Anna Bridge	180:96ed750bd169	947
Anna Bridge	180:96ed750bd169	948	/* DWT Folded-instruction Count Register Definitions */
Anna Bridge	180:96ed750bd169	949	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
Anna Bridge	180:96ed750bd169	950	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Anna Bridge	180:96ed750bd169	951
Anna Bridge	180:96ed750bd169	952	/* DWT Comparator Mask Register Definitions */
Anna Bridge	180:96ed750bd169	953	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
Anna Bridge	180:96ed750bd169	954	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Anna Bridge	180:96ed750bd169	955
Anna Bridge	180:96ed750bd169	956	/* DWT Comparator Function Register Definitions */
Anna Bridge	180:96ed750bd169	957	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
Anna Bridge	180:96ed750bd169	958	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Anna Bridge	180:96ed750bd169	959
Anna Bridge	180:96ed750bd169	960	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
Anna Bridge	180:96ed750bd169	961	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Anna Bridge	180:96ed750bd169	962
Anna Bridge	180:96ed750bd169	963	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
Anna Bridge	180:96ed750bd169	964	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Anna Bridge	180:96ed750bd169	965
Anna Bridge	180:96ed750bd169	966	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
Anna Bridge	180:96ed750bd169	967	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Anna Bridge	180:96ed750bd169	968
Anna Bridge	180:96ed750bd169	969	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
Anna Bridge	180:96ed750bd169	970	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Anna Bridge	180:96ed750bd169	971
Anna Bridge	180:96ed750bd169	972	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
Anna Bridge	180:96ed750bd169	973	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Anna Bridge	180:96ed750bd169	974
Anna Bridge	180:96ed750bd169	975	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
Anna Bridge	180:96ed750bd169	976	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Anna Bridge	180:96ed750bd169	977
Anna Bridge	180:96ed750bd169	978	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
Anna Bridge	180:96ed750bd169	979	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Anna Bridge	180:96ed750bd169	980
Anna Bridge	180:96ed750bd169	981	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
Anna Bridge	180:96ed750bd169	982	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Anna Bridge	180:96ed750bd169	983
Anna Bridge	180:96ed750bd169	984	/@}/ /* end of group CMSIS_DWT */
Anna Bridge	180:96ed750bd169	985
Anna Bridge	180:96ed750bd169	986
Anna Bridge	180:96ed750bd169	987	/**
Anna Bridge	180:96ed750bd169	988	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	989	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge	180:96ed750bd169	990	\brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge	180:96ed750bd169	991	@{
Anna Bridge	180:96ed750bd169	992	*/
Anna Bridge	180:96ed750bd169	993
Anna Bridge	180:96ed750bd169	994	/**
Anna Bridge	180:96ed750bd169	995	\brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge	180:96ed750bd169	996	*/
Anna Bridge	180:96ed750bd169	997	typedef struct
Anna Bridge	180:96ed750bd169	998	{
AnnaBridge	188:bcfe06ba3d64	999	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Anna Bridge	180:96ed750bd169	1000	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Anna Bridge	180:96ed750bd169	1001	uint32_t RESERVED0[2U];
Anna Bridge	180:96ed750bd169	1002	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Anna Bridge	180:96ed750bd169	1003	uint32_t RESERVED1[55U];
Anna Bridge	180:96ed750bd169	1004	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Anna Bridge	180:96ed750bd169	1005	uint32_t RESERVED2[131U];
Anna Bridge	180:96ed750bd169	1006	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Anna Bridge	180:96ed750bd169	1007	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Anna Bridge	180:96ed750bd169	1008	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Anna Bridge	180:96ed750bd169	1009	uint32_t RESERVED3[759U];
AnnaBridge	188:bcfe06ba3d64	1010	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
Anna Bridge	180:96ed750bd169	1011	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Anna Bridge	180:96ed750bd169	1012	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Anna Bridge	180:96ed750bd169	1013	uint32_t RESERVED4[1U];
Anna Bridge	180:96ed750bd169	1014	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Anna Bridge	180:96ed750bd169	1015	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Anna Bridge	180:96ed750bd169	1016	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Anna Bridge	180:96ed750bd169	1017	uint32_t RESERVED5[39U];
Anna Bridge	180:96ed750bd169	1018	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Anna Bridge	180:96ed750bd169	1019	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Anna Bridge	180:96ed750bd169	1020	uint32_t RESERVED7[8U];
Anna Bridge	180:96ed750bd169	1021	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Anna Bridge	180:96ed750bd169	1022	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Anna Bridge	180:96ed750bd169	1023	} TPI_Type;
Anna Bridge	180:96ed750bd169	1024
Anna Bridge	180:96ed750bd169	1025	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1026	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	188:bcfe06ba3d64	1027	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Anna Bridge	180:96ed750bd169	1028
Anna Bridge	180:96ed750bd169	1029	/* TPI Selected Pin Protocol Register Definitions */
Anna Bridge	180:96ed750bd169	1030	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
Anna Bridge	180:96ed750bd169	1031	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Anna Bridge	180:96ed750bd169	1032
Anna Bridge	180:96ed750bd169	1033	/* TPI Formatter and Flush Status Register Definitions */
Anna Bridge	180:96ed750bd169	1034	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
Anna Bridge	180:96ed750bd169	1035	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Anna Bridge	180:96ed750bd169	1036
Anna Bridge	180:96ed750bd169	1037	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
Anna Bridge	180:96ed750bd169	1038	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Anna Bridge	180:96ed750bd169	1039
Anna Bridge	180:96ed750bd169	1040	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
Anna Bridge	180:96ed750bd169	1041	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Anna Bridge	180:96ed750bd169	1042
Anna Bridge	180:96ed750bd169	1043	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
Anna Bridge	180:96ed750bd169	1044	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Anna Bridge	180:96ed750bd169	1045
Anna Bridge	180:96ed750bd169	1046	/* TPI Formatter and Flush Control Register Definitions */
Anna Bridge	180:96ed750bd169	1047	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
Anna Bridge	180:96ed750bd169	1048	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Anna Bridge	180:96ed750bd169	1049
Anna Bridge	180:96ed750bd169	1050	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
Anna Bridge	180:96ed750bd169	1051	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Anna Bridge	180:96ed750bd169	1052
Anna Bridge	180:96ed750bd169	1053	/* TPI TRIGGER Register Definitions */
Anna Bridge	180:96ed750bd169	1054	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
Anna Bridge	180:96ed750bd169	1055	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Anna Bridge	180:96ed750bd169	1056
Anna Bridge	180:96ed750bd169	1057	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge	180:96ed750bd169	1058	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1059	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1060
Anna Bridge	180:96ed750bd169	1061	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
Anna Bridge	180:96ed750bd169	1062	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1063
Anna Bridge	180:96ed750bd169	1064	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1065	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1066
Anna Bridge	180:96ed750bd169	1067	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
Anna Bridge	180:96ed750bd169	1068	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1069
Anna Bridge	180:96ed750bd169	1070	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
Anna Bridge	180:96ed750bd169	1071	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Anna Bridge	180:96ed750bd169	1072
Anna Bridge	180:96ed750bd169	1073	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
Anna Bridge	180:96ed750bd169	1074	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Anna Bridge	180:96ed750bd169	1075
Anna Bridge	180:96ed750bd169	1076	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
Anna Bridge	180:96ed750bd169	1077	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Anna Bridge	180:96ed750bd169	1078
Anna Bridge	180:96ed750bd169	1079	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1080	#define TPI_ITATBCTR2_ATREADY2_Pos 0U /!< TPI ITATBCTR2: ATREADY2 Position /
AnnaBridge	188:bcfe06ba3d64	1081	#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/) /!< TPI ITATBCTR2: ATREADY2 Mask /
AnnaBridge	188:bcfe06ba3d64	1082
AnnaBridge	188:bcfe06ba3d64	1083	#define TPI_ITATBCTR2_ATREADY1_Pos 0U /!< TPI ITATBCTR2: ATREADY1 Position /
AnnaBridge	188:bcfe06ba3d64	1084	#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/) /!< TPI ITATBCTR2: ATREADY1 Mask /
Anna Bridge	180:96ed750bd169	1085
Anna Bridge	180:96ed750bd169	1086	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge	180:96ed750bd169	1087	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1088	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1089
Anna Bridge	180:96ed750bd169	1090	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
Anna Bridge	180:96ed750bd169	1091	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1092
Anna Bridge	180:96ed750bd169	1093	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
Anna Bridge	180:96ed750bd169	1094	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Anna Bridge	180:96ed750bd169	1095
Anna Bridge	180:96ed750bd169	1096	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
Anna Bridge	180:96ed750bd169	1097	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Anna Bridge	180:96ed750bd169	1098
Anna Bridge	180:96ed750bd169	1099	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
Anna Bridge	180:96ed750bd169	1100	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Anna Bridge	180:96ed750bd169	1101
Anna Bridge	180:96ed750bd169	1102	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
Anna Bridge	180:96ed750bd169	1103	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Anna Bridge	180:96ed750bd169	1104
Anna Bridge	180:96ed750bd169	1105	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
Anna Bridge	180:96ed750bd169	1106	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Anna Bridge	180:96ed750bd169	1107
Anna Bridge	180:96ed750bd169	1108	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1109	#define TPI_ITATBCTR0_ATREADY2_Pos 0U /!< TPI ITATBCTR0: ATREADY2 Position /
AnnaBridge	188:bcfe06ba3d64	1110	#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/) /!< TPI ITATBCTR0: ATREADY2 Mask /
AnnaBridge	188:bcfe06ba3d64	1111
AnnaBridge	188:bcfe06ba3d64	1112	#define TPI_ITATBCTR0_ATREADY1_Pos 0U /!< TPI ITATBCTR0: ATREADY1 Position /
AnnaBridge	188:bcfe06ba3d64	1113	#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/) /!< TPI ITATBCTR0: ATREADY1 Mask /
Anna Bridge	180:96ed750bd169	1114
Anna Bridge	180:96ed750bd169	1115	/* TPI Integration Mode Control Register Definitions */
Anna Bridge	180:96ed750bd169	1116	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	188:bcfe06ba3d64	1117	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Anna Bridge	180:96ed750bd169	1118
Anna Bridge	180:96ed750bd169	1119	/* TPI DEVID Register Definitions */
Anna Bridge	180:96ed750bd169	1120	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
Anna Bridge	180:96ed750bd169	1121	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Anna Bridge	180:96ed750bd169	1122
Anna Bridge	180:96ed750bd169	1123	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
Anna Bridge	180:96ed750bd169	1124	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Anna Bridge	180:96ed750bd169	1125
Anna Bridge	180:96ed750bd169	1126	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
Anna Bridge	180:96ed750bd169	1127	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Anna Bridge	180:96ed750bd169	1128
Anna Bridge	180:96ed750bd169	1129	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
Anna Bridge	180:96ed750bd169	1130	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Anna Bridge	180:96ed750bd169	1131
Anna Bridge	180:96ed750bd169	1132	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
Anna Bridge	180:96ed750bd169	1133	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Anna Bridge	180:96ed750bd169	1134
Anna Bridge	180:96ed750bd169	1135	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
Anna Bridge	180:96ed750bd169	1136	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Anna Bridge	180:96ed750bd169	1137
Anna Bridge	180:96ed750bd169	1138	/* TPI DEVTYPE Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1139	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	188:bcfe06ba3d64	1140	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Anna Bridge	180:96ed750bd169	1141
AnnaBridge	188:bcfe06ba3d64	1142	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	188:bcfe06ba3d64	1143	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Anna Bridge	180:96ed750bd169	1144
Anna Bridge	180:96ed750bd169	1145	/@}/ /* end of group CMSIS_TPI */
Anna Bridge	180:96ed750bd169	1146
Anna Bridge	180:96ed750bd169	1147
Anna Bridge	180:96ed750bd169	1148	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1149	/**
Anna Bridge	180:96ed750bd169	1150	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1151	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge	180:96ed750bd169	1152	\brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge	180:96ed750bd169	1153	@{
Anna Bridge	180:96ed750bd169	1154	*/
Anna Bridge	180:96ed750bd169	1155
Anna Bridge	180:96ed750bd169	1156	/**
Anna Bridge	180:96ed750bd169	1157	\brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge	180:96ed750bd169	1158	*/
Anna Bridge	180:96ed750bd169	1159	typedef struct
Anna Bridge	180:96ed750bd169	1160	{
Anna Bridge	180:96ed750bd169	1161	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Anna Bridge	180:96ed750bd169	1162	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Anna Bridge	180:96ed750bd169	1163	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Anna Bridge	180:96ed750bd169	1164	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Anna Bridge	180:96ed750bd169	1165	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1166	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Anna Bridge	180:96ed750bd169	1167	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1168	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Anna Bridge	180:96ed750bd169	1169	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1170	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Anna Bridge	180:96ed750bd169	1171	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Anna Bridge	180:96ed750bd169	1172	} MPU_Type;
Anna Bridge	180:96ed750bd169	1173
Anna Bridge	180:96ed750bd169	1174	#define MPU_TYPE_RALIASES 4U
Anna Bridge	180:96ed750bd169	1175
Anna Bridge	180:96ed750bd169	1176	/* MPU Type Register Definitions */
Anna Bridge	180:96ed750bd169	1177	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
Anna Bridge	180:96ed750bd169	1178	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Anna Bridge	180:96ed750bd169	1179
Anna Bridge	180:96ed750bd169	1180	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
Anna Bridge	180:96ed750bd169	1181	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Anna Bridge	180:96ed750bd169	1182
Anna Bridge	180:96ed750bd169	1183	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
Anna Bridge	180:96ed750bd169	1184	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Anna Bridge	180:96ed750bd169	1185
Anna Bridge	180:96ed750bd169	1186	/* MPU Control Register Definitions */
Anna Bridge	180:96ed750bd169	1187	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
Anna Bridge	180:96ed750bd169	1188	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Anna Bridge	180:96ed750bd169	1189
Anna Bridge	180:96ed750bd169	1190	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
Anna Bridge	180:96ed750bd169	1191	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Anna Bridge	180:96ed750bd169	1192
Anna Bridge	180:96ed750bd169	1193	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	1194	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	1195
Anna Bridge	180:96ed750bd169	1196	/* MPU Region Number Register Definitions */
Anna Bridge	180:96ed750bd169	1197	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
Anna Bridge	180:96ed750bd169	1198	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Anna Bridge	180:96ed750bd169	1199
Anna Bridge	180:96ed750bd169	1200	/* MPU Region Base Address Register Definitions */
Anna Bridge	180:96ed750bd169	1201	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
Anna Bridge	180:96ed750bd169	1202	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Anna Bridge	180:96ed750bd169	1203
Anna Bridge	180:96ed750bd169	1204	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
Anna Bridge	180:96ed750bd169	1205	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Anna Bridge	180:96ed750bd169	1206
Anna Bridge	180:96ed750bd169	1207	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
Anna Bridge	180:96ed750bd169	1208	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Anna Bridge	180:96ed750bd169	1209
Anna Bridge	180:96ed750bd169	1210	/* MPU Region Attribute and Size Register Definitions */
Anna Bridge	180:96ed750bd169	1211	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
Anna Bridge	180:96ed750bd169	1212	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Anna Bridge	180:96ed750bd169	1213
Anna Bridge	180:96ed750bd169	1214	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
Anna Bridge	180:96ed750bd169	1215	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Anna Bridge	180:96ed750bd169	1216
Anna Bridge	180:96ed750bd169	1217	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
Anna Bridge	180:96ed750bd169	1218	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Anna Bridge	180:96ed750bd169	1219
Anna Bridge	180:96ed750bd169	1220	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
Anna Bridge	180:96ed750bd169	1221	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Anna Bridge	180:96ed750bd169	1222
Anna Bridge	180:96ed750bd169	1223	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
Anna Bridge	180:96ed750bd169	1224	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Anna Bridge	180:96ed750bd169	1225
Anna Bridge	180:96ed750bd169	1226	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
Anna Bridge	180:96ed750bd169	1227	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Anna Bridge	180:96ed750bd169	1228
Anna Bridge	180:96ed750bd169	1229	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
Anna Bridge	180:96ed750bd169	1230	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Anna Bridge	180:96ed750bd169	1231
Anna Bridge	180:96ed750bd169	1232	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
Anna Bridge	180:96ed750bd169	1233	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Anna Bridge	180:96ed750bd169	1234
Anna Bridge	180:96ed750bd169	1235	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
Anna Bridge	180:96ed750bd169	1236	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Anna Bridge	180:96ed750bd169	1237
Anna Bridge	180:96ed750bd169	1238	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
Anna Bridge	180:96ed750bd169	1239	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Anna Bridge	180:96ed750bd169	1240
Anna Bridge	180:96ed750bd169	1241	/@} end of group CMSIS_MPU /
Anna Bridge	180:96ed750bd169	1242	#endif
Anna Bridge	180:96ed750bd169	1243
Anna Bridge	180:96ed750bd169	1244
Anna Bridge	180:96ed750bd169	1245	/**
Anna Bridge	180:96ed750bd169	1246	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1247	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge	180:96ed750bd169	1248	\brief Type definitions for the Core Debug Registers
Anna Bridge	180:96ed750bd169	1249	@{
Anna Bridge	180:96ed750bd169	1250	*/
Anna Bridge	180:96ed750bd169	1251
Anna Bridge	180:96ed750bd169	1252	/**
Anna Bridge	180:96ed750bd169	1253	\brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge	180:96ed750bd169	1254	*/
Anna Bridge	180:96ed750bd169	1255	typedef struct
Anna Bridge	180:96ed750bd169	1256	{
Anna Bridge	180:96ed750bd169	1257	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Anna Bridge	180:96ed750bd169	1258	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Anna Bridge	180:96ed750bd169	1259	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Anna Bridge	180:96ed750bd169	1260	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Anna Bridge	180:96ed750bd169	1261	} CoreDebug_Type;
Anna Bridge	180:96ed750bd169	1262
Anna Bridge	180:96ed750bd169	1263	/* Debug Halting Control and Status Register Definitions */
Anna Bridge	180:96ed750bd169	1264	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
Anna Bridge	180:96ed750bd169	1265	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Anna Bridge	180:96ed750bd169	1266
Anna Bridge	180:96ed750bd169	1267	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
Anna Bridge	180:96ed750bd169	1268	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Anna Bridge	180:96ed750bd169	1269
Anna Bridge	180:96ed750bd169	1270	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Anna Bridge	180:96ed750bd169	1271	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Anna Bridge	180:96ed750bd169	1272
Anna Bridge	180:96ed750bd169	1273	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
Anna Bridge	180:96ed750bd169	1274	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Anna Bridge	180:96ed750bd169	1275
Anna Bridge	180:96ed750bd169	1276	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
Anna Bridge	180:96ed750bd169	1277	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Anna Bridge	180:96ed750bd169	1278
Anna Bridge	180:96ed750bd169	1279	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
Anna Bridge	180:96ed750bd169	1280	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Anna Bridge	180:96ed750bd169	1281
Anna Bridge	180:96ed750bd169	1282	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
Anna Bridge	180:96ed750bd169	1283	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Anna Bridge	180:96ed750bd169	1284
Anna Bridge	180:96ed750bd169	1285	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Anna Bridge	180:96ed750bd169	1286	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Anna Bridge	180:96ed750bd169	1287
Anna Bridge	180:96ed750bd169	1288	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
Anna Bridge	180:96ed750bd169	1289	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Anna Bridge	180:96ed750bd169	1290
Anna Bridge	180:96ed750bd169	1291	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
Anna Bridge	180:96ed750bd169	1292	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Anna Bridge	180:96ed750bd169	1293
Anna Bridge	180:96ed750bd169	1294	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
Anna Bridge	180:96ed750bd169	1295	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Anna Bridge	180:96ed750bd169	1296
Anna Bridge	180:96ed750bd169	1297	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
Anna Bridge	180:96ed750bd169	1298	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Anna Bridge	180:96ed750bd169	1299
Anna Bridge	180:96ed750bd169	1300	/* Debug Core Register Selector Register Definitions */
Anna Bridge	180:96ed750bd169	1301	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
Anna Bridge	180:96ed750bd169	1302	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Anna Bridge	180:96ed750bd169	1303
Anna Bridge	180:96ed750bd169	1304	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
Anna Bridge	180:96ed750bd169	1305	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Anna Bridge	180:96ed750bd169	1306
Anna Bridge	180:96ed750bd169	1307	/* Debug Exception and Monitor Control Register Definitions */
Anna Bridge	180:96ed750bd169	1308	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
Anna Bridge	180:96ed750bd169	1309	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Anna Bridge	180:96ed750bd169	1310
Anna Bridge	180:96ed750bd169	1311	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
Anna Bridge	180:96ed750bd169	1312	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Anna Bridge	180:96ed750bd169	1313
Anna Bridge	180:96ed750bd169	1314	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
Anna Bridge	180:96ed750bd169	1315	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Anna Bridge	180:96ed750bd169	1316
Anna Bridge	180:96ed750bd169	1317	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
Anna Bridge	180:96ed750bd169	1318	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Anna Bridge	180:96ed750bd169	1319
Anna Bridge	180:96ed750bd169	1320	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
Anna Bridge	180:96ed750bd169	1321	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Anna Bridge	180:96ed750bd169	1322
Anna Bridge	180:96ed750bd169	1323	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
Anna Bridge	180:96ed750bd169	1324	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Anna Bridge	180:96ed750bd169	1325
Anna Bridge	180:96ed750bd169	1326	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
Anna Bridge	180:96ed750bd169	1327	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Anna Bridge	180:96ed750bd169	1328
Anna Bridge	180:96ed750bd169	1329	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
Anna Bridge	180:96ed750bd169	1330	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Anna Bridge	180:96ed750bd169	1331
Anna Bridge	180:96ed750bd169	1332	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
Anna Bridge	180:96ed750bd169	1333	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Anna Bridge	180:96ed750bd169	1334
Anna Bridge	180:96ed750bd169	1335	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
Anna Bridge	180:96ed750bd169	1336	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Anna Bridge	180:96ed750bd169	1337
Anna Bridge	180:96ed750bd169	1338	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
Anna Bridge	180:96ed750bd169	1339	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Anna Bridge	180:96ed750bd169	1340
Anna Bridge	180:96ed750bd169	1341	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
Anna Bridge	180:96ed750bd169	1342	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Anna Bridge	180:96ed750bd169	1343
Anna Bridge	180:96ed750bd169	1344	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
Anna Bridge	180:96ed750bd169	1345	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Anna Bridge	180:96ed750bd169	1346
Anna Bridge	180:96ed750bd169	1347	/@} end of group CMSIS_CoreDebug /
Anna Bridge	180:96ed750bd169	1348
Anna Bridge	180:96ed750bd169	1349
Anna Bridge	180:96ed750bd169	1350	/**
Anna Bridge	180:96ed750bd169	1351	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1352	\defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge	180:96ed750bd169	1353	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge	180:96ed750bd169	1354	@{
Anna Bridge	180:96ed750bd169	1355	*/
Anna Bridge	180:96ed750bd169	1356
Anna Bridge	180:96ed750bd169	1357	/**
Anna Bridge	180:96ed750bd169	1358	\brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge	180:96ed750bd169	1359	\param[in] field Name of the register bit field.
Anna Bridge	180:96ed750bd169	1360	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge	180:96ed750bd169	1361	\return Masked and shifted value.
Anna Bridge	180:96ed750bd169	1362	*/
Anna Bridge	180:96ed750bd169	1363	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge	180:96ed750bd169	1364
Anna Bridge	180:96ed750bd169	1365	/**
Anna Bridge	180:96ed750bd169	1366	\brief Mask and shift a register value to extract a bit filed value.
Anna Bridge	180:96ed750bd169	1367	\param[in] field Name of the register bit field.
Anna Bridge	180:96ed750bd169	1368	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge	180:96ed750bd169	1369	\return Masked and shifted bit field value.
Anna Bridge	180:96ed750bd169	1370	*/
Anna Bridge	180:96ed750bd169	1371	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge	180:96ed750bd169	1372
Anna Bridge	180:96ed750bd169	1373	/@} end of group CMSIS_core_bitfield /
Anna Bridge	180:96ed750bd169	1374
Anna Bridge	180:96ed750bd169	1375
Anna Bridge	180:96ed750bd169	1376	/**
Anna Bridge	180:96ed750bd169	1377	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1378	\defgroup CMSIS_core_base Core Definitions
Anna Bridge	180:96ed750bd169	1379	\brief Definitions for base addresses, unions, and structures.
Anna Bridge	180:96ed750bd169	1380	@{
Anna Bridge	180:96ed750bd169	1381	*/
Anna Bridge	180:96ed750bd169	1382
Anna Bridge	180:96ed750bd169	1383	/* Memory mapping of Core Hardware */
Anna Bridge	180:96ed750bd169	1384	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Anna Bridge	180:96ed750bd169	1385	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Anna Bridge	180:96ed750bd169	1386	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Anna Bridge	180:96ed750bd169	1387	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Anna Bridge	180:96ed750bd169	1388	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Anna Bridge	180:96ed750bd169	1389	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Anna Bridge	180:96ed750bd169	1390	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Anna Bridge	180:96ed750bd169	1391	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Anna Bridge	180:96ed750bd169	1392
Anna Bridge	180:96ed750bd169	1393	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Anna Bridge	180:96ed750bd169	1394	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Anna Bridge	180:96ed750bd169	1395	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Anna Bridge	180:96ed750bd169	1396	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Anna Bridge	180:96ed750bd169	1397	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Anna Bridge	180:96ed750bd169	1398	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Anna Bridge	180:96ed750bd169	1399	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Anna Bridge	180:96ed750bd169	1400	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Anna Bridge	180:96ed750bd169	1401
Anna Bridge	180:96ed750bd169	1402	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1403	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Anna Bridge	180:96ed750bd169	1404	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Anna Bridge	180:96ed750bd169	1405	#endif
Anna Bridge	180:96ed750bd169	1406
Anna Bridge	180:96ed750bd169	1407	/@} /
Anna Bridge	180:96ed750bd169	1408
Anna Bridge	180:96ed750bd169	1409
Anna Bridge	180:96ed750bd169	1410
Anna Bridge	180:96ed750bd169	1411	/*******************************************************************************
Anna Bridge	180:96ed750bd169	1412	* Hardware Abstraction Layer
Anna Bridge	180:96ed750bd169	1413	Core Function Interface contains:
Anna Bridge	180:96ed750bd169	1414	- Core NVIC Functions
Anna Bridge	180:96ed750bd169	1415	- Core SysTick Functions
Anna Bridge	180:96ed750bd169	1416	- Core Debug Functions
Anna Bridge	180:96ed750bd169	1417	- Core Register Access Functions
Anna Bridge	180:96ed750bd169	1418	******************************************************************************/
Anna Bridge	180:96ed750bd169	1419	/**
Anna Bridge	180:96ed750bd169	1420	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge	180:96ed750bd169	1421	*/
Anna Bridge	180:96ed750bd169	1422
Anna Bridge	180:96ed750bd169	1423
Anna Bridge	180:96ed750bd169	1424
Anna Bridge	180:96ed750bd169	1425	/* ########################## NVIC functions #################################### */
Anna Bridge	180:96ed750bd169	1426	/**
Anna Bridge	180:96ed750bd169	1427	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	1428	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge	180:96ed750bd169	1429	\brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge	180:96ed750bd169	1430	@{
Anna Bridge	180:96ed750bd169	1431	*/
Anna Bridge	180:96ed750bd169	1432
Anna Bridge	180:96ed750bd169	1433	#ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge	180:96ed750bd169	1434	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1435	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge	180:96ed750bd169	1436	#endif
Anna Bridge	180:96ed750bd169	1437	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1438	#else
Anna Bridge	180:96ed750bd169	1439	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge	180:96ed750bd169	1440	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge	180:96ed750bd169	1441	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge	180:96ed750bd169	1442	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge	180:96ed750bd169	1443	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge	180:96ed750bd169	1444	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge	180:96ed750bd169	1445	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge	180:96ed750bd169	1446	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge	180:96ed750bd169	1447	#define NVIC_GetActive __NVIC_GetActive
Anna Bridge	180:96ed750bd169	1448	#define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge	180:96ed750bd169	1449	#define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge	180:96ed750bd169	1450	#define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge	180:96ed750bd169	1451	#endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge	180:96ed750bd169	1452
Anna Bridge	180:96ed750bd169	1453	#ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge	180:96ed750bd169	1454	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1455	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge	180:96ed750bd169	1456	#endif
Anna Bridge	180:96ed750bd169	1457	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	1458	#else
Anna Bridge	180:96ed750bd169	1459	#define NVIC_SetVector __NVIC_SetVector
Anna Bridge	180:96ed750bd169	1460	#define NVIC_GetVector __NVIC_GetVector
Anna Bridge	180:96ed750bd169	1461	#endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge	180:96ed750bd169	1462
Anna Bridge	180:96ed750bd169	1463	#define NVIC_USER_IRQ_OFFSET 16
Anna Bridge	180:96ed750bd169	1464
Anna Bridge	180:96ed750bd169	1465
AnnaBridge	188:bcfe06ba3d64	1466	/* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge	188:bcfe06ba3d64	1467	#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge	188:bcfe06ba3d64	1468	#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge	188:bcfe06ba3d64	1469	#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge	188:bcfe06ba3d64	1470
Anna Bridge	180:96ed750bd169	1471
Anna Bridge	180:96ed750bd169	1472	/**
Anna Bridge	180:96ed750bd169	1473	\brief Set Priority Grouping
Anna Bridge	180:96ed750bd169	1474	\details Sets the priority grouping field using the required unlock sequence.
Anna Bridge	180:96ed750bd169	1475	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	180:96ed750bd169	1476	Only values from 0..7 are used.
Anna Bridge	180:96ed750bd169	1477	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	1478	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	1479	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	180:96ed750bd169	1480	*/
Anna Bridge	180:96ed750bd169	1481	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge	180:96ed750bd169	1482	{
Anna Bridge	180:96ed750bd169	1483	uint32_t reg_value;
Anna Bridge	180:96ed750bd169	1484	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	1485
Anna Bridge	180:96ed750bd169	1486	reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge	180:96ed750bd169	1487	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	180:96ed750bd169	1488	reg_value = (reg_value \|
Anna Bridge	180:96ed750bd169	1489	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	186:707f6e361f3e	1490	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
Anna Bridge	180:96ed750bd169	1491	SCB->AIRCR = reg_value;
Anna Bridge	180:96ed750bd169	1492	}
Anna Bridge	180:96ed750bd169	1493
Anna Bridge	180:96ed750bd169	1494
Anna Bridge	180:96ed750bd169	1495	/**
Anna Bridge	180:96ed750bd169	1496	\brief Get Priority Grouping
Anna Bridge	180:96ed750bd169	1497	\details Reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge	180:96ed750bd169	1498	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	180:96ed750bd169	1499	*/
Anna Bridge	180:96ed750bd169	1500	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge	180:96ed750bd169	1501	{
Anna Bridge	180:96ed750bd169	1502	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	180:96ed750bd169	1503	}
Anna Bridge	180:96ed750bd169	1504
Anna Bridge	180:96ed750bd169	1505
Anna Bridge	180:96ed750bd169	1506	/**
Anna Bridge	180:96ed750bd169	1507	\brief Enable Interrupt
Anna Bridge	180:96ed750bd169	1508	\details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	1509	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1510	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1511	*/
Anna Bridge	180:96ed750bd169	1512	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1513	{
Anna Bridge	180:96ed750bd169	1514	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1515	{
Anna Bridge	186:707f6e361f3e	1516	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1517	}
Anna Bridge	180:96ed750bd169	1518	}
Anna Bridge	180:96ed750bd169	1519
Anna Bridge	180:96ed750bd169	1520
Anna Bridge	180:96ed750bd169	1521	/**
Anna Bridge	180:96ed750bd169	1522	\brief Get Interrupt Enable status
Anna Bridge	180:96ed750bd169	1523	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	1524	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1525	\return 0 Interrupt is not enabled.
Anna Bridge	180:96ed750bd169	1526	\return 1 Interrupt is enabled.
Anna Bridge	180:96ed750bd169	1527	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1528	*/
Anna Bridge	180:96ed750bd169	1529	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1530	{
Anna Bridge	180:96ed750bd169	1531	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1532	{
Anna Bridge	186:707f6e361f3e	1533	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	1534	}
Anna Bridge	180:96ed750bd169	1535	else
Anna Bridge	180:96ed750bd169	1536	{
Anna Bridge	180:96ed750bd169	1537	return(0U);
Anna Bridge	180:96ed750bd169	1538	}
Anna Bridge	180:96ed750bd169	1539	}
Anna Bridge	180:96ed750bd169	1540
Anna Bridge	180:96ed750bd169	1541
Anna Bridge	180:96ed750bd169	1542	/**
Anna Bridge	180:96ed750bd169	1543	\brief Disable Interrupt
Anna Bridge	180:96ed750bd169	1544	\details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	1545	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1546	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1547	*/
Anna Bridge	180:96ed750bd169	1548	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1549	{
Anna Bridge	180:96ed750bd169	1550	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1551	{
Anna Bridge	186:707f6e361f3e	1552	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1553	__DSB();
Anna Bridge	180:96ed750bd169	1554	__ISB();
Anna Bridge	180:96ed750bd169	1555	}
Anna Bridge	180:96ed750bd169	1556	}
Anna Bridge	180:96ed750bd169	1557
Anna Bridge	180:96ed750bd169	1558
Anna Bridge	180:96ed750bd169	1559	/**
Anna Bridge	180:96ed750bd169	1560	\brief Get Pending Interrupt
Anna Bridge	180:96ed750bd169	1561	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge	180:96ed750bd169	1562	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1563	\return 0 Interrupt status is not pending.
Anna Bridge	180:96ed750bd169	1564	\return 1 Interrupt status is pending.
Anna Bridge	180:96ed750bd169	1565	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1566	*/
Anna Bridge	180:96ed750bd169	1567	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1568	{
Anna Bridge	180:96ed750bd169	1569	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1570	{
Anna Bridge	186:707f6e361f3e	1571	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	1572	}
Anna Bridge	180:96ed750bd169	1573	else
Anna Bridge	180:96ed750bd169	1574	{
Anna Bridge	180:96ed750bd169	1575	return(0U);
Anna Bridge	180:96ed750bd169	1576	}
Anna Bridge	180:96ed750bd169	1577	}
Anna Bridge	180:96ed750bd169	1578
Anna Bridge	180:96ed750bd169	1579
Anna Bridge	180:96ed750bd169	1580	/**
Anna Bridge	180:96ed750bd169	1581	\brief Set Pending Interrupt
Anna Bridge	180:96ed750bd169	1582	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	180:96ed750bd169	1583	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1584	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1585	*/
Anna Bridge	180:96ed750bd169	1586	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1587	{
Anna Bridge	180:96ed750bd169	1588	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1589	{
Anna Bridge	186:707f6e361f3e	1590	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1591	}
Anna Bridge	180:96ed750bd169	1592	}
Anna Bridge	180:96ed750bd169	1593
Anna Bridge	180:96ed750bd169	1594
Anna Bridge	180:96ed750bd169	1595	/**
Anna Bridge	180:96ed750bd169	1596	\brief Clear Pending Interrupt
Anna Bridge	180:96ed750bd169	1597	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	180:96ed750bd169	1598	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1599	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1600	*/
Anna Bridge	180:96ed750bd169	1601	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1602	{
Anna Bridge	180:96ed750bd169	1603	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1604	{
Anna Bridge	186:707f6e361f3e	1605	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	1606	}
Anna Bridge	180:96ed750bd169	1607	}
Anna Bridge	180:96ed750bd169	1608
Anna Bridge	180:96ed750bd169	1609
Anna Bridge	180:96ed750bd169	1610	/**
Anna Bridge	180:96ed750bd169	1611	\brief Get Active Interrupt
Anna Bridge	180:96ed750bd169	1612	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	1613	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	1614	\return 0 Interrupt status is not active.
Anna Bridge	180:96ed750bd169	1615	\return 1 Interrupt status is active.
Anna Bridge	180:96ed750bd169	1616	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	1617	*/
Anna Bridge	180:96ed750bd169	1618	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1619	{
Anna Bridge	180:96ed750bd169	1620	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1621	{
Anna Bridge	186:707f6e361f3e	1622	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	1623	}
Anna Bridge	180:96ed750bd169	1624	else
Anna Bridge	180:96ed750bd169	1625	{
Anna Bridge	180:96ed750bd169	1626	return(0U);
Anna Bridge	180:96ed750bd169	1627	}
Anna Bridge	180:96ed750bd169	1628	}
Anna Bridge	180:96ed750bd169	1629
Anna Bridge	180:96ed750bd169	1630
Anna Bridge	180:96ed750bd169	1631	/**
Anna Bridge	180:96ed750bd169	1632	\brief Set Interrupt Priority
Anna Bridge	180:96ed750bd169	1633	\details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge	180:96ed750bd169	1634	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	1635	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	1636	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	1637	\param [in] priority Priority to set.
Anna Bridge	180:96ed750bd169	1638	\note The priority cannot be set for every processor exception.
Anna Bridge	180:96ed750bd169	1639	*/
Anna Bridge	180:96ed750bd169	1640	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	180:96ed750bd169	1641	{
Anna Bridge	180:96ed750bd169	1642	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1643	{
Anna Bridge	186:707f6e361f3e	1644	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	1645	}
Anna Bridge	180:96ed750bd169	1646	else
Anna Bridge	180:96ed750bd169	1647	{
Anna Bridge	186:707f6e361f3e	1648	SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	1649	}
Anna Bridge	180:96ed750bd169	1650	}
Anna Bridge	180:96ed750bd169	1651
Anna Bridge	180:96ed750bd169	1652
Anna Bridge	180:96ed750bd169	1653	/**
Anna Bridge	180:96ed750bd169	1654	\brief Get Interrupt Priority
Anna Bridge	180:96ed750bd169	1655	\details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge	180:96ed750bd169	1656	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	1657	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	1658	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	1659	\return Interrupt Priority.
Anna Bridge	180:96ed750bd169	1660	Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge	180:96ed750bd169	1661	*/
Anna Bridge	180:96ed750bd169	1662	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1663	{
Anna Bridge	180:96ed750bd169	1664
Anna Bridge	180:96ed750bd169	1665	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	1666	{
Anna Bridge	186:707f6e361f3e	1667	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	1668	}
Anna Bridge	180:96ed750bd169	1669	else
Anna Bridge	180:96ed750bd169	1670	{
Anna Bridge	186:707f6e361f3e	1671	return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	1672	}
Anna Bridge	180:96ed750bd169	1673	}
Anna Bridge	180:96ed750bd169	1674
Anna Bridge	180:96ed750bd169	1675
Anna Bridge	180:96ed750bd169	1676	/**
Anna Bridge	180:96ed750bd169	1677	\brief Encode Priority
Anna Bridge	180:96ed750bd169	1678	\details Encodes the priority for an interrupt with the given priority group,
Anna Bridge	180:96ed750bd169	1679	preemptive priority value, and subpriority value.
Anna Bridge	180:96ed750bd169	1680	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	1681	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	1682	\param [in] PriorityGroup Used priority group.
Anna Bridge	180:96ed750bd169	1683	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	180:96ed750bd169	1684	\param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge	180:96ed750bd169	1685	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge	180:96ed750bd169	1686	*/
Anna Bridge	180:96ed750bd169	1687	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge	180:96ed750bd169	1688	{
Anna Bridge	180:96ed750bd169	1689	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	1690	uint32_t PreemptPriorityBits;
Anna Bridge	180:96ed750bd169	1691	uint32_t SubPriorityBits;
Anna Bridge	180:96ed750bd169	1692
Anna Bridge	180:96ed750bd169	1693	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	180:96ed750bd169	1694	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	180:96ed750bd169	1695
Anna Bridge	180:96ed750bd169	1696	return (
Anna Bridge	180:96ed750bd169	1697	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Anna Bridge	180:96ed750bd169	1698	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge	180:96ed750bd169	1699	);
Anna Bridge	180:96ed750bd169	1700	}
Anna Bridge	180:96ed750bd169	1701
Anna Bridge	180:96ed750bd169	1702
Anna Bridge	180:96ed750bd169	1703	/**
Anna Bridge	180:96ed750bd169	1704	\brief Decode Priority
Anna Bridge	180:96ed750bd169	1705	\details Decodes an interrupt priority value with a given priority group to
Anna Bridge	180:96ed750bd169	1706	preemptive priority value and subpriority value.
Anna Bridge	180:96ed750bd169	1707	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	1708	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	1709	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge	180:96ed750bd169	1710	\param [in] PriorityGroup Used priority group.
Anna Bridge	180:96ed750bd169	1711	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	180:96ed750bd169	1712	\param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge	180:96ed750bd169	1713	*/
Anna Bridge	180:96ed750bd169	1714	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Anna Bridge	180:96ed750bd169	1715	{
Anna Bridge	180:96ed750bd169	1716	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	1717	uint32_t PreemptPriorityBits;
Anna Bridge	180:96ed750bd169	1718	uint32_t SubPriorityBits;
Anna Bridge	180:96ed750bd169	1719
Anna Bridge	180:96ed750bd169	1720	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	180:96ed750bd169	1721	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	180:96ed750bd169	1722
Anna Bridge	180:96ed750bd169	1723	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge	180:96ed750bd169	1724	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge	180:96ed750bd169	1725	}
Anna Bridge	180:96ed750bd169	1726
Anna Bridge	180:96ed750bd169	1727
Anna Bridge	180:96ed750bd169	1728	/**
Anna Bridge	180:96ed750bd169	1729	\brief Set Interrupt Vector
Anna Bridge	180:96ed750bd169	1730	\details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge	180:96ed750bd169	1731	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	1732	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	1733	VTOR must been relocated to SRAM before.
Anna Bridge	180:96ed750bd169	1734	\param [in] IRQn Interrupt number
Anna Bridge	180:96ed750bd169	1735	\param [in] vector Address of interrupt handler function
Anna Bridge	180:96ed750bd169	1736	*/
Anna Bridge	180:96ed750bd169	1737	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge	180:96ed750bd169	1738	{
Anna Bridge	180:96ed750bd169	1739	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	180:96ed750bd169	1740	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge	180:96ed750bd169	1741	}
Anna Bridge	180:96ed750bd169	1742
Anna Bridge	180:96ed750bd169	1743
Anna Bridge	180:96ed750bd169	1744	/**
Anna Bridge	180:96ed750bd169	1745	\brief Get Interrupt Vector
Anna Bridge	180:96ed750bd169	1746	\details Reads an interrupt vector from interrupt vector table.
Anna Bridge	180:96ed750bd169	1747	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	1748	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	1749	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	1750	\return Address of interrupt handler function
Anna Bridge	180:96ed750bd169	1751	*/
Anna Bridge	180:96ed750bd169	1752	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	1753	{
Anna Bridge	180:96ed750bd169	1754	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	180:96ed750bd169	1755	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge	180:96ed750bd169	1756	}
Anna Bridge	180:96ed750bd169	1757
Anna Bridge	180:96ed750bd169	1758
Anna Bridge	180:96ed750bd169	1759	/**
Anna Bridge	180:96ed750bd169	1760	\brief System Reset
Anna Bridge	180:96ed750bd169	1761	\details Initiates a system reset request to reset the MCU.
Anna Bridge	180:96ed750bd169	1762	*/
AnnaBridge	188:bcfe06ba3d64	1763	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge	180:96ed750bd169	1764	{
Anna Bridge	180:96ed750bd169	1765	__DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge	180:96ed750bd169	1766	buffered write are completed before reset */
Anna Bridge	180:96ed750bd169	1767	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	180:96ed750bd169	1768	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Anna Bridge	180:96ed750bd169	1769	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge	180:96ed750bd169	1770	__DSB(); /* Ensure completion of memory access */
Anna Bridge	180:96ed750bd169	1771
Anna Bridge	180:96ed750bd169	1772	for(;;) /* wait until reset */
Anna Bridge	180:96ed750bd169	1773	{
Anna Bridge	180:96ed750bd169	1774	__NOP();
Anna Bridge	180:96ed750bd169	1775	}
Anna Bridge	180:96ed750bd169	1776	}
Anna Bridge	180:96ed750bd169	1777
Anna Bridge	180:96ed750bd169	1778	/@} end of CMSIS_Core_NVICFunctions /
Anna Bridge	180:96ed750bd169	1779
Anna Bridge	180:96ed750bd169	1780	/* ########################## MPU functions #################################### */
Anna Bridge	180:96ed750bd169	1781
Anna Bridge	180:96ed750bd169	1782	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1783
Anna Bridge	180:96ed750bd169	1784	#include "mpu_armv7.h"
Anna Bridge	180:96ed750bd169	1785
Anna Bridge	180:96ed750bd169	1786	#endif
Anna Bridge	180:96ed750bd169	1787
Anna Bridge	180:96ed750bd169	1788	/* ########################## FPU functions #################################### */
Anna Bridge	180:96ed750bd169	1789	/**
Anna Bridge	180:96ed750bd169	1790	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	1791	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge	180:96ed750bd169	1792	\brief Function that provides FPU type.
Anna Bridge	180:96ed750bd169	1793	@{
Anna Bridge	180:96ed750bd169	1794	*/
Anna Bridge	180:96ed750bd169	1795
Anna Bridge	180:96ed750bd169	1796	/**
Anna Bridge	180:96ed750bd169	1797	\brief get FPU type
Anna Bridge	180:96ed750bd169	1798	\details returns the FPU type
Anna Bridge	180:96ed750bd169	1799	\returns
Anna Bridge	180:96ed750bd169	1800	- \b 0: No FPU
Anna Bridge	180:96ed750bd169	1801	- \b 1: Single precision FPU
Anna Bridge	180:96ed750bd169	1802	- \b 2: Double + Single precision FPU
Anna Bridge	180:96ed750bd169	1803	*/
Anna Bridge	180:96ed750bd169	1804	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge	180:96ed750bd169	1805	{
Anna Bridge	180:96ed750bd169	1806	return 0U; /* No FPU */
Anna Bridge	180:96ed750bd169	1807	}
Anna Bridge	180:96ed750bd169	1808
Anna Bridge	180:96ed750bd169	1809
Anna Bridge	180:96ed750bd169	1810	/@} end of CMSIS_Core_FpuFunctions /
Anna Bridge	180:96ed750bd169	1811
Anna Bridge	180:96ed750bd169	1812
Anna Bridge	180:96ed750bd169	1813
Anna Bridge	180:96ed750bd169	1814	/* ################################## SysTick function ############################################ */
Anna Bridge	180:96ed750bd169	1815	/**
Anna Bridge	180:96ed750bd169	1816	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	1817	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge	180:96ed750bd169	1818	\brief Functions that configure the System.
Anna Bridge	180:96ed750bd169	1819	@{
Anna Bridge	180:96ed750bd169	1820	*/
Anna Bridge	180:96ed750bd169	1821
Anna Bridge	180:96ed750bd169	1822	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge	180:96ed750bd169	1823
Anna Bridge	180:96ed750bd169	1824	/**
Anna Bridge	180:96ed750bd169	1825	\brief System Tick Configuration
Anna Bridge	180:96ed750bd169	1826	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge	180:96ed750bd169	1827	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	180:96ed750bd169	1828	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	180:96ed750bd169	1829	\return 0 Function succeeded.
Anna Bridge	180:96ed750bd169	1830	\return 1 Function failed.
Anna Bridge	180:96ed750bd169	1831	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	180:96ed750bd169	1832	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	180:96ed750bd169	1833	must contain a vendor-specific implementation of this function.
Anna Bridge	180:96ed750bd169	1834	*/
Anna Bridge	180:96ed750bd169	1835	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge	180:96ed750bd169	1836	{
Anna Bridge	180:96ed750bd169	1837	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge	180:96ed750bd169	1838	{
Anna Bridge	180:96ed750bd169	1839	return (1UL); /* Reload value impossible */
Anna Bridge	180:96ed750bd169	1840	}
Anna Bridge	180:96ed750bd169	1841
Anna Bridge	180:96ed750bd169	1842	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	180:96ed750bd169	1843	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	180:96ed750bd169	1844	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	180:96ed750bd169	1845	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	180:96ed750bd169	1846	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	180:96ed750bd169	1847	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	180:96ed750bd169	1848	return (0UL); /* Function successful */
Anna Bridge	180:96ed750bd169	1849	}
Anna Bridge	180:96ed750bd169	1850
Anna Bridge	180:96ed750bd169	1851	#endif
Anna Bridge	180:96ed750bd169	1852
Anna Bridge	180:96ed750bd169	1853	/@} end of CMSIS_Core_SysTickFunctions /
Anna Bridge	180:96ed750bd169	1854
Anna Bridge	180:96ed750bd169	1855
Anna Bridge	180:96ed750bd169	1856
Anna Bridge	180:96ed750bd169	1857	/* ##################################### Debug In/Output function ########################################### */
Anna Bridge	180:96ed750bd169	1858	/**
Anna Bridge	180:96ed750bd169	1859	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	1860	\defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge	180:96ed750bd169	1861	\brief Functions that access the ITM debug interface.
Anna Bridge	180:96ed750bd169	1862	@{
Anna Bridge	180:96ed750bd169	1863	*/
Anna Bridge	180:96ed750bd169	1864
Anna Bridge	180:96ed750bd169	1865	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Anna Bridge	180:96ed750bd169	1866	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Anna Bridge	180:96ed750bd169	1867
Anna Bridge	180:96ed750bd169	1868
Anna Bridge	180:96ed750bd169	1869	/**
Anna Bridge	180:96ed750bd169	1870	\brief ITM Send Character
Anna Bridge	180:96ed750bd169	1871	\details Transmits a character via the ITM channel 0, and
Anna Bridge	180:96ed750bd169	1872	\li Just returns when no debugger is connected that has booked the output.
Anna Bridge	180:96ed750bd169	1873	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge	180:96ed750bd169	1874	\param [in] ch Character to transmit.
Anna Bridge	180:96ed750bd169	1875	\returns Character to transmit.
Anna Bridge	180:96ed750bd169	1876	*/
Anna Bridge	180:96ed750bd169	1877	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge	180:96ed750bd169	1878	{
Anna Bridge	180:96ed750bd169	1879	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge	180:96ed750bd169	1880	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge	180:96ed750bd169	1881	{
Anna Bridge	180:96ed750bd169	1882	while (ITM->PORT[0U].u32 == 0UL)
Anna Bridge	180:96ed750bd169	1883	{
Anna Bridge	180:96ed750bd169	1884	__NOP();
Anna Bridge	180:96ed750bd169	1885	}
Anna Bridge	180:96ed750bd169	1886	ITM->PORT[0U].u8 = (uint8_t)ch;
Anna Bridge	180:96ed750bd169	1887	}
Anna Bridge	180:96ed750bd169	1888	return (ch);
Anna Bridge	180:96ed750bd169	1889	}
Anna Bridge	180:96ed750bd169	1890
Anna Bridge	180:96ed750bd169	1891
Anna Bridge	180:96ed750bd169	1892	/**
Anna Bridge	180:96ed750bd169	1893	\brief ITM Receive Character
Anna Bridge	180:96ed750bd169	1894	\details Inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge	180:96ed750bd169	1895	\return Received character.
Anna Bridge	180:96ed750bd169	1896	\return -1 No character pending.
Anna Bridge	180:96ed750bd169	1897	*/
Anna Bridge	180:96ed750bd169	1898	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
Anna Bridge	180:96ed750bd169	1899	{
Anna Bridge	180:96ed750bd169	1900	int32_t ch = -1; /* no character available */
Anna Bridge	180:96ed750bd169	1901
Anna Bridge	180:96ed750bd169	1902	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Anna Bridge	180:96ed750bd169	1903	{
Anna Bridge	180:96ed750bd169	1904	ch = ITM_RxBuffer;
Anna Bridge	180:96ed750bd169	1905	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge	180:96ed750bd169	1906	}
Anna Bridge	180:96ed750bd169	1907
Anna Bridge	180:96ed750bd169	1908	return (ch);
Anna Bridge	180:96ed750bd169	1909	}
Anna Bridge	180:96ed750bd169	1910
Anna Bridge	180:96ed750bd169	1911
Anna Bridge	180:96ed750bd169	1912	/**
Anna Bridge	180:96ed750bd169	1913	\brief ITM Check Character
Anna Bridge	180:96ed750bd169	1914	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge	180:96ed750bd169	1915	\return 0 No character available.
Anna Bridge	180:96ed750bd169	1916	\return 1 Character available.
Anna Bridge	180:96ed750bd169	1917	*/
Anna Bridge	180:96ed750bd169	1918	__STATIC_INLINE int32_t ITM_CheckChar (void)
Anna Bridge	180:96ed750bd169	1919	{
Anna Bridge	180:96ed750bd169	1920
Anna Bridge	180:96ed750bd169	1921	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Anna Bridge	180:96ed750bd169	1922	{
Anna Bridge	180:96ed750bd169	1923	return (0); /* no character available */
Anna Bridge	180:96ed750bd169	1924	}
Anna Bridge	180:96ed750bd169	1925	else
Anna Bridge	180:96ed750bd169	1926	{
Anna Bridge	180:96ed750bd169	1927	return (1); /* character available */
Anna Bridge	180:96ed750bd169	1928	}
Anna Bridge	180:96ed750bd169	1929	}
Anna Bridge	180:96ed750bd169	1930
Anna Bridge	180:96ed750bd169	1931	/@} end of CMSIS_core_DebugFunctions /
Anna Bridge	180:96ed750bd169	1932
Anna Bridge	180:96ed750bd169	1933
Anna Bridge	180:96ed750bd169	1934
Anna Bridge	180:96ed750bd169	1935
Anna Bridge	180:96ed750bd169	1936	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	1937	}
Anna Bridge	180:96ed750bd169	1938	#endif
Anna Bridge	180:96ed750bd169	1939
Anna Bridge	180:96ed750bd169	1940	#endif /* __CORE_CM3_H_DEPENDANT */
Anna Bridge	180:96ed750bd169	1941
Anna Bridge	180:96ed750bd169	1942	#endif /* __CMSIS_GENERIC */