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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_M/core_cm23.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /**************************************************************************//**
Anna Bridge 180:96ed750bd169 2 * @file core_cm23.h
Anna Bridge 180:96ed750bd169 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
AnnaBridge 188:bcfe06ba3d64 4 * @version V5.0.7
AnnaBridge 188:bcfe06ba3d64 5 * @date 22. June 2018
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 186:707f6e361f3e 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #if defined ( __ICCARM__ )
Anna Bridge 186:707f6e361f3e 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 186:707f6e361f3e 27 #elif defined (__clang__)
Anna Bridge 180:96ed750bd169 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 180:96ed750bd169 29 #endif
Anna Bridge 180:96ed750bd169 30
Anna Bridge 180:96ed750bd169 31 #ifndef __CORE_CM23_H_GENERIC
Anna Bridge 180:96ed750bd169 32 #define __CORE_CM23_H_GENERIC
Anna Bridge 180:96ed750bd169 33
Anna Bridge 180:96ed750bd169 34 #include <stdint.h>
Anna Bridge 180:96ed750bd169 35
Anna Bridge 180:96ed750bd169 36 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 37 extern "C" {
Anna Bridge 180:96ed750bd169 38 #endif
Anna Bridge 180:96ed750bd169 39
Anna Bridge 180:96ed750bd169 40 /**
Anna Bridge 180:96ed750bd169 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 180:96ed750bd169 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 180:96ed750bd169 43
Anna Bridge 180:96ed750bd169 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 180:96ed750bd169 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 180:96ed750bd169 46
Anna Bridge 180:96ed750bd169 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 180:96ed750bd169 48 Unions are used for effective representation of core registers.
Anna Bridge 180:96ed750bd169 49
Anna Bridge 180:96ed750bd169 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 180:96ed750bd169 51 Function-like macros are used to allow more efficient code.
Anna Bridge 180:96ed750bd169 52 */
Anna Bridge 180:96ed750bd169 53
Anna Bridge 180:96ed750bd169 54
Anna Bridge 180:96ed750bd169 55 /*******************************************************************************
Anna Bridge 180:96ed750bd169 56 * CMSIS definitions
Anna Bridge 180:96ed750bd169 57 ******************************************************************************/
Anna Bridge 180:96ed750bd169 58 /**
Anna Bridge 180:96ed750bd169 59 \ingroup Cortex_M23
Anna Bridge 180:96ed750bd169 60 @{
Anna Bridge 180:96ed750bd169 61 */
Anna Bridge 180:96ed750bd169 62
Anna Bridge 180:96ed750bd169 63 #include "cmsis_version.h"
Anna Bridge 180:96ed750bd169 64
Anna Bridge 180:96ed750bd169 65 /* CMSIS definitions */
Anna Bridge 180:96ed750bd169 66 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 180:96ed750bd169 67 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 180:96ed750bd169 68 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 180:96ed750bd169 69 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 180:96ed750bd169 70
AnnaBridge 188:bcfe06ba3d64 71 #define __CORTEX_M (23U) /*!< Cortex-M Core */
Anna Bridge 180:96ed750bd169 72
Anna Bridge 180:96ed750bd169 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 180:96ed750bd169 74 This core does not support an FPU at all
Anna Bridge 180:96ed750bd169 75 */
Anna Bridge 180:96ed750bd169 76 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 77
Anna Bridge 180:96ed750bd169 78 #if defined ( __CC_ARM )
Anna Bridge 180:96ed750bd169 79 #if defined __TARGET_FPU_VFP
Anna Bridge 180:96ed750bd169 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 81 #endif
Anna Bridge 180:96ed750bd169 82
Anna Bridge 180:96ed750bd169 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 189:f392fc9709a3 84 #if defined __ARM_FP
Anna Bridge 180:96ed750bd169 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 86 #endif
Anna Bridge 180:96ed750bd169 87
Anna Bridge 180:96ed750bd169 88 #elif defined ( __GNUC__ )
Anna Bridge 180:96ed750bd169 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 180:96ed750bd169 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 91 #endif
Anna Bridge 180:96ed750bd169 92
Anna Bridge 180:96ed750bd169 93 #elif defined ( __ICCARM__ )
Anna Bridge 180:96ed750bd169 94 #if defined __ARMVFP__
Anna Bridge 180:96ed750bd169 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 96 #endif
Anna Bridge 180:96ed750bd169 97
Anna Bridge 180:96ed750bd169 98 #elif defined ( __TI_ARM__ )
Anna Bridge 180:96ed750bd169 99 #if defined __TI_VFP_SUPPORT__
Anna Bridge 180:96ed750bd169 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 101 #endif
Anna Bridge 180:96ed750bd169 102
Anna Bridge 180:96ed750bd169 103 #elif defined ( __TASKING__ )
Anna Bridge 180:96ed750bd169 104 #if defined __FPU_VFP__
Anna Bridge 180:96ed750bd169 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 106 #endif
Anna Bridge 180:96ed750bd169 107
Anna Bridge 180:96ed750bd169 108 #elif defined ( __CSMC__ )
Anna Bridge 180:96ed750bd169 109 #if ( __CSMC__ & 0x400U)
Anna Bridge 180:96ed750bd169 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 111 #endif
Anna Bridge 180:96ed750bd169 112
Anna Bridge 180:96ed750bd169 113 #endif
Anna Bridge 180:96ed750bd169 114
Anna Bridge 180:96ed750bd169 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 180:96ed750bd169 116
Anna Bridge 180:96ed750bd169 117
Anna Bridge 180:96ed750bd169 118 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 119 }
Anna Bridge 180:96ed750bd169 120 #endif
Anna Bridge 180:96ed750bd169 121
Anna Bridge 180:96ed750bd169 122 #endif /* __CORE_CM23_H_GENERIC */
Anna Bridge 180:96ed750bd169 123
Anna Bridge 180:96ed750bd169 124 #ifndef __CMSIS_GENERIC
Anna Bridge 180:96ed750bd169 125
Anna Bridge 180:96ed750bd169 126 #ifndef __CORE_CM23_H_DEPENDANT
Anna Bridge 180:96ed750bd169 127 #define __CORE_CM23_H_DEPENDANT
Anna Bridge 180:96ed750bd169 128
Anna Bridge 180:96ed750bd169 129 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 130 extern "C" {
Anna Bridge 180:96ed750bd169 131 #endif
Anna Bridge 180:96ed750bd169 132
Anna Bridge 180:96ed750bd169 133 /* check device defines and use defaults */
Anna Bridge 180:96ed750bd169 134 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 180:96ed750bd169 135 #ifndef __CM23_REV
Anna Bridge 180:96ed750bd169 136 #define __CM23_REV 0x0000U
Anna Bridge 180:96ed750bd169 137 #warning "__CM23_REV not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 138 #endif
Anna Bridge 180:96ed750bd169 139
Anna Bridge 180:96ed750bd169 140 #ifndef __FPU_PRESENT
Anna Bridge 180:96ed750bd169 141 #define __FPU_PRESENT 0U
Anna Bridge 180:96ed750bd169 142 #warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 143 #endif
Anna Bridge 180:96ed750bd169 144
Anna Bridge 180:96ed750bd169 145 #ifndef __MPU_PRESENT
Anna Bridge 180:96ed750bd169 146 #define __MPU_PRESENT 0U
Anna Bridge 180:96ed750bd169 147 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 148 #endif
Anna Bridge 180:96ed750bd169 149
Anna Bridge 180:96ed750bd169 150 #ifndef __SAUREGION_PRESENT
Anna Bridge 180:96ed750bd169 151 #define __SAUREGION_PRESENT 0U
Anna Bridge 180:96ed750bd169 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 153 #endif
Anna Bridge 180:96ed750bd169 154
Anna Bridge 180:96ed750bd169 155 #ifndef __VTOR_PRESENT
Anna Bridge 180:96ed750bd169 156 #define __VTOR_PRESENT 0U
Anna Bridge 180:96ed750bd169 157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 158 #endif
Anna Bridge 180:96ed750bd169 159
Anna Bridge 180:96ed750bd169 160 #ifndef __NVIC_PRIO_BITS
Anna Bridge 180:96ed750bd169 161 #define __NVIC_PRIO_BITS 2U
Anna Bridge 180:96ed750bd169 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 163 #endif
Anna Bridge 180:96ed750bd169 164
Anna Bridge 180:96ed750bd169 165 #ifndef __Vendor_SysTickConfig
Anna Bridge 180:96ed750bd169 166 #define __Vendor_SysTickConfig 0U
Anna Bridge 180:96ed750bd169 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 168 #endif
Anna Bridge 180:96ed750bd169 169
Anna Bridge 180:96ed750bd169 170 #ifndef __ETM_PRESENT
Anna Bridge 180:96ed750bd169 171 #define __ETM_PRESENT 0U
Anna Bridge 180:96ed750bd169 172 #warning "__ETM_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 173 #endif
Anna Bridge 180:96ed750bd169 174
Anna Bridge 180:96ed750bd169 175 #ifndef __MTB_PRESENT
Anna Bridge 180:96ed750bd169 176 #define __MTB_PRESENT 0U
Anna Bridge 180:96ed750bd169 177 #warning "__MTB_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 178 #endif
Anna Bridge 180:96ed750bd169 179
Anna Bridge 180:96ed750bd169 180 #endif
Anna Bridge 180:96ed750bd169 181
Anna Bridge 180:96ed750bd169 182 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 180:96ed750bd169 183 /**
Anna Bridge 180:96ed750bd169 184 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 180:96ed750bd169 185
Anna Bridge 180:96ed750bd169 186 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 180:96ed750bd169 187 \li to specify the access to peripheral variables.
Anna Bridge 180:96ed750bd169 188 \li for automatic generation of peripheral register debug information.
Anna Bridge 180:96ed750bd169 189 */
Anna Bridge 180:96ed750bd169 190 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 191 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 192 #else
Anna Bridge 180:96ed750bd169 193 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 194 #endif
Anna Bridge 180:96ed750bd169 195 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 180:96ed750bd169 196 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 180:96ed750bd169 197
Anna Bridge 180:96ed750bd169 198 /* following defines should be used for structure members */
Anna Bridge 180:96ed750bd169 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 180:96ed750bd169 200 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 180:96ed750bd169 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 180:96ed750bd169 202
Anna Bridge 180:96ed750bd169 203 /*@} end of group Cortex_M23 */
Anna Bridge 180:96ed750bd169 204
Anna Bridge 180:96ed750bd169 205
Anna Bridge 180:96ed750bd169 206
Anna Bridge 180:96ed750bd169 207 /*******************************************************************************
Anna Bridge 180:96ed750bd169 208 * Register Abstraction
Anna Bridge 180:96ed750bd169 209 Core Register contain:
Anna Bridge 180:96ed750bd169 210 - Core Register
Anna Bridge 180:96ed750bd169 211 - Core NVIC Register
Anna Bridge 180:96ed750bd169 212 - Core SCB Register
Anna Bridge 180:96ed750bd169 213 - Core SysTick Register
Anna Bridge 180:96ed750bd169 214 - Core Debug Register
Anna Bridge 180:96ed750bd169 215 - Core MPU Register
Anna Bridge 180:96ed750bd169 216 - Core SAU Register
Anna Bridge 180:96ed750bd169 217 ******************************************************************************/
Anna Bridge 180:96ed750bd169 218 /**
Anna Bridge 180:96ed750bd169 219 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 180:96ed750bd169 220 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 180:96ed750bd169 221 */
Anna Bridge 180:96ed750bd169 222
Anna Bridge 180:96ed750bd169 223 /**
Anna Bridge 180:96ed750bd169 224 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 225 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 180:96ed750bd169 226 \brief Core Register type definitions.
Anna Bridge 180:96ed750bd169 227 @{
Anna Bridge 180:96ed750bd169 228 */
Anna Bridge 180:96ed750bd169 229
Anna Bridge 180:96ed750bd169 230 /**
Anna Bridge 180:96ed750bd169 231 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 180:96ed750bd169 232 */
Anna Bridge 180:96ed750bd169 233 typedef union
Anna Bridge 180:96ed750bd169 234 {
Anna Bridge 180:96ed750bd169 235 struct
Anna Bridge 180:96ed750bd169 236 {
Anna Bridge 180:96ed750bd169 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 180:96ed750bd169 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 242 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 243 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 244 } APSR_Type;
Anna Bridge 180:96ed750bd169 245
Anna Bridge 180:96ed750bd169 246 /* APSR Register Definitions */
Anna Bridge 180:96ed750bd169 247 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 180:96ed750bd169 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 180:96ed750bd169 249
Anna Bridge 180:96ed750bd169 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 180:96ed750bd169 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 180:96ed750bd169 252
Anna Bridge 180:96ed750bd169 253 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 180:96ed750bd169 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 180:96ed750bd169 255
Anna Bridge 180:96ed750bd169 256 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 180:96ed750bd169 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 180:96ed750bd169 258
Anna Bridge 180:96ed750bd169 259
Anna Bridge 180:96ed750bd169 260 /**
Anna Bridge 180:96ed750bd169 261 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 180:96ed750bd169 262 */
Anna Bridge 180:96ed750bd169 263 typedef union
Anna Bridge 180:96ed750bd169 264 {
Anna Bridge 180:96ed750bd169 265 struct
Anna Bridge 180:96ed750bd169 266 {
Anna Bridge 180:96ed750bd169 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 180:96ed750bd169 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 180:96ed750bd169 269 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 270 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 271 } IPSR_Type;
Anna Bridge 180:96ed750bd169 272
Anna Bridge 180:96ed750bd169 273 /* IPSR Register Definitions */
Anna Bridge 180:96ed750bd169 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 180:96ed750bd169 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 180:96ed750bd169 276
Anna Bridge 180:96ed750bd169 277
Anna Bridge 180:96ed750bd169 278 /**
Anna Bridge 180:96ed750bd169 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 180:96ed750bd169 280 */
Anna Bridge 180:96ed750bd169 281 typedef union
Anna Bridge 180:96ed750bd169 282 {
Anna Bridge 180:96ed750bd169 283 struct
Anna Bridge 180:96ed750bd169 284 {
Anna Bridge 180:96ed750bd169 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 180:96ed750bd169 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 180:96ed750bd169 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 180:96ed750bd169 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 180:96ed750bd169 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 293 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 294 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 295 } xPSR_Type;
Anna Bridge 180:96ed750bd169 296
Anna Bridge 180:96ed750bd169 297 /* xPSR Register Definitions */
Anna Bridge 180:96ed750bd169 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 180:96ed750bd169 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 180:96ed750bd169 300
Anna Bridge 180:96ed750bd169 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 180:96ed750bd169 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 180:96ed750bd169 303
Anna Bridge 180:96ed750bd169 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 180:96ed750bd169 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 180:96ed750bd169 306
Anna Bridge 180:96ed750bd169 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 180:96ed750bd169 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 180:96ed750bd169 309
Anna Bridge 180:96ed750bd169 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 180:96ed750bd169 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 180:96ed750bd169 312
Anna Bridge 180:96ed750bd169 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 180:96ed750bd169 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 180:96ed750bd169 315
Anna Bridge 180:96ed750bd169 316
Anna Bridge 180:96ed750bd169 317 /**
Anna Bridge 180:96ed750bd169 318 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 180:96ed750bd169 319 */
Anna Bridge 180:96ed750bd169 320 typedef union
Anna Bridge 180:96ed750bd169 321 {
Anna Bridge 180:96ed750bd169 322 struct
Anna Bridge 180:96ed750bd169 323 {
Anna Bridge 180:96ed750bd169 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 180:96ed750bd169 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
Anna Bridge 180:96ed750bd169 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 180:96ed750bd169 327 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 328 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 329 } CONTROL_Type;
Anna Bridge 180:96ed750bd169 330
Anna Bridge 180:96ed750bd169 331 /* CONTROL Register Definitions */
Anna Bridge 180:96ed750bd169 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 180:96ed750bd169 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 180:96ed750bd169 334
Anna Bridge 180:96ed750bd169 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 180:96ed750bd169 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 180:96ed750bd169 337
Anna Bridge 180:96ed750bd169 338 /*@} end of group CMSIS_CORE */
Anna Bridge 180:96ed750bd169 339
Anna Bridge 180:96ed750bd169 340
Anna Bridge 180:96ed750bd169 341 /**
Anna Bridge 180:96ed750bd169 342 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 180:96ed750bd169 344 \brief Type definitions for the NVIC Registers
Anna Bridge 180:96ed750bd169 345 @{
Anna Bridge 180:96ed750bd169 346 */
Anna Bridge 180:96ed750bd169 347
Anna Bridge 180:96ed750bd169 348 /**
Anna Bridge 180:96ed750bd169 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 180:96ed750bd169 350 */
Anna Bridge 180:96ed750bd169 351 typedef struct
Anna Bridge 180:96ed750bd169 352 {
Anna Bridge 180:96ed750bd169 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 180:96ed750bd169 354 uint32_t RESERVED0[16U];
Anna Bridge 180:96ed750bd169 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 180:96ed750bd169 356 uint32_t RSERVED1[16U];
Anna Bridge 180:96ed750bd169 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 180:96ed750bd169 358 uint32_t RESERVED2[16U];
Anna Bridge 180:96ed750bd169 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 180:96ed750bd169 360 uint32_t RESERVED3[16U];
Anna Bridge 180:96ed750bd169 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Anna Bridge 180:96ed750bd169 362 uint32_t RESERVED4[16U];
Anna Bridge 180:96ed750bd169 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
Anna Bridge 180:96ed750bd169 364 uint32_t RESERVED5[16U];
Anna Bridge 180:96ed750bd169 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 180:96ed750bd169 366 } NVIC_Type;
Anna Bridge 180:96ed750bd169 367
Anna Bridge 180:96ed750bd169 368 /*@} end of group CMSIS_NVIC */
Anna Bridge 180:96ed750bd169 369
Anna Bridge 180:96ed750bd169 370
Anna Bridge 180:96ed750bd169 371 /**
Anna Bridge 180:96ed750bd169 372 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 373 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 180:96ed750bd169 374 \brief Type definitions for the System Control Block Registers
Anna Bridge 180:96ed750bd169 375 @{
Anna Bridge 180:96ed750bd169 376 */
Anna Bridge 180:96ed750bd169 377
Anna Bridge 180:96ed750bd169 378 /**
Anna Bridge 180:96ed750bd169 379 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 180:96ed750bd169 380 */
Anna Bridge 180:96ed750bd169 381 typedef struct
Anna Bridge 180:96ed750bd169 382 {
Anna Bridge 180:96ed750bd169 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 180:96ed750bd169 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 180:96ed750bd169 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 180:96ed750bd169 387 #else
Anna Bridge 180:96ed750bd169 388 uint32_t RESERVED0;
Anna Bridge 180:96ed750bd169 389 #endif
Anna Bridge 180:96ed750bd169 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 180:96ed750bd169 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 180:96ed750bd169 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 180:96ed750bd169 393 uint32_t RESERVED1;
Anna Bridge 180:96ed750bd169 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 180:96ed750bd169 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 180:96ed750bd169 396 } SCB_Type;
Anna Bridge 180:96ed750bd169 397
Anna Bridge 180:96ed750bd169 398 /* SCB CPUID Register Definitions */
Anna Bridge 180:96ed750bd169 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 180:96ed750bd169 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 180:96ed750bd169 401
Anna Bridge 180:96ed750bd169 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 180:96ed750bd169 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 180:96ed750bd169 404
Anna Bridge 180:96ed750bd169 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 180:96ed750bd169 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 180:96ed750bd169 407
Anna Bridge 180:96ed750bd169 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 180:96ed750bd169 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 180:96ed750bd169 410
Anna Bridge 180:96ed750bd169 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 180:96ed750bd169 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 180:96ed750bd169 413
Anna Bridge 180:96ed750bd169 414 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 180:96ed750bd169 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
Anna Bridge 180:96ed750bd169 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
Anna Bridge 180:96ed750bd169 417
AnnaBridge 188:bcfe06ba3d64 418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
AnnaBridge 188:bcfe06ba3d64 419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
AnnaBridge 188:bcfe06ba3d64 420
Anna Bridge 180:96ed750bd169 421 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
Anna Bridge 180:96ed750bd169 422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
Anna Bridge 180:96ed750bd169 423
Anna Bridge 180:96ed750bd169 424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 180:96ed750bd169 425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 180:96ed750bd169 426
Anna Bridge 180:96ed750bd169 427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 180:96ed750bd169 428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 180:96ed750bd169 429
Anna Bridge 180:96ed750bd169 430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 180:96ed750bd169 431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 180:96ed750bd169 432
Anna Bridge 180:96ed750bd169 433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 180:96ed750bd169 434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 180:96ed750bd169 435
Anna Bridge 180:96ed750bd169 436 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
Anna Bridge 180:96ed750bd169 437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
Anna Bridge 180:96ed750bd169 438
Anna Bridge 180:96ed750bd169 439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 180:96ed750bd169 440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 180:96ed750bd169 441
Anna Bridge 180:96ed750bd169 442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 180:96ed750bd169 443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 180:96ed750bd169 444
Anna Bridge 180:96ed750bd169 445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 180:96ed750bd169 446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 180:96ed750bd169 447
Anna Bridge 180:96ed750bd169 448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
Anna Bridge 180:96ed750bd169 449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Anna Bridge 180:96ed750bd169 450
Anna Bridge 180:96ed750bd169 451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 180:96ed750bd169 452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 180:96ed750bd169 453
Anna Bridge 180:96ed750bd169 454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 455 /* SCB Vector Table Offset Register Definitions */
Anna Bridge 180:96ed750bd169 456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 180:96ed750bd169 457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 180:96ed750bd169 458 #endif
Anna Bridge 180:96ed750bd169 459
Anna Bridge 180:96ed750bd169 460 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 180:96ed750bd169 461 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 180:96ed750bd169 462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 180:96ed750bd169 463
Anna Bridge 180:96ed750bd169 464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 180:96ed750bd169 465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 180:96ed750bd169 466
Anna Bridge 180:96ed750bd169 467 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 180:96ed750bd169 468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 180:96ed750bd169 469
Anna Bridge 180:96ed750bd169 470 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
Anna Bridge 180:96ed750bd169 471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
Anna Bridge 180:96ed750bd169 472
Anna Bridge 180:96ed750bd169 473 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
Anna Bridge 180:96ed750bd169 474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
Anna Bridge 180:96ed750bd169 475
Anna Bridge 180:96ed750bd169 476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
Anna Bridge 180:96ed750bd169 477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
Anna Bridge 180:96ed750bd169 478
Anna Bridge 180:96ed750bd169 479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 180:96ed750bd169 480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 180:96ed750bd169 481
Anna Bridge 180:96ed750bd169 482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 180:96ed750bd169 483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 180:96ed750bd169 484
Anna Bridge 180:96ed750bd169 485 /* SCB System Control Register Definitions */
Anna Bridge 180:96ed750bd169 486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 180:96ed750bd169 487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 180:96ed750bd169 488
Anna Bridge 180:96ed750bd169 489 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
Anna Bridge 180:96ed750bd169 490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
Anna Bridge 180:96ed750bd169 491
Anna Bridge 180:96ed750bd169 492 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 180:96ed750bd169 493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 180:96ed750bd169 494
Anna Bridge 180:96ed750bd169 495 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 180:96ed750bd169 496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 180:96ed750bd169 497
Anna Bridge 180:96ed750bd169 498 /* SCB Configuration Control Register Definitions */
Anna Bridge 180:96ed750bd169 499 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
Anna Bridge 180:96ed750bd169 500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
Anna Bridge 180:96ed750bd169 501
Anna Bridge 180:96ed750bd169 502 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
Anna Bridge 180:96ed750bd169 503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
Anna Bridge 180:96ed750bd169 504
Anna Bridge 180:96ed750bd169 505 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
Anna Bridge 180:96ed750bd169 506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
Anna Bridge 180:96ed750bd169 507
Anna Bridge 180:96ed750bd169 508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
Anna Bridge 180:96ed750bd169 509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
Anna Bridge 180:96ed750bd169 510
Anna Bridge 180:96ed750bd169 511 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
Anna Bridge 180:96ed750bd169 512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Anna Bridge 180:96ed750bd169 513
Anna Bridge 180:96ed750bd169 514 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
Anna Bridge 180:96ed750bd169 515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Anna Bridge 180:96ed750bd169 516
Anna Bridge 180:96ed750bd169 517 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 180:96ed750bd169 518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 180:96ed750bd169 519
Anna Bridge 180:96ed750bd169 520 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
Anna Bridge 180:96ed750bd169 521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Anna Bridge 180:96ed750bd169 522
Anna Bridge 180:96ed750bd169 523 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 180:96ed750bd169 524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
Anna Bridge 180:96ed750bd169 525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
Anna Bridge 180:96ed750bd169 526
Anna Bridge 180:96ed750bd169 527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 180:96ed750bd169 528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 180:96ed750bd169 529
Anna Bridge 180:96ed750bd169 530 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
Anna Bridge 180:96ed750bd169 531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Anna Bridge 180:96ed750bd169 532
Anna Bridge 180:96ed750bd169 533 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
Anna Bridge 180:96ed750bd169 534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Anna Bridge 180:96ed750bd169 535
Anna Bridge 180:96ed750bd169 536 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
Anna Bridge 180:96ed750bd169 537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Anna Bridge 180:96ed750bd169 538
Anna Bridge 180:96ed750bd169 539 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
Anna Bridge 180:96ed750bd169 540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
Anna Bridge 180:96ed750bd169 541
Anna Bridge 180:96ed750bd169 542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
Anna Bridge 180:96ed750bd169 543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
Anna Bridge 180:96ed750bd169 544
Anna Bridge 180:96ed750bd169 545 /*@} end of group CMSIS_SCB */
Anna Bridge 180:96ed750bd169 546
Anna Bridge 180:96ed750bd169 547
Anna Bridge 180:96ed750bd169 548 /**
Anna Bridge 180:96ed750bd169 549 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 550 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 180:96ed750bd169 551 \brief Type definitions for the System Timer Registers.
Anna Bridge 180:96ed750bd169 552 @{
Anna Bridge 180:96ed750bd169 553 */
Anna Bridge 180:96ed750bd169 554
Anna Bridge 180:96ed750bd169 555 /**
Anna Bridge 180:96ed750bd169 556 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 180:96ed750bd169 557 */
Anna Bridge 180:96ed750bd169 558 typedef struct
Anna Bridge 180:96ed750bd169 559 {
Anna Bridge 180:96ed750bd169 560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 180:96ed750bd169 561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 180:96ed750bd169 562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 180:96ed750bd169 563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 180:96ed750bd169 564 } SysTick_Type;
Anna Bridge 180:96ed750bd169 565
Anna Bridge 180:96ed750bd169 566 /* SysTick Control / Status Register Definitions */
Anna Bridge 180:96ed750bd169 567 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 180:96ed750bd169 568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 180:96ed750bd169 569
Anna Bridge 180:96ed750bd169 570 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 180:96ed750bd169 571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 180:96ed750bd169 572
Anna Bridge 180:96ed750bd169 573 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 180:96ed750bd169 574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 180:96ed750bd169 575
Anna Bridge 180:96ed750bd169 576 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 578
Anna Bridge 180:96ed750bd169 579 /* SysTick Reload Register Definitions */
Anna Bridge 180:96ed750bd169 580 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 180:96ed750bd169 581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 180:96ed750bd169 582
Anna Bridge 180:96ed750bd169 583 /* SysTick Current Register Definitions */
Anna Bridge 180:96ed750bd169 584 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 180:96ed750bd169 585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 180:96ed750bd169 586
Anna Bridge 180:96ed750bd169 587 /* SysTick Calibration Register Definitions */
Anna Bridge 180:96ed750bd169 588 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 180:96ed750bd169 589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 180:96ed750bd169 590
Anna Bridge 180:96ed750bd169 591 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 180:96ed750bd169 592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 180:96ed750bd169 593
Anna Bridge 180:96ed750bd169 594 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 180:96ed750bd169 595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 180:96ed750bd169 596
Anna Bridge 180:96ed750bd169 597 /*@} end of group CMSIS_SysTick */
Anna Bridge 180:96ed750bd169 598
Anna Bridge 180:96ed750bd169 599
Anna Bridge 180:96ed750bd169 600 /**
Anna Bridge 180:96ed750bd169 601 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge 180:96ed750bd169 603 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge 180:96ed750bd169 604 @{
Anna Bridge 180:96ed750bd169 605 */
Anna Bridge 180:96ed750bd169 606
Anna Bridge 180:96ed750bd169 607 /**
Anna Bridge 180:96ed750bd169 608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge 180:96ed750bd169 609 */
Anna Bridge 180:96ed750bd169 610 typedef struct
Anna Bridge 180:96ed750bd169 611 {
Anna Bridge 180:96ed750bd169 612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Anna Bridge 180:96ed750bd169 613 uint32_t RESERVED0[6U];
Anna Bridge 180:96ed750bd169 614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Anna Bridge 180:96ed750bd169 615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Anna Bridge 180:96ed750bd169 616 uint32_t RESERVED1[1U];
Anna Bridge 180:96ed750bd169 617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Anna Bridge 180:96ed750bd169 618 uint32_t RESERVED2[1U];
Anna Bridge 180:96ed750bd169 619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Anna Bridge 180:96ed750bd169 620 uint32_t RESERVED3[1U];
Anna Bridge 180:96ed750bd169 621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Anna Bridge 180:96ed750bd169 622 uint32_t RESERVED4[1U];
Anna Bridge 180:96ed750bd169 623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Anna Bridge 180:96ed750bd169 624 uint32_t RESERVED5[1U];
Anna Bridge 180:96ed750bd169 625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Anna Bridge 180:96ed750bd169 626 uint32_t RESERVED6[1U];
Anna Bridge 180:96ed750bd169 627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Anna Bridge 180:96ed750bd169 628 uint32_t RESERVED7[1U];
Anna Bridge 180:96ed750bd169 629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Anna Bridge 180:96ed750bd169 630 uint32_t RESERVED8[1U];
Anna Bridge 180:96ed750bd169 631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
Anna Bridge 180:96ed750bd169 632 uint32_t RESERVED9[1U];
Anna Bridge 180:96ed750bd169 633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
Anna Bridge 180:96ed750bd169 634 uint32_t RESERVED10[1U];
Anna Bridge 180:96ed750bd169 635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
Anna Bridge 180:96ed750bd169 636 uint32_t RESERVED11[1U];
Anna Bridge 180:96ed750bd169 637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
Anna Bridge 180:96ed750bd169 638 uint32_t RESERVED12[1U];
Anna Bridge 180:96ed750bd169 639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
Anna Bridge 180:96ed750bd169 640 uint32_t RESERVED13[1U];
Anna Bridge 180:96ed750bd169 641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
Anna Bridge 180:96ed750bd169 642 uint32_t RESERVED14[1U];
Anna Bridge 180:96ed750bd169 643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
Anna Bridge 180:96ed750bd169 644 uint32_t RESERVED15[1U];
Anna Bridge 180:96ed750bd169 645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
Anna Bridge 180:96ed750bd169 646 uint32_t RESERVED16[1U];
Anna Bridge 180:96ed750bd169 647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
Anna Bridge 180:96ed750bd169 648 uint32_t RESERVED17[1U];
Anna Bridge 180:96ed750bd169 649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
Anna Bridge 180:96ed750bd169 650 uint32_t RESERVED18[1U];
Anna Bridge 180:96ed750bd169 651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
Anna Bridge 180:96ed750bd169 652 uint32_t RESERVED19[1U];
Anna Bridge 180:96ed750bd169 653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
Anna Bridge 180:96ed750bd169 654 uint32_t RESERVED20[1U];
Anna Bridge 180:96ed750bd169 655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
Anna Bridge 180:96ed750bd169 656 uint32_t RESERVED21[1U];
Anna Bridge 180:96ed750bd169 657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
Anna Bridge 180:96ed750bd169 658 uint32_t RESERVED22[1U];
Anna Bridge 180:96ed750bd169 659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
Anna Bridge 180:96ed750bd169 660 uint32_t RESERVED23[1U];
Anna Bridge 180:96ed750bd169 661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
Anna Bridge 180:96ed750bd169 662 uint32_t RESERVED24[1U];
Anna Bridge 180:96ed750bd169 663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
Anna Bridge 180:96ed750bd169 664 uint32_t RESERVED25[1U];
Anna Bridge 180:96ed750bd169 665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
Anna Bridge 180:96ed750bd169 666 uint32_t RESERVED26[1U];
Anna Bridge 180:96ed750bd169 667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
Anna Bridge 180:96ed750bd169 668 uint32_t RESERVED27[1U];
Anna Bridge 180:96ed750bd169 669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
Anna Bridge 180:96ed750bd169 670 uint32_t RESERVED28[1U];
Anna Bridge 180:96ed750bd169 671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
Anna Bridge 180:96ed750bd169 672 uint32_t RESERVED29[1U];
Anna Bridge 180:96ed750bd169 673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
Anna Bridge 180:96ed750bd169 674 uint32_t RESERVED30[1U];
Anna Bridge 180:96ed750bd169 675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
Anna Bridge 180:96ed750bd169 676 uint32_t RESERVED31[1U];
Anna Bridge 180:96ed750bd169 677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
Anna Bridge 180:96ed750bd169 678 } DWT_Type;
Anna Bridge 180:96ed750bd169 679
Anna Bridge 180:96ed750bd169 680 /* DWT Control Register Definitions */
Anna Bridge 180:96ed750bd169 681 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
Anna Bridge 180:96ed750bd169 682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Anna Bridge 180:96ed750bd169 683
Anna Bridge 180:96ed750bd169 684 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
Anna Bridge 180:96ed750bd169 685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Anna Bridge 180:96ed750bd169 686
Anna Bridge 180:96ed750bd169 687 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
Anna Bridge 180:96ed750bd169 688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Anna Bridge 180:96ed750bd169 689
Anna Bridge 180:96ed750bd169 690 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
Anna Bridge 180:96ed750bd169 691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Anna Bridge 180:96ed750bd169 692
Anna Bridge 180:96ed750bd169 693 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
Anna Bridge 180:96ed750bd169 694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Anna Bridge 180:96ed750bd169 695
Anna Bridge 180:96ed750bd169 696 /* DWT Comparator Function Register Definitions */
Anna Bridge 180:96ed750bd169 697 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
Anna Bridge 180:96ed750bd169 698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
Anna Bridge 180:96ed750bd169 699
Anna Bridge 180:96ed750bd169 700 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
Anna Bridge 180:96ed750bd169 701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Anna Bridge 180:96ed750bd169 702
Anna Bridge 180:96ed750bd169 703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
Anna Bridge 180:96ed750bd169 704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Anna Bridge 180:96ed750bd169 705
Anna Bridge 180:96ed750bd169 706 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
Anna Bridge 180:96ed750bd169 707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
Anna Bridge 180:96ed750bd169 708
Anna Bridge 180:96ed750bd169 709 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
Anna Bridge 180:96ed750bd169 710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
Anna Bridge 180:96ed750bd169 711
Anna Bridge 180:96ed750bd169 712 /*@}*/ /* end of group CMSIS_DWT */
Anna Bridge 180:96ed750bd169 713
Anna Bridge 180:96ed750bd169 714
Anna Bridge 180:96ed750bd169 715 /**
Anna Bridge 180:96ed750bd169 716 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 717 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge 180:96ed750bd169 718 \brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge 180:96ed750bd169 719 @{
Anna Bridge 180:96ed750bd169 720 */
Anna Bridge 180:96ed750bd169 721
Anna Bridge 180:96ed750bd169 722 /**
Anna Bridge 180:96ed750bd169 723 \brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge 180:96ed750bd169 724 */
Anna Bridge 180:96ed750bd169 725 typedef struct
Anna Bridge 180:96ed750bd169 726 {
AnnaBridge 188:bcfe06ba3d64 727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Anna Bridge 180:96ed750bd169 728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Anna Bridge 180:96ed750bd169 729 uint32_t RESERVED0[2U];
Anna Bridge 180:96ed750bd169 730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Anna Bridge 180:96ed750bd169 731 uint32_t RESERVED1[55U];
Anna Bridge 180:96ed750bd169 732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Anna Bridge 180:96ed750bd169 733 uint32_t RESERVED2[131U];
Anna Bridge 180:96ed750bd169 734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Anna Bridge 180:96ed750bd169 735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 188:bcfe06ba3d64 736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
Anna Bridge 180:96ed750bd169 737 uint32_t RESERVED3[759U];
AnnaBridge 188:bcfe06ba3d64 738 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
AnnaBridge 188:bcfe06ba3d64 739 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
AnnaBridge 188:bcfe06ba3d64 740 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
Anna Bridge 180:96ed750bd169 741 uint32_t RESERVED4[1U];
AnnaBridge 188:bcfe06ba3d64 742 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
AnnaBridge 188:bcfe06ba3d64 743 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
Anna Bridge 180:96ed750bd169 744 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Anna Bridge 180:96ed750bd169 745 uint32_t RESERVED5[39U];
Anna Bridge 180:96ed750bd169 746 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Anna Bridge 180:96ed750bd169 747 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Anna Bridge 180:96ed750bd169 748 uint32_t RESERVED7[8U];
AnnaBridge 188:bcfe06ba3d64 749 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
AnnaBridge 188:bcfe06ba3d64 750 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
Anna Bridge 180:96ed750bd169 751 } TPI_Type;
Anna Bridge 180:96ed750bd169 752
Anna Bridge 180:96ed750bd169 753 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 188:bcfe06ba3d64 754 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 188:bcfe06ba3d64 755 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Anna Bridge 180:96ed750bd169 756
Anna Bridge 180:96ed750bd169 757 /* TPI Selected Pin Protocol Register Definitions */
Anna Bridge 180:96ed750bd169 758 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
Anna Bridge 180:96ed750bd169 759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Anna Bridge 180:96ed750bd169 760
Anna Bridge 180:96ed750bd169 761 /* TPI Formatter and Flush Status Register Definitions */
Anna Bridge 180:96ed750bd169 762 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
Anna Bridge 180:96ed750bd169 763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Anna Bridge 180:96ed750bd169 764
Anna Bridge 180:96ed750bd169 765 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
Anna Bridge 180:96ed750bd169 766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Anna Bridge 180:96ed750bd169 767
Anna Bridge 180:96ed750bd169 768 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
Anna Bridge 180:96ed750bd169 769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Anna Bridge 180:96ed750bd169 770
Anna Bridge 180:96ed750bd169 771 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
Anna Bridge 180:96ed750bd169 772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Anna Bridge 180:96ed750bd169 773
Anna Bridge 180:96ed750bd169 774 /* TPI Formatter and Flush Control Register Definitions */
Anna Bridge 180:96ed750bd169 775 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
Anna Bridge 180:96ed750bd169 776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Anna Bridge 180:96ed750bd169 777
AnnaBridge 188:bcfe06ba3d64 778 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
AnnaBridge 188:bcfe06ba3d64 779 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
AnnaBridge 188:bcfe06ba3d64 780
Anna Bridge 180:96ed750bd169 781 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
Anna Bridge 180:96ed750bd169 782 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Anna Bridge 180:96ed750bd169 783
Anna Bridge 180:96ed750bd169 784 /* TPI TRIGGER Register Definitions */
Anna Bridge 180:96ed750bd169 785 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
Anna Bridge 180:96ed750bd169 786 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Anna Bridge 180:96ed750bd169 787
AnnaBridge 188:bcfe06ba3d64 788 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
AnnaBridge 188:bcfe06ba3d64 789 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
AnnaBridge 188:bcfe06ba3d64 790 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
AnnaBridge 188:bcfe06ba3d64 791
AnnaBridge 188:bcfe06ba3d64 792 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
AnnaBridge 188:bcfe06ba3d64 793 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
Anna Bridge 180:96ed750bd169 794
AnnaBridge 188:bcfe06ba3d64 795 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
AnnaBridge 188:bcfe06ba3d64 796 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
Anna Bridge 180:96ed750bd169 797
AnnaBridge 188:bcfe06ba3d64 798 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
AnnaBridge 188:bcfe06ba3d64 799 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
Anna Bridge 180:96ed750bd169 800
AnnaBridge 188:bcfe06ba3d64 801 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
AnnaBridge 188:bcfe06ba3d64 802 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
Anna Bridge 180:96ed750bd169 803
AnnaBridge 188:bcfe06ba3d64 804 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
AnnaBridge 188:bcfe06ba3d64 805 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
Anna Bridge 180:96ed750bd169 806
AnnaBridge 188:bcfe06ba3d64 807 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
AnnaBridge 188:bcfe06ba3d64 808 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
Anna Bridge 180:96ed750bd169 809
AnnaBridge 188:bcfe06ba3d64 810 /* TPI Integration Test ATB Control Register 2 Register Definitions */
AnnaBridge 188:bcfe06ba3d64 811 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
AnnaBridge 188:bcfe06ba3d64 812 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
Anna Bridge 180:96ed750bd169 813
AnnaBridge 188:bcfe06ba3d64 814 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
AnnaBridge 188:bcfe06ba3d64 815 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
AnnaBridge 188:bcfe06ba3d64 816
AnnaBridge 188:bcfe06ba3d64 817 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
AnnaBridge 188:bcfe06ba3d64 818 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
AnnaBridge 188:bcfe06ba3d64 819
AnnaBridge 188:bcfe06ba3d64 820 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
AnnaBridge 188:bcfe06ba3d64 821 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
Anna Bridge 180:96ed750bd169 822
AnnaBridge 188:bcfe06ba3d64 823 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
AnnaBridge 188:bcfe06ba3d64 824 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
AnnaBridge 188:bcfe06ba3d64 825 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
AnnaBridge 188:bcfe06ba3d64 826
AnnaBridge 188:bcfe06ba3d64 827 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
AnnaBridge 188:bcfe06ba3d64 828 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
Anna Bridge 180:96ed750bd169 829
AnnaBridge 188:bcfe06ba3d64 830 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
AnnaBridge 188:bcfe06ba3d64 831 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
Anna Bridge 180:96ed750bd169 832
AnnaBridge 188:bcfe06ba3d64 833 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
AnnaBridge 188:bcfe06ba3d64 834 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
Anna Bridge 180:96ed750bd169 835
AnnaBridge 188:bcfe06ba3d64 836 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
AnnaBridge 188:bcfe06ba3d64 837 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
Anna Bridge 180:96ed750bd169 838
AnnaBridge 188:bcfe06ba3d64 839 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
AnnaBridge 188:bcfe06ba3d64 840 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
Anna Bridge 180:96ed750bd169 841
AnnaBridge 188:bcfe06ba3d64 842 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
AnnaBridge 188:bcfe06ba3d64 843 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
Anna Bridge 180:96ed750bd169 844
AnnaBridge 188:bcfe06ba3d64 845 /* TPI Integration Test ATB Control Register 0 Definitions */
AnnaBridge 188:bcfe06ba3d64 846 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
AnnaBridge 188:bcfe06ba3d64 847 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
Anna Bridge 180:96ed750bd169 848
AnnaBridge 188:bcfe06ba3d64 849 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
AnnaBridge 188:bcfe06ba3d64 850 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
AnnaBridge 188:bcfe06ba3d64 851
AnnaBridge 188:bcfe06ba3d64 852 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
AnnaBridge 188:bcfe06ba3d64 853 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
AnnaBridge 188:bcfe06ba3d64 854
AnnaBridge 188:bcfe06ba3d64 855 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
AnnaBridge 188:bcfe06ba3d64 856 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
Anna Bridge 180:96ed750bd169 857
Anna Bridge 180:96ed750bd169 858 /* TPI Integration Mode Control Register Definitions */
Anna Bridge 180:96ed750bd169 859 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 188:bcfe06ba3d64 860 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Anna Bridge 180:96ed750bd169 861
Anna Bridge 180:96ed750bd169 862 /* TPI DEVID Register Definitions */
Anna Bridge 180:96ed750bd169 863 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
Anna Bridge 180:96ed750bd169 864 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Anna Bridge 180:96ed750bd169 865
Anna Bridge 180:96ed750bd169 866 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
Anna Bridge 180:96ed750bd169 867 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Anna Bridge 180:96ed750bd169 868
Anna Bridge 180:96ed750bd169 869 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
Anna Bridge 180:96ed750bd169 870 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Anna Bridge 180:96ed750bd169 871
AnnaBridge 188:bcfe06ba3d64 872 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
AnnaBridge 188:bcfe06ba3d64 873 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
Anna Bridge 180:96ed750bd169 874
Anna Bridge 180:96ed750bd169 875 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 188:bcfe06ba3d64 876 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Anna Bridge 180:96ed750bd169 877
Anna Bridge 180:96ed750bd169 878 /* TPI DEVTYPE Register Definitions */
AnnaBridge 188:bcfe06ba3d64 879 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 188:bcfe06ba3d64 880 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Anna Bridge 180:96ed750bd169 881
AnnaBridge 188:bcfe06ba3d64 882 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 188:bcfe06ba3d64 883 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Anna Bridge 180:96ed750bd169 884
Anna Bridge 180:96ed750bd169 885 /*@}*/ /* end of group CMSIS_TPI */
Anna Bridge 180:96ed750bd169 886
Anna Bridge 180:96ed750bd169 887
Anna Bridge 180:96ed750bd169 888 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 889 /**
Anna Bridge 180:96ed750bd169 890 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 891 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 180:96ed750bd169 892 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 180:96ed750bd169 893 @{
Anna Bridge 180:96ed750bd169 894 */
Anna Bridge 180:96ed750bd169 895
Anna Bridge 180:96ed750bd169 896 /**
Anna Bridge 180:96ed750bd169 897 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 180:96ed750bd169 898 */
Anna Bridge 180:96ed750bd169 899 typedef struct
Anna Bridge 180:96ed750bd169 900 {
Anna Bridge 180:96ed750bd169 901 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 180:96ed750bd169 902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 180:96ed750bd169 903 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
Anna Bridge 180:96ed750bd169 904 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 180:96ed750bd169 905 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
Anna Bridge 180:96ed750bd169 906 uint32_t RESERVED0[7U];
Anna Bridge 180:96ed750bd169 907 union {
Anna Bridge 180:96ed750bd169 908 __IOM uint32_t MAIR[2];
Anna Bridge 180:96ed750bd169 909 struct {
Anna Bridge 180:96ed750bd169 910 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
Anna Bridge 180:96ed750bd169 911 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
Anna Bridge 180:96ed750bd169 912 };
Anna Bridge 180:96ed750bd169 913 };
Anna Bridge 180:96ed750bd169 914 } MPU_Type;
Anna Bridge 180:96ed750bd169 915
Anna Bridge 180:96ed750bd169 916 #define MPU_TYPE_RALIASES 1U
Anna Bridge 180:96ed750bd169 917
Anna Bridge 180:96ed750bd169 918 /* MPU Type Register Definitions */
Anna Bridge 180:96ed750bd169 919 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 180:96ed750bd169 920 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 180:96ed750bd169 921
Anna Bridge 180:96ed750bd169 922 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 180:96ed750bd169 923 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 180:96ed750bd169 924
Anna Bridge 180:96ed750bd169 925 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 180:96ed750bd169 926 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 180:96ed750bd169 927
Anna Bridge 180:96ed750bd169 928 /* MPU Control Register Definitions */
Anna Bridge 180:96ed750bd169 929 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 180:96ed750bd169 930 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 180:96ed750bd169 931
Anna Bridge 180:96ed750bd169 932 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 180:96ed750bd169 933 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 180:96ed750bd169 934
Anna Bridge 180:96ed750bd169 935 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 936 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 937
Anna Bridge 180:96ed750bd169 938 /* MPU Region Number Register Definitions */
Anna Bridge 180:96ed750bd169 939 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 180:96ed750bd169 940 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 180:96ed750bd169 941
Anna Bridge 180:96ed750bd169 942 /* MPU Region Base Address Register Definitions */
Anna Bridge 180:96ed750bd169 943 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
Anna Bridge 180:96ed750bd169 944 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
Anna Bridge 180:96ed750bd169 945
Anna Bridge 180:96ed750bd169 946 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
Anna Bridge 180:96ed750bd169 947 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
Anna Bridge 180:96ed750bd169 948
Anna Bridge 180:96ed750bd169 949 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
Anna Bridge 180:96ed750bd169 950 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
Anna Bridge 180:96ed750bd169 951
Anna Bridge 180:96ed750bd169 952 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
Anna Bridge 180:96ed750bd169 953 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
Anna Bridge 180:96ed750bd169 954
Anna Bridge 180:96ed750bd169 955 /* MPU Region Limit Address Register Definitions */
Anna Bridge 180:96ed750bd169 956 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
Anna Bridge 180:96ed750bd169 957 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
Anna Bridge 180:96ed750bd169 958
Anna Bridge 180:96ed750bd169 959 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
Anna Bridge 180:96ed750bd169 960 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
Anna Bridge 180:96ed750bd169 961
Anna Bridge 180:96ed750bd169 962 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
Anna Bridge 180:96ed750bd169 963 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
Anna Bridge 180:96ed750bd169 964
Anna Bridge 180:96ed750bd169 965 /* MPU Memory Attribute Indirection Register 0 Definitions */
Anna Bridge 180:96ed750bd169 966 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
Anna Bridge 180:96ed750bd169 967 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
Anna Bridge 180:96ed750bd169 968
Anna Bridge 180:96ed750bd169 969 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
Anna Bridge 180:96ed750bd169 970 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
Anna Bridge 180:96ed750bd169 971
Anna Bridge 180:96ed750bd169 972 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
Anna Bridge 180:96ed750bd169 973 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
Anna Bridge 180:96ed750bd169 974
Anna Bridge 180:96ed750bd169 975 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
Anna Bridge 180:96ed750bd169 976 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
Anna Bridge 180:96ed750bd169 977
Anna Bridge 180:96ed750bd169 978 /* MPU Memory Attribute Indirection Register 1 Definitions */
Anna Bridge 180:96ed750bd169 979 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
Anna Bridge 180:96ed750bd169 980 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
Anna Bridge 180:96ed750bd169 981
Anna Bridge 180:96ed750bd169 982 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
Anna Bridge 180:96ed750bd169 983 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
Anna Bridge 180:96ed750bd169 984
Anna Bridge 180:96ed750bd169 985 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
Anna Bridge 180:96ed750bd169 986 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
Anna Bridge 180:96ed750bd169 987
Anna Bridge 180:96ed750bd169 988 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
Anna Bridge 180:96ed750bd169 989 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
Anna Bridge 180:96ed750bd169 990
Anna Bridge 180:96ed750bd169 991 /*@} end of group CMSIS_MPU */
Anna Bridge 180:96ed750bd169 992 #endif
Anna Bridge 180:96ed750bd169 993
Anna Bridge 180:96ed750bd169 994
Anna Bridge 180:96ed750bd169 995 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 996 /**
Anna Bridge 180:96ed750bd169 997 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 998 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
Anna Bridge 180:96ed750bd169 999 \brief Type definitions for the Security Attribution Unit (SAU)
Anna Bridge 180:96ed750bd169 1000 @{
Anna Bridge 180:96ed750bd169 1001 */
Anna Bridge 180:96ed750bd169 1002
Anna Bridge 180:96ed750bd169 1003 /**
Anna Bridge 180:96ed750bd169 1004 \brief Structure type to access the Security Attribution Unit (SAU).
Anna Bridge 180:96ed750bd169 1005 */
Anna Bridge 180:96ed750bd169 1006 typedef struct
Anna Bridge 180:96ed750bd169 1007 {
Anna Bridge 180:96ed750bd169 1008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
Anna Bridge 180:96ed750bd169 1009 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
Anna Bridge 180:96ed750bd169 1010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1011 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
Anna Bridge 180:96ed750bd169 1012 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
Anna Bridge 180:96ed750bd169 1013 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
Anna Bridge 180:96ed750bd169 1014 #endif
Anna Bridge 180:96ed750bd169 1015 } SAU_Type;
Anna Bridge 180:96ed750bd169 1016
Anna Bridge 180:96ed750bd169 1017 /* SAU Control Register Definitions */
Anna Bridge 180:96ed750bd169 1018 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
Anna Bridge 180:96ed750bd169 1019 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
Anna Bridge 180:96ed750bd169 1020
Anna Bridge 180:96ed750bd169 1021 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 1022 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 1023
Anna Bridge 180:96ed750bd169 1024 /* SAU Type Register Definitions */
Anna Bridge 180:96ed750bd169 1025 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
Anna Bridge 180:96ed750bd169 1026 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
Anna Bridge 180:96ed750bd169 1027
Anna Bridge 180:96ed750bd169 1028 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1029 /* SAU Region Number Register Definitions */
Anna Bridge 180:96ed750bd169 1030 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
Anna Bridge 180:96ed750bd169 1031 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
Anna Bridge 180:96ed750bd169 1032
Anna Bridge 180:96ed750bd169 1033 /* SAU Region Base Address Register Definitions */
Anna Bridge 180:96ed750bd169 1034 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
Anna Bridge 180:96ed750bd169 1035 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
Anna Bridge 180:96ed750bd169 1036
Anna Bridge 180:96ed750bd169 1037 /* SAU Region Limit Address Register Definitions */
Anna Bridge 180:96ed750bd169 1038 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
Anna Bridge 180:96ed750bd169 1039 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
Anna Bridge 180:96ed750bd169 1040
Anna Bridge 180:96ed750bd169 1041 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
Anna Bridge 180:96ed750bd169 1042 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
Anna Bridge 180:96ed750bd169 1043
Anna Bridge 180:96ed750bd169 1044 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
Anna Bridge 180:96ed750bd169 1045 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
Anna Bridge 180:96ed750bd169 1046
Anna Bridge 180:96ed750bd169 1047 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Anna Bridge 180:96ed750bd169 1048
Anna Bridge 180:96ed750bd169 1049 /*@} end of group CMSIS_SAU */
Anna Bridge 180:96ed750bd169 1050 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 180:96ed750bd169 1051
Anna Bridge 180:96ed750bd169 1052
Anna Bridge 180:96ed750bd169 1053 /**
Anna Bridge 180:96ed750bd169 1054 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 1055 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 180:96ed750bd169 1056 \brief Type definitions for the Core Debug Registers
Anna Bridge 180:96ed750bd169 1057 @{
Anna Bridge 180:96ed750bd169 1058 */
Anna Bridge 180:96ed750bd169 1059
Anna Bridge 180:96ed750bd169 1060 /**
Anna Bridge 180:96ed750bd169 1061 \brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge 180:96ed750bd169 1062 */
Anna Bridge 180:96ed750bd169 1063 typedef struct
Anna Bridge 180:96ed750bd169 1064 {
Anna Bridge 180:96ed750bd169 1065 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Anna Bridge 180:96ed750bd169 1066 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Anna Bridge 180:96ed750bd169 1067 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Anna Bridge 180:96ed750bd169 1068 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Anna Bridge 180:96ed750bd169 1069 uint32_t RESERVED4[1U];
Anna Bridge 180:96ed750bd169 1070 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
Anna Bridge 180:96ed750bd169 1071 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
Anna Bridge 180:96ed750bd169 1072 } CoreDebug_Type;
Anna Bridge 180:96ed750bd169 1073
Anna Bridge 180:96ed750bd169 1074 /* Debug Halting Control and Status Register Definitions */
Anna Bridge 180:96ed750bd169 1075 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
Anna Bridge 180:96ed750bd169 1076 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Anna Bridge 180:96ed750bd169 1077
Anna Bridge 180:96ed750bd169 1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
Anna Bridge 180:96ed750bd169 1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
Anna Bridge 180:96ed750bd169 1080
Anna Bridge 180:96ed750bd169 1081 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
Anna Bridge 180:96ed750bd169 1082 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Anna Bridge 180:96ed750bd169 1083
Anna Bridge 180:96ed750bd169 1084 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Anna Bridge 180:96ed750bd169 1085 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Anna Bridge 180:96ed750bd169 1086
Anna Bridge 180:96ed750bd169 1087 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
Anna Bridge 180:96ed750bd169 1088 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Anna Bridge 180:96ed750bd169 1089
Anna Bridge 180:96ed750bd169 1090 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
Anna Bridge 180:96ed750bd169 1091 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Anna Bridge 180:96ed750bd169 1092
Anna Bridge 180:96ed750bd169 1093 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
Anna Bridge 180:96ed750bd169 1094 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Anna Bridge 180:96ed750bd169 1095
Anna Bridge 180:96ed750bd169 1096 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
Anna Bridge 180:96ed750bd169 1097 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Anna Bridge 180:96ed750bd169 1098
Anna Bridge 180:96ed750bd169 1099 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
Anna Bridge 180:96ed750bd169 1100 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Anna Bridge 180:96ed750bd169 1101
Anna Bridge 180:96ed750bd169 1102 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
Anna Bridge 180:96ed750bd169 1103 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Anna Bridge 180:96ed750bd169 1104
Anna Bridge 180:96ed750bd169 1105 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
Anna Bridge 180:96ed750bd169 1106 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Anna Bridge 180:96ed750bd169 1107
Anna Bridge 180:96ed750bd169 1108 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Anna Bridge 180:96ed750bd169 1109 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Anna Bridge 180:96ed750bd169 1110
Anna Bridge 180:96ed750bd169 1111 /* Debug Core Register Selector Register Definitions */
Anna Bridge 180:96ed750bd169 1112 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
Anna Bridge 180:96ed750bd169 1113 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Anna Bridge 180:96ed750bd169 1114
Anna Bridge 180:96ed750bd169 1115 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
Anna Bridge 180:96ed750bd169 1116 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Anna Bridge 180:96ed750bd169 1117
Anna Bridge 180:96ed750bd169 1118 /* Debug Exception and Monitor Control Register */
Anna Bridge 180:96ed750bd169 1119 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
Anna Bridge 180:96ed750bd169 1120 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
Anna Bridge 180:96ed750bd169 1121
Anna Bridge 180:96ed750bd169 1122 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
Anna Bridge 180:96ed750bd169 1123 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Anna Bridge 180:96ed750bd169 1124
Anna Bridge 180:96ed750bd169 1125 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
Anna Bridge 180:96ed750bd169 1126 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Anna Bridge 180:96ed750bd169 1127
Anna Bridge 180:96ed750bd169 1128 /* Debug Authentication Control Register Definitions */
Anna Bridge 180:96ed750bd169 1129 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
Anna Bridge 180:96ed750bd169 1130 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
Anna Bridge 180:96ed750bd169 1131
Anna Bridge 180:96ed750bd169 1132 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
Anna Bridge 180:96ed750bd169 1133 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
Anna Bridge 180:96ed750bd169 1134
Anna Bridge 180:96ed750bd169 1135 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
Anna Bridge 180:96ed750bd169 1136 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
Anna Bridge 180:96ed750bd169 1137
Anna Bridge 180:96ed750bd169 1138 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
Anna Bridge 180:96ed750bd169 1139 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
Anna Bridge 180:96ed750bd169 1140
Anna Bridge 180:96ed750bd169 1141 /* Debug Security Control and Status Register Definitions */
Anna Bridge 180:96ed750bd169 1142 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
Anna Bridge 180:96ed750bd169 1143 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
Anna Bridge 180:96ed750bd169 1144
Anna Bridge 180:96ed750bd169 1145 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
Anna Bridge 180:96ed750bd169 1146 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
Anna Bridge 180:96ed750bd169 1147
Anna Bridge 180:96ed750bd169 1148 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
Anna Bridge 180:96ed750bd169 1149 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
Anna Bridge 180:96ed750bd169 1150
Anna Bridge 180:96ed750bd169 1151 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 180:96ed750bd169 1152
Anna Bridge 180:96ed750bd169 1153
Anna Bridge 180:96ed750bd169 1154 /**
Anna Bridge 180:96ed750bd169 1155 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 1156 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 180:96ed750bd169 1157 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 180:96ed750bd169 1158 @{
Anna Bridge 180:96ed750bd169 1159 */
Anna Bridge 180:96ed750bd169 1160
Anna Bridge 180:96ed750bd169 1161 /**
Anna Bridge 180:96ed750bd169 1162 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 180:96ed750bd169 1163 \param[in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 1164 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 1165 \return Masked and shifted value.
Anna Bridge 180:96ed750bd169 1166 */
Anna Bridge 180:96ed750bd169 1167 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 180:96ed750bd169 1168
Anna Bridge 180:96ed750bd169 1169 /**
Anna Bridge 180:96ed750bd169 1170 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 180:96ed750bd169 1171 \param[in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 1172 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 1173 \return Masked and shifted bit field value.
Anna Bridge 180:96ed750bd169 1174 */
Anna Bridge 180:96ed750bd169 1175 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 180:96ed750bd169 1176
Anna Bridge 180:96ed750bd169 1177 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 180:96ed750bd169 1178
Anna Bridge 180:96ed750bd169 1179
Anna Bridge 180:96ed750bd169 1180 /**
Anna Bridge 180:96ed750bd169 1181 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 1182 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 180:96ed750bd169 1183 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 180:96ed750bd169 1184 @{
Anna Bridge 180:96ed750bd169 1185 */
Anna Bridge 180:96ed750bd169 1186
Anna Bridge 180:96ed750bd169 1187 /* Memory mapping of Core Hardware */
Anna Bridge 180:96ed750bd169 1188 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 180:96ed750bd169 1189 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Anna Bridge 180:96ed750bd169 1190 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Anna Bridge 180:96ed750bd169 1191 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Anna Bridge 180:96ed750bd169 1192 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 180:96ed750bd169 1193 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 180:96ed750bd169 1194 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 180:96ed750bd169 1195
Anna Bridge 180:96ed750bd169 1196
Anna Bridge 180:96ed750bd169 1197 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 180:96ed750bd169 1198 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 180:96ed750bd169 1199 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 180:96ed750bd169 1200 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Anna Bridge 180:96ed750bd169 1201 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Anna Bridge 180:96ed750bd169 1202 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
Anna Bridge 180:96ed750bd169 1203
Anna Bridge 180:96ed750bd169 1204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1205 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 180:96ed750bd169 1206 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 180:96ed750bd169 1207 #endif
Anna Bridge 180:96ed750bd169 1208
Anna Bridge 180:96ed750bd169 1209 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 1210 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
Anna Bridge 180:96ed750bd169 1211 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
Anna Bridge 180:96ed750bd169 1212 #endif
Anna Bridge 180:96ed750bd169 1213
Anna Bridge 180:96ed750bd169 1214 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 1215 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
Anna Bridge 180:96ed750bd169 1216 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
Anna Bridge 180:96ed750bd169 1217 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
Anna Bridge 180:96ed750bd169 1218 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
Anna Bridge 180:96ed750bd169 1219 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
Anna Bridge 180:96ed750bd169 1220
Anna Bridge 180:96ed750bd169 1221 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
Anna Bridge 180:96ed750bd169 1222 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
Anna Bridge 180:96ed750bd169 1223 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
Anna Bridge 180:96ed750bd169 1224 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
Anna Bridge 180:96ed750bd169 1225
Anna Bridge 180:96ed750bd169 1226 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1227 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
Anna Bridge 180:96ed750bd169 1228 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
Anna Bridge 180:96ed750bd169 1229 #endif
Anna Bridge 180:96ed750bd169 1230
Anna Bridge 180:96ed750bd169 1231 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 180:96ed750bd169 1232 /*@} */
Anna Bridge 180:96ed750bd169 1233
Anna Bridge 180:96ed750bd169 1234
Anna Bridge 180:96ed750bd169 1235
Anna Bridge 180:96ed750bd169 1236 /*******************************************************************************
Anna Bridge 180:96ed750bd169 1237 * Hardware Abstraction Layer
Anna Bridge 180:96ed750bd169 1238 Core Function Interface contains:
Anna Bridge 180:96ed750bd169 1239 - Core NVIC Functions
Anna Bridge 180:96ed750bd169 1240 - Core SysTick Functions
Anna Bridge 180:96ed750bd169 1241 - Core Register Access Functions
Anna Bridge 180:96ed750bd169 1242 ******************************************************************************/
Anna Bridge 180:96ed750bd169 1243 /**
Anna Bridge 180:96ed750bd169 1244 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 180:96ed750bd169 1245 */
Anna Bridge 180:96ed750bd169 1246
Anna Bridge 180:96ed750bd169 1247
Anna Bridge 180:96ed750bd169 1248
Anna Bridge 180:96ed750bd169 1249 /* ########################## NVIC functions #################################### */
Anna Bridge 180:96ed750bd169 1250 /**
Anna Bridge 180:96ed750bd169 1251 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 1252 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 180:96ed750bd169 1253 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 180:96ed750bd169 1254 @{
Anna Bridge 180:96ed750bd169 1255 */
Anna Bridge 180:96ed750bd169 1256
Anna Bridge 180:96ed750bd169 1257 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 180:96ed750bd169 1258 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 1259 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 180:96ed750bd169 1260 #endif
Anna Bridge 180:96ed750bd169 1261 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 1262 #else
Anna Bridge 180:96ed750bd169 1263 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
Anna Bridge 180:96ed750bd169 1264 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
Anna Bridge 180:96ed750bd169 1265 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 180:96ed750bd169 1266 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 180:96ed750bd169 1267 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 180:96ed750bd169 1268 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 180:96ed750bd169 1269 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 180:96ed750bd169 1270 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 180:96ed750bd169 1271 #define NVIC_GetActive __NVIC_GetActive
Anna Bridge 180:96ed750bd169 1272 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 180:96ed750bd169 1273 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 180:96ed750bd169 1274 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 180:96ed750bd169 1275 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 180:96ed750bd169 1276
Anna Bridge 180:96ed750bd169 1277 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 180:96ed750bd169 1278 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 1279 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 180:96ed750bd169 1280 #endif
Anna Bridge 180:96ed750bd169 1281 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 1282 #else
Anna Bridge 180:96ed750bd169 1283 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 180:96ed750bd169 1284 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 180:96ed750bd169 1285 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 180:96ed750bd169 1286
Anna Bridge 180:96ed750bd169 1287 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 180:96ed750bd169 1288
Anna Bridge 180:96ed750bd169 1289
AnnaBridge 188:bcfe06ba3d64 1290 /* Special LR values for Secure/Non-Secure call handling and exception handling */
AnnaBridge 188:bcfe06ba3d64 1291
AnnaBridge 188:bcfe06ba3d64 1292 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
AnnaBridge 188:bcfe06ba3d64 1293 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
AnnaBridge 188:bcfe06ba3d64 1294
AnnaBridge 188:bcfe06ba3d64 1295 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
AnnaBridge 188:bcfe06ba3d64 1296 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
AnnaBridge 188:bcfe06ba3d64 1297 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
AnnaBridge 188:bcfe06ba3d64 1298 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
AnnaBridge 188:bcfe06ba3d64 1299 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
AnnaBridge 188:bcfe06ba3d64 1300 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
AnnaBridge 188:bcfe06ba3d64 1301 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
AnnaBridge 188:bcfe06ba3d64 1302 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
AnnaBridge 188:bcfe06ba3d64 1303
AnnaBridge 188:bcfe06ba3d64 1304 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
AnnaBridge 188:bcfe06ba3d64 1305 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
AnnaBridge 188:bcfe06ba3d64 1306 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
AnnaBridge 188:bcfe06ba3d64 1307 #else
AnnaBridge 188:bcfe06ba3d64 1308 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
AnnaBridge 188:bcfe06ba3d64 1309 #endif
AnnaBridge 188:bcfe06ba3d64 1310
AnnaBridge 188:bcfe06ba3d64 1311
Anna Bridge 186:707f6e361f3e 1312 /* Interrupt Priorities are WORD accessible only under Armv6-M */
Anna Bridge 180:96ed750bd169 1313 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 180:96ed750bd169 1314 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 180:96ed750bd169 1315 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 180:96ed750bd169 1316 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 180:96ed750bd169 1317
AnnaBridge 188:bcfe06ba3d64 1318 #define __NVIC_SetPriorityGrouping(X) (void)(X)
AnnaBridge 188:bcfe06ba3d64 1319 #define __NVIC_GetPriorityGrouping() (0U)
Anna Bridge 180:96ed750bd169 1320
Anna Bridge 180:96ed750bd169 1321 /**
Anna Bridge 180:96ed750bd169 1322 \brief Enable Interrupt
Anna Bridge 180:96ed750bd169 1323 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 1324 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1325 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1326 */
Anna Bridge 180:96ed750bd169 1327 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1328 {
Anna Bridge 180:96ed750bd169 1329 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1330 {
Anna Bridge 186:707f6e361f3e 1331 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1332 }
Anna Bridge 180:96ed750bd169 1333 }
Anna Bridge 180:96ed750bd169 1334
Anna Bridge 180:96ed750bd169 1335
Anna Bridge 180:96ed750bd169 1336 /**
Anna Bridge 180:96ed750bd169 1337 \brief Get Interrupt Enable status
Anna Bridge 180:96ed750bd169 1338 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 1339 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1340 \return 0 Interrupt is not enabled.
Anna Bridge 180:96ed750bd169 1341 \return 1 Interrupt is enabled.
Anna Bridge 180:96ed750bd169 1342 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1343 */
Anna Bridge 180:96ed750bd169 1344 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1345 {
Anna Bridge 180:96ed750bd169 1346 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1347 {
Anna Bridge 186:707f6e361f3e 1348 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1349 }
Anna Bridge 180:96ed750bd169 1350 else
Anna Bridge 180:96ed750bd169 1351 {
Anna Bridge 180:96ed750bd169 1352 return(0U);
Anna Bridge 180:96ed750bd169 1353 }
Anna Bridge 180:96ed750bd169 1354 }
Anna Bridge 180:96ed750bd169 1355
Anna Bridge 180:96ed750bd169 1356
Anna Bridge 180:96ed750bd169 1357 /**
Anna Bridge 180:96ed750bd169 1358 \brief Disable Interrupt
Anna Bridge 180:96ed750bd169 1359 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 1360 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1361 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1362 */
Anna Bridge 180:96ed750bd169 1363 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1364 {
Anna Bridge 180:96ed750bd169 1365 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1366 {
Anna Bridge 186:707f6e361f3e 1367 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1368 __DSB();
Anna Bridge 180:96ed750bd169 1369 __ISB();
Anna Bridge 180:96ed750bd169 1370 }
Anna Bridge 180:96ed750bd169 1371 }
Anna Bridge 180:96ed750bd169 1372
Anna Bridge 180:96ed750bd169 1373
Anna Bridge 180:96ed750bd169 1374 /**
Anna Bridge 180:96ed750bd169 1375 \brief Get Pending Interrupt
Anna Bridge 180:96ed750bd169 1376 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 180:96ed750bd169 1377 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1378 \return 0 Interrupt status is not pending.
Anna Bridge 180:96ed750bd169 1379 \return 1 Interrupt status is pending.
Anna Bridge 180:96ed750bd169 1380 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1381 */
Anna Bridge 180:96ed750bd169 1382 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1383 {
Anna Bridge 180:96ed750bd169 1384 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1385 {
Anna Bridge 186:707f6e361f3e 1386 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1387 }
Anna Bridge 180:96ed750bd169 1388 else
Anna Bridge 180:96ed750bd169 1389 {
Anna Bridge 180:96ed750bd169 1390 return(0U);
Anna Bridge 180:96ed750bd169 1391 }
Anna Bridge 180:96ed750bd169 1392 }
Anna Bridge 180:96ed750bd169 1393
Anna Bridge 180:96ed750bd169 1394
Anna Bridge 180:96ed750bd169 1395 /**
Anna Bridge 180:96ed750bd169 1396 \brief Set Pending Interrupt
Anna Bridge 180:96ed750bd169 1397 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 180:96ed750bd169 1398 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1399 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1400 */
Anna Bridge 180:96ed750bd169 1401 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1402 {
Anna Bridge 180:96ed750bd169 1403 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1404 {
Anna Bridge 186:707f6e361f3e 1405 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1406 }
Anna Bridge 180:96ed750bd169 1407 }
Anna Bridge 180:96ed750bd169 1408
Anna Bridge 180:96ed750bd169 1409
Anna Bridge 180:96ed750bd169 1410 /**
Anna Bridge 180:96ed750bd169 1411 \brief Clear Pending Interrupt
Anna Bridge 180:96ed750bd169 1412 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 180:96ed750bd169 1413 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1414 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1415 */
Anna Bridge 180:96ed750bd169 1416 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1417 {
Anna Bridge 180:96ed750bd169 1418 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1419 {
Anna Bridge 186:707f6e361f3e 1420 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1421 }
Anna Bridge 180:96ed750bd169 1422 }
Anna Bridge 180:96ed750bd169 1423
Anna Bridge 180:96ed750bd169 1424
Anna Bridge 180:96ed750bd169 1425 /**
Anna Bridge 180:96ed750bd169 1426 \brief Get Active Interrupt
Anna Bridge 180:96ed750bd169 1427 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge 180:96ed750bd169 1428 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1429 \return 0 Interrupt status is not active.
Anna Bridge 180:96ed750bd169 1430 \return 1 Interrupt status is active.
Anna Bridge 180:96ed750bd169 1431 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1432 */
Anna Bridge 180:96ed750bd169 1433 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1434 {
Anna Bridge 180:96ed750bd169 1435 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1436 {
Anna Bridge 186:707f6e361f3e 1437 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1438 }
Anna Bridge 180:96ed750bd169 1439 else
Anna Bridge 180:96ed750bd169 1440 {
Anna Bridge 180:96ed750bd169 1441 return(0U);
Anna Bridge 180:96ed750bd169 1442 }
Anna Bridge 180:96ed750bd169 1443 }
Anna Bridge 180:96ed750bd169 1444
Anna Bridge 180:96ed750bd169 1445
Anna Bridge 180:96ed750bd169 1446 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 1447 /**
Anna Bridge 180:96ed750bd169 1448 \brief Get Interrupt Target State
Anna Bridge 180:96ed750bd169 1449 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 180:96ed750bd169 1450 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1451 \return 0 if interrupt is assigned to Secure
Anna Bridge 180:96ed750bd169 1452 \return 1 if interrupt is assigned to Non Secure
Anna Bridge 180:96ed750bd169 1453 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1454 */
Anna Bridge 180:96ed750bd169 1455 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1456 {
Anna Bridge 180:96ed750bd169 1457 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1458 {
Anna Bridge 186:707f6e361f3e 1459 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1460 }
Anna Bridge 180:96ed750bd169 1461 else
Anna Bridge 180:96ed750bd169 1462 {
Anna Bridge 180:96ed750bd169 1463 return(0U);
Anna Bridge 180:96ed750bd169 1464 }
Anna Bridge 180:96ed750bd169 1465 }
Anna Bridge 180:96ed750bd169 1466
Anna Bridge 180:96ed750bd169 1467
Anna Bridge 180:96ed750bd169 1468 /**
Anna Bridge 180:96ed750bd169 1469 \brief Set Interrupt Target State
Anna Bridge 180:96ed750bd169 1470 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 180:96ed750bd169 1471 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1472 \return 0 if interrupt is assigned to Secure
Anna Bridge 180:96ed750bd169 1473 1 if interrupt is assigned to Non Secure
Anna Bridge 180:96ed750bd169 1474 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1475 */
Anna Bridge 180:96ed750bd169 1476 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1477 {
Anna Bridge 180:96ed750bd169 1478 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1479 {
Anna Bridge 186:707f6e361f3e 1480 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 186:707f6e361f3e 1481 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1482 }
Anna Bridge 180:96ed750bd169 1483 else
Anna Bridge 180:96ed750bd169 1484 {
Anna Bridge 180:96ed750bd169 1485 return(0U);
Anna Bridge 180:96ed750bd169 1486 }
Anna Bridge 180:96ed750bd169 1487 }
Anna Bridge 180:96ed750bd169 1488
Anna Bridge 180:96ed750bd169 1489
Anna Bridge 180:96ed750bd169 1490 /**
Anna Bridge 180:96ed750bd169 1491 \brief Clear Interrupt Target State
Anna Bridge 180:96ed750bd169 1492 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 180:96ed750bd169 1493 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1494 \return 0 if interrupt is assigned to Secure
Anna Bridge 180:96ed750bd169 1495 1 if interrupt is assigned to Non Secure
Anna Bridge 180:96ed750bd169 1496 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1497 */
Anna Bridge 180:96ed750bd169 1498 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1499 {
Anna Bridge 180:96ed750bd169 1500 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1501 {
Anna Bridge 186:707f6e361f3e 1502 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 186:707f6e361f3e 1503 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1504 }
Anna Bridge 180:96ed750bd169 1505 else
Anna Bridge 180:96ed750bd169 1506 {
Anna Bridge 180:96ed750bd169 1507 return(0U);
Anna Bridge 180:96ed750bd169 1508 }
Anna Bridge 180:96ed750bd169 1509 }
Anna Bridge 180:96ed750bd169 1510 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 180:96ed750bd169 1511
Anna Bridge 180:96ed750bd169 1512
Anna Bridge 180:96ed750bd169 1513 /**
Anna Bridge 180:96ed750bd169 1514 \brief Set Interrupt Priority
Anna Bridge 180:96ed750bd169 1515 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 180:96ed750bd169 1516 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 1517 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 1518 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 1519 \param [in] priority Priority to set.
Anna Bridge 180:96ed750bd169 1520 \note The priority cannot be set for every processor exception.
Anna Bridge 180:96ed750bd169 1521 */
Anna Bridge 180:96ed750bd169 1522 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 180:96ed750bd169 1523 {
Anna Bridge 180:96ed750bd169 1524 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1525 {
Anna Bridge 180:96ed750bd169 1526 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 1527 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 1528 }
Anna Bridge 180:96ed750bd169 1529 else
Anna Bridge 180:96ed750bd169 1530 {
Anna Bridge 180:96ed750bd169 1531 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 1532 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 1533 }
Anna Bridge 180:96ed750bd169 1534 }
Anna Bridge 180:96ed750bd169 1535
Anna Bridge 180:96ed750bd169 1536
Anna Bridge 180:96ed750bd169 1537 /**
Anna Bridge 180:96ed750bd169 1538 \brief Get Interrupt Priority
Anna Bridge 180:96ed750bd169 1539 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 180:96ed750bd169 1540 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 1541 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 1542 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 1543 \return Interrupt Priority.
Anna Bridge 180:96ed750bd169 1544 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 180:96ed750bd169 1545 */
Anna Bridge 180:96ed750bd169 1546 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1547 {
Anna Bridge 180:96ed750bd169 1548
Anna Bridge 180:96ed750bd169 1549 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1550 {
Anna Bridge 180:96ed750bd169 1551 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 1552 }
Anna Bridge 180:96ed750bd169 1553 else
Anna Bridge 180:96ed750bd169 1554 {
Anna Bridge 180:96ed750bd169 1555 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 1556 }
Anna Bridge 180:96ed750bd169 1557 }
Anna Bridge 180:96ed750bd169 1558
Anna Bridge 180:96ed750bd169 1559
Anna Bridge 180:96ed750bd169 1560 /**
AnnaBridge 188:bcfe06ba3d64 1561 \brief Encode Priority
AnnaBridge 188:bcfe06ba3d64 1562 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 188:bcfe06ba3d64 1563 preemptive priority value, and subpriority value.
AnnaBridge 188:bcfe06ba3d64 1564 In case of a conflict between priority grouping and available
AnnaBridge 188:bcfe06ba3d64 1565 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 188:bcfe06ba3d64 1566 \param [in] PriorityGroup Used priority group.
AnnaBridge 188:bcfe06ba3d64 1567 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 1568 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 1569 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 188:bcfe06ba3d64 1570 */
AnnaBridge 188:bcfe06ba3d64 1571 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 188:bcfe06ba3d64 1572 {
AnnaBridge 188:bcfe06ba3d64 1573 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 188:bcfe06ba3d64 1574 uint32_t PreemptPriorityBits;
AnnaBridge 188:bcfe06ba3d64 1575 uint32_t SubPriorityBits;
AnnaBridge 188:bcfe06ba3d64 1576
AnnaBridge 188:bcfe06ba3d64 1577 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 188:bcfe06ba3d64 1578 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 188:bcfe06ba3d64 1579
AnnaBridge 188:bcfe06ba3d64 1580 return (
AnnaBridge 188:bcfe06ba3d64 1581 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 188:bcfe06ba3d64 1582 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 188:bcfe06ba3d64 1583 );
AnnaBridge 188:bcfe06ba3d64 1584 }
AnnaBridge 188:bcfe06ba3d64 1585
AnnaBridge 188:bcfe06ba3d64 1586
AnnaBridge 188:bcfe06ba3d64 1587 /**
AnnaBridge 188:bcfe06ba3d64 1588 \brief Decode Priority
AnnaBridge 188:bcfe06ba3d64 1589 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 188:bcfe06ba3d64 1590 preemptive priority value and subpriority value.
AnnaBridge 188:bcfe06ba3d64 1591 In case of a conflict between priority grouping and available
AnnaBridge 188:bcfe06ba3d64 1592 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 188:bcfe06ba3d64 1593 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 188:bcfe06ba3d64 1594 \param [in] PriorityGroup Used priority group.
AnnaBridge 188:bcfe06ba3d64 1595 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 1596 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 1597 */
AnnaBridge 188:bcfe06ba3d64 1598 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 188:bcfe06ba3d64 1599 {
AnnaBridge 188:bcfe06ba3d64 1600 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 188:bcfe06ba3d64 1601 uint32_t PreemptPriorityBits;
AnnaBridge 188:bcfe06ba3d64 1602 uint32_t SubPriorityBits;
AnnaBridge 188:bcfe06ba3d64 1603
AnnaBridge 188:bcfe06ba3d64 1604 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 188:bcfe06ba3d64 1605 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 188:bcfe06ba3d64 1606
AnnaBridge 188:bcfe06ba3d64 1607 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 188:bcfe06ba3d64 1608 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 188:bcfe06ba3d64 1609 }
AnnaBridge 188:bcfe06ba3d64 1610
AnnaBridge 188:bcfe06ba3d64 1611
AnnaBridge 188:bcfe06ba3d64 1612 /**
Anna Bridge 180:96ed750bd169 1613 \brief Set Interrupt Vector
Anna Bridge 180:96ed750bd169 1614 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 180:96ed750bd169 1615 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 1616 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 1617 VTOR must been relocated to SRAM before.
Anna Bridge 180:96ed750bd169 1618 If VTOR is not present address 0 must be mapped to SRAM.
Anna Bridge 180:96ed750bd169 1619 \param [in] IRQn Interrupt number
Anna Bridge 180:96ed750bd169 1620 \param [in] vector Address of interrupt handler function
Anna Bridge 180:96ed750bd169 1621 */
Anna Bridge 180:96ed750bd169 1622 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 180:96ed750bd169 1623 {
Anna Bridge 180:96ed750bd169 1624 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1625 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 180:96ed750bd169 1626 #else
Anna Bridge 180:96ed750bd169 1627 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 180:96ed750bd169 1628 #endif
Anna Bridge 180:96ed750bd169 1629 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 180:96ed750bd169 1630 }
Anna Bridge 180:96ed750bd169 1631
Anna Bridge 180:96ed750bd169 1632
Anna Bridge 180:96ed750bd169 1633 /**
Anna Bridge 180:96ed750bd169 1634 \brief Get Interrupt Vector
Anna Bridge 180:96ed750bd169 1635 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 180:96ed750bd169 1636 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 1637 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 1638 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 1639 \return Address of interrupt handler function
Anna Bridge 180:96ed750bd169 1640 */
Anna Bridge 180:96ed750bd169 1641 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1642 {
Anna Bridge 180:96ed750bd169 1643 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1644 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 180:96ed750bd169 1645 #else
Anna Bridge 180:96ed750bd169 1646 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 180:96ed750bd169 1647 #endif
Anna Bridge 180:96ed750bd169 1648 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 180:96ed750bd169 1649 }
Anna Bridge 180:96ed750bd169 1650
Anna Bridge 180:96ed750bd169 1651
Anna Bridge 180:96ed750bd169 1652 /**
Anna Bridge 180:96ed750bd169 1653 \brief System Reset
Anna Bridge 180:96ed750bd169 1654 \details Initiates a system reset request to reset the MCU.
Anna Bridge 180:96ed750bd169 1655 */
AnnaBridge 188:bcfe06ba3d64 1656 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 180:96ed750bd169 1657 {
Anna Bridge 180:96ed750bd169 1658 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 180:96ed750bd169 1659 buffered write are completed before reset */
Anna Bridge 180:96ed750bd169 1660 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 180:96ed750bd169 1661 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 180:96ed750bd169 1662 __DSB(); /* Ensure completion of memory access */
Anna Bridge 180:96ed750bd169 1663
Anna Bridge 180:96ed750bd169 1664 for(;;) /* wait until reset */
Anna Bridge 180:96ed750bd169 1665 {
Anna Bridge 180:96ed750bd169 1666 __NOP();
Anna Bridge 180:96ed750bd169 1667 }
Anna Bridge 180:96ed750bd169 1668 }
Anna Bridge 180:96ed750bd169 1669
Anna Bridge 180:96ed750bd169 1670 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 1671 /**
Anna Bridge 180:96ed750bd169 1672 \brief Enable Interrupt (non-secure)
Anna Bridge 180:96ed750bd169 1673 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 180:96ed750bd169 1674 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1675 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1676 */
Anna Bridge 180:96ed750bd169 1677 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1678 {
Anna Bridge 180:96ed750bd169 1679 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1680 {
Anna Bridge 186:707f6e361f3e 1681 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1682 }
Anna Bridge 180:96ed750bd169 1683 }
Anna Bridge 180:96ed750bd169 1684
Anna Bridge 180:96ed750bd169 1685
Anna Bridge 180:96ed750bd169 1686 /**
Anna Bridge 180:96ed750bd169 1687 \brief Get Interrupt Enable status (non-secure)
Anna Bridge 180:96ed750bd169 1688 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 180:96ed750bd169 1689 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1690 \return 0 Interrupt is not enabled.
Anna Bridge 180:96ed750bd169 1691 \return 1 Interrupt is enabled.
Anna Bridge 180:96ed750bd169 1692 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1693 */
Anna Bridge 180:96ed750bd169 1694 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1695 {
Anna Bridge 180:96ed750bd169 1696 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1697 {
Anna Bridge 186:707f6e361f3e 1698 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1699 }
Anna Bridge 180:96ed750bd169 1700 else
Anna Bridge 180:96ed750bd169 1701 {
Anna Bridge 180:96ed750bd169 1702 return(0U);
Anna Bridge 180:96ed750bd169 1703 }
Anna Bridge 180:96ed750bd169 1704 }
Anna Bridge 180:96ed750bd169 1705
Anna Bridge 180:96ed750bd169 1706
Anna Bridge 180:96ed750bd169 1707 /**
Anna Bridge 180:96ed750bd169 1708 \brief Disable Interrupt (non-secure)
Anna Bridge 180:96ed750bd169 1709 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 180:96ed750bd169 1710 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1711 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1712 */
Anna Bridge 180:96ed750bd169 1713 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1714 {
Anna Bridge 180:96ed750bd169 1715 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1716 {
Anna Bridge 186:707f6e361f3e 1717 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1718 }
Anna Bridge 180:96ed750bd169 1719 }
Anna Bridge 180:96ed750bd169 1720
Anna Bridge 180:96ed750bd169 1721
Anna Bridge 180:96ed750bd169 1722 /**
Anna Bridge 180:96ed750bd169 1723 \brief Get Pending Interrupt (non-secure)
Anna Bridge 180:96ed750bd169 1724 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Anna Bridge 180:96ed750bd169 1725 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1726 \return 0 Interrupt status is not pending.
Anna Bridge 180:96ed750bd169 1727 \return 1 Interrupt status is pending.
Anna Bridge 180:96ed750bd169 1728 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1729 */
Anna Bridge 180:96ed750bd169 1730 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1731 {
Anna Bridge 180:96ed750bd169 1732 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1733 {
Anna Bridge 186:707f6e361f3e 1734 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1735 }
Anna Bridge 180:96ed750bd169 1736 else
Anna Bridge 180:96ed750bd169 1737 {
Anna Bridge 180:96ed750bd169 1738 return(0U);
Anna Bridge 180:96ed750bd169 1739 }
Anna Bridge 180:96ed750bd169 1740 }
Anna Bridge 180:96ed750bd169 1741
Anna Bridge 180:96ed750bd169 1742
Anna Bridge 180:96ed750bd169 1743 /**
Anna Bridge 180:96ed750bd169 1744 \brief Set Pending Interrupt (non-secure)
Anna Bridge 180:96ed750bd169 1745 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge 180:96ed750bd169 1746 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1747 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1748 */
Anna Bridge 180:96ed750bd169 1749 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1750 {
Anna Bridge 180:96ed750bd169 1751 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1752 {
Anna Bridge 186:707f6e361f3e 1753 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1754 }
Anna Bridge 180:96ed750bd169 1755 }
Anna Bridge 180:96ed750bd169 1756
Anna Bridge 180:96ed750bd169 1757
Anna Bridge 180:96ed750bd169 1758 /**
Anna Bridge 180:96ed750bd169 1759 \brief Clear Pending Interrupt (non-secure)
Anna Bridge 180:96ed750bd169 1760 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge 180:96ed750bd169 1761 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1762 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1763 */
Anna Bridge 180:96ed750bd169 1764 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1765 {
Anna Bridge 180:96ed750bd169 1766 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1767 {
Anna Bridge 186:707f6e361f3e 1768 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 1769 }
Anna Bridge 180:96ed750bd169 1770 }
Anna Bridge 180:96ed750bd169 1771
Anna Bridge 180:96ed750bd169 1772
Anna Bridge 180:96ed750bd169 1773 /**
Anna Bridge 180:96ed750bd169 1774 \brief Get Active Interrupt (non-secure)
Anna Bridge 180:96ed750bd169 1775 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Anna Bridge 180:96ed750bd169 1776 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 1777 \return 0 Interrupt status is not active.
Anna Bridge 180:96ed750bd169 1778 \return 1 Interrupt status is active.
Anna Bridge 180:96ed750bd169 1779 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 1780 */
Anna Bridge 180:96ed750bd169 1781 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1782 {
Anna Bridge 180:96ed750bd169 1783 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1784 {
Anna Bridge 186:707f6e361f3e 1785 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 1786 }
Anna Bridge 180:96ed750bd169 1787 else
Anna Bridge 180:96ed750bd169 1788 {
Anna Bridge 180:96ed750bd169 1789 return(0U);
Anna Bridge 180:96ed750bd169 1790 }
Anna Bridge 180:96ed750bd169 1791 }
Anna Bridge 180:96ed750bd169 1792
Anna Bridge 180:96ed750bd169 1793
Anna Bridge 180:96ed750bd169 1794 /**
Anna Bridge 180:96ed750bd169 1795 \brief Set Interrupt Priority (non-secure)
Anna Bridge 180:96ed750bd169 1796 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge 180:96ed750bd169 1797 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 1798 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 1799 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 1800 \param [in] priority Priority to set.
Anna Bridge 180:96ed750bd169 1801 \note The priority cannot be set for every non-secure processor exception.
Anna Bridge 180:96ed750bd169 1802 */
Anna Bridge 180:96ed750bd169 1803 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 180:96ed750bd169 1804 {
Anna Bridge 180:96ed750bd169 1805 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1806 {
Anna Bridge 180:96ed750bd169 1807 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 1808 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 1809 }
Anna Bridge 180:96ed750bd169 1810 else
Anna Bridge 180:96ed750bd169 1811 {
Anna Bridge 180:96ed750bd169 1812 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 1813 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 1814 }
Anna Bridge 180:96ed750bd169 1815 }
Anna Bridge 180:96ed750bd169 1816
Anna Bridge 180:96ed750bd169 1817
Anna Bridge 180:96ed750bd169 1818 /**
Anna Bridge 180:96ed750bd169 1819 \brief Get Interrupt Priority (non-secure)
Anna Bridge 180:96ed750bd169 1820 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge 180:96ed750bd169 1821 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 1822 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 1823 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 1824 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 180:96ed750bd169 1825 */
Anna Bridge 180:96ed750bd169 1826 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1827 {
Anna Bridge 180:96ed750bd169 1828
Anna Bridge 180:96ed750bd169 1829 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 1830 {
Anna Bridge 180:96ed750bd169 1831 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 1832 }
Anna Bridge 180:96ed750bd169 1833 else
Anna Bridge 180:96ed750bd169 1834 {
Anna Bridge 180:96ed750bd169 1835 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 1836 }
Anna Bridge 180:96ed750bd169 1837 }
Anna Bridge 180:96ed750bd169 1838 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 180:96ed750bd169 1839
Anna Bridge 180:96ed750bd169 1840 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 180:96ed750bd169 1841
Anna Bridge 180:96ed750bd169 1842 /* ########################## MPU functions #################################### */
Anna Bridge 180:96ed750bd169 1843
Anna Bridge 180:96ed750bd169 1844 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1845
Anna Bridge 180:96ed750bd169 1846 #include "mpu_armv8.h"
Anna Bridge 180:96ed750bd169 1847
Anna Bridge 180:96ed750bd169 1848 #endif
Anna Bridge 180:96ed750bd169 1849
Anna Bridge 180:96ed750bd169 1850 /* ########################## FPU functions #################################### */
Anna Bridge 180:96ed750bd169 1851 /**
Anna Bridge 180:96ed750bd169 1852 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 1853 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 180:96ed750bd169 1854 \brief Function that provides FPU type.
Anna Bridge 180:96ed750bd169 1855 @{
Anna Bridge 180:96ed750bd169 1856 */
Anna Bridge 180:96ed750bd169 1857
Anna Bridge 180:96ed750bd169 1858 /**
Anna Bridge 180:96ed750bd169 1859 \brief get FPU type
Anna Bridge 180:96ed750bd169 1860 \details returns the FPU type
Anna Bridge 180:96ed750bd169 1861 \returns
Anna Bridge 180:96ed750bd169 1862 - \b 0: No FPU
Anna Bridge 180:96ed750bd169 1863 - \b 1: Single precision FPU
Anna Bridge 180:96ed750bd169 1864 - \b 2: Double + Single precision FPU
Anna Bridge 180:96ed750bd169 1865 */
Anna Bridge 180:96ed750bd169 1866 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 180:96ed750bd169 1867 {
Anna Bridge 180:96ed750bd169 1868 return 0U; /* No FPU */
Anna Bridge 180:96ed750bd169 1869 }
Anna Bridge 180:96ed750bd169 1870
Anna Bridge 180:96ed750bd169 1871
Anna Bridge 180:96ed750bd169 1872 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 180:96ed750bd169 1873
Anna Bridge 180:96ed750bd169 1874
Anna Bridge 180:96ed750bd169 1875
Anna Bridge 180:96ed750bd169 1876 /* ########################## SAU functions #################################### */
Anna Bridge 180:96ed750bd169 1877 /**
Anna Bridge 180:96ed750bd169 1878 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 1879 \defgroup CMSIS_Core_SAUFunctions SAU Functions
Anna Bridge 180:96ed750bd169 1880 \brief Functions that configure the SAU.
Anna Bridge 180:96ed750bd169 1881 @{
Anna Bridge 180:96ed750bd169 1882 */
Anna Bridge 180:96ed750bd169 1883
Anna Bridge 180:96ed750bd169 1884 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 1885
Anna Bridge 180:96ed750bd169 1886 /**
Anna Bridge 180:96ed750bd169 1887 \brief Enable SAU
Anna Bridge 180:96ed750bd169 1888 \details Enables the Security Attribution Unit (SAU).
Anna Bridge 180:96ed750bd169 1889 */
Anna Bridge 180:96ed750bd169 1890 __STATIC_INLINE void TZ_SAU_Enable(void)
Anna Bridge 180:96ed750bd169 1891 {
Anna Bridge 180:96ed750bd169 1892 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
Anna Bridge 180:96ed750bd169 1893 }
Anna Bridge 180:96ed750bd169 1894
Anna Bridge 180:96ed750bd169 1895
Anna Bridge 180:96ed750bd169 1896
Anna Bridge 180:96ed750bd169 1897 /**
Anna Bridge 180:96ed750bd169 1898 \brief Disable SAU
Anna Bridge 180:96ed750bd169 1899 \details Disables the Security Attribution Unit (SAU).
Anna Bridge 180:96ed750bd169 1900 */
Anna Bridge 180:96ed750bd169 1901 __STATIC_INLINE void TZ_SAU_Disable(void)
Anna Bridge 180:96ed750bd169 1902 {
Anna Bridge 180:96ed750bd169 1903 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Anna Bridge 180:96ed750bd169 1904 }
Anna Bridge 180:96ed750bd169 1905
Anna Bridge 180:96ed750bd169 1906 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 180:96ed750bd169 1907
Anna Bridge 180:96ed750bd169 1908 /*@} end of CMSIS_Core_SAUFunctions */
Anna Bridge 180:96ed750bd169 1909
Anna Bridge 180:96ed750bd169 1910
Anna Bridge 180:96ed750bd169 1911
Anna Bridge 180:96ed750bd169 1912
Anna Bridge 180:96ed750bd169 1913 /* ################################## SysTick function ############################################ */
Anna Bridge 180:96ed750bd169 1914 /**
Anna Bridge 180:96ed750bd169 1915 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 1916 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 180:96ed750bd169 1917 \brief Functions that configure the System.
Anna Bridge 180:96ed750bd169 1918 @{
Anna Bridge 180:96ed750bd169 1919 */
Anna Bridge 180:96ed750bd169 1920
Anna Bridge 180:96ed750bd169 1921 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 180:96ed750bd169 1922
Anna Bridge 180:96ed750bd169 1923 /**
Anna Bridge 180:96ed750bd169 1924 \brief System Tick Configuration
Anna Bridge 180:96ed750bd169 1925 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 180:96ed750bd169 1926 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 180:96ed750bd169 1927 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 180:96ed750bd169 1928 \return 0 Function succeeded.
Anna Bridge 180:96ed750bd169 1929 \return 1 Function failed.
Anna Bridge 180:96ed750bd169 1930 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 180:96ed750bd169 1931 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 180:96ed750bd169 1932 must contain a vendor-specific implementation of this function.
Anna Bridge 180:96ed750bd169 1933 */
Anna Bridge 180:96ed750bd169 1934 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 180:96ed750bd169 1935 {
Anna Bridge 180:96ed750bd169 1936 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 180:96ed750bd169 1937 {
Anna Bridge 180:96ed750bd169 1938 return (1UL); /* Reload value impossible */
Anna Bridge 180:96ed750bd169 1939 }
Anna Bridge 180:96ed750bd169 1940
Anna Bridge 180:96ed750bd169 1941 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 180:96ed750bd169 1942 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 180:96ed750bd169 1943 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 180:96ed750bd169 1944 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 180:96ed750bd169 1945 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 180:96ed750bd169 1946 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 180:96ed750bd169 1947 return (0UL); /* Function successful */
Anna Bridge 180:96ed750bd169 1948 }
Anna Bridge 180:96ed750bd169 1949
Anna Bridge 180:96ed750bd169 1950 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 180:96ed750bd169 1951 /**
Anna Bridge 180:96ed750bd169 1952 \brief System Tick Configuration (non-secure)
Anna Bridge 180:96ed750bd169 1953 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Anna Bridge 180:96ed750bd169 1954 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 180:96ed750bd169 1955 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 180:96ed750bd169 1956 \return 0 Function succeeded.
Anna Bridge 180:96ed750bd169 1957 \return 1 Function failed.
Anna Bridge 180:96ed750bd169 1958 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 180:96ed750bd169 1959 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 180:96ed750bd169 1960 must contain a vendor-specific implementation of this function.
Anna Bridge 180:96ed750bd169 1961
Anna Bridge 180:96ed750bd169 1962 */
Anna Bridge 180:96ed750bd169 1963 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Anna Bridge 180:96ed750bd169 1964 {
Anna Bridge 180:96ed750bd169 1965 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 180:96ed750bd169 1966 {
Anna Bridge 180:96ed750bd169 1967 return (1UL); /* Reload value impossible */
Anna Bridge 180:96ed750bd169 1968 }
Anna Bridge 180:96ed750bd169 1969
Anna Bridge 180:96ed750bd169 1970 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 180:96ed750bd169 1971 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 180:96ed750bd169 1972 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 180:96ed750bd169 1973 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 180:96ed750bd169 1974 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 180:96ed750bd169 1975 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 180:96ed750bd169 1976 return (0UL); /* Function successful */
Anna Bridge 180:96ed750bd169 1977 }
Anna Bridge 180:96ed750bd169 1978 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 180:96ed750bd169 1979
Anna Bridge 180:96ed750bd169 1980 #endif
Anna Bridge 180:96ed750bd169 1981
Anna Bridge 180:96ed750bd169 1982 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 180:96ed750bd169 1983
Anna Bridge 180:96ed750bd169 1984
Anna Bridge 180:96ed750bd169 1985
Anna Bridge 180:96ed750bd169 1986
Anna Bridge 180:96ed750bd169 1987 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 1988 }
Anna Bridge 180:96ed750bd169 1989 #endif
Anna Bridge 180:96ed750bd169 1990
Anna Bridge 180:96ed750bd169 1991 #endif /* __CORE_CM23_H_DEPENDANT */
Anna Bridge 180:96ed750bd169 1992
Anna Bridge 180:96ed750bd169 1993 #endif /* __CMSIS_GENERIC */