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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_M/core_armv8mml.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 188:bcfe06ba3d64

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
Anna Bridge	180:96ed750bd169	1	/************************************************************************//
Anna Bridge	180:96ed750bd169	2	* @file core_armv8mml.h
Anna Bridge	186:707f6e361f3e	3	* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
AnnaBridge	188:bcfe06ba3d64	4	* @version V5.0.7
AnnaBridge	188:bcfe06ba3d64	5	* @date 06. July 2018
Anna Bridge	180:96ed750bd169	6	******************************************************************************/
Anna Bridge	180:96ed750bd169	7	/*
Anna Bridge	186:707f6e361f3e	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge	180:96ed750bd169	9	*
Anna Bridge	180:96ed750bd169	10	* SPDX-License-Identifier: Apache-2.0
Anna Bridge	180:96ed750bd169	11	*
Anna Bridge	180:96ed750bd169	12	* Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge	180:96ed750bd169	13	* not use this file except in compliance with the License.
Anna Bridge	180:96ed750bd169	14	* You may obtain a copy of the License at
Anna Bridge	180:96ed750bd169	15	*
Anna Bridge	180:96ed750bd169	16	* www.apache.org/licenses/LICENSE-2.0
Anna Bridge	180:96ed750bd169	17	*
Anna Bridge	180:96ed750bd169	18	* Unless required by applicable law or agreed to in writing, software
Anna Bridge	180:96ed750bd169	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge	180:96ed750bd169	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge	180:96ed750bd169	21	* See the License for the specific language governing permissions and
Anna Bridge	180:96ed750bd169	22	* limitations under the License.
Anna Bridge	180:96ed750bd169	23	*/
Anna Bridge	180:96ed750bd169	24
Anna Bridge	180:96ed750bd169	25	#if defined ( __ICCARM__ )
Anna Bridge	186:707f6e361f3e	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	186:707f6e361f3e	27	#elif defined (__clang__)
Anna Bridge	180:96ed750bd169	28	#pragma clang system_header /* treat file as system include file */
Anna Bridge	180:96ed750bd169	29	#endif
Anna Bridge	180:96ed750bd169	30
Anna Bridge	180:96ed750bd169	31	#ifndef __CORE_ARMV8MML_H_GENERIC
Anna Bridge	180:96ed750bd169	32	#define __CORE_ARMV8MML_H_GENERIC
Anna Bridge	180:96ed750bd169	33
Anna Bridge	180:96ed750bd169	34	#include <stdint.h>
Anna Bridge	180:96ed750bd169	35
Anna Bridge	180:96ed750bd169	36	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	37	extern "C" {
Anna Bridge	180:96ed750bd169	38	#endif
Anna Bridge	180:96ed750bd169	39
Anna Bridge	180:96ed750bd169	40	/**
Anna Bridge	180:96ed750bd169	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge	180:96ed750bd169	42	CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge	180:96ed750bd169	43
Anna Bridge	180:96ed750bd169	44	\li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge	180:96ed750bd169	45	Function definitions in header files are used to allow 'inlining'.
Anna Bridge	180:96ed750bd169	46
Anna Bridge	180:96ed750bd169	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge	180:96ed750bd169	48	Unions are used for effective representation of core registers.
Anna Bridge	180:96ed750bd169	49
Anna Bridge	180:96ed750bd169	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge	180:96ed750bd169	51	Function-like macros are used to allow more efficient code.
Anna Bridge	180:96ed750bd169	52	*/
Anna Bridge	180:96ed750bd169	53
Anna Bridge	180:96ed750bd169	54
Anna Bridge	180:96ed750bd169	55	/*******************************************************************************
Anna Bridge	180:96ed750bd169	56	* CMSIS definitions
Anna Bridge	180:96ed750bd169	57	******************************************************************************/
Anna Bridge	180:96ed750bd169	58	/**
Anna Bridge	180:96ed750bd169	59	\ingroup Cortex_ARMv8MML
Anna Bridge	180:96ed750bd169	60	@{
Anna Bridge	180:96ed750bd169	61	*/
Anna Bridge	180:96ed750bd169	62
Anna Bridge	180:96ed750bd169	63	#include "cmsis_version.h"
AnnaBridge	188:bcfe06ba3d64	64
Anna Bridge	186:707f6e361f3e	65	/* CMSIS Armv8MML definitions */
Anna Bridge	180:96ed750bd169	66	#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	180:96ed750bd169	67	#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
Anna Bridge	180:96ed750bd169	68	#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	180:96ed750bd169	69	__ARMv8MML_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
Anna Bridge	180:96ed750bd169	70
Anna Bridge	180:96ed750bd169	71	#define __CORTEX_M (81U) /!< Cortex-M Core /
Anna Bridge	180:96ed750bd169	72
Anna Bridge	180:96ed750bd169	73	/** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge	180:96ed750bd169	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Anna Bridge	180:96ed750bd169	75	*/
Anna Bridge	180:96ed750bd169	76	#if defined ( __CC_ARM )
Anna Bridge	180:96ed750bd169	77	#if defined __TARGET_FPU_VFP
Anna Bridge	180:96ed750bd169	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	79	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	80	#else
Anna Bridge	180:96ed750bd169	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	82	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	83	#endif
Anna Bridge	180:96ed750bd169	84	#else
Anna Bridge	180:96ed750bd169	85	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	86	#endif
Anna Bridge	180:96ed750bd169	87
Anna Bridge	180:96ed750bd169	88	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	180:96ed750bd169	89	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	90	#define __DSP_USED 1U
Anna Bridge	180:96ed750bd169	91	#else
Anna Bridge	180:96ed750bd169	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	188:bcfe06ba3d64	93	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	94	#endif
Anna Bridge	180:96ed750bd169	95	#else
Anna Bridge	180:96ed750bd169	96	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	97	#endif
AnnaBridge	188:bcfe06ba3d64	98
Anna Bridge	180:96ed750bd169	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	189:f392fc9709a3	100	#if defined __ARM_FP
Anna Bridge	180:96ed750bd169	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	102	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	103	#else
Anna Bridge	180:96ed750bd169	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	105	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	106	#endif
Anna Bridge	180:96ed750bd169	107	#else
Anna Bridge	180:96ed750bd169	108	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	109	#endif
Anna Bridge	180:96ed750bd169	110
Anna Bridge	180:96ed750bd169	111	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	180:96ed750bd169	112	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	113	#define __DSP_USED 1U
Anna Bridge	180:96ed750bd169	114	#else
Anna Bridge	180:96ed750bd169	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	188:bcfe06ba3d64	116	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	117	#endif
Anna Bridge	180:96ed750bd169	118	#else
Anna Bridge	180:96ed750bd169	119	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	120	#endif
Anna Bridge	180:96ed750bd169	121
Anna Bridge	180:96ed750bd169	122	#elif defined ( __GNUC__ )
Anna Bridge	180:96ed750bd169	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge	180:96ed750bd169	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	125	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	126	#else
Anna Bridge	180:96ed750bd169	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	128	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	129	#endif
Anna Bridge	180:96ed750bd169	130	#else
Anna Bridge	180:96ed750bd169	131	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	132	#endif
AnnaBridge	188:bcfe06ba3d64	133
Anna Bridge	180:96ed750bd169	134	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	180:96ed750bd169	135	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	136	#define __DSP_USED 1U
Anna Bridge	180:96ed750bd169	137	#else
Anna Bridge	180:96ed750bd169	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	188:bcfe06ba3d64	139	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	140	#endif
Anna Bridge	180:96ed750bd169	141	#else
Anna Bridge	180:96ed750bd169	142	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	143	#endif
AnnaBridge	188:bcfe06ba3d64	144
Anna Bridge	180:96ed750bd169	145	#elif defined ( __ICCARM__ )
Anna Bridge	180:96ed750bd169	146	#if defined __ARMVFP__
Anna Bridge	180:96ed750bd169	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	148	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	149	#else
Anna Bridge	180:96ed750bd169	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	151	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	152	#endif
Anna Bridge	180:96ed750bd169	153	#else
Anna Bridge	180:96ed750bd169	154	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	155	#endif
Anna Bridge	180:96ed750bd169	156
Anna Bridge	180:96ed750bd169	157	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	180:96ed750bd169	158	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	159	#define __DSP_USED 1U
Anna Bridge	180:96ed750bd169	160	#else
Anna Bridge	180:96ed750bd169	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	188:bcfe06ba3d64	162	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	163	#endif
Anna Bridge	180:96ed750bd169	164	#else
Anna Bridge	180:96ed750bd169	165	#define __DSP_USED 0U
Anna Bridge	180:96ed750bd169	166	#endif
AnnaBridge	188:bcfe06ba3d64	167
Anna Bridge	180:96ed750bd169	168	#elif defined ( __TI_ARM__ )
Anna Bridge	180:96ed750bd169	169	#if defined __TI_VFP_SUPPORT__
Anna Bridge	180:96ed750bd169	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	171	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	172	#else
Anna Bridge	180:96ed750bd169	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	174	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	175	#endif
Anna Bridge	180:96ed750bd169	176	#else
Anna Bridge	180:96ed750bd169	177	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	178	#endif
Anna Bridge	180:96ed750bd169	179
Anna Bridge	180:96ed750bd169	180	#elif defined ( __TASKING__ )
Anna Bridge	180:96ed750bd169	181	#if defined __FPU_VFP__
Anna Bridge	180:96ed750bd169	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	183	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	184	#else
Anna Bridge	180:96ed750bd169	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	186	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	187	#endif
Anna Bridge	180:96ed750bd169	188	#else
Anna Bridge	180:96ed750bd169	189	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	190	#endif
Anna Bridge	180:96ed750bd169	191
Anna Bridge	180:96ed750bd169	192	#elif defined ( __CSMC__ )
Anna Bridge	180:96ed750bd169	193	#if ( __CSMC__ & 0x400U)
Anna Bridge	180:96ed750bd169	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	195	#define __FPU_USED 1U
Anna Bridge	180:96ed750bd169	196	#else
Anna Bridge	180:96ed750bd169	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	180:96ed750bd169	198	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	199	#endif
Anna Bridge	180:96ed750bd169	200	#else
Anna Bridge	180:96ed750bd169	201	#define __FPU_USED 0U
Anna Bridge	180:96ed750bd169	202	#endif
Anna Bridge	180:96ed750bd169	203
Anna Bridge	180:96ed750bd169	204	#endif
Anna Bridge	180:96ed750bd169	205
Anna Bridge	180:96ed750bd169	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge	180:96ed750bd169	207
Anna Bridge	180:96ed750bd169	208
Anna Bridge	180:96ed750bd169	209	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	210	}
Anna Bridge	180:96ed750bd169	211	#endif
Anna Bridge	180:96ed750bd169	212
Anna Bridge	180:96ed750bd169	213	#endif /* __CORE_ARMV8MML_H_GENERIC */
Anna Bridge	180:96ed750bd169	214
Anna Bridge	180:96ed750bd169	215	#ifndef __CMSIS_GENERIC
Anna Bridge	180:96ed750bd169	216
Anna Bridge	180:96ed750bd169	217	#ifndef __CORE_ARMV8MML_H_DEPENDANT
Anna Bridge	180:96ed750bd169	218	#define __CORE_ARMV8MML_H_DEPENDANT
Anna Bridge	180:96ed750bd169	219
Anna Bridge	180:96ed750bd169	220	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	221	extern "C" {
Anna Bridge	180:96ed750bd169	222	#endif
Anna Bridge	180:96ed750bd169	223
Anna Bridge	180:96ed750bd169	224	/* check device defines and use defaults */
Anna Bridge	180:96ed750bd169	225	#if defined __CHECK_DEVICE_DEFINES
Anna Bridge	180:96ed750bd169	226	#ifndef __ARMv8MML_REV
Anna Bridge	180:96ed750bd169	227	#define __ARMv8MML_REV 0x0000U
Anna Bridge	180:96ed750bd169	228	#warning "__ARMv8MML_REV not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	229	#endif
Anna Bridge	180:96ed750bd169	230
Anna Bridge	180:96ed750bd169	231	#ifndef __FPU_PRESENT
Anna Bridge	180:96ed750bd169	232	#define __FPU_PRESENT 0U
Anna Bridge	180:96ed750bd169	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	234	#endif
Anna Bridge	180:96ed750bd169	235
Anna Bridge	180:96ed750bd169	236	#ifndef __MPU_PRESENT
Anna Bridge	180:96ed750bd169	237	#define __MPU_PRESENT 0U
Anna Bridge	180:96ed750bd169	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	239	#endif
Anna Bridge	180:96ed750bd169	240
Anna Bridge	180:96ed750bd169	241	#ifndef __SAUREGION_PRESENT
Anna Bridge	180:96ed750bd169	242	#define __SAUREGION_PRESENT 0U
Anna Bridge	180:96ed750bd169	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	244	#endif
Anna Bridge	180:96ed750bd169	245
Anna Bridge	180:96ed750bd169	246	#ifndef __DSP_PRESENT
Anna Bridge	180:96ed750bd169	247	#define __DSP_PRESENT 0U
Anna Bridge	180:96ed750bd169	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	249	#endif
Anna Bridge	180:96ed750bd169	250
Anna Bridge	180:96ed750bd169	251	#ifndef __NVIC_PRIO_BITS
Anna Bridge	180:96ed750bd169	252	#define __NVIC_PRIO_BITS 3U
Anna Bridge	180:96ed750bd169	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	254	#endif
Anna Bridge	180:96ed750bd169	255
Anna Bridge	180:96ed750bd169	256	#ifndef __Vendor_SysTickConfig
Anna Bridge	180:96ed750bd169	257	#define __Vendor_SysTickConfig 0U
Anna Bridge	180:96ed750bd169	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge	180:96ed750bd169	259	#endif
Anna Bridge	180:96ed750bd169	260	#endif
Anna Bridge	180:96ed750bd169	261
Anna Bridge	180:96ed750bd169	262	/* IO definitions (access restrictions to peripheral registers) */
Anna Bridge	180:96ed750bd169	263	/**
Anna Bridge	180:96ed750bd169	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge	180:96ed750bd169	265
Anna Bridge	180:96ed750bd169	266	<strong>IO Type Qualifiers</strong> are used
Anna Bridge	180:96ed750bd169	267	\li to specify the access to peripheral variables.
Anna Bridge	180:96ed750bd169	268	\li for automatic generation of peripheral register debug information.
Anna Bridge	180:96ed750bd169	269	*/
Anna Bridge	180:96ed750bd169	270	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	271	#define __I volatile /!< Defines 'read only' permissions /
Anna Bridge	180:96ed750bd169	272	#else
Anna Bridge	180:96ed750bd169	273	#define __I volatile const /!< Defines 'read only' permissions /
Anna Bridge	180:96ed750bd169	274	#endif
Anna Bridge	180:96ed750bd169	275	#define __O volatile /!< Defines 'write only' permissions /
Anna Bridge	180:96ed750bd169	276	#define __IO volatile /!< Defines 'read / write' permissions /
Anna Bridge	180:96ed750bd169	277
Anna Bridge	180:96ed750bd169	278	/* following defines should be used for structure members */
Anna Bridge	180:96ed750bd169	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
Anna Bridge	180:96ed750bd169	280	#define __OM volatile /! Defines 'write only' structure member permissions /
Anna Bridge	180:96ed750bd169	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
Anna Bridge	180:96ed750bd169	282
Anna Bridge	180:96ed750bd169	283	/@} end of group ARMv8MML /
Anna Bridge	180:96ed750bd169	284
Anna Bridge	180:96ed750bd169	285
Anna Bridge	180:96ed750bd169	286
Anna Bridge	180:96ed750bd169	287	/*******************************************************************************
Anna Bridge	180:96ed750bd169	288	* Register Abstraction
Anna Bridge	180:96ed750bd169	289	Core Register contain:
Anna Bridge	180:96ed750bd169	290	- Core Register
Anna Bridge	180:96ed750bd169	291	- Core NVIC Register
Anna Bridge	180:96ed750bd169	292	- Core SCB Register
Anna Bridge	180:96ed750bd169	293	- Core SysTick Register
Anna Bridge	180:96ed750bd169	294	- Core Debug Register
Anna Bridge	180:96ed750bd169	295	- Core MPU Register
Anna Bridge	180:96ed750bd169	296	- Core SAU Register
Anna Bridge	180:96ed750bd169	297	- Core FPU Register
Anna Bridge	180:96ed750bd169	298	******************************************************************************/
Anna Bridge	180:96ed750bd169	299	/**
Anna Bridge	180:96ed750bd169	300	\defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge	180:96ed750bd169	301	\brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge	180:96ed750bd169	302	*/
Anna Bridge	180:96ed750bd169	303
Anna Bridge	180:96ed750bd169	304	/**
Anna Bridge	180:96ed750bd169	305	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	306	\defgroup CMSIS_CORE Status and Control Registers
Anna Bridge	180:96ed750bd169	307	\brief Core Register type definitions.
Anna Bridge	180:96ed750bd169	308	@{
Anna Bridge	180:96ed750bd169	309	*/
Anna Bridge	180:96ed750bd169	310
Anna Bridge	180:96ed750bd169	311	/**
Anna Bridge	180:96ed750bd169	312	\brief Union type to access the Application Program Status Register (APSR).
Anna Bridge	180:96ed750bd169	313	*/
Anna Bridge	180:96ed750bd169	314	typedef union
Anna Bridge	180:96ed750bd169	315	{
Anna Bridge	180:96ed750bd169	316	struct
Anna Bridge	180:96ed750bd169	317	{
Anna Bridge	180:96ed750bd169	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Anna Bridge	180:96ed750bd169	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	180:96ed750bd169	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Anna Bridge	180:96ed750bd169	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	180:96ed750bd169	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	180:96ed750bd169	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	180:96ed750bd169	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	180:96ed750bd169	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	180:96ed750bd169	326	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	327	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	328	} APSR_Type;
Anna Bridge	180:96ed750bd169	329
Anna Bridge	180:96ed750bd169	330	/* APSR Register Definitions */
Anna Bridge	180:96ed750bd169	331	#define APSR_N_Pos 31U /!< APSR: N Position /
Anna Bridge	180:96ed750bd169	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Anna Bridge	180:96ed750bd169	333
Anna Bridge	180:96ed750bd169	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
Anna Bridge	180:96ed750bd169	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Anna Bridge	180:96ed750bd169	336
Anna Bridge	180:96ed750bd169	337	#define APSR_C_Pos 29U /!< APSR: C Position /
Anna Bridge	180:96ed750bd169	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Anna Bridge	180:96ed750bd169	339
Anna Bridge	180:96ed750bd169	340	#define APSR_V_Pos 28U /!< APSR: V Position /
Anna Bridge	180:96ed750bd169	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Anna Bridge	180:96ed750bd169	342
Anna Bridge	180:96ed750bd169	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
Anna Bridge	180:96ed750bd169	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Anna Bridge	180:96ed750bd169	345
Anna Bridge	180:96ed750bd169	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
Anna Bridge	180:96ed750bd169	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Anna Bridge	180:96ed750bd169	348
Anna Bridge	180:96ed750bd169	349
Anna Bridge	180:96ed750bd169	350	/**
Anna Bridge	180:96ed750bd169	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge	180:96ed750bd169	352	*/
Anna Bridge	180:96ed750bd169	353	typedef union
Anna Bridge	180:96ed750bd169	354	{
Anna Bridge	180:96ed750bd169	355	struct
Anna Bridge	180:96ed750bd169	356	{
Anna Bridge	180:96ed750bd169	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	180:96ed750bd169	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Anna Bridge	180:96ed750bd169	359	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	360	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	361	} IPSR_Type;
Anna Bridge	180:96ed750bd169	362
Anna Bridge	180:96ed750bd169	363	/* IPSR Register Definitions */
Anna Bridge	180:96ed750bd169	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
Anna Bridge	180:96ed750bd169	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Anna Bridge	180:96ed750bd169	366
Anna Bridge	180:96ed750bd169	367
Anna Bridge	180:96ed750bd169	368	/**
Anna Bridge	180:96ed750bd169	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge	180:96ed750bd169	370	*/
Anna Bridge	180:96ed750bd169	371	typedef union
Anna Bridge	180:96ed750bd169	372	{
Anna Bridge	180:96ed750bd169	373	struct
Anna Bridge	180:96ed750bd169	374	{
Anna Bridge	180:96ed750bd169	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	180:96ed750bd169	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Anna Bridge	180:96ed750bd169	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	180:96ed750bd169	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Anna Bridge	180:96ed750bd169	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Anna Bridge	180:96ed750bd169	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Anna Bridge	180:96ed750bd169	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	180:96ed750bd169	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	180:96ed750bd169	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	180:96ed750bd169	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	180:96ed750bd169	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	180:96ed750bd169	386	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	387	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	388	} xPSR_Type;
Anna Bridge	180:96ed750bd169	389
Anna Bridge	180:96ed750bd169	390	/* xPSR Register Definitions */
Anna Bridge	180:96ed750bd169	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
Anna Bridge	180:96ed750bd169	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Anna Bridge	180:96ed750bd169	393
Anna Bridge	180:96ed750bd169	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
Anna Bridge	180:96ed750bd169	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Anna Bridge	180:96ed750bd169	396
Anna Bridge	180:96ed750bd169	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
Anna Bridge	180:96ed750bd169	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Anna Bridge	180:96ed750bd169	399
Anna Bridge	180:96ed750bd169	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
Anna Bridge	180:96ed750bd169	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Anna Bridge	180:96ed750bd169	402
Anna Bridge	180:96ed750bd169	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
Anna Bridge	180:96ed750bd169	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Anna Bridge	180:96ed750bd169	405
Anna Bridge	180:96ed750bd169	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
Anna Bridge	180:96ed750bd169	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Anna Bridge	180:96ed750bd169	408
Anna Bridge	180:96ed750bd169	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
Anna Bridge	180:96ed750bd169	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Anna Bridge	180:96ed750bd169	411
Anna Bridge	180:96ed750bd169	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
Anna Bridge	180:96ed750bd169	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Anna Bridge	180:96ed750bd169	414
Anna Bridge	180:96ed750bd169	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
Anna Bridge	180:96ed750bd169	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Anna Bridge	180:96ed750bd169	417
Anna Bridge	180:96ed750bd169	418
Anna Bridge	180:96ed750bd169	419	/**
Anna Bridge	180:96ed750bd169	420	\brief Union type to access the Control Registers (CONTROL).
Anna Bridge	180:96ed750bd169	421	*/
Anna Bridge	180:96ed750bd169	422	typedef union
Anna Bridge	180:96ed750bd169	423	{
Anna Bridge	180:96ed750bd169	424	struct
Anna Bridge	180:96ed750bd169	425	{
Anna Bridge	180:96ed750bd169	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Anna Bridge	180:96ed750bd169	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
Anna Bridge	180:96ed750bd169	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
Anna Bridge	180:96ed750bd169	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
Anna Bridge	180:96ed750bd169	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
Anna Bridge	180:96ed750bd169	431	} b; /!< Structure used for bit access /
Anna Bridge	180:96ed750bd169	432	uint32_t w; /!< Type used for word access /
Anna Bridge	180:96ed750bd169	433	} CONTROL_Type;
Anna Bridge	180:96ed750bd169	434
Anna Bridge	180:96ed750bd169	435	/* CONTROL Register Definitions */
Anna Bridge	180:96ed750bd169	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
Anna Bridge	180:96ed750bd169	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
Anna Bridge	180:96ed750bd169	438
Anna Bridge	180:96ed750bd169	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
Anna Bridge	180:96ed750bd169	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Anna Bridge	180:96ed750bd169	441
Anna Bridge	180:96ed750bd169	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
Anna Bridge	180:96ed750bd169	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Anna Bridge	180:96ed750bd169	444
Anna Bridge	180:96ed750bd169	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
Anna Bridge	180:96ed750bd169	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Anna Bridge	180:96ed750bd169	447
Anna Bridge	180:96ed750bd169	448	/@} end of group CMSIS_CORE /
Anna Bridge	180:96ed750bd169	449
Anna Bridge	180:96ed750bd169	450
Anna Bridge	180:96ed750bd169	451	/**
Anna Bridge	180:96ed750bd169	452	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge	180:96ed750bd169	454	\brief Type definitions for the NVIC Registers
Anna Bridge	180:96ed750bd169	455	@{
Anna Bridge	180:96ed750bd169	456	*/
Anna Bridge	180:96ed750bd169	457
Anna Bridge	180:96ed750bd169	458	/**
Anna Bridge	180:96ed750bd169	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge	180:96ed750bd169	460	*/
Anna Bridge	180:96ed750bd169	461	typedef struct
Anna Bridge	180:96ed750bd169	462	{
Anna Bridge	180:96ed750bd169	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Anna Bridge	180:96ed750bd169	464	uint32_t RESERVED0[16U];
Anna Bridge	180:96ed750bd169	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Anna Bridge	180:96ed750bd169	466	uint32_t RSERVED1[16U];
Anna Bridge	180:96ed750bd169	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Anna Bridge	180:96ed750bd169	468	uint32_t RESERVED2[16U];
Anna Bridge	180:96ed750bd169	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Anna Bridge	180:96ed750bd169	470	uint32_t RESERVED3[16U];
Anna Bridge	180:96ed750bd169	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Anna Bridge	180:96ed750bd169	472	uint32_t RESERVED4[16U];
Anna Bridge	180:96ed750bd169	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
Anna Bridge	180:96ed750bd169	474	uint32_t RESERVED5[16U];
Anna Bridge	180:96ed750bd169	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Anna Bridge	180:96ed750bd169	476	uint32_t RESERVED6[580U];
Anna Bridge	180:96ed750bd169	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Anna Bridge	180:96ed750bd169	478	} NVIC_Type;
Anna Bridge	180:96ed750bd169	479
Anna Bridge	180:96ed750bd169	480	/* Software Triggered Interrupt Register Definitions */
Anna Bridge	180:96ed750bd169	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
Anna Bridge	180:96ed750bd169	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Anna Bridge	180:96ed750bd169	483
Anna Bridge	180:96ed750bd169	484	/@} end of group CMSIS_NVIC /
Anna Bridge	180:96ed750bd169	485
Anna Bridge	180:96ed750bd169	486
Anna Bridge	180:96ed750bd169	487	/**
Anna Bridge	180:96ed750bd169	488	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	489	\defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge	180:96ed750bd169	490	\brief Type definitions for the System Control Block Registers
Anna Bridge	180:96ed750bd169	491	@{
Anna Bridge	180:96ed750bd169	492	*/
Anna Bridge	180:96ed750bd169	493
Anna Bridge	180:96ed750bd169	494	/**
Anna Bridge	180:96ed750bd169	495	\brief Structure type to access the System Control Block (SCB).
Anna Bridge	180:96ed750bd169	496	*/
Anna Bridge	180:96ed750bd169	497	typedef struct
Anna Bridge	180:96ed750bd169	498	{
Anna Bridge	180:96ed750bd169	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Anna Bridge	180:96ed750bd169	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Anna Bridge	180:96ed750bd169	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Anna Bridge	180:96ed750bd169	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Anna Bridge	180:96ed750bd169	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Anna Bridge	180:96ed750bd169	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Anna Bridge	180:96ed750bd169	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Anna Bridge	180:96ed750bd169	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Anna Bridge	180:96ed750bd169	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Anna Bridge	180:96ed750bd169	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Anna Bridge	180:96ed750bd169	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Anna Bridge	180:96ed750bd169	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Anna Bridge	180:96ed750bd169	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Anna Bridge	180:96ed750bd169	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Anna Bridge	180:96ed750bd169	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Anna Bridge	180:96ed750bd169	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Anna Bridge	180:96ed750bd169	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Anna Bridge	180:96ed750bd169	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Anna Bridge	180:96ed750bd169	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Anna Bridge	180:96ed750bd169	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Anna Bridge	180:96ed750bd169	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Anna Bridge	180:96ed750bd169	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Anna Bridge	180:96ed750bd169	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Anna Bridge	180:96ed750bd169	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Anna Bridge	180:96ed750bd169	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
Anna Bridge	180:96ed750bd169	524	uint32_t RESERVED3[92U];
Anna Bridge	180:96ed750bd169	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Anna Bridge	180:96ed750bd169	526	uint32_t RESERVED4[15U];
Anna Bridge	180:96ed750bd169	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Anna Bridge	180:96ed750bd169	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	180:96ed750bd169	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
Anna Bridge	180:96ed750bd169	530	uint32_t RESERVED5[1U];
Anna Bridge	180:96ed750bd169	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Anna Bridge	180:96ed750bd169	532	uint32_t RESERVED6[1U];
Anna Bridge	180:96ed750bd169	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Anna Bridge	180:96ed750bd169	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Anna Bridge	180:96ed750bd169	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Anna Bridge	180:96ed750bd169	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Anna Bridge	180:96ed750bd169	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Anna Bridge	180:96ed750bd169	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Anna Bridge	180:96ed750bd169	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Anna Bridge	180:96ed750bd169	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Anna Bridge	180:96ed750bd169	541	uint32_t RESERVED7[6U];
Anna Bridge	180:96ed750bd169	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Anna Bridge	180:96ed750bd169	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Anna Bridge	180:96ed750bd169	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Anna Bridge	180:96ed750bd169	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Anna Bridge	180:96ed750bd169	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Anna Bridge	180:96ed750bd169	547	uint32_t RESERVED8[1U];
Anna Bridge	180:96ed750bd169	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Anna Bridge	180:96ed750bd169	549	} SCB_Type;
Anna Bridge	180:96ed750bd169	550
Anna Bridge	180:96ed750bd169	551	/* SCB CPUID Register Definitions */
Anna Bridge	180:96ed750bd169	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
Anna Bridge	180:96ed750bd169	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Anna Bridge	180:96ed750bd169	554
Anna Bridge	180:96ed750bd169	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
Anna Bridge	180:96ed750bd169	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Anna Bridge	180:96ed750bd169	557
Anna Bridge	180:96ed750bd169	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
Anna Bridge	180:96ed750bd169	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Anna Bridge	180:96ed750bd169	560
Anna Bridge	180:96ed750bd169	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
Anna Bridge	180:96ed750bd169	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Anna Bridge	180:96ed750bd169	563
Anna Bridge	180:96ed750bd169	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
Anna Bridge	180:96ed750bd169	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Anna Bridge	180:96ed750bd169	566
Anna Bridge	180:96ed750bd169	567	/* SCB Interrupt Control State Register Definitions */
Anna Bridge	180:96ed750bd169	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
Anna Bridge	180:96ed750bd169	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
Anna Bridge	180:96ed750bd169	570
AnnaBridge	188:bcfe06ba3d64	571	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
AnnaBridge	188:bcfe06ba3d64	572	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
AnnaBridge	188:bcfe06ba3d64	573
Anna Bridge	180:96ed750bd169	574	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
Anna Bridge	180:96ed750bd169	575	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
Anna Bridge	180:96ed750bd169	576
Anna Bridge	180:96ed750bd169	577	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
Anna Bridge	180:96ed750bd169	578	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Anna Bridge	180:96ed750bd169	579
Anna Bridge	180:96ed750bd169	580	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
Anna Bridge	180:96ed750bd169	581	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Anna Bridge	180:96ed750bd169	582
Anna Bridge	180:96ed750bd169	583	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
Anna Bridge	180:96ed750bd169	584	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Anna Bridge	180:96ed750bd169	585
Anna Bridge	180:96ed750bd169	586	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
Anna Bridge	180:96ed750bd169	587	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Anna Bridge	180:96ed750bd169	588
Anna Bridge	180:96ed750bd169	589	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
Anna Bridge	180:96ed750bd169	590	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
Anna Bridge	180:96ed750bd169	591
Anna Bridge	180:96ed750bd169	592	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
Anna Bridge	180:96ed750bd169	593	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Anna Bridge	180:96ed750bd169	594
Anna Bridge	180:96ed750bd169	595	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
Anna Bridge	180:96ed750bd169	596	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Anna Bridge	180:96ed750bd169	597
Anna Bridge	180:96ed750bd169	598	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
Anna Bridge	180:96ed750bd169	599	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Anna Bridge	180:96ed750bd169	600
Anna Bridge	180:96ed750bd169	601	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
Anna Bridge	180:96ed750bd169	602	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Anna Bridge	180:96ed750bd169	603
Anna Bridge	180:96ed750bd169	604	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
Anna Bridge	180:96ed750bd169	605	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Anna Bridge	180:96ed750bd169	606
Anna Bridge	180:96ed750bd169	607	/* SCB Vector Table Offset Register Definitions */
Anna Bridge	180:96ed750bd169	608	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Anna Bridge	180:96ed750bd169	609	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Anna Bridge	180:96ed750bd169	610
Anna Bridge	180:96ed750bd169	611	/* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge	180:96ed750bd169	612	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
Anna Bridge	180:96ed750bd169	613	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Anna Bridge	180:96ed750bd169	614
Anna Bridge	180:96ed750bd169	615	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
Anna Bridge	180:96ed750bd169	616	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Anna Bridge	180:96ed750bd169	617
Anna Bridge	180:96ed750bd169	618	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
Anna Bridge	180:96ed750bd169	619	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Anna Bridge	180:96ed750bd169	620
Anna Bridge	180:96ed750bd169	621	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
Anna Bridge	180:96ed750bd169	622	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
Anna Bridge	180:96ed750bd169	623
Anna Bridge	180:96ed750bd169	624	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
Anna Bridge	180:96ed750bd169	625	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
Anna Bridge	180:96ed750bd169	626
Anna Bridge	180:96ed750bd169	627	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
Anna Bridge	180:96ed750bd169	628	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Anna Bridge	180:96ed750bd169	629
Anna Bridge	180:96ed750bd169	630	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
Anna Bridge	180:96ed750bd169	631	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
Anna Bridge	180:96ed750bd169	632
Anna Bridge	180:96ed750bd169	633	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
Anna Bridge	180:96ed750bd169	634	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Anna Bridge	180:96ed750bd169	635
Anna Bridge	180:96ed750bd169	636	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
Anna Bridge	180:96ed750bd169	637	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Anna Bridge	180:96ed750bd169	638
Anna Bridge	180:96ed750bd169	639	/* SCB System Control Register Definitions */
Anna Bridge	180:96ed750bd169	640	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
Anna Bridge	180:96ed750bd169	641	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Anna Bridge	180:96ed750bd169	642
Anna Bridge	180:96ed750bd169	643	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
Anna Bridge	180:96ed750bd169	644	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
Anna Bridge	180:96ed750bd169	645
Anna Bridge	180:96ed750bd169	646	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
Anna Bridge	180:96ed750bd169	647	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Anna Bridge	180:96ed750bd169	648
Anna Bridge	180:96ed750bd169	649	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
Anna Bridge	180:96ed750bd169	650	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Anna Bridge	180:96ed750bd169	651
Anna Bridge	180:96ed750bd169	652	/* SCB Configuration Control Register Definitions */
Anna Bridge	180:96ed750bd169	653	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
Anna Bridge	180:96ed750bd169	654	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
Anna Bridge	180:96ed750bd169	655
Anna Bridge	180:96ed750bd169	656	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
Anna Bridge	180:96ed750bd169	657	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
Anna Bridge	180:96ed750bd169	658
Anna Bridge	180:96ed750bd169	659	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
Anna Bridge	180:96ed750bd169	660	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
Anna Bridge	180:96ed750bd169	661
Anna Bridge	180:96ed750bd169	662	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
Anna Bridge	180:96ed750bd169	663	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
Anna Bridge	180:96ed750bd169	664
Anna Bridge	180:96ed750bd169	665	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
Anna Bridge	180:96ed750bd169	666	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Anna Bridge	180:96ed750bd169	667
Anna Bridge	180:96ed750bd169	668	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
Anna Bridge	180:96ed750bd169	669	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Anna Bridge	180:96ed750bd169	670
Anna Bridge	180:96ed750bd169	671	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
Anna Bridge	180:96ed750bd169	672	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Anna Bridge	180:96ed750bd169	673
Anna Bridge	180:96ed750bd169	674	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
Anna Bridge	180:96ed750bd169	675	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Anna Bridge	180:96ed750bd169	676
Anna Bridge	180:96ed750bd169	677	/* SCB System Handler Control and State Register Definitions */
Anna Bridge	180:96ed750bd169	678	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	679	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	680
Anna Bridge	180:96ed750bd169	681	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	682	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	683
Anna Bridge	180:96ed750bd169	684	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
Anna Bridge	180:96ed750bd169	685	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
Anna Bridge	180:96ed750bd169	686
Anna Bridge	180:96ed750bd169	687	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
Anna Bridge	180:96ed750bd169	688	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Anna Bridge	180:96ed750bd169	689
Anna Bridge	180:96ed750bd169	690	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
Anna Bridge	180:96ed750bd169	691	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Anna Bridge	180:96ed750bd169	692
Anna Bridge	180:96ed750bd169	693	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
Anna Bridge	180:96ed750bd169	694	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Anna Bridge	180:96ed750bd169	695
Anna Bridge	180:96ed750bd169	696	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
Anna Bridge	180:96ed750bd169	697	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Anna Bridge	180:96ed750bd169	698
Anna Bridge	180:96ed750bd169	699	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	700	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	701
Anna Bridge	180:96ed750bd169	702	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	703	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	704
Anna Bridge	180:96ed750bd169	705	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
Anna Bridge	180:96ed750bd169	706	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Anna Bridge	180:96ed750bd169	707
Anna Bridge	180:96ed750bd169	708	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
Anna Bridge	180:96ed750bd169	709	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Anna Bridge	180:96ed750bd169	710
Anna Bridge	180:96ed750bd169	711	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
Anna Bridge	180:96ed750bd169	712	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Anna Bridge	180:96ed750bd169	713
Anna Bridge	180:96ed750bd169	714	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
Anna Bridge	180:96ed750bd169	715	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Anna Bridge	180:96ed750bd169	716
Anna Bridge	180:96ed750bd169	717	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
Anna Bridge	180:96ed750bd169	718	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Anna Bridge	180:96ed750bd169	719
Anna Bridge	180:96ed750bd169	720	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
Anna Bridge	180:96ed750bd169	721	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
Anna Bridge	180:96ed750bd169	722
Anna Bridge	180:96ed750bd169	723	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
Anna Bridge	180:96ed750bd169	724	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
Anna Bridge	180:96ed750bd169	725
Anna Bridge	180:96ed750bd169	726	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
Anna Bridge	180:96ed750bd169	727	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Anna Bridge	180:96ed750bd169	728
Anna Bridge	180:96ed750bd169	729	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
Anna Bridge	180:96ed750bd169	730	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
Anna Bridge	180:96ed750bd169	731
Anna Bridge	180:96ed750bd169	732	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
Anna Bridge	180:96ed750bd169	733	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Anna Bridge	180:96ed750bd169	734
Anna Bridge	180:96ed750bd169	735	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
Anna Bridge	180:96ed750bd169	736	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Anna Bridge	180:96ed750bd169	737
Anna Bridge	180:96ed750bd169	738	/* SCB Configurable Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	739	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
Anna Bridge	180:96ed750bd169	740	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	741
Anna Bridge	180:96ed750bd169	742	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
Anna Bridge	180:96ed750bd169	743	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	744
Anna Bridge	180:96ed750bd169	745	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
Anna Bridge	180:96ed750bd169	746	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Anna Bridge	180:96ed750bd169	747
Anna Bridge	180:96ed750bd169	748	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	749	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
Anna Bridge	180:96ed750bd169	750	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
Anna Bridge	180:96ed750bd169	751
Anna Bridge	180:96ed750bd169	752	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
Anna Bridge	180:96ed750bd169	753	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
Anna Bridge	180:96ed750bd169	754
Anna Bridge	180:96ed750bd169	755	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
Anna Bridge	180:96ed750bd169	756	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
Anna Bridge	180:96ed750bd169	757
Anna Bridge	180:96ed750bd169	758	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
Anna Bridge	180:96ed750bd169	759	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
Anna Bridge	180:96ed750bd169	760
Anna Bridge	180:96ed750bd169	761	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
Anna Bridge	180:96ed750bd169	762	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
Anna Bridge	180:96ed750bd169	763
Anna Bridge	180:96ed750bd169	764	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
Anna Bridge	180:96ed750bd169	765	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
Anna Bridge	180:96ed750bd169	766
Anna Bridge	180:96ed750bd169	767	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	768	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
Anna Bridge	180:96ed750bd169	769	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
Anna Bridge	180:96ed750bd169	770
Anna Bridge	180:96ed750bd169	771	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
Anna Bridge	180:96ed750bd169	772	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
Anna Bridge	180:96ed750bd169	773
Anna Bridge	180:96ed750bd169	774	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
Anna Bridge	180:96ed750bd169	775	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
Anna Bridge	180:96ed750bd169	776
Anna Bridge	180:96ed750bd169	777	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
Anna Bridge	180:96ed750bd169	778	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
Anna Bridge	180:96ed750bd169	779
Anna Bridge	180:96ed750bd169	780	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
Anna Bridge	180:96ed750bd169	781	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
Anna Bridge	180:96ed750bd169	782
Anna Bridge	180:96ed750bd169	783	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
Anna Bridge	180:96ed750bd169	784	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
Anna Bridge	180:96ed750bd169	785
Anna Bridge	180:96ed750bd169	786	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
Anna Bridge	180:96ed750bd169	787	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
Anna Bridge	180:96ed750bd169	788
Anna Bridge	180:96ed750bd169	789	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	180:96ed750bd169	790	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
Anna Bridge	180:96ed750bd169	791	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
Anna Bridge	180:96ed750bd169	792
Anna Bridge	180:96ed750bd169	793	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
Anna Bridge	180:96ed750bd169	794	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
Anna Bridge	180:96ed750bd169	795
Anna Bridge	180:96ed750bd169	796	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
Anna Bridge	180:96ed750bd169	797	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
Anna Bridge	180:96ed750bd169	798
Anna Bridge	180:96ed750bd169	799	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
Anna Bridge	180:96ed750bd169	800	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
Anna Bridge	180:96ed750bd169	801
Anna Bridge	180:96ed750bd169	802	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
Anna Bridge	180:96ed750bd169	803	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
Anna Bridge	180:96ed750bd169	804
Anna Bridge	180:96ed750bd169	805	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
Anna Bridge	180:96ed750bd169	806	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
Anna Bridge	180:96ed750bd169	807
Anna Bridge	180:96ed750bd169	808	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
Anna Bridge	180:96ed750bd169	809	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
Anna Bridge	180:96ed750bd169	810
Anna Bridge	180:96ed750bd169	811	/* SCB Hard Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	812	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
Anna Bridge	180:96ed750bd169	813	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Anna Bridge	180:96ed750bd169	814
Anna Bridge	180:96ed750bd169	815	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
Anna Bridge	180:96ed750bd169	816	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Anna Bridge	180:96ed750bd169	817
Anna Bridge	180:96ed750bd169	818	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
Anna Bridge	180:96ed750bd169	819	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Anna Bridge	180:96ed750bd169	820
Anna Bridge	180:96ed750bd169	821	/* SCB Debug Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	822	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
Anna Bridge	180:96ed750bd169	823	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Anna Bridge	180:96ed750bd169	824
Anna Bridge	180:96ed750bd169	825	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
Anna Bridge	180:96ed750bd169	826	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Anna Bridge	180:96ed750bd169	827
Anna Bridge	180:96ed750bd169	828	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
Anna Bridge	180:96ed750bd169	829	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Anna Bridge	180:96ed750bd169	830
Anna Bridge	180:96ed750bd169	831	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
Anna Bridge	180:96ed750bd169	832	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Anna Bridge	180:96ed750bd169	833
Anna Bridge	180:96ed750bd169	834	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
Anna Bridge	180:96ed750bd169	835	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Anna Bridge	180:96ed750bd169	836
Anna Bridge	180:96ed750bd169	837	/* SCB Non-Secure Access Control Register Definitions */
Anna Bridge	180:96ed750bd169	838	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
Anna Bridge	180:96ed750bd169	839	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
Anna Bridge	180:96ed750bd169	840
Anna Bridge	180:96ed750bd169	841	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
Anna Bridge	180:96ed750bd169	842	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
Anna Bridge	180:96ed750bd169	843
Anna Bridge	180:96ed750bd169	844	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
Anna Bridge	180:96ed750bd169	845	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
Anna Bridge	180:96ed750bd169	846
Anna Bridge	180:96ed750bd169	847	/* SCB Cache Level ID Register Definitions */
Anna Bridge	180:96ed750bd169	848	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
Anna Bridge	180:96ed750bd169	849	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Anna Bridge	180:96ed750bd169	850
Anna Bridge	180:96ed750bd169	851	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
Anna Bridge	180:96ed750bd169	852	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
Anna Bridge	180:96ed750bd169	853
Anna Bridge	180:96ed750bd169	854	/* SCB Cache Type Register Definitions */
Anna Bridge	180:96ed750bd169	855	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
Anna Bridge	180:96ed750bd169	856	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Anna Bridge	180:96ed750bd169	857
Anna Bridge	180:96ed750bd169	858	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
Anna Bridge	180:96ed750bd169	859	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Anna Bridge	180:96ed750bd169	860
Anna Bridge	180:96ed750bd169	861	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
Anna Bridge	180:96ed750bd169	862	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Anna Bridge	180:96ed750bd169	863
Anna Bridge	180:96ed750bd169	864	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
Anna Bridge	180:96ed750bd169	865	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Anna Bridge	180:96ed750bd169	866
Anna Bridge	180:96ed750bd169	867	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
Anna Bridge	180:96ed750bd169	868	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Anna Bridge	180:96ed750bd169	869
Anna Bridge	180:96ed750bd169	870	/* SCB Cache Size ID Register Definitions */
Anna Bridge	180:96ed750bd169	871	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
Anna Bridge	180:96ed750bd169	872	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Anna Bridge	180:96ed750bd169	873
Anna Bridge	180:96ed750bd169	874	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
Anna Bridge	180:96ed750bd169	875	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Anna Bridge	180:96ed750bd169	876
Anna Bridge	180:96ed750bd169	877	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
Anna Bridge	180:96ed750bd169	878	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Anna Bridge	180:96ed750bd169	879
Anna Bridge	180:96ed750bd169	880	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
Anna Bridge	180:96ed750bd169	881	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Anna Bridge	180:96ed750bd169	882
Anna Bridge	180:96ed750bd169	883	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
Anna Bridge	180:96ed750bd169	884	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Anna Bridge	180:96ed750bd169	885
Anna Bridge	180:96ed750bd169	886	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
Anna Bridge	180:96ed750bd169	887	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Anna Bridge	180:96ed750bd169	888
Anna Bridge	180:96ed750bd169	889	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
Anna Bridge	180:96ed750bd169	890	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Anna Bridge	180:96ed750bd169	891
Anna Bridge	180:96ed750bd169	892	/* SCB Cache Size Selection Register Definitions */
Anna Bridge	180:96ed750bd169	893	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
Anna Bridge	180:96ed750bd169	894	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Anna Bridge	180:96ed750bd169	895
Anna Bridge	180:96ed750bd169	896	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
Anna Bridge	180:96ed750bd169	897	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Anna Bridge	180:96ed750bd169	898
Anna Bridge	180:96ed750bd169	899	/* SCB Software Triggered Interrupt Register Definitions */
Anna Bridge	180:96ed750bd169	900	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
Anna Bridge	180:96ed750bd169	901	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Anna Bridge	180:96ed750bd169	902
Anna Bridge	180:96ed750bd169	903	/* SCB D-Cache Invalidate by Set-way Register Definitions */
Anna Bridge	180:96ed750bd169	904	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
Anna Bridge	180:96ed750bd169	905	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
Anna Bridge	180:96ed750bd169	906
Anna Bridge	180:96ed750bd169	907	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
Anna Bridge	180:96ed750bd169	908	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
Anna Bridge	180:96ed750bd169	909
Anna Bridge	180:96ed750bd169	910	/* SCB D-Cache Clean by Set-way Register Definitions */
Anna Bridge	180:96ed750bd169	911	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
Anna Bridge	180:96ed750bd169	912	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
Anna Bridge	180:96ed750bd169	913
Anna Bridge	180:96ed750bd169	914	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
Anna Bridge	180:96ed750bd169	915	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
Anna Bridge	180:96ed750bd169	916
Anna Bridge	180:96ed750bd169	917	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
Anna Bridge	180:96ed750bd169	918	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
Anna Bridge	180:96ed750bd169	919	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
Anna Bridge	180:96ed750bd169	920
Anna Bridge	180:96ed750bd169	921	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
Anna Bridge	180:96ed750bd169	922	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
Anna Bridge	180:96ed750bd169	923
Anna Bridge	180:96ed750bd169	924	/* Instruction Tightly-Coupled Memory Control Register Definitions */
Anna Bridge	180:96ed750bd169	925	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
Anna Bridge	180:96ed750bd169	926	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Anna Bridge	180:96ed750bd169	927
Anna Bridge	180:96ed750bd169	928	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
Anna Bridge	180:96ed750bd169	929	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Anna Bridge	180:96ed750bd169	930
Anna Bridge	180:96ed750bd169	931	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
Anna Bridge	180:96ed750bd169	932	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Anna Bridge	180:96ed750bd169	933
Anna Bridge	180:96ed750bd169	934	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
Anna Bridge	180:96ed750bd169	935	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Anna Bridge	180:96ed750bd169	936
Anna Bridge	180:96ed750bd169	937	/* Data Tightly-Coupled Memory Control Register Definitions */
Anna Bridge	180:96ed750bd169	938	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
Anna Bridge	180:96ed750bd169	939	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Anna Bridge	180:96ed750bd169	940
Anna Bridge	180:96ed750bd169	941	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
Anna Bridge	180:96ed750bd169	942	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Anna Bridge	180:96ed750bd169	943
Anna Bridge	180:96ed750bd169	944	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
Anna Bridge	180:96ed750bd169	945	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Anna Bridge	180:96ed750bd169	946
Anna Bridge	180:96ed750bd169	947	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
Anna Bridge	180:96ed750bd169	948	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Anna Bridge	180:96ed750bd169	949
Anna Bridge	180:96ed750bd169	950	/* AHBP Control Register Definitions */
Anna Bridge	180:96ed750bd169	951	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
Anna Bridge	180:96ed750bd169	952	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Anna Bridge	180:96ed750bd169	953
Anna Bridge	180:96ed750bd169	954	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
Anna Bridge	180:96ed750bd169	955	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Anna Bridge	180:96ed750bd169	956
Anna Bridge	180:96ed750bd169	957	/* L1 Cache Control Register Definitions */
Anna Bridge	180:96ed750bd169	958	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
Anna Bridge	180:96ed750bd169	959	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Anna Bridge	180:96ed750bd169	960
Anna Bridge	180:96ed750bd169	961	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
Anna Bridge	180:96ed750bd169	962	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Anna Bridge	180:96ed750bd169	963
Anna Bridge	180:96ed750bd169	964	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
Anna Bridge	180:96ed750bd169	965	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Anna Bridge	180:96ed750bd169	966
Anna Bridge	180:96ed750bd169	967	/* AHBS Control Register Definitions */
Anna Bridge	180:96ed750bd169	968	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
Anna Bridge	180:96ed750bd169	969	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Anna Bridge	180:96ed750bd169	970
Anna Bridge	180:96ed750bd169	971	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
Anna Bridge	180:96ed750bd169	972	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Anna Bridge	180:96ed750bd169	973
Anna Bridge	180:96ed750bd169	974	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
Anna Bridge	180:96ed750bd169	975	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Anna Bridge	180:96ed750bd169	976
Anna Bridge	180:96ed750bd169	977	/* Auxiliary Bus Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	978	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
Anna Bridge	180:96ed750bd169	979	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Anna Bridge	180:96ed750bd169	980
Anna Bridge	180:96ed750bd169	981	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
Anna Bridge	180:96ed750bd169	982	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Anna Bridge	180:96ed750bd169	983
Anna Bridge	180:96ed750bd169	984	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
Anna Bridge	180:96ed750bd169	985	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Anna Bridge	180:96ed750bd169	986
Anna Bridge	180:96ed750bd169	987	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
Anna Bridge	180:96ed750bd169	988	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Anna Bridge	180:96ed750bd169	989
Anna Bridge	180:96ed750bd169	990	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
Anna Bridge	180:96ed750bd169	991	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Anna Bridge	180:96ed750bd169	992
Anna Bridge	180:96ed750bd169	993	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
Anna Bridge	180:96ed750bd169	994	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Anna Bridge	180:96ed750bd169	995
Anna Bridge	180:96ed750bd169	996	/@} end of group CMSIS_SCB /
Anna Bridge	180:96ed750bd169	997
Anna Bridge	180:96ed750bd169	998
Anna Bridge	180:96ed750bd169	999	/**
Anna Bridge	180:96ed750bd169	1000	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1001	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge	180:96ed750bd169	1002	\brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge	180:96ed750bd169	1003	@{
Anna Bridge	180:96ed750bd169	1004	*/
Anna Bridge	180:96ed750bd169	1005
Anna Bridge	180:96ed750bd169	1006	/**
Anna Bridge	180:96ed750bd169	1007	\brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge	180:96ed750bd169	1008	*/
Anna Bridge	180:96ed750bd169	1009	typedef struct
Anna Bridge	180:96ed750bd169	1010	{
Anna Bridge	180:96ed750bd169	1011	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	1012	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Anna Bridge	180:96ed750bd169	1013	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Anna Bridge	180:96ed750bd169	1014	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
Anna Bridge	180:96ed750bd169	1015	} SCnSCB_Type;
Anna Bridge	180:96ed750bd169	1016
Anna Bridge	180:96ed750bd169	1017	/* Interrupt Controller Type Register Definitions */
Anna Bridge	180:96ed750bd169	1018	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
Anna Bridge	180:96ed750bd169	1019	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Anna Bridge	180:96ed750bd169	1020
Anna Bridge	180:96ed750bd169	1021	/@} end of group CMSIS_SCnotSCB /
Anna Bridge	180:96ed750bd169	1022
Anna Bridge	180:96ed750bd169	1023
Anna Bridge	180:96ed750bd169	1024	/**
Anna Bridge	180:96ed750bd169	1025	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1026	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge	180:96ed750bd169	1027	\brief Type definitions for the System Timer Registers.
Anna Bridge	180:96ed750bd169	1028	@{
Anna Bridge	180:96ed750bd169	1029	*/
Anna Bridge	180:96ed750bd169	1030
Anna Bridge	180:96ed750bd169	1031	/**
Anna Bridge	180:96ed750bd169	1032	\brief Structure type to access the System Timer (SysTick).
Anna Bridge	180:96ed750bd169	1033	*/
Anna Bridge	180:96ed750bd169	1034	typedef struct
Anna Bridge	180:96ed750bd169	1035	{
Anna Bridge	180:96ed750bd169	1036	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Anna Bridge	180:96ed750bd169	1037	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Anna Bridge	180:96ed750bd169	1038	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Anna Bridge	180:96ed750bd169	1039	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Anna Bridge	180:96ed750bd169	1040	} SysTick_Type;
Anna Bridge	180:96ed750bd169	1041
Anna Bridge	180:96ed750bd169	1042	/* SysTick Control / Status Register Definitions */
Anna Bridge	180:96ed750bd169	1043	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
Anna Bridge	180:96ed750bd169	1044	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Anna Bridge	180:96ed750bd169	1045
Anna Bridge	180:96ed750bd169	1046	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
Anna Bridge	180:96ed750bd169	1047	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Anna Bridge	180:96ed750bd169	1048
Anna Bridge	180:96ed750bd169	1049	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
Anna Bridge	180:96ed750bd169	1050	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Anna Bridge	180:96ed750bd169	1051
Anna Bridge	180:96ed750bd169	1052	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	1053	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	1054
Anna Bridge	180:96ed750bd169	1055	/* SysTick Reload Register Definitions */
Anna Bridge	180:96ed750bd169	1056	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
Anna Bridge	180:96ed750bd169	1057	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Anna Bridge	180:96ed750bd169	1058
Anna Bridge	180:96ed750bd169	1059	/* SysTick Current Register Definitions */
Anna Bridge	180:96ed750bd169	1060	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
Anna Bridge	180:96ed750bd169	1061	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Anna Bridge	180:96ed750bd169	1062
Anna Bridge	180:96ed750bd169	1063	/* SysTick Calibration Register Definitions */
Anna Bridge	180:96ed750bd169	1064	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
Anna Bridge	180:96ed750bd169	1065	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Anna Bridge	180:96ed750bd169	1066
Anna Bridge	180:96ed750bd169	1067	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
Anna Bridge	180:96ed750bd169	1068	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Anna Bridge	180:96ed750bd169	1069
Anna Bridge	180:96ed750bd169	1070	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
Anna Bridge	180:96ed750bd169	1071	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Anna Bridge	180:96ed750bd169	1072
Anna Bridge	180:96ed750bd169	1073	/@} end of group CMSIS_SysTick /
Anna Bridge	180:96ed750bd169	1074
Anna Bridge	180:96ed750bd169	1075
Anna Bridge	180:96ed750bd169	1076	/**
Anna Bridge	180:96ed750bd169	1077	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1078	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge	180:96ed750bd169	1079	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge	180:96ed750bd169	1080	@{
Anna Bridge	180:96ed750bd169	1081	*/
Anna Bridge	180:96ed750bd169	1082
Anna Bridge	180:96ed750bd169	1083	/**
Anna Bridge	180:96ed750bd169	1084	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge	180:96ed750bd169	1085	*/
Anna Bridge	180:96ed750bd169	1086	typedef struct
Anna Bridge	180:96ed750bd169	1087	{
Anna Bridge	180:96ed750bd169	1088	__OM union
Anna Bridge	180:96ed750bd169	1089	{
Anna Bridge	180:96ed750bd169	1090	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Anna Bridge	180:96ed750bd169	1091	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Anna Bridge	180:96ed750bd169	1092	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Anna Bridge	180:96ed750bd169	1093	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Anna Bridge	180:96ed750bd169	1094	uint32_t RESERVED0[864U];
Anna Bridge	180:96ed750bd169	1095	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Anna Bridge	180:96ed750bd169	1096	uint32_t RESERVED1[15U];
Anna Bridge	180:96ed750bd169	1097	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Anna Bridge	180:96ed750bd169	1098	uint32_t RESERVED2[15U];
Anna Bridge	180:96ed750bd169	1099	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Anna Bridge	180:96ed750bd169	1100	uint32_t RESERVED3[29U];
Anna Bridge	180:96ed750bd169	1101	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Anna Bridge	180:96ed750bd169	1102	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Anna Bridge	180:96ed750bd169	1103	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Anna Bridge	180:96ed750bd169	1104	uint32_t RESERVED4[43U];
Anna Bridge	180:96ed750bd169	1105	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Anna Bridge	180:96ed750bd169	1106	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Anna Bridge	180:96ed750bd169	1107	uint32_t RESERVED5[1U];
Anna Bridge	180:96ed750bd169	1108	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
Anna Bridge	180:96ed750bd169	1109	uint32_t RESERVED6[4U];
Anna Bridge	180:96ed750bd169	1110	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Anna Bridge	180:96ed750bd169	1111	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Anna Bridge	180:96ed750bd169	1112	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Anna Bridge	180:96ed750bd169	1113	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Anna Bridge	180:96ed750bd169	1114	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Anna Bridge	180:96ed750bd169	1115	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Anna Bridge	180:96ed750bd169	1116	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Anna Bridge	180:96ed750bd169	1117	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Anna Bridge	180:96ed750bd169	1118	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Anna Bridge	180:96ed750bd169	1119	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Anna Bridge	180:96ed750bd169	1120	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Anna Bridge	180:96ed750bd169	1121	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Anna Bridge	180:96ed750bd169	1122	} ITM_Type;
Anna Bridge	180:96ed750bd169	1123
Anna Bridge	180:96ed750bd169	1124	/* ITM Stimulus Port Register Definitions */
Anna Bridge	180:96ed750bd169	1125	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
Anna Bridge	180:96ed750bd169	1126	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
Anna Bridge	180:96ed750bd169	1127
Anna Bridge	180:96ed750bd169	1128	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
Anna Bridge	180:96ed750bd169	1129	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
Anna Bridge	180:96ed750bd169	1130
Anna Bridge	180:96ed750bd169	1131	/* ITM Trace Privilege Register Definitions */
Anna Bridge	180:96ed750bd169	1132	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	180:96ed750bd169	1133	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Anna Bridge	180:96ed750bd169	1134
Anna Bridge	180:96ed750bd169	1135	/* ITM Trace Control Register Definitions */
Anna Bridge	180:96ed750bd169	1136	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
Anna Bridge	180:96ed750bd169	1137	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Anna Bridge	180:96ed750bd169	1138
Anna Bridge	180:96ed750bd169	1139	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
Anna Bridge	180:96ed750bd169	1140	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
Anna Bridge	180:96ed750bd169	1141
Anna Bridge	180:96ed750bd169	1142	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
Anna Bridge	180:96ed750bd169	1143	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Anna Bridge	180:96ed750bd169	1144
Anna Bridge	180:96ed750bd169	1145	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
Anna Bridge	180:96ed750bd169	1146	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
Anna Bridge	180:96ed750bd169	1147
Anna Bridge	180:96ed750bd169	1148	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
Anna Bridge	180:96ed750bd169	1149	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
Anna Bridge	180:96ed750bd169	1150
Anna Bridge	180:96ed750bd169	1151	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
Anna Bridge	180:96ed750bd169	1152	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Anna Bridge	180:96ed750bd169	1153
Anna Bridge	180:96ed750bd169	1154	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
Anna Bridge	180:96ed750bd169	1155	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Anna Bridge	180:96ed750bd169	1156
Anna Bridge	180:96ed750bd169	1157	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
Anna Bridge	180:96ed750bd169	1158	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Anna Bridge	180:96ed750bd169	1159
Anna Bridge	180:96ed750bd169	1160	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
Anna Bridge	180:96ed750bd169	1161	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Anna Bridge	180:96ed750bd169	1162
Anna Bridge	180:96ed750bd169	1163	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
Anna Bridge	180:96ed750bd169	1164	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Anna Bridge	180:96ed750bd169	1165
Anna Bridge	180:96ed750bd169	1166	/* ITM Integration Write Register Definitions */
Anna Bridge	180:96ed750bd169	1167	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
Anna Bridge	180:96ed750bd169	1168	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Anna Bridge	180:96ed750bd169	1169
Anna Bridge	180:96ed750bd169	1170	/* ITM Integration Read Register Definitions */
Anna Bridge	180:96ed750bd169	1171	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
Anna Bridge	180:96ed750bd169	1172	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Anna Bridge	180:96ed750bd169	1173
Anna Bridge	180:96ed750bd169	1174	/* ITM Integration Mode Control Register Definitions */
Anna Bridge	180:96ed750bd169	1175	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
Anna Bridge	180:96ed750bd169	1176	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Anna Bridge	180:96ed750bd169	1177
Anna Bridge	180:96ed750bd169	1178	/* ITM Lock Status Register Definitions */
Anna Bridge	180:96ed750bd169	1179	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
Anna Bridge	180:96ed750bd169	1180	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Anna Bridge	180:96ed750bd169	1181
Anna Bridge	180:96ed750bd169	1182	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
Anna Bridge	180:96ed750bd169	1183	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Anna Bridge	180:96ed750bd169	1184
Anna Bridge	180:96ed750bd169	1185	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
Anna Bridge	180:96ed750bd169	1186	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Anna Bridge	180:96ed750bd169	1187
Anna Bridge	180:96ed750bd169	1188	/@}/ /* end of group CMSIS_ITM */
Anna Bridge	180:96ed750bd169	1189
Anna Bridge	180:96ed750bd169	1190
Anna Bridge	180:96ed750bd169	1191	/**
Anna Bridge	180:96ed750bd169	1192	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1193	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge	180:96ed750bd169	1194	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge	180:96ed750bd169	1195	@{
Anna Bridge	180:96ed750bd169	1196	*/
Anna Bridge	180:96ed750bd169	1197
Anna Bridge	180:96ed750bd169	1198	/**
Anna Bridge	180:96ed750bd169	1199	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge	180:96ed750bd169	1200	*/
Anna Bridge	180:96ed750bd169	1201	typedef struct
Anna Bridge	180:96ed750bd169	1202	{
Anna Bridge	180:96ed750bd169	1203	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Anna Bridge	180:96ed750bd169	1204	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Anna Bridge	180:96ed750bd169	1205	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Anna Bridge	180:96ed750bd169	1206	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Anna Bridge	180:96ed750bd169	1207	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Anna Bridge	180:96ed750bd169	1208	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Anna Bridge	180:96ed750bd169	1209	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Anna Bridge	180:96ed750bd169	1210	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Anna Bridge	180:96ed750bd169	1211	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Anna Bridge	180:96ed750bd169	1212	uint32_t RESERVED1[1U];
Anna Bridge	180:96ed750bd169	1213	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Anna Bridge	180:96ed750bd169	1214	uint32_t RESERVED2[1U];
Anna Bridge	180:96ed750bd169	1215	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Anna Bridge	180:96ed750bd169	1216	uint32_t RESERVED3[1U];
Anna Bridge	180:96ed750bd169	1217	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Anna Bridge	180:96ed750bd169	1218	uint32_t RESERVED4[1U];
Anna Bridge	180:96ed750bd169	1219	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Anna Bridge	180:96ed750bd169	1220	uint32_t RESERVED5[1U];
Anna Bridge	180:96ed750bd169	1221	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Anna Bridge	180:96ed750bd169	1222	uint32_t RESERVED6[1U];
Anna Bridge	180:96ed750bd169	1223	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Anna Bridge	180:96ed750bd169	1224	uint32_t RESERVED7[1U];
Anna Bridge	180:96ed750bd169	1225	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Anna Bridge	180:96ed750bd169	1226	uint32_t RESERVED8[1U];
Anna Bridge	180:96ed750bd169	1227	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
Anna Bridge	180:96ed750bd169	1228	uint32_t RESERVED9[1U];
Anna Bridge	180:96ed750bd169	1229	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
Anna Bridge	180:96ed750bd169	1230	uint32_t RESERVED10[1U];
Anna Bridge	180:96ed750bd169	1231	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
Anna Bridge	180:96ed750bd169	1232	uint32_t RESERVED11[1U];
Anna Bridge	180:96ed750bd169	1233	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
Anna Bridge	180:96ed750bd169	1234	uint32_t RESERVED12[1U];
Anna Bridge	180:96ed750bd169	1235	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
Anna Bridge	180:96ed750bd169	1236	uint32_t RESERVED13[1U];
Anna Bridge	180:96ed750bd169	1237	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
Anna Bridge	180:96ed750bd169	1238	uint32_t RESERVED14[1U];
Anna Bridge	180:96ed750bd169	1239	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
Anna Bridge	180:96ed750bd169	1240	uint32_t RESERVED15[1U];
Anna Bridge	180:96ed750bd169	1241	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
Anna Bridge	180:96ed750bd169	1242	uint32_t RESERVED16[1U];
Anna Bridge	180:96ed750bd169	1243	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
Anna Bridge	180:96ed750bd169	1244	uint32_t RESERVED17[1U];
Anna Bridge	180:96ed750bd169	1245	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
Anna Bridge	180:96ed750bd169	1246	uint32_t RESERVED18[1U];
Anna Bridge	180:96ed750bd169	1247	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
Anna Bridge	180:96ed750bd169	1248	uint32_t RESERVED19[1U];
Anna Bridge	180:96ed750bd169	1249	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
Anna Bridge	180:96ed750bd169	1250	uint32_t RESERVED20[1U];
Anna Bridge	180:96ed750bd169	1251	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
Anna Bridge	180:96ed750bd169	1252	uint32_t RESERVED21[1U];
Anna Bridge	180:96ed750bd169	1253	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
Anna Bridge	180:96ed750bd169	1254	uint32_t RESERVED22[1U];
Anna Bridge	180:96ed750bd169	1255	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
Anna Bridge	180:96ed750bd169	1256	uint32_t RESERVED23[1U];
Anna Bridge	180:96ed750bd169	1257	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
Anna Bridge	180:96ed750bd169	1258	uint32_t RESERVED24[1U];
Anna Bridge	180:96ed750bd169	1259	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
Anna Bridge	180:96ed750bd169	1260	uint32_t RESERVED25[1U];
Anna Bridge	180:96ed750bd169	1261	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
Anna Bridge	180:96ed750bd169	1262	uint32_t RESERVED26[1U];
Anna Bridge	180:96ed750bd169	1263	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
Anna Bridge	180:96ed750bd169	1264	uint32_t RESERVED27[1U];
Anna Bridge	180:96ed750bd169	1265	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
Anna Bridge	180:96ed750bd169	1266	uint32_t RESERVED28[1U];
Anna Bridge	180:96ed750bd169	1267	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
Anna Bridge	180:96ed750bd169	1268	uint32_t RESERVED29[1U];
Anna Bridge	180:96ed750bd169	1269	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
Anna Bridge	180:96ed750bd169	1270	uint32_t RESERVED30[1U];
Anna Bridge	180:96ed750bd169	1271	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
Anna Bridge	180:96ed750bd169	1272	uint32_t RESERVED31[1U];
Anna Bridge	180:96ed750bd169	1273	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
Anna Bridge	180:96ed750bd169	1274	uint32_t RESERVED32[934U];
Anna Bridge	180:96ed750bd169	1275	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Anna Bridge	180:96ed750bd169	1276	uint32_t RESERVED33[1U];
Anna Bridge	180:96ed750bd169	1277	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
Anna Bridge	180:96ed750bd169	1278	} DWT_Type;
Anna Bridge	180:96ed750bd169	1279
Anna Bridge	180:96ed750bd169	1280	/* DWT Control Register Definitions */
Anna Bridge	180:96ed750bd169	1281	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
Anna Bridge	180:96ed750bd169	1282	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Anna Bridge	180:96ed750bd169	1283
Anna Bridge	180:96ed750bd169	1284	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
Anna Bridge	180:96ed750bd169	1285	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Anna Bridge	180:96ed750bd169	1286
Anna Bridge	180:96ed750bd169	1287	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
Anna Bridge	180:96ed750bd169	1288	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Anna Bridge	180:96ed750bd169	1289
Anna Bridge	180:96ed750bd169	1290	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
Anna Bridge	180:96ed750bd169	1291	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Anna Bridge	180:96ed750bd169	1292
Anna Bridge	180:96ed750bd169	1293	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
Anna Bridge	180:96ed750bd169	1294	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Anna Bridge	180:96ed750bd169	1295
Anna Bridge	180:96ed750bd169	1296	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
Anna Bridge	180:96ed750bd169	1297	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
Anna Bridge	180:96ed750bd169	1298
Anna Bridge	180:96ed750bd169	1299	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
Anna Bridge	180:96ed750bd169	1300	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Anna Bridge	180:96ed750bd169	1301
Anna Bridge	180:96ed750bd169	1302	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
Anna Bridge	180:96ed750bd169	1303	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Anna Bridge	180:96ed750bd169	1304
Anna Bridge	180:96ed750bd169	1305	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
Anna Bridge	180:96ed750bd169	1306	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Anna Bridge	180:96ed750bd169	1307
Anna Bridge	180:96ed750bd169	1308	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
Anna Bridge	180:96ed750bd169	1309	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Anna Bridge	180:96ed750bd169	1310
Anna Bridge	180:96ed750bd169	1311	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
Anna Bridge	180:96ed750bd169	1312	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Anna Bridge	180:96ed750bd169	1313
Anna Bridge	180:96ed750bd169	1314	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
Anna Bridge	180:96ed750bd169	1315	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Anna Bridge	180:96ed750bd169	1316
Anna Bridge	180:96ed750bd169	1317	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
Anna Bridge	180:96ed750bd169	1318	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Anna Bridge	180:96ed750bd169	1319
Anna Bridge	180:96ed750bd169	1320	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
Anna Bridge	180:96ed750bd169	1321	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Anna Bridge	180:96ed750bd169	1322
Anna Bridge	180:96ed750bd169	1323	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
Anna Bridge	180:96ed750bd169	1324	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Anna Bridge	180:96ed750bd169	1325
Anna Bridge	180:96ed750bd169	1326	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
Anna Bridge	180:96ed750bd169	1327	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Anna Bridge	180:96ed750bd169	1328
Anna Bridge	180:96ed750bd169	1329	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
Anna Bridge	180:96ed750bd169	1330	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Anna Bridge	180:96ed750bd169	1331
Anna Bridge	180:96ed750bd169	1332	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
Anna Bridge	180:96ed750bd169	1333	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Anna Bridge	180:96ed750bd169	1334
Anna Bridge	180:96ed750bd169	1335	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
Anna Bridge	180:96ed750bd169	1336	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Anna Bridge	180:96ed750bd169	1337
Anna Bridge	180:96ed750bd169	1338	/* DWT CPI Count Register Definitions */
Anna Bridge	180:96ed750bd169	1339	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
Anna Bridge	180:96ed750bd169	1340	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Anna Bridge	180:96ed750bd169	1341
Anna Bridge	180:96ed750bd169	1342	/* DWT Exception Overhead Count Register Definitions */
Anna Bridge	180:96ed750bd169	1343	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
Anna Bridge	180:96ed750bd169	1344	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Anna Bridge	180:96ed750bd169	1345
Anna Bridge	180:96ed750bd169	1346	/* DWT Sleep Count Register Definitions */
Anna Bridge	180:96ed750bd169	1347	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
Anna Bridge	180:96ed750bd169	1348	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Anna Bridge	180:96ed750bd169	1349
Anna Bridge	180:96ed750bd169	1350	/* DWT LSU Count Register Definitions */
Anna Bridge	180:96ed750bd169	1351	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
Anna Bridge	180:96ed750bd169	1352	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Anna Bridge	180:96ed750bd169	1353
Anna Bridge	180:96ed750bd169	1354	/* DWT Folded-instruction Count Register Definitions */
Anna Bridge	180:96ed750bd169	1355	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
Anna Bridge	180:96ed750bd169	1356	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Anna Bridge	180:96ed750bd169	1357
Anna Bridge	180:96ed750bd169	1358	/* DWT Comparator Function Register Definitions */
Anna Bridge	180:96ed750bd169	1359	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
Anna Bridge	180:96ed750bd169	1360	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
Anna Bridge	180:96ed750bd169	1361
Anna Bridge	180:96ed750bd169	1362	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
Anna Bridge	180:96ed750bd169	1363	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Anna Bridge	180:96ed750bd169	1364
Anna Bridge	180:96ed750bd169	1365	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
Anna Bridge	180:96ed750bd169	1366	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Anna Bridge	180:96ed750bd169	1367
Anna Bridge	180:96ed750bd169	1368	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
Anna Bridge	180:96ed750bd169	1369	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
Anna Bridge	180:96ed750bd169	1370
Anna Bridge	180:96ed750bd169	1371	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
Anna Bridge	180:96ed750bd169	1372	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
Anna Bridge	180:96ed750bd169	1373
Anna Bridge	180:96ed750bd169	1374	/@}/ /* end of group CMSIS_DWT */
Anna Bridge	180:96ed750bd169	1375
Anna Bridge	180:96ed750bd169	1376
Anna Bridge	180:96ed750bd169	1377	/**
Anna Bridge	180:96ed750bd169	1378	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1379	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge	180:96ed750bd169	1380	\brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge	180:96ed750bd169	1381	@{
Anna Bridge	180:96ed750bd169	1382	*/
Anna Bridge	180:96ed750bd169	1383
Anna Bridge	180:96ed750bd169	1384	/**
Anna Bridge	180:96ed750bd169	1385	\brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge	180:96ed750bd169	1386	*/
Anna Bridge	180:96ed750bd169	1387	typedef struct
Anna Bridge	180:96ed750bd169	1388	{
AnnaBridge	188:bcfe06ba3d64	1389	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register /
AnnaBridge	188:bcfe06ba3d64	1390	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register /
Anna Bridge	180:96ed750bd169	1391	uint32_t RESERVED0[2U];
Anna Bridge	180:96ed750bd169	1392	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Anna Bridge	180:96ed750bd169	1393	uint32_t RESERVED1[55U];
Anna Bridge	180:96ed750bd169	1394	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Anna Bridge	180:96ed750bd169	1395	uint32_t RESERVED2[131U];
Anna Bridge	180:96ed750bd169	1396	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Anna Bridge	180:96ed750bd169	1397	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	188:bcfe06ba3d64	1398	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
AnnaBridge	188:bcfe06ba3d64	1399	uint32_t RESERVED3[809U];
AnnaBridge	188:bcfe06ba3d64	1400	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) Software Lock Access Register /
AnnaBridge	188:bcfe06ba3d64	1401	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) Software Lock Status Register /
AnnaBridge	188:bcfe06ba3d64	1402	uint32_t RESERVED4[4U];
AnnaBridge	188:bcfe06ba3d64	1403	__IM uint32_t TYPE; /!< Offset: 0xFC8 (R/ ) Device Identifier Register /
AnnaBridge	188:bcfe06ba3d64	1404	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Register /
Anna Bridge	180:96ed750bd169	1405	} TPI_Type;
Anna Bridge	180:96ed750bd169	1406
Anna Bridge	180:96ed750bd169	1407	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1408	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
AnnaBridge	188:bcfe06ba3d64	1409	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
Anna Bridge	180:96ed750bd169	1410
Anna Bridge	180:96ed750bd169	1411	/* TPI Selected Pin Protocol Register Definitions */
Anna Bridge	180:96ed750bd169	1412	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
Anna Bridge	180:96ed750bd169	1413	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Anna Bridge	180:96ed750bd169	1414
Anna Bridge	180:96ed750bd169	1415	/* TPI Formatter and Flush Status Register Definitions */
Anna Bridge	180:96ed750bd169	1416	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
Anna Bridge	180:96ed750bd169	1417	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Anna Bridge	180:96ed750bd169	1418
Anna Bridge	180:96ed750bd169	1419	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
Anna Bridge	180:96ed750bd169	1420	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Anna Bridge	180:96ed750bd169	1421
Anna Bridge	180:96ed750bd169	1422	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
Anna Bridge	180:96ed750bd169	1423	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Anna Bridge	180:96ed750bd169	1424
Anna Bridge	180:96ed750bd169	1425	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
Anna Bridge	180:96ed750bd169	1426	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Anna Bridge	180:96ed750bd169	1427
Anna Bridge	180:96ed750bd169	1428	/* TPI Formatter and Flush Control Register Definitions */
Anna Bridge	180:96ed750bd169	1429	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
Anna Bridge	180:96ed750bd169	1430	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Anna Bridge	180:96ed750bd169	1431
AnnaBridge	188:bcfe06ba3d64	1432	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
AnnaBridge	188:bcfe06ba3d64	1433	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
AnnaBridge	188:bcfe06ba3d64	1434
Anna Bridge	180:96ed750bd169	1435	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
Anna Bridge	180:96ed750bd169	1436	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Anna Bridge	180:96ed750bd169	1437
AnnaBridge	188:bcfe06ba3d64	1438	/* TPI Periodic Synchronization Control Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1439	#define TPI_PSCR_PSCount_Pos 0U /!< TPI PSCR: PSCount Position /
AnnaBridge	188:bcfe06ba3d64	1440	#define TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/) /!< TPI PSCR: TPSCount Mask /
AnnaBridge	188:bcfe06ba3d64	1441
AnnaBridge	188:bcfe06ba3d64	1442	/* TPI Software Lock Status Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1443	#define TPI_LSR_nTT_Pos 1U /!< TPI LSR: Not thirty-two bit. Position /
AnnaBridge	188:bcfe06ba3d64	1444	#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /!< TPI LSR: Not thirty-two bit. Mask /
AnnaBridge	188:bcfe06ba3d64	1445
AnnaBridge	188:bcfe06ba3d64	1446	#define TPI_LSR_SLK_Pos 1U /!< TPI LSR: Software Lock status Position /
AnnaBridge	188:bcfe06ba3d64	1447	#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /!< TPI LSR: Software Lock status Mask /
AnnaBridge	188:bcfe06ba3d64	1448
AnnaBridge	188:bcfe06ba3d64	1449	#define TPI_LSR_SLI_Pos 0U /!< TPI LSR: Software Lock implemented Position /
AnnaBridge	188:bcfe06ba3d64	1450	#define TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/) /!< TPI LSR: Software Lock implemented Mask /
Anna Bridge	180:96ed750bd169	1451
Anna Bridge	180:96ed750bd169	1452	/* TPI DEVID Register Definitions */
Anna Bridge	180:96ed750bd169	1453	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
Anna Bridge	180:96ed750bd169	1454	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Anna Bridge	180:96ed750bd169	1455
Anna Bridge	180:96ed750bd169	1456	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
Anna Bridge	180:96ed750bd169	1457	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Anna Bridge	180:96ed750bd169	1458
Anna Bridge	180:96ed750bd169	1459	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
Anna Bridge	180:96ed750bd169	1460	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Anna Bridge	180:96ed750bd169	1461
AnnaBridge	188:bcfe06ba3d64	1462	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFO depth Position /
AnnaBridge	188:bcfe06ba3d64	1463	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFO depth Mask /
Anna Bridge	180:96ed750bd169	1464
Anna Bridge	180:96ed750bd169	1465	/* TPI DEVTYPE Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1466	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	188:bcfe06ba3d64	1467	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	188:bcfe06ba3d64	1468
AnnaBridge	188:bcfe06ba3d64	1469	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
Anna Bridge	180:96ed750bd169	1470	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Anna Bridge	180:96ed750bd169	1471
Anna Bridge	180:96ed750bd169	1472	/@}/ /* end of group CMSIS_TPI */
Anna Bridge	180:96ed750bd169	1473
Anna Bridge	180:96ed750bd169	1474
Anna Bridge	180:96ed750bd169	1475	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1476	/**
Anna Bridge	180:96ed750bd169	1477	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1478	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge	180:96ed750bd169	1479	\brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge	180:96ed750bd169	1480	@{
Anna Bridge	180:96ed750bd169	1481	*/
Anna Bridge	180:96ed750bd169	1482
Anna Bridge	180:96ed750bd169	1483	/**
Anna Bridge	180:96ed750bd169	1484	\brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge	180:96ed750bd169	1485	*/
Anna Bridge	180:96ed750bd169	1486	typedef struct
Anna Bridge	180:96ed750bd169	1487	{
Anna Bridge	180:96ed750bd169	1488	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Anna Bridge	180:96ed750bd169	1489	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Anna Bridge	180:96ed750bd169	1490	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
Anna Bridge	180:96ed750bd169	1491	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Anna Bridge	180:96ed750bd169	1492	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
Anna Bridge	180:96ed750bd169	1493	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
Anna Bridge	180:96ed750bd169	1494	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
Anna Bridge	180:96ed750bd169	1495	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
Anna Bridge	180:96ed750bd169	1496	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
Anna Bridge	180:96ed750bd169	1497	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
Anna Bridge	180:96ed750bd169	1498	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
Anna Bridge	180:96ed750bd169	1499	uint32_t RESERVED0[1];
Anna Bridge	180:96ed750bd169	1500	union {
Anna Bridge	180:96ed750bd169	1501	__IOM uint32_t MAIR[2];
Anna Bridge	180:96ed750bd169	1502	struct {
Anna Bridge	180:96ed750bd169	1503	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
Anna Bridge	180:96ed750bd169	1504	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
Anna Bridge	180:96ed750bd169	1505	};
Anna Bridge	180:96ed750bd169	1506	};
Anna Bridge	180:96ed750bd169	1507	} MPU_Type;
Anna Bridge	180:96ed750bd169	1508
Anna Bridge	180:96ed750bd169	1509	#define MPU_TYPE_RALIASES 4U
Anna Bridge	180:96ed750bd169	1510
Anna Bridge	180:96ed750bd169	1511	/* MPU Type Register Definitions */
Anna Bridge	180:96ed750bd169	1512	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
Anna Bridge	180:96ed750bd169	1513	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Anna Bridge	180:96ed750bd169	1514
Anna Bridge	180:96ed750bd169	1515	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
Anna Bridge	180:96ed750bd169	1516	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Anna Bridge	180:96ed750bd169	1517
Anna Bridge	180:96ed750bd169	1518	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
Anna Bridge	180:96ed750bd169	1519	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Anna Bridge	180:96ed750bd169	1520
Anna Bridge	180:96ed750bd169	1521	/* MPU Control Register Definitions */
Anna Bridge	180:96ed750bd169	1522	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
Anna Bridge	180:96ed750bd169	1523	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Anna Bridge	180:96ed750bd169	1524
Anna Bridge	180:96ed750bd169	1525	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
Anna Bridge	180:96ed750bd169	1526	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Anna Bridge	180:96ed750bd169	1527
Anna Bridge	180:96ed750bd169	1528	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	1529	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	1530
Anna Bridge	180:96ed750bd169	1531	/* MPU Region Number Register Definitions */
Anna Bridge	180:96ed750bd169	1532	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
Anna Bridge	180:96ed750bd169	1533	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Anna Bridge	180:96ed750bd169	1534
Anna Bridge	180:96ed750bd169	1535	/* MPU Region Base Address Register Definitions */
AnnaBridge	188:bcfe06ba3d64	1536	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
AnnaBridge	188:bcfe06ba3d64	1537	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
Anna Bridge	180:96ed750bd169	1538
Anna Bridge	180:96ed750bd169	1539	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
Anna Bridge	180:96ed750bd169	1540	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
Anna Bridge	180:96ed750bd169	1541
Anna Bridge	180:96ed750bd169	1542	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
Anna Bridge	180:96ed750bd169	1543	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
Anna Bridge	180:96ed750bd169	1544
Anna Bridge	180:96ed750bd169	1545	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
Anna Bridge	180:96ed750bd169	1546	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
Anna Bridge	180:96ed750bd169	1547
Anna Bridge	180:96ed750bd169	1548	/* MPU Region Limit Address Register Definitions */
Anna Bridge	180:96ed750bd169	1549	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
Anna Bridge	180:96ed750bd169	1550	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
Anna Bridge	180:96ed750bd169	1551
Anna Bridge	180:96ed750bd169	1552	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
Anna Bridge	180:96ed750bd169	1553	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
Anna Bridge	180:96ed750bd169	1554
Anna Bridge	180:96ed750bd169	1555	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
Anna Bridge	180:96ed750bd169	1556	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
Anna Bridge	180:96ed750bd169	1557
Anna Bridge	180:96ed750bd169	1558	/* MPU Memory Attribute Indirection Register 0 Definitions */
Anna Bridge	180:96ed750bd169	1559	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
Anna Bridge	180:96ed750bd169	1560	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
Anna Bridge	180:96ed750bd169	1561
Anna Bridge	180:96ed750bd169	1562	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
Anna Bridge	180:96ed750bd169	1563	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
Anna Bridge	180:96ed750bd169	1564
Anna Bridge	180:96ed750bd169	1565	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
Anna Bridge	180:96ed750bd169	1566	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
Anna Bridge	180:96ed750bd169	1567
Anna Bridge	180:96ed750bd169	1568	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
Anna Bridge	180:96ed750bd169	1569	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
Anna Bridge	180:96ed750bd169	1570
Anna Bridge	180:96ed750bd169	1571	/* MPU Memory Attribute Indirection Register 1 Definitions */
Anna Bridge	180:96ed750bd169	1572	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
Anna Bridge	180:96ed750bd169	1573	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
Anna Bridge	180:96ed750bd169	1574
Anna Bridge	180:96ed750bd169	1575	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
Anna Bridge	180:96ed750bd169	1576	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
Anna Bridge	180:96ed750bd169	1577
Anna Bridge	180:96ed750bd169	1578	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
Anna Bridge	180:96ed750bd169	1579	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
Anna Bridge	180:96ed750bd169	1580
Anna Bridge	180:96ed750bd169	1581	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
Anna Bridge	180:96ed750bd169	1582	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
Anna Bridge	180:96ed750bd169	1583
Anna Bridge	180:96ed750bd169	1584	/@} end of group CMSIS_MPU /
Anna Bridge	180:96ed750bd169	1585	#endif
Anna Bridge	180:96ed750bd169	1586
Anna Bridge	180:96ed750bd169	1587
Anna Bridge	180:96ed750bd169	1588	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	1589	/**
Anna Bridge	180:96ed750bd169	1590	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1591	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
Anna Bridge	180:96ed750bd169	1592	\brief Type definitions for the Security Attribution Unit (SAU)
Anna Bridge	180:96ed750bd169	1593	@{
Anna Bridge	180:96ed750bd169	1594	*/
Anna Bridge	180:96ed750bd169	1595
Anna Bridge	180:96ed750bd169	1596	/**
Anna Bridge	180:96ed750bd169	1597	\brief Structure type to access the Security Attribution Unit (SAU).
Anna Bridge	180:96ed750bd169	1598	*/
Anna Bridge	180:96ed750bd169	1599	typedef struct
Anna Bridge	180:96ed750bd169	1600	{
Anna Bridge	180:96ed750bd169	1601	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
Anna Bridge	180:96ed750bd169	1602	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
Anna Bridge	180:96ed750bd169	1603	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1604	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
Anna Bridge	180:96ed750bd169	1605	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
Anna Bridge	180:96ed750bd169	1606	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
Anna Bridge	180:96ed750bd169	1607	#else
Anna Bridge	180:96ed750bd169	1608	uint32_t RESERVED0[3];
Anna Bridge	180:96ed750bd169	1609	#endif
Anna Bridge	180:96ed750bd169	1610	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
Anna Bridge	180:96ed750bd169	1611	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
Anna Bridge	180:96ed750bd169	1612	} SAU_Type;
Anna Bridge	180:96ed750bd169	1613
Anna Bridge	180:96ed750bd169	1614	/* SAU Control Register Definitions */
Anna Bridge	180:96ed750bd169	1615	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
Anna Bridge	180:96ed750bd169	1616	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
Anna Bridge	180:96ed750bd169	1617
Anna Bridge	180:96ed750bd169	1618	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
Anna Bridge	180:96ed750bd169	1619	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
Anna Bridge	180:96ed750bd169	1620
Anna Bridge	180:96ed750bd169	1621	/* SAU Type Register Definitions */
Anna Bridge	180:96ed750bd169	1622	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
Anna Bridge	180:96ed750bd169	1623	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
Anna Bridge	180:96ed750bd169	1624
Anna Bridge	180:96ed750bd169	1625	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1626	/* SAU Region Number Register Definitions */
Anna Bridge	180:96ed750bd169	1627	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
Anna Bridge	180:96ed750bd169	1628	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
Anna Bridge	180:96ed750bd169	1629
Anna Bridge	180:96ed750bd169	1630	/* SAU Region Base Address Register Definitions */
Anna Bridge	180:96ed750bd169	1631	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
Anna Bridge	180:96ed750bd169	1632	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
Anna Bridge	180:96ed750bd169	1633
Anna Bridge	180:96ed750bd169	1634	/* SAU Region Limit Address Register Definitions */
Anna Bridge	180:96ed750bd169	1635	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
Anna Bridge	180:96ed750bd169	1636	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
Anna Bridge	180:96ed750bd169	1637
Anna Bridge	180:96ed750bd169	1638	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
Anna Bridge	180:96ed750bd169	1639	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
Anna Bridge	180:96ed750bd169	1640
Anna Bridge	180:96ed750bd169	1641	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
Anna Bridge	180:96ed750bd169	1642	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
Anna Bridge	180:96ed750bd169	1643
Anna Bridge	180:96ed750bd169	1644	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Anna Bridge	180:96ed750bd169	1645
Anna Bridge	180:96ed750bd169	1646	/* Secure Fault Status Register Definitions */
Anna Bridge	180:96ed750bd169	1647	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
Anna Bridge	180:96ed750bd169	1648	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
Anna Bridge	180:96ed750bd169	1649
Anna Bridge	180:96ed750bd169	1650	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
Anna Bridge	180:96ed750bd169	1651	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
Anna Bridge	180:96ed750bd169	1652
Anna Bridge	180:96ed750bd169	1653	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
Anna Bridge	180:96ed750bd169	1654	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
Anna Bridge	180:96ed750bd169	1655
Anna Bridge	180:96ed750bd169	1656	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
Anna Bridge	180:96ed750bd169	1657	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
Anna Bridge	180:96ed750bd169	1658
Anna Bridge	180:96ed750bd169	1659	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
Anna Bridge	180:96ed750bd169	1660	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
Anna Bridge	180:96ed750bd169	1661
Anna Bridge	180:96ed750bd169	1662	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
Anna Bridge	180:96ed750bd169	1663	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
Anna Bridge	180:96ed750bd169	1664
Anna Bridge	180:96ed750bd169	1665	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
Anna Bridge	180:96ed750bd169	1666	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
Anna Bridge	180:96ed750bd169	1667
Anna Bridge	180:96ed750bd169	1668	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
Anna Bridge	180:96ed750bd169	1669	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
Anna Bridge	180:96ed750bd169	1670
Anna Bridge	180:96ed750bd169	1671	/@} end of group CMSIS_SAU /
Anna Bridge	180:96ed750bd169	1672	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	180:96ed750bd169	1673
Anna Bridge	180:96ed750bd169	1674
Anna Bridge	180:96ed750bd169	1675	/**
Anna Bridge	180:96ed750bd169	1676	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1677	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Anna Bridge	180:96ed750bd169	1678	\brief Type definitions for the Floating Point Unit (FPU)
Anna Bridge	180:96ed750bd169	1679	@{
Anna Bridge	180:96ed750bd169	1680	*/
Anna Bridge	180:96ed750bd169	1681
Anna Bridge	180:96ed750bd169	1682	/**
Anna Bridge	180:96ed750bd169	1683	\brief Structure type to access the Floating Point Unit (FPU).
Anna Bridge	180:96ed750bd169	1684	*/
Anna Bridge	180:96ed750bd169	1685	typedef struct
Anna Bridge	180:96ed750bd169	1686	{
Anna Bridge	180:96ed750bd169	1687	uint32_t RESERVED0[1U];
Anna Bridge	180:96ed750bd169	1688	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Anna Bridge	180:96ed750bd169	1689	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Anna Bridge	180:96ed750bd169	1690	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Anna Bridge	180:96ed750bd169	1691	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Anna Bridge	180:96ed750bd169	1692	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Anna Bridge	180:96ed750bd169	1693	} FPU_Type;
Anna Bridge	180:96ed750bd169	1694
Anna Bridge	180:96ed750bd169	1695	/* Floating-Point Context Control Register Definitions */
Anna Bridge	180:96ed750bd169	1696	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
Anna Bridge	180:96ed750bd169	1697	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Anna Bridge	180:96ed750bd169	1698
Anna Bridge	180:96ed750bd169	1699	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
Anna Bridge	180:96ed750bd169	1700	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Anna Bridge	180:96ed750bd169	1701
Anna Bridge	180:96ed750bd169	1702	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
Anna Bridge	180:96ed750bd169	1703	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
Anna Bridge	180:96ed750bd169	1704
Anna Bridge	180:96ed750bd169	1705	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
Anna Bridge	180:96ed750bd169	1706	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
Anna Bridge	180:96ed750bd169	1707
Anna Bridge	180:96ed750bd169	1708	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
Anna Bridge	180:96ed750bd169	1709	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
Anna Bridge	180:96ed750bd169	1710
Anna Bridge	180:96ed750bd169	1711	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
Anna Bridge	180:96ed750bd169	1712	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
Anna Bridge	180:96ed750bd169	1713
Anna Bridge	180:96ed750bd169	1714	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
Anna Bridge	180:96ed750bd169	1715	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
Anna Bridge	180:96ed750bd169	1716
Anna Bridge	180:96ed750bd169	1717	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
Anna Bridge	180:96ed750bd169	1718	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
Anna Bridge	180:96ed750bd169	1719
Anna Bridge	180:96ed750bd169	1720	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
Anna Bridge	180:96ed750bd169	1721	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Anna Bridge	180:96ed750bd169	1722
Anna Bridge	180:96ed750bd169	1723	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
Anna Bridge	180:96ed750bd169	1724	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
Anna Bridge	180:96ed750bd169	1725
Anna Bridge	180:96ed750bd169	1726	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
Anna Bridge	180:96ed750bd169	1727	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Anna Bridge	180:96ed750bd169	1728
Anna Bridge	180:96ed750bd169	1729	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
Anna Bridge	180:96ed750bd169	1730	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Anna Bridge	180:96ed750bd169	1731
Anna Bridge	180:96ed750bd169	1732	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
Anna Bridge	180:96ed750bd169	1733	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Anna Bridge	180:96ed750bd169	1734
Anna Bridge	180:96ed750bd169	1735	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
Anna Bridge	180:96ed750bd169	1736	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Anna Bridge	180:96ed750bd169	1737
Anna Bridge	180:96ed750bd169	1738	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
Anna Bridge	180:96ed750bd169	1739	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
Anna Bridge	180:96ed750bd169	1740
Anna Bridge	180:96ed750bd169	1741	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
Anna Bridge	180:96ed750bd169	1742	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Anna Bridge	180:96ed750bd169	1743
Anna Bridge	180:96ed750bd169	1744	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
Anna Bridge	180:96ed750bd169	1745	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Anna Bridge	180:96ed750bd169	1746
Anna Bridge	180:96ed750bd169	1747	/* Floating-Point Context Address Register Definitions */
Anna Bridge	180:96ed750bd169	1748	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
Anna Bridge	180:96ed750bd169	1749	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Anna Bridge	180:96ed750bd169	1750
Anna Bridge	180:96ed750bd169	1751	/* Floating-Point Default Status Control Register Definitions */
Anna Bridge	180:96ed750bd169	1752	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
Anna Bridge	180:96ed750bd169	1753	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Anna Bridge	180:96ed750bd169	1754
Anna Bridge	180:96ed750bd169	1755	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
Anna Bridge	180:96ed750bd169	1756	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Anna Bridge	180:96ed750bd169	1757
Anna Bridge	180:96ed750bd169	1758	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
Anna Bridge	180:96ed750bd169	1759	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Anna Bridge	180:96ed750bd169	1760
Anna Bridge	180:96ed750bd169	1761	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
Anna Bridge	180:96ed750bd169	1762	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Anna Bridge	180:96ed750bd169	1763
Anna Bridge	180:96ed750bd169	1764	/* Media and FP Feature Register 0 Definitions */
Anna Bridge	180:96ed750bd169	1765	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
Anna Bridge	180:96ed750bd169	1766	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Anna Bridge	180:96ed750bd169	1767
Anna Bridge	180:96ed750bd169	1768	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
Anna Bridge	180:96ed750bd169	1769	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Anna Bridge	180:96ed750bd169	1770
Anna Bridge	180:96ed750bd169	1771	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
Anna Bridge	180:96ed750bd169	1772	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Anna Bridge	180:96ed750bd169	1773
Anna Bridge	180:96ed750bd169	1774	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
Anna Bridge	180:96ed750bd169	1775	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Anna Bridge	180:96ed750bd169	1776
Anna Bridge	180:96ed750bd169	1777	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
Anna Bridge	180:96ed750bd169	1778	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Anna Bridge	180:96ed750bd169	1779
Anna Bridge	180:96ed750bd169	1780	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
Anna Bridge	180:96ed750bd169	1781	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Anna Bridge	180:96ed750bd169	1782
Anna Bridge	180:96ed750bd169	1783	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
Anna Bridge	180:96ed750bd169	1784	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Anna Bridge	180:96ed750bd169	1785
Anna Bridge	180:96ed750bd169	1786	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
Anna Bridge	180:96ed750bd169	1787	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Anna Bridge	180:96ed750bd169	1788
Anna Bridge	180:96ed750bd169	1789	/* Media and FP Feature Register 1 Definitions */
Anna Bridge	180:96ed750bd169	1790	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
Anna Bridge	180:96ed750bd169	1791	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Anna Bridge	180:96ed750bd169	1792
Anna Bridge	180:96ed750bd169	1793	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
Anna Bridge	180:96ed750bd169	1794	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Anna Bridge	180:96ed750bd169	1795
Anna Bridge	180:96ed750bd169	1796	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
Anna Bridge	180:96ed750bd169	1797	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Anna Bridge	180:96ed750bd169	1798
Anna Bridge	180:96ed750bd169	1799	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
Anna Bridge	180:96ed750bd169	1800	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Anna Bridge	180:96ed750bd169	1801
Anna Bridge	180:96ed750bd169	1802	/@} end of group CMSIS_FPU /
Anna Bridge	180:96ed750bd169	1803
Anna Bridge	180:96ed750bd169	1804
Anna Bridge	180:96ed750bd169	1805	/**
Anna Bridge	180:96ed750bd169	1806	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1807	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge	180:96ed750bd169	1808	\brief Type definitions for the Core Debug Registers
Anna Bridge	180:96ed750bd169	1809	@{
Anna Bridge	180:96ed750bd169	1810	*/
Anna Bridge	180:96ed750bd169	1811
Anna Bridge	180:96ed750bd169	1812	/**
Anna Bridge	180:96ed750bd169	1813	\brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge	180:96ed750bd169	1814	*/
Anna Bridge	180:96ed750bd169	1815	typedef struct
Anna Bridge	180:96ed750bd169	1816	{
Anna Bridge	180:96ed750bd169	1817	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Anna Bridge	180:96ed750bd169	1818	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Anna Bridge	180:96ed750bd169	1819	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Anna Bridge	180:96ed750bd169	1820	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Anna Bridge	180:96ed750bd169	1821	uint32_t RESERVED4[1U];
Anna Bridge	180:96ed750bd169	1822	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
Anna Bridge	180:96ed750bd169	1823	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
Anna Bridge	180:96ed750bd169	1824	} CoreDebug_Type;
Anna Bridge	180:96ed750bd169	1825
Anna Bridge	180:96ed750bd169	1826	/* Debug Halting Control and Status Register Definitions */
Anna Bridge	180:96ed750bd169	1827	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
Anna Bridge	180:96ed750bd169	1828	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Anna Bridge	180:96ed750bd169	1829
Anna Bridge	180:96ed750bd169	1830	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
Anna Bridge	180:96ed750bd169	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
Anna Bridge	180:96ed750bd169	1832
Anna Bridge	180:96ed750bd169	1833	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
Anna Bridge	180:96ed750bd169	1834	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Anna Bridge	180:96ed750bd169	1835
Anna Bridge	180:96ed750bd169	1836	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Anna Bridge	180:96ed750bd169	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Anna Bridge	180:96ed750bd169	1838
Anna Bridge	180:96ed750bd169	1839	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
Anna Bridge	180:96ed750bd169	1840	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Anna Bridge	180:96ed750bd169	1841
Anna Bridge	180:96ed750bd169	1842	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
Anna Bridge	180:96ed750bd169	1843	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Anna Bridge	180:96ed750bd169	1844
Anna Bridge	180:96ed750bd169	1845	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
Anna Bridge	180:96ed750bd169	1846	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Anna Bridge	180:96ed750bd169	1847
Anna Bridge	180:96ed750bd169	1848	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
Anna Bridge	180:96ed750bd169	1849	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Anna Bridge	180:96ed750bd169	1850
Anna Bridge	180:96ed750bd169	1851	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Anna Bridge	180:96ed750bd169	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Anna Bridge	180:96ed750bd169	1853
Anna Bridge	180:96ed750bd169	1854	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
Anna Bridge	180:96ed750bd169	1855	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Anna Bridge	180:96ed750bd169	1856
Anna Bridge	180:96ed750bd169	1857	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
Anna Bridge	180:96ed750bd169	1858	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Anna Bridge	180:96ed750bd169	1859
Anna Bridge	180:96ed750bd169	1860	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
Anna Bridge	180:96ed750bd169	1861	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Anna Bridge	180:96ed750bd169	1862
Anna Bridge	180:96ed750bd169	1863	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
Anna Bridge	180:96ed750bd169	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Anna Bridge	180:96ed750bd169	1865
Anna Bridge	180:96ed750bd169	1866	/* Debug Core Register Selector Register Definitions */
Anna Bridge	180:96ed750bd169	1867	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
Anna Bridge	180:96ed750bd169	1868	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Anna Bridge	180:96ed750bd169	1869
Anna Bridge	180:96ed750bd169	1870	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
Anna Bridge	180:96ed750bd169	1871	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Anna Bridge	180:96ed750bd169	1872
Anna Bridge	180:96ed750bd169	1873	/* Debug Exception and Monitor Control Register Definitions */
Anna Bridge	180:96ed750bd169	1874	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
Anna Bridge	180:96ed750bd169	1875	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Anna Bridge	180:96ed750bd169	1876
Anna Bridge	180:96ed750bd169	1877	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
Anna Bridge	180:96ed750bd169	1878	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Anna Bridge	180:96ed750bd169	1879
Anna Bridge	180:96ed750bd169	1880	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
Anna Bridge	180:96ed750bd169	1881	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Anna Bridge	180:96ed750bd169	1882
Anna Bridge	180:96ed750bd169	1883	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
Anna Bridge	180:96ed750bd169	1884	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Anna Bridge	180:96ed750bd169	1885
Anna Bridge	180:96ed750bd169	1886	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
Anna Bridge	180:96ed750bd169	1887	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Anna Bridge	180:96ed750bd169	1888
Anna Bridge	180:96ed750bd169	1889	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
Anna Bridge	180:96ed750bd169	1890	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Anna Bridge	180:96ed750bd169	1891
Anna Bridge	180:96ed750bd169	1892	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
Anna Bridge	180:96ed750bd169	1893	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Anna Bridge	180:96ed750bd169	1894
Anna Bridge	180:96ed750bd169	1895	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
Anna Bridge	180:96ed750bd169	1896	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Anna Bridge	180:96ed750bd169	1897
Anna Bridge	180:96ed750bd169	1898	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
Anna Bridge	180:96ed750bd169	1899	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Anna Bridge	180:96ed750bd169	1900
Anna Bridge	180:96ed750bd169	1901	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
Anna Bridge	180:96ed750bd169	1902	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Anna Bridge	180:96ed750bd169	1903
Anna Bridge	180:96ed750bd169	1904	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
Anna Bridge	180:96ed750bd169	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Anna Bridge	180:96ed750bd169	1906
Anna Bridge	180:96ed750bd169	1907	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
Anna Bridge	180:96ed750bd169	1908	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Anna Bridge	180:96ed750bd169	1909
Anna Bridge	180:96ed750bd169	1910	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
Anna Bridge	180:96ed750bd169	1911	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Anna Bridge	180:96ed750bd169	1912
Anna Bridge	180:96ed750bd169	1913	/* Debug Authentication Control Register Definitions */
Anna Bridge	180:96ed750bd169	1914	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
Anna Bridge	180:96ed750bd169	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
Anna Bridge	180:96ed750bd169	1916
Anna Bridge	180:96ed750bd169	1917	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
Anna Bridge	180:96ed750bd169	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
Anna Bridge	180:96ed750bd169	1919
Anna Bridge	180:96ed750bd169	1920	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
Anna Bridge	180:96ed750bd169	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
Anna Bridge	180:96ed750bd169	1922
Anna Bridge	180:96ed750bd169	1923	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
Anna Bridge	180:96ed750bd169	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
Anna Bridge	180:96ed750bd169	1925
Anna Bridge	180:96ed750bd169	1926	/* Debug Security Control and Status Register Definitions */
Anna Bridge	180:96ed750bd169	1927	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
Anna Bridge	180:96ed750bd169	1928	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
Anna Bridge	180:96ed750bd169	1929
Anna Bridge	180:96ed750bd169	1930	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
Anna Bridge	180:96ed750bd169	1931	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
Anna Bridge	180:96ed750bd169	1932
Anna Bridge	180:96ed750bd169	1933	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
Anna Bridge	180:96ed750bd169	1934	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
Anna Bridge	180:96ed750bd169	1935
Anna Bridge	180:96ed750bd169	1936	/@} end of group CMSIS_CoreDebug /
Anna Bridge	180:96ed750bd169	1937
Anna Bridge	180:96ed750bd169	1938
Anna Bridge	180:96ed750bd169	1939	/**
Anna Bridge	180:96ed750bd169	1940	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1941	\defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge	180:96ed750bd169	1942	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge	180:96ed750bd169	1943	@{
Anna Bridge	180:96ed750bd169	1944	*/
Anna Bridge	180:96ed750bd169	1945
Anna Bridge	180:96ed750bd169	1946	/**
Anna Bridge	180:96ed750bd169	1947	\brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge	180:96ed750bd169	1948	\param[in] field Name of the register bit field.
Anna Bridge	180:96ed750bd169	1949	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge	180:96ed750bd169	1950	\return Masked and shifted value.
Anna Bridge	180:96ed750bd169	1951	*/
Anna Bridge	180:96ed750bd169	1952	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge	180:96ed750bd169	1953
Anna Bridge	180:96ed750bd169	1954	/**
Anna Bridge	180:96ed750bd169	1955	\brief Mask and shift a register value to extract a bit filed value.
Anna Bridge	180:96ed750bd169	1956	\param[in] field Name of the register bit field.
Anna Bridge	180:96ed750bd169	1957	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge	180:96ed750bd169	1958	\return Masked and shifted bit field value.
Anna Bridge	180:96ed750bd169	1959	*/
Anna Bridge	180:96ed750bd169	1960	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge	180:96ed750bd169	1961
Anna Bridge	180:96ed750bd169	1962	/@} end of group CMSIS_core_bitfield /
Anna Bridge	180:96ed750bd169	1963
Anna Bridge	180:96ed750bd169	1964
Anna Bridge	180:96ed750bd169	1965	/**
Anna Bridge	180:96ed750bd169	1966	\ingroup CMSIS_core_register
Anna Bridge	180:96ed750bd169	1967	\defgroup CMSIS_core_base Core Definitions
Anna Bridge	180:96ed750bd169	1968	\brief Definitions for base addresses, unions, and structures.
Anna Bridge	180:96ed750bd169	1969	@{
Anna Bridge	180:96ed750bd169	1970	*/
Anna Bridge	180:96ed750bd169	1971
Anna Bridge	180:96ed750bd169	1972	/* Memory mapping of Core Hardware */
Anna Bridge	180:96ed750bd169	1973	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Anna Bridge	180:96ed750bd169	1974	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Anna Bridge	180:96ed750bd169	1975	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Anna Bridge	180:96ed750bd169	1976	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Anna Bridge	180:96ed750bd169	1977	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Anna Bridge	180:96ed750bd169	1978	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Anna Bridge	180:96ed750bd169	1979	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Anna Bridge	180:96ed750bd169	1980	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Anna Bridge	180:96ed750bd169	1981
Anna Bridge	180:96ed750bd169	1982	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Anna Bridge	180:96ed750bd169	1983	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Anna Bridge	180:96ed750bd169	1984	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Anna Bridge	180:96ed750bd169	1985	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Anna Bridge	180:96ed750bd169	1986	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Anna Bridge	180:96ed750bd169	1987	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Anna Bridge	180:96ed750bd169	1988	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Anna Bridge	180:96ed750bd169	1989	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
Anna Bridge	180:96ed750bd169	1990
Anna Bridge	180:96ed750bd169	1991	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	1992	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Anna Bridge	180:96ed750bd169	1993	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Anna Bridge	180:96ed750bd169	1994	#endif
Anna Bridge	180:96ed750bd169	1995
Anna Bridge	180:96ed750bd169	1996	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	1997	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
Anna Bridge	180:96ed750bd169	1998	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
Anna Bridge	180:96ed750bd169	1999	#endif
Anna Bridge	180:96ed750bd169	2000
Anna Bridge	180:96ed750bd169	2001	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Anna Bridge	180:96ed750bd169	2002	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Anna Bridge	180:96ed750bd169	2003
Anna Bridge	180:96ed750bd169	2004	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	2005	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
Anna Bridge	180:96ed750bd169	2006	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
Anna Bridge	180:96ed750bd169	2007	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
Anna Bridge	180:96ed750bd169	2008	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
Anna Bridge	180:96ed750bd169	2009	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
Anna Bridge	180:96ed750bd169	2010
Anna Bridge	180:96ed750bd169	2011	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
Anna Bridge	180:96ed750bd169	2012	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
Anna Bridge	180:96ed750bd169	2013	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
Anna Bridge	180:96ed750bd169	2014	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
Anna Bridge	180:96ed750bd169	2015	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
Anna Bridge	180:96ed750bd169	2016
Anna Bridge	180:96ed750bd169	2017	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2018	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
Anna Bridge	180:96ed750bd169	2019	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
Anna Bridge	180:96ed750bd169	2020	#endif
Anna Bridge	180:96ed750bd169	2021
Anna Bridge	180:96ed750bd169	2022	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
Anna Bridge	180:96ed750bd169	2023	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
Anna Bridge	180:96ed750bd169	2024
Anna Bridge	180:96ed750bd169	2025	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	180:96ed750bd169	2026	/@} /
Anna Bridge	180:96ed750bd169	2027
Anna Bridge	180:96ed750bd169	2028
Anna Bridge	180:96ed750bd169	2029
Anna Bridge	180:96ed750bd169	2030	/*******************************************************************************
Anna Bridge	180:96ed750bd169	2031	* Hardware Abstraction Layer
Anna Bridge	180:96ed750bd169	2032	Core Function Interface contains:
Anna Bridge	180:96ed750bd169	2033	- Core NVIC Functions
Anna Bridge	180:96ed750bd169	2034	- Core SysTick Functions
Anna Bridge	180:96ed750bd169	2035	- Core Debug Functions
Anna Bridge	180:96ed750bd169	2036	- Core Register Access Functions
Anna Bridge	180:96ed750bd169	2037	******************************************************************************/
Anna Bridge	180:96ed750bd169	2038	/**
Anna Bridge	180:96ed750bd169	2039	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge	180:96ed750bd169	2040	*/
Anna Bridge	180:96ed750bd169	2041
Anna Bridge	180:96ed750bd169	2042
Anna Bridge	180:96ed750bd169	2043
Anna Bridge	180:96ed750bd169	2044	/* ########################## NVIC functions #################################### */
Anna Bridge	180:96ed750bd169	2045	/**
Anna Bridge	180:96ed750bd169	2046	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2047	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge	180:96ed750bd169	2048	\brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge	180:96ed750bd169	2049	@{
Anna Bridge	180:96ed750bd169	2050	*/
Anna Bridge	180:96ed750bd169	2051
Anna Bridge	180:96ed750bd169	2052	#ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge	180:96ed750bd169	2053	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	2054	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge	180:96ed750bd169	2055	#endif
Anna Bridge	180:96ed750bd169	2056	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	2057	#else
Anna Bridge	180:96ed750bd169	2058	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge	180:96ed750bd169	2059	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge	180:96ed750bd169	2060	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge	180:96ed750bd169	2061	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge	180:96ed750bd169	2062	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge	180:96ed750bd169	2063	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge	180:96ed750bd169	2064	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge	180:96ed750bd169	2065	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge	180:96ed750bd169	2066	#define NVIC_GetActive __NVIC_GetActive
Anna Bridge	180:96ed750bd169	2067	#define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge	180:96ed750bd169	2068	#define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge	180:96ed750bd169	2069	#define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge	180:96ed750bd169	2070	#endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge	180:96ed750bd169	2071
Anna Bridge	180:96ed750bd169	2072	#ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge	180:96ed750bd169	2073	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	2074	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge	180:96ed750bd169	2075	#endif
Anna Bridge	180:96ed750bd169	2076	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	180:96ed750bd169	2077	#else
Anna Bridge	180:96ed750bd169	2078	#define NVIC_SetVector __NVIC_SetVector
Anna Bridge	180:96ed750bd169	2079	#define NVIC_GetVector __NVIC_GetVector
Anna Bridge	180:96ed750bd169	2080	#endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge	180:96ed750bd169	2081
Anna Bridge	180:96ed750bd169	2082	#define NVIC_USER_IRQ_OFFSET 16
Anna Bridge	180:96ed750bd169	2083
Anna Bridge	180:96ed750bd169	2084
AnnaBridge	188:bcfe06ba3d64	2085	/* Special LR values for Secure/Non-Secure call handling and exception handling */
AnnaBridge	188:bcfe06ba3d64	2086
AnnaBridge	188:bcfe06ba3d64	2087	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
AnnaBridge	188:bcfe06ba3d64	2088	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
AnnaBridge	188:bcfe06ba3d64	2089
AnnaBridge	188:bcfe06ba3d64	2090	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
AnnaBridge	188:bcfe06ba3d64	2091	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
AnnaBridge	188:bcfe06ba3d64	2092	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
AnnaBridge	188:bcfe06ba3d64	2093	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
AnnaBridge	188:bcfe06ba3d64	2094	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
AnnaBridge	188:bcfe06ba3d64	2095	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
AnnaBridge	188:bcfe06ba3d64	2096	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
AnnaBridge	188:bcfe06ba3d64	2097	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
AnnaBridge	188:bcfe06ba3d64	2098
AnnaBridge	188:bcfe06ba3d64	2099	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
AnnaBridge	188:bcfe06ba3d64	2100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
AnnaBridge	188:bcfe06ba3d64	2101	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
AnnaBridge	188:bcfe06ba3d64	2102	#else
AnnaBridge	188:bcfe06ba3d64	2103	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
AnnaBridge	188:bcfe06ba3d64	2104	#endif
AnnaBridge	188:bcfe06ba3d64	2105
Anna Bridge	180:96ed750bd169	2106
Anna Bridge	180:96ed750bd169	2107	/**
Anna Bridge	180:96ed750bd169	2108	\brief Set Priority Grouping
Anna Bridge	180:96ed750bd169	2109	\details Sets the priority grouping field using the required unlock sequence.
Anna Bridge	180:96ed750bd169	2110	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	180:96ed750bd169	2111	Only values from 0..7 are used.
Anna Bridge	180:96ed750bd169	2112	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	2113	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	2114	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	180:96ed750bd169	2115	*/
Anna Bridge	180:96ed750bd169	2116	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge	180:96ed750bd169	2117	{
Anna Bridge	180:96ed750bd169	2118	uint32_t reg_value;
Anna Bridge	180:96ed750bd169	2119	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	2120
Anna Bridge	180:96ed750bd169	2121	reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge	180:96ed750bd169	2122	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	180:96ed750bd169	2123	reg_value = (reg_value \|
Anna Bridge	180:96ed750bd169	2124	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	180:96ed750bd169	2125	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Anna Bridge	180:96ed750bd169	2126	SCB->AIRCR = reg_value;
Anna Bridge	180:96ed750bd169	2127	}
Anna Bridge	180:96ed750bd169	2128
Anna Bridge	180:96ed750bd169	2129
Anna Bridge	180:96ed750bd169	2130	/**
Anna Bridge	180:96ed750bd169	2131	\brief Get Priority Grouping
Anna Bridge	180:96ed750bd169	2132	\details Reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge	180:96ed750bd169	2133	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	180:96ed750bd169	2134	*/
Anna Bridge	180:96ed750bd169	2135	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge	180:96ed750bd169	2136	{
Anna Bridge	180:96ed750bd169	2137	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	180:96ed750bd169	2138	}
Anna Bridge	180:96ed750bd169	2139
Anna Bridge	180:96ed750bd169	2140
Anna Bridge	180:96ed750bd169	2141	/**
Anna Bridge	180:96ed750bd169	2142	\brief Enable Interrupt
Anna Bridge	180:96ed750bd169	2143	\details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	2144	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2145	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2146	*/
Anna Bridge	180:96ed750bd169	2147	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2148	{
Anna Bridge	180:96ed750bd169	2149	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2150	{
Anna Bridge	186:707f6e361f3e	2151	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2152	}
Anna Bridge	180:96ed750bd169	2153	}
Anna Bridge	180:96ed750bd169	2154
Anna Bridge	180:96ed750bd169	2155
Anna Bridge	180:96ed750bd169	2156	/**
Anna Bridge	180:96ed750bd169	2157	\brief Get Interrupt Enable status
Anna Bridge	180:96ed750bd169	2158	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	2159	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2160	\return 0 Interrupt is not enabled.
Anna Bridge	180:96ed750bd169	2161	\return 1 Interrupt is enabled.
Anna Bridge	180:96ed750bd169	2162	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2163	*/
Anna Bridge	180:96ed750bd169	2164	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2165	{
Anna Bridge	180:96ed750bd169	2166	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2167	{
Anna Bridge	186:707f6e361f3e	2168	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2169	}
Anna Bridge	180:96ed750bd169	2170	else
Anna Bridge	180:96ed750bd169	2171	{
Anna Bridge	180:96ed750bd169	2172	return(0U);
Anna Bridge	180:96ed750bd169	2173	}
Anna Bridge	180:96ed750bd169	2174	}
Anna Bridge	180:96ed750bd169	2175
Anna Bridge	180:96ed750bd169	2176
Anna Bridge	180:96ed750bd169	2177	/**
Anna Bridge	180:96ed750bd169	2178	\brief Disable Interrupt
Anna Bridge	180:96ed750bd169	2179	\details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	180:96ed750bd169	2180	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2181	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2182	*/
Anna Bridge	180:96ed750bd169	2183	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2184	{
Anna Bridge	180:96ed750bd169	2185	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2186	{
Anna Bridge	186:707f6e361f3e	2187	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2188	__DSB();
Anna Bridge	180:96ed750bd169	2189	__ISB();
Anna Bridge	180:96ed750bd169	2190	}
Anna Bridge	180:96ed750bd169	2191	}
Anna Bridge	180:96ed750bd169	2192
Anna Bridge	180:96ed750bd169	2193
Anna Bridge	180:96ed750bd169	2194	/**
Anna Bridge	180:96ed750bd169	2195	\brief Get Pending Interrupt
Anna Bridge	180:96ed750bd169	2196	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge	180:96ed750bd169	2197	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2198	\return 0 Interrupt status is not pending.
Anna Bridge	180:96ed750bd169	2199	\return 1 Interrupt status is pending.
Anna Bridge	180:96ed750bd169	2200	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2201	*/
Anna Bridge	180:96ed750bd169	2202	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2203	{
Anna Bridge	180:96ed750bd169	2204	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2205	{
Anna Bridge	186:707f6e361f3e	2206	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2207	}
Anna Bridge	180:96ed750bd169	2208	else
Anna Bridge	180:96ed750bd169	2209	{
Anna Bridge	180:96ed750bd169	2210	return(0U);
Anna Bridge	180:96ed750bd169	2211	}
Anna Bridge	180:96ed750bd169	2212	}
Anna Bridge	180:96ed750bd169	2213
Anna Bridge	180:96ed750bd169	2214
Anna Bridge	180:96ed750bd169	2215	/**
Anna Bridge	180:96ed750bd169	2216	\brief Set Pending Interrupt
Anna Bridge	180:96ed750bd169	2217	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	180:96ed750bd169	2218	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2219	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2220	*/
Anna Bridge	180:96ed750bd169	2221	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2222	{
Anna Bridge	180:96ed750bd169	2223	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2224	{
Anna Bridge	186:707f6e361f3e	2225	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2226	}
Anna Bridge	180:96ed750bd169	2227	}
Anna Bridge	180:96ed750bd169	2228
Anna Bridge	180:96ed750bd169	2229
Anna Bridge	180:96ed750bd169	2230	/**
Anna Bridge	180:96ed750bd169	2231	\brief Clear Pending Interrupt
Anna Bridge	180:96ed750bd169	2232	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	180:96ed750bd169	2233	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2234	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2235	*/
Anna Bridge	180:96ed750bd169	2236	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2237	{
Anna Bridge	180:96ed750bd169	2238	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2239	{
Anna Bridge	186:707f6e361f3e	2240	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2241	}
Anna Bridge	180:96ed750bd169	2242	}
Anna Bridge	180:96ed750bd169	2243
Anna Bridge	180:96ed750bd169	2244
Anna Bridge	180:96ed750bd169	2245	/**
Anna Bridge	180:96ed750bd169	2246	\brief Get Active Interrupt
Anna Bridge	180:96ed750bd169	2247	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	2248	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2249	\return 0 Interrupt status is not active.
Anna Bridge	180:96ed750bd169	2250	\return 1 Interrupt status is active.
Anna Bridge	180:96ed750bd169	2251	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2252	*/
Anna Bridge	180:96ed750bd169	2253	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2254	{
Anna Bridge	180:96ed750bd169	2255	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2256	{
Anna Bridge	186:707f6e361f3e	2257	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2258	}
Anna Bridge	180:96ed750bd169	2259	else
Anna Bridge	180:96ed750bd169	2260	{
Anna Bridge	180:96ed750bd169	2261	return(0U);
Anna Bridge	180:96ed750bd169	2262	}
Anna Bridge	180:96ed750bd169	2263	}
Anna Bridge	180:96ed750bd169	2264
Anna Bridge	180:96ed750bd169	2265
Anna Bridge	180:96ed750bd169	2266	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	2267	/**
Anna Bridge	180:96ed750bd169	2268	\brief Get Interrupt Target State
Anna Bridge	180:96ed750bd169	2269	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	2270	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2271	\return 0 if interrupt is assigned to Secure
Anna Bridge	180:96ed750bd169	2272	\return 1 if interrupt is assigned to Non Secure
Anna Bridge	180:96ed750bd169	2273	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2274	*/
Anna Bridge	180:96ed750bd169	2275	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2276	{
Anna Bridge	180:96ed750bd169	2277	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2278	{
Anna Bridge	186:707f6e361f3e	2279	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2280	}
Anna Bridge	180:96ed750bd169	2281	else
Anna Bridge	180:96ed750bd169	2282	{
Anna Bridge	180:96ed750bd169	2283	return(0U);
Anna Bridge	180:96ed750bd169	2284	}
Anna Bridge	180:96ed750bd169	2285	}
Anna Bridge	180:96ed750bd169	2286
Anna Bridge	180:96ed750bd169	2287
Anna Bridge	180:96ed750bd169	2288	/**
Anna Bridge	180:96ed750bd169	2289	\brief Set Interrupt Target State
Anna Bridge	180:96ed750bd169	2290	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	2291	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2292	\return 0 if interrupt is assigned to Secure
Anna Bridge	180:96ed750bd169	2293	1 if interrupt is assigned to Non Secure
Anna Bridge	180:96ed750bd169	2294	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2295	*/
Anna Bridge	180:96ed750bd169	2296	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2297	{
Anna Bridge	180:96ed750bd169	2298	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2299	{
Anna Bridge	186:707f6e361f3e	2300	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	186:707f6e361f3e	2301	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2302	}
Anna Bridge	180:96ed750bd169	2303	else
Anna Bridge	180:96ed750bd169	2304	{
Anna Bridge	180:96ed750bd169	2305	return(0U);
Anna Bridge	180:96ed750bd169	2306	}
Anna Bridge	180:96ed750bd169	2307	}
Anna Bridge	180:96ed750bd169	2308
Anna Bridge	180:96ed750bd169	2309
Anna Bridge	180:96ed750bd169	2310	/**
Anna Bridge	180:96ed750bd169	2311	\brief Clear Interrupt Target State
Anna Bridge	180:96ed750bd169	2312	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	2313	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2314	\return 0 if interrupt is assigned to Secure
Anna Bridge	180:96ed750bd169	2315	1 if interrupt is assigned to Non Secure
Anna Bridge	180:96ed750bd169	2316	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2317	*/
Anna Bridge	180:96ed750bd169	2318	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2319	{
Anna Bridge	180:96ed750bd169	2320	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2321	{
Anna Bridge	186:707f6e361f3e	2322	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	186:707f6e361f3e	2323	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2324	}
Anna Bridge	180:96ed750bd169	2325	else
Anna Bridge	180:96ed750bd169	2326	{
Anna Bridge	180:96ed750bd169	2327	return(0U);
Anna Bridge	180:96ed750bd169	2328	}
Anna Bridge	180:96ed750bd169	2329	}
Anna Bridge	180:96ed750bd169	2330	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	180:96ed750bd169	2331
Anna Bridge	180:96ed750bd169	2332
Anna Bridge	180:96ed750bd169	2333	/**
Anna Bridge	180:96ed750bd169	2334	\brief Set Interrupt Priority
Anna Bridge	180:96ed750bd169	2335	\details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge	180:96ed750bd169	2336	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2337	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2338	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2339	\param [in] priority Priority to set.
Anna Bridge	180:96ed750bd169	2340	\note The priority cannot be set for every processor exception.
Anna Bridge	180:96ed750bd169	2341	*/
Anna Bridge	180:96ed750bd169	2342	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	180:96ed750bd169	2343	{
Anna Bridge	180:96ed750bd169	2344	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2345	{
Anna Bridge	186:707f6e361f3e	2346	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	2347	}
Anna Bridge	180:96ed750bd169	2348	else
Anna Bridge	180:96ed750bd169	2349	{
Anna Bridge	186:707f6e361f3e	2350	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	2351	}
Anna Bridge	180:96ed750bd169	2352	}
Anna Bridge	180:96ed750bd169	2353
Anna Bridge	180:96ed750bd169	2354
Anna Bridge	180:96ed750bd169	2355	/**
Anna Bridge	180:96ed750bd169	2356	\brief Get Interrupt Priority
Anna Bridge	180:96ed750bd169	2357	\details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge	180:96ed750bd169	2358	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2359	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2360	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2361	\return Interrupt Priority.
Anna Bridge	180:96ed750bd169	2362	Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge	180:96ed750bd169	2363	*/
Anna Bridge	180:96ed750bd169	2364	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2365	{
Anna Bridge	180:96ed750bd169	2366
Anna Bridge	180:96ed750bd169	2367	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2368	{
Anna Bridge	186:707f6e361f3e	2369	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	2370	}
Anna Bridge	180:96ed750bd169	2371	else
Anna Bridge	180:96ed750bd169	2372	{
Anna Bridge	186:707f6e361f3e	2373	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	2374	}
Anna Bridge	180:96ed750bd169	2375	}
Anna Bridge	180:96ed750bd169	2376
Anna Bridge	180:96ed750bd169	2377
Anna Bridge	180:96ed750bd169	2378	/**
Anna Bridge	180:96ed750bd169	2379	\brief Encode Priority
Anna Bridge	180:96ed750bd169	2380	\details Encodes the priority for an interrupt with the given priority group,
Anna Bridge	180:96ed750bd169	2381	preemptive priority value, and subpriority value.
Anna Bridge	180:96ed750bd169	2382	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	2383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	2384	\param [in] PriorityGroup Used priority group.
Anna Bridge	180:96ed750bd169	2385	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	180:96ed750bd169	2386	\param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge	180:96ed750bd169	2387	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge	180:96ed750bd169	2388	*/
Anna Bridge	180:96ed750bd169	2389	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge	180:96ed750bd169	2390	{
Anna Bridge	180:96ed750bd169	2391	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	2392	uint32_t PreemptPriorityBits;
Anna Bridge	180:96ed750bd169	2393	uint32_t SubPriorityBits;
Anna Bridge	180:96ed750bd169	2394
Anna Bridge	180:96ed750bd169	2395	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	180:96ed750bd169	2396	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	180:96ed750bd169	2397
Anna Bridge	180:96ed750bd169	2398	return (
Anna Bridge	180:96ed750bd169	2399	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Anna Bridge	180:96ed750bd169	2400	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge	180:96ed750bd169	2401	);
Anna Bridge	180:96ed750bd169	2402	}
Anna Bridge	180:96ed750bd169	2403
Anna Bridge	180:96ed750bd169	2404
Anna Bridge	180:96ed750bd169	2405	/**
Anna Bridge	180:96ed750bd169	2406	\brief Decode Priority
Anna Bridge	180:96ed750bd169	2407	\details Decodes an interrupt priority value with a given priority group to
Anna Bridge	180:96ed750bd169	2408	preemptive priority value and subpriority value.
Anna Bridge	180:96ed750bd169	2409	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	2410	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	2411	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge	180:96ed750bd169	2412	\param [in] PriorityGroup Used priority group.
Anna Bridge	180:96ed750bd169	2413	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	180:96ed750bd169	2414	\param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge	180:96ed750bd169	2415	*/
Anna Bridge	180:96ed750bd169	2416	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Anna Bridge	180:96ed750bd169	2417	{
Anna Bridge	180:96ed750bd169	2418	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	2419	uint32_t PreemptPriorityBits;
Anna Bridge	180:96ed750bd169	2420	uint32_t SubPriorityBits;
Anna Bridge	180:96ed750bd169	2421
Anna Bridge	180:96ed750bd169	2422	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	180:96ed750bd169	2423	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	180:96ed750bd169	2424
Anna Bridge	180:96ed750bd169	2425	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge	180:96ed750bd169	2426	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge	180:96ed750bd169	2427	}
Anna Bridge	180:96ed750bd169	2428
Anna Bridge	180:96ed750bd169	2429
Anna Bridge	180:96ed750bd169	2430	/**
Anna Bridge	180:96ed750bd169	2431	\brief Set Interrupt Vector
Anna Bridge	180:96ed750bd169	2432	\details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge	180:96ed750bd169	2433	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2434	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2435	VTOR must been relocated to SRAM before.
Anna Bridge	180:96ed750bd169	2436	\param [in] IRQn Interrupt number
Anna Bridge	180:96ed750bd169	2437	\param [in] vector Address of interrupt handler function
Anna Bridge	180:96ed750bd169	2438	*/
Anna Bridge	180:96ed750bd169	2439	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge	180:96ed750bd169	2440	{
Anna Bridge	180:96ed750bd169	2441	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	180:96ed750bd169	2442	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge	180:96ed750bd169	2443	}
Anna Bridge	180:96ed750bd169	2444
Anna Bridge	180:96ed750bd169	2445
Anna Bridge	180:96ed750bd169	2446	/**
Anna Bridge	180:96ed750bd169	2447	\brief Get Interrupt Vector
Anna Bridge	180:96ed750bd169	2448	\details Reads an interrupt vector from interrupt vector table.
Anna Bridge	180:96ed750bd169	2449	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2450	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2451	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2452	\return Address of interrupt handler function
Anna Bridge	180:96ed750bd169	2453	*/
Anna Bridge	180:96ed750bd169	2454	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2455	{
Anna Bridge	180:96ed750bd169	2456	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	180:96ed750bd169	2457	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge	180:96ed750bd169	2458	}
Anna Bridge	180:96ed750bd169	2459
Anna Bridge	180:96ed750bd169	2460
Anna Bridge	180:96ed750bd169	2461	/**
Anna Bridge	180:96ed750bd169	2462	\brief System Reset
Anna Bridge	180:96ed750bd169	2463	\details Initiates a system reset request to reset the MCU.
Anna Bridge	180:96ed750bd169	2464	*/
AnnaBridge	188:bcfe06ba3d64	2465	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge	180:96ed750bd169	2466	{
Anna Bridge	180:96ed750bd169	2467	__DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge	180:96ed750bd169	2468	buffered write are completed before reset */
Anna Bridge	180:96ed750bd169	2469	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	180:96ed750bd169	2470	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Anna Bridge	180:96ed750bd169	2471	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge	180:96ed750bd169	2472	__DSB(); /* Ensure completion of memory access */
Anna Bridge	180:96ed750bd169	2473
Anna Bridge	180:96ed750bd169	2474	for(;;) /* wait until reset */
Anna Bridge	180:96ed750bd169	2475	{
Anna Bridge	180:96ed750bd169	2476	__NOP();
Anna Bridge	180:96ed750bd169	2477	}
Anna Bridge	180:96ed750bd169	2478	}
Anna Bridge	180:96ed750bd169	2479
Anna Bridge	180:96ed750bd169	2480	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	2481	/**
Anna Bridge	180:96ed750bd169	2482	\brief Set Priority Grouping (non-secure)
Anna Bridge	180:96ed750bd169	2483	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
Anna Bridge	180:96ed750bd169	2484	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	180:96ed750bd169	2485	Only values from 0..7 are used.
Anna Bridge	180:96ed750bd169	2486	In case of a conflict between priority grouping and available
Anna Bridge	180:96ed750bd169	2487	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	180:96ed750bd169	2488	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	180:96ed750bd169	2489	*/
Anna Bridge	180:96ed750bd169	2490	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
Anna Bridge	180:96ed750bd169	2491	{
Anna Bridge	180:96ed750bd169	2492	uint32_t reg_value;
Anna Bridge	180:96ed750bd169	2493	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	180:96ed750bd169	2494
Anna Bridge	180:96ed750bd169	2495	reg_value = SCB_NS->AIRCR; /* read old register configuration */
Anna Bridge	180:96ed750bd169	2496	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	180:96ed750bd169	2497	reg_value = (reg_value \|
Anna Bridge	180:96ed750bd169	2498	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	180:96ed750bd169	2499	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Anna Bridge	180:96ed750bd169	2500	SCB_NS->AIRCR = reg_value;
Anna Bridge	180:96ed750bd169	2501	}
Anna Bridge	180:96ed750bd169	2502
Anna Bridge	180:96ed750bd169	2503
Anna Bridge	180:96ed750bd169	2504	/**
Anna Bridge	180:96ed750bd169	2505	\brief Get Priority Grouping (non-secure)
Anna Bridge	180:96ed750bd169	2506	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
Anna Bridge	180:96ed750bd169	2507	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	180:96ed750bd169	2508	*/
Anna Bridge	180:96ed750bd169	2509	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
Anna Bridge	180:96ed750bd169	2510	{
Anna Bridge	180:96ed750bd169	2511	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	180:96ed750bd169	2512	}
Anna Bridge	180:96ed750bd169	2513
Anna Bridge	180:96ed750bd169	2514
Anna Bridge	180:96ed750bd169	2515	/**
Anna Bridge	180:96ed750bd169	2516	\brief Enable Interrupt (non-secure)
Anna Bridge	180:96ed750bd169	2517	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge	180:96ed750bd169	2518	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2519	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2520	*/
Anna Bridge	180:96ed750bd169	2521	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2522	{
Anna Bridge	180:96ed750bd169	2523	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2524	{
Anna Bridge	186:707f6e361f3e	2525	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2526	}
Anna Bridge	180:96ed750bd169	2527	}
Anna Bridge	180:96ed750bd169	2528
Anna Bridge	180:96ed750bd169	2529
Anna Bridge	180:96ed750bd169	2530	/**
Anna Bridge	180:96ed750bd169	2531	\brief Get Interrupt Enable status (non-secure)
Anna Bridge	180:96ed750bd169	2532	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Anna Bridge	180:96ed750bd169	2533	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2534	\return 0 Interrupt is not enabled.
Anna Bridge	180:96ed750bd169	2535	\return 1 Interrupt is enabled.
Anna Bridge	180:96ed750bd169	2536	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2537	*/
Anna Bridge	180:96ed750bd169	2538	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2539	{
Anna Bridge	180:96ed750bd169	2540	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2541	{
Anna Bridge	186:707f6e361f3e	2542	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2543	}
Anna Bridge	180:96ed750bd169	2544	else
Anna Bridge	180:96ed750bd169	2545	{
Anna Bridge	180:96ed750bd169	2546	return(0U);
Anna Bridge	180:96ed750bd169	2547	}
Anna Bridge	180:96ed750bd169	2548	}
Anna Bridge	180:96ed750bd169	2549
Anna Bridge	180:96ed750bd169	2550
Anna Bridge	180:96ed750bd169	2551	/**
Anna Bridge	180:96ed750bd169	2552	\brief Disable Interrupt (non-secure)
Anna Bridge	180:96ed750bd169	2553	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge	180:96ed750bd169	2554	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2555	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2556	*/
Anna Bridge	180:96ed750bd169	2557	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2558	{
Anna Bridge	180:96ed750bd169	2559	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2560	{
Anna Bridge	186:707f6e361f3e	2561	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2562	}
Anna Bridge	180:96ed750bd169	2563	}
Anna Bridge	180:96ed750bd169	2564
Anna Bridge	180:96ed750bd169	2565
Anna Bridge	180:96ed750bd169	2566	/**
Anna Bridge	180:96ed750bd169	2567	\brief Get Pending Interrupt (non-secure)
Anna Bridge	180:96ed750bd169	2568	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Anna Bridge	180:96ed750bd169	2569	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2570	\return 0 Interrupt status is not pending.
Anna Bridge	180:96ed750bd169	2571	\return 1 Interrupt status is pending.
Anna Bridge	180:96ed750bd169	2572	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2573	*/
Anna Bridge	180:96ed750bd169	2574	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2575	{
Anna Bridge	180:96ed750bd169	2576	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2577	{
Anna Bridge	186:707f6e361f3e	2578	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2579	}
Anna Bridge	180:96ed750bd169	2580	else
Anna Bridge	180:96ed750bd169	2581	{
Anna Bridge	180:96ed750bd169	2582	return(0U);
Anna Bridge	180:96ed750bd169	2583	}
Anna Bridge	180:96ed750bd169	2584	}
Anna Bridge	180:96ed750bd169	2585
Anna Bridge	180:96ed750bd169	2586
Anna Bridge	180:96ed750bd169	2587	/**
Anna Bridge	180:96ed750bd169	2588	\brief Set Pending Interrupt (non-secure)
Anna Bridge	180:96ed750bd169	2589	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge	180:96ed750bd169	2590	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2591	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2592	*/
Anna Bridge	180:96ed750bd169	2593	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2594	{
Anna Bridge	180:96ed750bd169	2595	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2596	{
Anna Bridge	186:707f6e361f3e	2597	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2598	}
Anna Bridge	180:96ed750bd169	2599	}
Anna Bridge	180:96ed750bd169	2600
Anna Bridge	180:96ed750bd169	2601
Anna Bridge	180:96ed750bd169	2602	/**
Anna Bridge	180:96ed750bd169	2603	\brief Clear Pending Interrupt (non-secure)
Anna Bridge	180:96ed750bd169	2604	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge	180:96ed750bd169	2605	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2606	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2607	*/
Anna Bridge	180:96ed750bd169	2608	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2609	{
Anna Bridge	180:96ed750bd169	2610	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2611	{
Anna Bridge	186:707f6e361f3e	2612	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	180:96ed750bd169	2613	}
Anna Bridge	180:96ed750bd169	2614	}
Anna Bridge	180:96ed750bd169	2615
Anna Bridge	180:96ed750bd169	2616
Anna Bridge	180:96ed750bd169	2617	/**
Anna Bridge	180:96ed750bd169	2618	\brief Get Active Interrupt (non-secure)
Anna Bridge	180:96ed750bd169	2619	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Anna Bridge	180:96ed750bd169	2620	\param [in] IRQn Device specific interrupt number.
Anna Bridge	180:96ed750bd169	2621	\return 0 Interrupt status is not active.
Anna Bridge	180:96ed750bd169	2622	\return 1 Interrupt status is active.
Anna Bridge	180:96ed750bd169	2623	\note IRQn must not be negative.
Anna Bridge	180:96ed750bd169	2624	*/
Anna Bridge	180:96ed750bd169	2625	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2626	{
Anna Bridge	180:96ed750bd169	2627	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2628	{
Anna Bridge	186:707f6e361f3e	2629	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	180:96ed750bd169	2630	}
Anna Bridge	180:96ed750bd169	2631	else
Anna Bridge	180:96ed750bd169	2632	{
Anna Bridge	180:96ed750bd169	2633	return(0U);
Anna Bridge	180:96ed750bd169	2634	}
Anna Bridge	180:96ed750bd169	2635	}
Anna Bridge	180:96ed750bd169	2636
Anna Bridge	180:96ed750bd169	2637
Anna Bridge	180:96ed750bd169	2638	/**
Anna Bridge	180:96ed750bd169	2639	\brief Set Interrupt Priority (non-secure)
Anna Bridge	180:96ed750bd169	2640	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge	180:96ed750bd169	2641	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2642	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2643	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2644	\param [in] priority Priority to set.
Anna Bridge	180:96ed750bd169	2645	\note The priority cannot be set for every non-secure processor exception.
Anna Bridge	180:96ed750bd169	2646	*/
Anna Bridge	180:96ed750bd169	2647	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	180:96ed750bd169	2648	{
Anna Bridge	180:96ed750bd169	2649	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2650	{
Anna Bridge	186:707f6e361f3e	2651	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	2652	}
Anna Bridge	180:96ed750bd169	2653	else
Anna Bridge	180:96ed750bd169	2654	{
Anna Bridge	186:707f6e361f3e	2655	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	180:96ed750bd169	2656	}
Anna Bridge	180:96ed750bd169	2657	}
Anna Bridge	180:96ed750bd169	2658
Anna Bridge	180:96ed750bd169	2659
Anna Bridge	180:96ed750bd169	2660	/**
Anna Bridge	180:96ed750bd169	2661	\brief Get Interrupt Priority (non-secure)
Anna Bridge	180:96ed750bd169	2662	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge	180:96ed750bd169	2663	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	180:96ed750bd169	2664	or negative to specify a processor exception.
Anna Bridge	180:96ed750bd169	2665	\param [in] IRQn Interrupt number.
Anna Bridge	180:96ed750bd169	2666	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge	180:96ed750bd169	2667	*/
Anna Bridge	180:96ed750bd169	2668	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Anna Bridge	180:96ed750bd169	2669	{
Anna Bridge	180:96ed750bd169	2670
Anna Bridge	180:96ed750bd169	2671	if ((int32_t)(IRQn) >= 0)
Anna Bridge	180:96ed750bd169	2672	{
Anna Bridge	186:707f6e361f3e	2673	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	2674	}
Anna Bridge	180:96ed750bd169	2675	else
Anna Bridge	180:96ed750bd169	2676	{
Anna Bridge	186:707f6e361f3e	2677	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	180:96ed750bd169	2678	}
Anna Bridge	180:96ed750bd169	2679	}
Anna Bridge	180:96ed750bd169	2680	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	180:96ed750bd169	2681
Anna Bridge	180:96ed750bd169	2682	/@} end of CMSIS_Core_NVICFunctions /
Anna Bridge	180:96ed750bd169	2683
Anna Bridge	180:96ed750bd169	2684	/* ########################## MPU functions #################################### */
Anna Bridge	180:96ed750bd169	2685
Anna Bridge	180:96ed750bd169	2686	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	180:96ed750bd169	2687
Anna Bridge	180:96ed750bd169	2688	#include "mpu_armv8.h"
Anna Bridge	180:96ed750bd169	2689
Anna Bridge	180:96ed750bd169	2690	#endif
Anna Bridge	180:96ed750bd169	2691
Anna Bridge	180:96ed750bd169	2692	/* ########################## FPU functions #################################### */
Anna Bridge	180:96ed750bd169	2693	/**
Anna Bridge	180:96ed750bd169	2694	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2695	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge	180:96ed750bd169	2696	\brief Function that provides FPU type.
Anna Bridge	180:96ed750bd169	2697	@{
Anna Bridge	180:96ed750bd169	2698	*/
Anna Bridge	180:96ed750bd169	2699
Anna Bridge	180:96ed750bd169	2700	/**
Anna Bridge	180:96ed750bd169	2701	\brief get FPU type
Anna Bridge	180:96ed750bd169	2702	\details returns the FPU type
Anna Bridge	180:96ed750bd169	2703	\returns
Anna Bridge	180:96ed750bd169	2704	- \b 0: No FPU
Anna Bridge	180:96ed750bd169	2705	- \b 1: Single precision FPU
Anna Bridge	180:96ed750bd169	2706	- \b 2: Double + Single precision FPU
Anna Bridge	180:96ed750bd169	2707	*/
Anna Bridge	180:96ed750bd169	2708	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge	180:96ed750bd169	2709	{
Anna Bridge	180:96ed750bd169	2710	uint32_t mvfr0;
Anna Bridge	180:96ed750bd169	2711
Anna Bridge	180:96ed750bd169	2712	mvfr0 = FPU->MVFR0;
Anna Bridge	180:96ed750bd169	2713	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
Anna Bridge	180:96ed750bd169	2714	{
Anna Bridge	180:96ed750bd169	2715	return 2U; /* Double + Single precision FPU */
Anna Bridge	180:96ed750bd169	2716	}
Anna Bridge	180:96ed750bd169	2717	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
Anna Bridge	180:96ed750bd169	2718	{
Anna Bridge	180:96ed750bd169	2719	return 1U; /* Single precision FPU */
Anna Bridge	180:96ed750bd169	2720	}
Anna Bridge	180:96ed750bd169	2721	else
Anna Bridge	180:96ed750bd169	2722	{
Anna Bridge	180:96ed750bd169	2723	return 0U; /* No FPU */
Anna Bridge	180:96ed750bd169	2724	}
Anna Bridge	180:96ed750bd169	2725	}
Anna Bridge	180:96ed750bd169	2726
Anna Bridge	180:96ed750bd169	2727
Anna Bridge	180:96ed750bd169	2728	/@} end of CMSIS_Core_FpuFunctions /
Anna Bridge	180:96ed750bd169	2729
Anna Bridge	180:96ed750bd169	2730
Anna Bridge	180:96ed750bd169	2731
Anna Bridge	180:96ed750bd169	2732	/* ########################## SAU functions #################################### */
Anna Bridge	180:96ed750bd169	2733	/**
Anna Bridge	180:96ed750bd169	2734	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2735	\defgroup CMSIS_Core_SAUFunctions SAU Functions
Anna Bridge	180:96ed750bd169	2736	\brief Functions that configure the SAU.
Anna Bridge	180:96ed750bd169	2737	@{
Anna Bridge	180:96ed750bd169	2738	*/
Anna Bridge	180:96ed750bd169	2739
Anna Bridge	180:96ed750bd169	2740	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	2741
Anna Bridge	180:96ed750bd169	2742	/**
Anna Bridge	180:96ed750bd169	2743	\brief Enable SAU
Anna Bridge	180:96ed750bd169	2744	\details Enables the Security Attribution Unit (SAU).
Anna Bridge	180:96ed750bd169	2745	*/
Anna Bridge	180:96ed750bd169	2746	__STATIC_INLINE void TZ_SAU_Enable(void)
Anna Bridge	180:96ed750bd169	2747	{
Anna Bridge	180:96ed750bd169	2748	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
Anna Bridge	180:96ed750bd169	2749	}
Anna Bridge	180:96ed750bd169	2750
Anna Bridge	180:96ed750bd169	2751
Anna Bridge	180:96ed750bd169	2752
Anna Bridge	180:96ed750bd169	2753	/**
Anna Bridge	180:96ed750bd169	2754	\brief Disable SAU
Anna Bridge	180:96ed750bd169	2755	\details Disables the Security Attribution Unit (SAU).
Anna Bridge	180:96ed750bd169	2756	*/
Anna Bridge	180:96ed750bd169	2757	__STATIC_INLINE void TZ_SAU_Disable(void)
Anna Bridge	180:96ed750bd169	2758	{
Anna Bridge	180:96ed750bd169	2759	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Anna Bridge	180:96ed750bd169	2760	}
Anna Bridge	180:96ed750bd169	2761
Anna Bridge	180:96ed750bd169	2762	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	180:96ed750bd169	2763
Anna Bridge	180:96ed750bd169	2764	/@} end of CMSIS_Core_SAUFunctions /
Anna Bridge	180:96ed750bd169	2765
Anna Bridge	180:96ed750bd169	2766
Anna Bridge	180:96ed750bd169	2767
Anna Bridge	180:96ed750bd169	2768
Anna Bridge	180:96ed750bd169	2769	/* ################################## SysTick function ############################################ */
Anna Bridge	180:96ed750bd169	2770	/**
Anna Bridge	180:96ed750bd169	2771	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2772	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge	180:96ed750bd169	2773	\brief Functions that configure the System.
Anna Bridge	180:96ed750bd169	2774	@{
Anna Bridge	180:96ed750bd169	2775	*/
Anna Bridge	180:96ed750bd169	2776
Anna Bridge	180:96ed750bd169	2777	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge	180:96ed750bd169	2778
Anna Bridge	180:96ed750bd169	2779	/**
Anna Bridge	180:96ed750bd169	2780	\brief System Tick Configuration
Anna Bridge	180:96ed750bd169	2781	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge	180:96ed750bd169	2782	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	180:96ed750bd169	2783	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	180:96ed750bd169	2784	\return 0 Function succeeded.
Anna Bridge	180:96ed750bd169	2785	\return 1 Function failed.
Anna Bridge	180:96ed750bd169	2786	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	180:96ed750bd169	2787	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	180:96ed750bd169	2788	must contain a vendor-specific implementation of this function.
Anna Bridge	180:96ed750bd169	2789	*/
Anna Bridge	180:96ed750bd169	2790	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge	180:96ed750bd169	2791	{
Anna Bridge	180:96ed750bd169	2792	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge	180:96ed750bd169	2793	{
Anna Bridge	180:96ed750bd169	2794	return (1UL); /* Reload value impossible */
Anna Bridge	180:96ed750bd169	2795	}
Anna Bridge	180:96ed750bd169	2796
Anna Bridge	180:96ed750bd169	2797	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	180:96ed750bd169	2798	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	180:96ed750bd169	2799	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	180:96ed750bd169	2800	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	180:96ed750bd169	2801	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	180:96ed750bd169	2802	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	180:96ed750bd169	2803	return (0UL); /* Function successful */
Anna Bridge	180:96ed750bd169	2804	}
Anna Bridge	180:96ed750bd169	2805
Anna Bridge	180:96ed750bd169	2806	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	180:96ed750bd169	2807	/**
Anna Bridge	180:96ed750bd169	2808	\brief System Tick Configuration (non-secure)
Anna Bridge	180:96ed750bd169	2809	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Anna Bridge	180:96ed750bd169	2810	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	180:96ed750bd169	2811	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	180:96ed750bd169	2812	\return 0 Function succeeded.
Anna Bridge	180:96ed750bd169	2813	\return 1 Function failed.
Anna Bridge	180:96ed750bd169	2814	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	180:96ed750bd169	2815	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	180:96ed750bd169	2816	must contain a vendor-specific implementation of this function.
Anna Bridge	180:96ed750bd169	2817
Anna Bridge	180:96ed750bd169	2818	*/
Anna Bridge	180:96ed750bd169	2819	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Anna Bridge	180:96ed750bd169	2820	{
Anna Bridge	180:96ed750bd169	2821	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge	180:96ed750bd169	2822	{
Anna Bridge	180:96ed750bd169	2823	return (1UL); /* Reload value impossible */
Anna Bridge	180:96ed750bd169	2824	}
Anna Bridge	180:96ed750bd169	2825
Anna Bridge	180:96ed750bd169	2826	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	180:96ed750bd169	2827	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	180:96ed750bd169	2828	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	180:96ed750bd169	2829	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	180:96ed750bd169	2830	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	180:96ed750bd169	2831	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	180:96ed750bd169	2832	return (0UL); /* Function successful */
Anna Bridge	180:96ed750bd169	2833	}
Anna Bridge	180:96ed750bd169	2834	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	180:96ed750bd169	2835
Anna Bridge	180:96ed750bd169	2836	#endif
Anna Bridge	180:96ed750bd169	2837
Anna Bridge	180:96ed750bd169	2838	/@} end of CMSIS_Core_SysTickFunctions /
Anna Bridge	180:96ed750bd169	2839
Anna Bridge	180:96ed750bd169	2840
Anna Bridge	180:96ed750bd169	2841
Anna Bridge	180:96ed750bd169	2842	/* ##################################### Debug In/Output function ########################################### */
Anna Bridge	180:96ed750bd169	2843	/**
Anna Bridge	180:96ed750bd169	2844	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	180:96ed750bd169	2845	\defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge	180:96ed750bd169	2846	\brief Functions that access the ITM debug interface.
Anna Bridge	180:96ed750bd169	2847	@{
Anna Bridge	180:96ed750bd169	2848	*/
Anna Bridge	180:96ed750bd169	2849
Anna Bridge	180:96ed750bd169	2850	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Anna Bridge	180:96ed750bd169	2851	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Anna Bridge	180:96ed750bd169	2852
Anna Bridge	180:96ed750bd169	2853
Anna Bridge	180:96ed750bd169	2854	/**
Anna Bridge	180:96ed750bd169	2855	\brief ITM Send Character
Anna Bridge	180:96ed750bd169	2856	\details Transmits a character via the ITM channel 0, and
Anna Bridge	180:96ed750bd169	2857	\li Just returns when no debugger is connected that has booked the output.
Anna Bridge	180:96ed750bd169	2858	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge	180:96ed750bd169	2859	\param [in] ch Character to transmit.
Anna Bridge	180:96ed750bd169	2860	\returns Character to transmit.
Anna Bridge	180:96ed750bd169	2861	*/
Anna Bridge	180:96ed750bd169	2862	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge	180:96ed750bd169	2863	{
Anna Bridge	180:96ed750bd169	2864	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge	180:96ed750bd169	2865	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge	180:96ed750bd169	2866	{
Anna Bridge	180:96ed750bd169	2867	while (ITM->PORT[0U].u32 == 0UL)
Anna Bridge	180:96ed750bd169	2868	{
Anna Bridge	180:96ed750bd169	2869	__NOP();
Anna Bridge	180:96ed750bd169	2870	}
Anna Bridge	180:96ed750bd169	2871	ITM->PORT[0U].u8 = (uint8_t)ch;
Anna Bridge	180:96ed750bd169	2872	}
Anna Bridge	180:96ed750bd169	2873	return (ch);
Anna Bridge	180:96ed750bd169	2874	}
Anna Bridge	180:96ed750bd169	2875
Anna Bridge	180:96ed750bd169	2876
Anna Bridge	180:96ed750bd169	2877	/**
Anna Bridge	180:96ed750bd169	2878	\brief ITM Receive Character
Anna Bridge	180:96ed750bd169	2879	\details Inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge	180:96ed750bd169	2880	\return Received character.
Anna Bridge	180:96ed750bd169	2881	\return -1 No character pending.
Anna Bridge	180:96ed750bd169	2882	*/
Anna Bridge	180:96ed750bd169	2883	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
Anna Bridge	180:96ed750bd169	2884	{
Anna Bridge	180:96ed750bd169	2885	int32_t ch = -1; /* no character available */
Anna Bridge	180:96ed750bd169	2886
Anna Bridge	180:96ed750bd169	2887	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Anna Bridge	180:96ed750bd169	2888	{
Anna Bridge	180:96ed750bd169	2889	ch = ITM_RxBuffer;
Anna Bridge	180:96ed750bd169	2890	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge	180:96ed750bd169	2891	}
Anna Bridge	180:96ed750bd169	2892
Anna Bridge	180:96ed750bd169	2893	return (ch);
Anna Bridge	180:96ed750bd169	2894	}
Anna Bridge	180:96ed750bd169	2895
Anna Bridge	180:96ed750bd169	2896
Anna Bridge	180:96ed750bd169	2897	/**
Anna Bridge	180:96ed750bd169	2898	\brief ITM Check Character
Anna Bridge	180:96ed750bd169	2899	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge	180:96ed750bd169	2900	\return 0 No character available.
Anna Bridge	180:96ed750bd169	2901	\return 1 Character available.
Anna Bridge	180:96ed750bd169	2902	*/
Anna Bridge	180:96ed750bd169	2903	__STATIC_INLINE int32_t ITM_CheckChar (void)
Anna Bridge	180:96ed750bd169	2904	{
Anna Bridge	180:96ed750bd169	2905
Anna Bridge	180:96ed750bd169	2906	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Anna Bridge	180:96ed750bd169	2907	{
Anna Bridge	180:96ed750bd169	2908	return (0); /* no character available */
Anna Bridge	180:96ed750bd169	2909	}
Anna Bridge	180:96ed750bd169	2910	else
Anna Bridge	180:96ed750bd169	2911	{
Anna Bridge	180:96ed750bd169	2912	return (1); /* character available */
Anna Bridge	180:96ed750bd169	2913	}
Anna Bridge	180:96ed750bd169	2914	}
Anna Bridge	180:96ed750bd169	2915
Anna Bridge	180:96ed750bd169	2916	/@} end of CMSIS_core_DebugFunctions /
Anna Bridge	180:96ed750bd169	2917
Anna Bridge	180:96ed750bd169	2918
Anna Bridge	180:96ed750bd169	2919
Anna Bridge	180:96ed750bd169	2920
Anna Bridge	180:96ed750bd169	2921	#ifdef __cplusplus
Anna Bridge	180:96ed750bd169	2922	}
Anna Bridge	180:96ed750bd169	2923	#endif
Anna Bridge	180:96ed750bd169	2924
Anna Bridge	180:96ed750bd169	2925	#endif /* __CORE_ARMV8MML_H_DEPENDANT */
Anna Bridge	180:96ed750bd169	2926
Anna Bridge	180:96ed750bd169	2927	#endif /* __CMSIS_GENERIC */