mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/mpu_armv7.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
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AnnaBridge | 189:f392fc9709a3 | 1 | /****************************************************************************** |
AnnaBridge | 189:f392fc9709a3 | 2 | * @file mpu_armv7.h |
AnnaBridge | 189:f392fc9709a3 | 3 | * @brief CMSIS MPU API for Armv7-M MPU |
AnnaBridge | 189:f392fc9709a3 | 4 | * @version V5.0.5 |
AnnaBridge | 189:f392fc9709a3 | 5 | * @date 06. September 2018 |
AnnaBridge | 189:f392fc9709a3 | 6 | ******************************************************************************/ |
AnnaBridge | 189:f392fc9709a3 | 7 | /* |
AnnaBridge | 189:f392fc9709a3 | 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
AnnaBridge | 189:f392fc9709a3 | 9 | * |
AnnaBridge | 189:f392fc9709a3 | 10 | * SPDX-License-Identifier: Apache-2.0 |
AnnaBridge | 189:f392fc9709a3 | 11 | * |
AnnaBridge | 189:f392fc9709a3 | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
AnnaBridge | 189:f392fc9709a3 | 13 | * not use this file except in compliance with the License. |
AnnaBridge | 189:f392fc9709a3 | 14 | * You may obtain a copy of the License at |
AnnaBridge | 189:f392fc9709a3 | 15 | * |
AnnaBridge | 189:f392fc9709a3 | 16 | * www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 189:f392fc9709a3 | 17 | * |
AnnaBridge | 189:f392fc9709a3 | 18 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 189:f392fc9709a3 | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
AnnaBridge | 189:f392fc9709a3 | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 189:f392fc9709a3 | 21 | * See the License for the specific language governing permissions and |
AnnaBridge | 189:f392fc9709a3 | 22 | * limitations under the License. |
AnnaBridge | 189:f392fc9709a3 | 23 | */ |
AnnaBridge | 189:f392fc9709a3 | 24 | |
AnnaBridge | 189:f392fc9709a3 | 25 | #if defined ( __ICCARM__ ) |
AnnaBridge | 189:f392fc9709a3 | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
AnnaBridge | 189:f392fc9709a3 | 27 | #elif defined (__clang__) |
AnnaBridge | 189:f392fc9709a3 | 28 | #pragma clang system_header /* treat file as system include file */ |
AnnaBridge | 189:f392fc9709a3 | 29 | #endif |
AnnaBridge | 189:f392fc9709a3 | 30 | |
AnnaBridge | 189:f392fc9709a3 | 31 | #ifndef ARM_MPU_ARMV7_H |
AnnaBridge | 189:f392fc9709a3 | 32 | #define ARM_MPU_ARMV7_H |
AnnaBridge | 189:f392fc9709a3 | 33 | |
AnnaBridge | 189:f392fc9709a3 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes |
AnnaBridge | 189:f392fc9709a3 | 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes |
AnnaBridge | 189:f392fc9709a3 | 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes |
AnnaBridge | 189:f392fc9709a3 | 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes |
AnnaBridge | 189:f392fc9709a3 | 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes |
AnnaBridge | 189:f392fc9709a3 | 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte |
AnnaBridge | 189:f392fc9709a3 | 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes |
AnnaBridge | 189:f392fc9709a3 | 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes |
AnnaBridge | 189:f392fc9709a3 | 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes |
AnnaBridge | 189:f392fc9709a3 | 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes |
AnnaBridge | 189:f392fc9709a3 | 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes |
AnnaBridge | 189:f392fc9709a3 | 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes |
AnnaBridge | 189:f392fc9709a3 | 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes |
AnnaBridge | 189:f392fc9709a3 | 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes |
AnnaBridge | 189:f392fc9709a3 | 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes |
AnnaBridge | 189:f392fc9709a3 | 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte |
AnnaBridge | 189:f392fc9709a3 | 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes |
AnnaBridge | 189:f392fc9709a3 | 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes |
AnnaBridge | 189:f392fc9709a3 | 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes |
AnnaBridge | 189:f392fc9709a3 | 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes |
AnnaBridge | 189:f392fc9709a3 | 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes |
AnnaBridge | 189:f392fc9709a3 | 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes |
AnnaBridge | 189:f392fc9709a3 | 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes |
AnnaBridge | 189:f392fc9709a3 | 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes |
AnnaBridge | 189:f392fc9709a3 | 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes |
AnnaBridge | 189:f392fc9709a3 | 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte |
AnnaBridge | 189:f392fc9709a3 | 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes |
AnnaBridge | 189:f392fc9709a3 | 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes |
AnnaBridge | 189:f392fc9709a3 | 62 | |
AnnaBridge | 189:f392fc9709a3 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access |
AnnaBridge | 189:f392fc9709a3 | 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only |
AnnaBridge | 189:f392fc9709a3 | 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only |
AnnaBridge | 189:f392fc9709a3 | 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access |
AnnaBridge | 189:f392fc9709a3 | 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only |
AnnaBridge | 189:f392fc9709a3 | 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access |
AnnaBridge | 189:f392fc9709a3 | 69 | |
AnnaBridge | 189:f392fc9709a3 | 70 | /** MPU Region Base Address Register Value |
AnnaBridge | 189:f392fc9709a3 | 71 | * |
AnnaBridge | 189:f392fc9709a3 | 72 | * \param Region The region to be configured, number 0 to 15. |
AnnaBridge | 189:f392fc9709a3 | 73 | * \param BaseAddress The base address for the region. |
AnnaBridge | 189:f392fc9709a3 | 74 | */ |
AnnaBridge | 189:f392fc9709a3 | 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ |
AnnaBridge | 189:f392fc9709a3 | 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 78 | (MPU_RBAR_VALID_Msk)) |
AnnaBridge | 189:f392fc9709a3 | 79 | |
AnnaBridge | 189:f392fc9709a3 | 80 | /** |
AnnaBridge | 189:f392fc9709a3 | 81 | * MPU Memory Access Attributes |
AnnaBridge | 189:f392fc9709a3 | 82 | * |
AnnaBridge | 189:f392fc9709a3 | 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. |
AnnaBridge | 189:f392fc9709a3 | 84 | * \param IsShareable Region is shareable between multiple bus masters. |
AnnaBridge | 189:f392fc9709a3 | 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. |
AnnaBridge | 189:f392fc9709a3 | 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. |
AnnaBridge | 189:f392fc9709a3 | 87 | */ |
AnnaBridge | 189:f392fc9709a3 | 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ |
AnnaBridge | 189:f392fc9709a3 | 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) |
AnnaBridge | 189:f392fc9709a3 | 93 | |
AnnaBridge | 189:f392fc9709a3 | 94 | /** |
AnnaBridge | 189:f392fc9709a3 | 95 | * MPU Region Attribute and Size Register Value |
AnnaBridge | 189:f392fc9709a3 | 96 | * |
AnnaBridge | 189:f392fc9709a3 | 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. |
AnnaBridge | 189:f392fc9709a3 | 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. |
AnnaBridge | 189:f392fc9709a3 | 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. |
AnnaBridge | 189:f392fc9709a3 | 100 | * \param SubRegionDisable Sub-region disable field. |
AnnaBridge | 189:f392fc9709a3 | 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. |
AnnaBridge | 189:f392fc9709a3 | 102 | */ |
AnnaBridge | 189:f392fc9709a3 | 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ |
AnnaBridge | 189:f392fc9709a3 | 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ |
AnnaBridge | 189:f392fc9709a3 | 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ |
AnnaBridge | 189:f392fc9709a3 | 109 | (((MPU_RASR_ENABLE_Msk)))) |
AnnaBridge | 189:f392fc9709a3 | 110 | |
AnnaBridge | 189:f392fc9709a3 | 111 | /** |
AnnaBridge | 189:f392fc9709a3 | 112 | * MPU Region Attribute and Size Register Value |
AnnaBridge | 189:f392fc9709a3 | 113 | * |
AnnaBridge | 189:f392fc9709a3 | 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. |
AnnaBridge | 189:f392fc9709a3 | 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. |
AnnaBridge | 189:f392fc9709a3 | 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. |
AnnaBridge | 189:f392fc9709a3 | 117 | * \param IsShareable Region is shareable between multiple bus masters. |
AnnaBridge | 189:f392fc9709a3 | 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. |
AnnaBridge | 189:f392fc9709a3 | 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. |
AnnaBridge | 189:f392fc9709a3 | 120 | * \param SubRegionDisable Sub-region disable field. |
AnnaBridge | 189:f392fc9709a3 | 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. |
AnnaBridge | 189:f392fc9709a3 | 122 | */ |
AnnaBridge | 189:f392fc9709a3 | 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ |
AnnaBridge | 189:f392fc9709a3 | 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) |
AnnaBridge | 189:f392fc9709a3 | 125 | |
AnnaBridge | 189:f392fc9709a3 | 126 | /** |
AnnaBridge | 189:f392fc9709a3 | 127 | * MPU Memory Access Attribute for strongly ordered memory. |
AnnaBridge | 189:f392fc9709a3 | 128 | * - TEX: 000b |
AnnaBridge | 189:f392fc9709a3 | 129 | * - Shareable |
AnnaBridge | 189:f392fc9709a3 | 130 | * - Non-cacheable |
AnnaBridge | 189:f392fc9709a3 | 131 | * - Non-bufferable |
AnnaBridge | 189:f392fc9709a3 | 132 | */ |
AnnaBridge | 189:f392fc9709a3 | 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) |
AnnaBridge | 189:f392fc9709a3 | 134 | |
AnnaBridge | 189:f392fc9709a3 | 135 | /** |
AnnaBridge | 189:f392fc9709a3 | 136 | * MPU Memory Access Attribute for device memory. |
AnnaBridge | 189:f392fc9709a3 | 137 | * - TEX: 000b (if non-shareable) or 010b (if shareable) |
AnnaBridge | 189:f392fc9709a3 | 138 | * - Shareable or non-shareable |
AnnaBridge | 189:f392fc9709a3 | 139 | * - Non-cacheable |
AnnaBridge | 189:f392fc9709a3 | 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) |
AnnaBridge | 189:f392fc9709a3 | 141 | * |
AnnaBridge | 189:f392fc9709a3 | 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. |
AnnaBridge | 189:f392fc9709a3 | 143 | */ |
AnnaBridge | 189:f392fc9709a3 | 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) |
AnnaBridge | 189:f392fc9709a3 | 145 | |
AnnaBridge | 189:f392fc9709a3 | 146 | /** |
AnnaBridge | 189:f392fc9709a3 | 147 | * MPU Memory Access Attribute for normal memory. |
AnnaBridge | 189:f392fc9709a3 | 148 | * - TEX: 1BBb (reflecting outer cacheability rules) |
AnnaBridge | 189:f392fc9709a3 | 149 | * - Shareable or non-shareable |
AnnaBridge | 189:f392fc9709a3 | 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) |
AnnaBridge | 189:f392fc9709a3 | 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) |
AnnaBridge | 189:f392fc9709a3 | 152 | * |
AnnaBridge | 189:f392fc9709a3 | 153 | * \param OuterCp Configures the outer cache policy. |
AnnaBridge | 189:f392fc9709a3 | 154 | * \param InnerCp Configures the inner cache policy. |
AnnaBridge | 189:f392fc9709a3 | 155 | * \param IsShareable Configures the memory as shareable or non-shareable. |
AnnaBridge | 189:f392fc9709a3 | 156 | */ |
AnnaBridge | 189:f392fc9709a3 | 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) |
AnnaBridge | 189:f392fc9709a3 | 158 | |
AnnaBridge | 189:f392fc9709a3 | 159 | /** |
AnnaBridge | 189:f392fc9709a3 | 160 | * MPU Memory Access Attribute non-cacheable policy. |
AnnaBridge | 189:f392fc9709a3 | 161 | */ |
AnnaBridge | 189:f392fc9709a3 | 162 | #define ARM_MPU_CACHEP_NOCACHE 0U |
AnnaBridge | 189:f392fc9709a3 | 163 | |
AnnaBridge | 189:f392fc9709a3 | 164 | /** |
AnnaBridge | 189:f392fc9709a3 | 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. |
AnnaBridge | 189:f392fc9709a3 | 166 | */ |
AnnaBridge | 189:f392fc9709a3 | 167 | #define ARM_MPU_CACHEP_WB_WRA 1U |
AnnaBridge | 189:f392fc9709a3 | 168 | |
AnnaBridge | 189:f392fc9709a3 | 169 | /** |
AnnaBridge | 189:f392fc9709a3 | 170 | * MPU Memory Access Attribute write-through, no write allocate policy. |
AnnaBridge | 189:f392fc9709a3 | 171 | */ |
AnnaBridge | 189:f392fc9709a3 | 172 | #define ARM_MPU_CACHEP_WT_NWA 2U |
AnnaBridge | 189:f392fc9709a3 | 173 | |
AnnaBridge | 189:f392fc9709a3 | 174 | /** |
AnnaBridge | 189:f392fc9709a3 | 175 | * MPU Memory Access Attribute write-back, no write allocate policy. |
AnnaBridge | 189:f392fc9709a3 | 176 | */ |
AnnaBridge | 189:f392fc9709a3 | 177 | #define ARM_MPU_CACHEP_WB_NWA 3U |
AnnaBridge | 189:f392fc9709a3 | 178 | |
AnnaBridge | 189:f392fc9709a3 | 179 | |
AnnaBridge | 189:f392fc9709a3 | 180 | /** |
AnnaBridge | 189:f392fc9709a3 | 181 | * Struct for a single MPU Region |
AnnaBridge | 189:f392fc9709a3 | 182 | */ |
AnnaBridge | 189:f392fc9709a3 | 183 | typedef struct { |
AnnaBridge | 189:f392fc9709a3 | 184 | uint32_t RBAR; //!< The region base address register value (RBAR) |
AnnaBridge | 189:f392fc9709a3 | 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR |
AnnaBridge | 189:f392fc9709a3 | 186 | } ARM_MPU_Region_t; |
AnnaBridge | 189:f392fc9709a3 | 187 | |
AnnaBridge | 189:f392fc9709a3 | 188 | /** Enable the MPU. |
AnnaBridge | 189:f392fc9709a3 | 189 | * \param MPU_Control Default access permissions for unconfigured regions. |
AnnaBridge | 189:f392fc9709a3 | 190 | */ |
AnnaBridge | 189:f392fc9709a3 | 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) |
AnnaBridge | 189:f392fc9709a3 | 192 | { |
AnnaBridge | 189:f392fc9709a3 | 193 | __DSB(); |
AnnaBridge | 189:f392fc9709a3 | 194 | __ISB(); |
AnnaBridge | 189:f392fc9709a3 | 195 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
AnnaBridge | 189:f392fc9709a3 | 196 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk |
AnnaBridge | 189:f392fc9709a3 | 197 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
AnnaBridge | 189:f392fc9709a3 | 198 | #endif |
AnnaBridge | 189:f392fc9709a3 | 199 | } |
AnnaBridge | 189:f392fc9709a3 | 200 | |
AnnaBridge | 189:f392fc9709a3 | 201 | /** Disable the MPU. |
AnnaBridge | 189:f392fc9709a3 | 202 | */ |
AnnaBridge | 189:f392fc9709a3 | 203 | __STATIC_INLINE void ARM_MPU_Disable(void) |
AnnaBridge | 189:f392fc9709a3 | 204 | { |
AnnaBridge | 189:f392fc9709a3 | 205 | __DSB(); |
AnnaBridge | 189:f392fc9709a3 | 206 | __ISB(); |
AnnaBridge | 189:f392fc9709a3 | 207 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk |
AnnaBridge | 189:f392fc9709a3 | 208 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
AnnaBridge | 189:f392fc9709a3 | 209 | #endif |
AnnaBridge | 189:f392fc9709a3 | 210 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
AnnaBridge | 189:f392fc9709a3 | 211 | } |
AnnaBridge | 189:f392fc9709a3 | 212 | |
AnnaBridge | 189:f392fc9709a3 | 213 | /** Clear and disable the given MPU region. |
AnnaBridge | 189:f392fc9709a3 | 214 | * \param rnr Region number to be cleared. |
AnnaBridge | 189:f392fc9709a3 | 215 | */ |
AnnaBridge | 189:f392fc9709a3 | 216 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) |
AnnaBridge | 189:f392fc9709a3 | 217 | { |
AnnaBridge | 189:f392fc9709a3 | 218 | MPU->RNR = rnr; |
AnnaBridge | 189:f392fc9709a3 | 219 | MPU->RASR = 0U; |
AnnaBridge | 189:f392fc9709a3 | 220 | } |
AnnaBridge | 189:f392fc9709a3 | 221 | |
AnnaBridge | 189:f392fc9709a3 | 222 | /** Configure an MPU region. |
AnnaBridge | 189:f392fc9709a3 | 223 | * \param rbar Value for RBAR register. |
AnnaBridge | 189:f392fc9709a3 | 224 | * \param rsar Value for RSAR register. |
AnnaBridge | 189:f392fc9709a3 | 225 | */ |
AnnaBridge | 189:f392fc9709a3 | 226 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) |
AnnaBridge | 189:f392fc9709a3 | 227 | { |
AnnaBridge | 189:f392fc9709a3 | 228 | MPU->RBAR = rbar; |
AnnaBridge | 189:f392fc9709a3 | 229 | MPU->RASR = rasr; |
AnnaBridge | 189:f392fc9709a3 | 230 | } |
AnnaBridge | 189:f392fc9709a3 | 231 | |
AnnaBridge | 189:f392fc9709a3 | 232 | /** Configure the given MPU region. |
AnnaBridge | 189:f392fc9709a3 | 233 | * \param rnr Region number to be configured. |
AnnaBridge | 189:f392fc9709a3 | 234 | * \param rbar Value for RBAR register. |
AnnaBridge | 189:f392fc9709a3 | 235 | * \param rsar Value for RSAR register. |
AnnaBridge | 189:f392fc9709a3 | 236 | */ |
AnnaBridge | 189:f392fc9709a3 | 237 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) |
AnnaBridge | 189:f392fc9709a3 | 238 | { |
AnnaBridge | 189:f392fc9709a3 | 239 | MPU->RNR = rnr; |
AnnaBridge | 189:f392fc9709a3 | 240 | MPU->RBAR = rbar; |
AnnaBridge | 189:f392fc9709a3 | 241 | MPU->RASR = rasr; |
AnnaBridge | 189:f392fc9709a3 | 242 | } |
AnnaBridge | 189:f392fc9709a3 | 243 | |
AnnaBridge | 189:f392fc9709a3 | 244 | /** Memcopy with strictly ordered memory access, e.g. for register targets. |
AnnaBridge | 189:f392fc9709a3 | 245 | * \param dst Destination data is copied to. |
AnnaBridge | 189:f392fc9709a3 | 246 | * \param src Source data is copied from. |
AnnaBridge | 189:f392fc9709a3 | 247 | * \param len Amount of data words to be copied. |
AnnaBridge | 189:f392fc9709a3 | 248 | */ |
AnnaBridge | 189:f392fc9709a3 | 249 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) |
AnnaBridge | 189:f392fc9709a3 | 250 | { |
AnnaBridge | 189:f392fc9709a3 | 251 | uint32_t i; |
AnnaBridge | 189:f392fc9709a3 | 252 | for (i = 0U; i < len; ++i) |
AnnaBridge | 189:f392fc9709a3 | 253 | { |
AnnaBridge | 189:f392fc9709a3 | 254 | dst[i] = src[i]; |
AnnaBridge | 189:f392fc9709a3 | 255 | } |
AnnaBridge | 189:f392fc9709a3 | 256 | } |
AnnaBridge | 189:f392fc9709a3 | 257 | |
AnnaBridge | 189:f392fc9709a3 | 258 | /** Load the given number of MPU regions from a table. |
AnnaBridge | 189:f392fc9709a3 | 259 | * \param table Pointer to the MPU configuration table. |
AnnaBridge | 189:f392fc9709a3 | 260 | * \param cnt Amount of regions to be configured. |
AnnaBridge | 189:f392fc9709a3 | 261 | */ |
AnnaBridge | 189:f392fc9709a3 | 262 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) |
AnnaBridge | 189:f392fc9709a3 | 263 | { |
AnnaBridge | 189:f392fc9709a3 | 264 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; |
AnnaBridge | 189:f392fc9709a3 | 265 | while (cnt > MPU_TYPE_RALIASES) { |
AnnaBridge | 189:f392fc9709a3 | 266 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); |
AnnaBridge | 189:f392fc9709a3 | 267 | table += MPU_TYPE_RALIASES; |
AnnaBridge | 189:f392fc9709a3 | 268 | cnt -= MPU_TYPE_RALIASES; |
AnnaBridge | 189:f392fc9709a3 | 269 | } |
AnnaBridge | 189:f392fc9709a3 | 270 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); |
AnnaBridge | 189:f392fc9709a3 | 271 | } |
AnnaBridge | 189:f392fc9709a3 | 272 | |
AnnaBridge | 189:f392fc9709a3 | 273 | #endif |