mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_spi.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f2xx_hal_spi.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.1.3 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 29-June-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief SPI HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the Serial Peripheral Interface (SPI) peripheral: |
<> | 144:ef7eb2e8f9f7 | 10 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 12 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 13 | * + Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 16 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 18 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 19 | [..] |
<> | 144:ef7eb2e8f9f7 | 20 | The SPI HAL driver can be used as follows: |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | (#) Declare a SPI_HandleTypeDef handle structure, for example: |
<> | 144:ef7eb2e8f9f7 | 23 | SPI_HandleTypeDef hspi; |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: |
<> | 144:ef7eb2e8f9f7 | 26 | (##) Enable the SPIx interface clock |
<> | 144:ef7eb2e8f9f7 | 27 | (##) SPI pins configuration |
<> | 144:ef7eb2e8f9f7 | 28 | (+++) Enable the clock for the SPI GPIOs |
<> | 144:ef7eb2e8f9f7 | 29 | (+++) Configure these SPI pins as alternate function push-pull |
<> | 144:ef7eb2e8f9f7 | 30 | (##) NVIC configuration if you need to use interrupt process |
<> | 144:ef7eb2e8f9f7 | 31 | (+++) Configure the SPIx interrupt priority |
<> | 144:ef7eb2e8f9f7 | 32 | (+++) Enable the NVIC SPI IRQ handle |
<> | 144:ef7eb2e8f9f7 | 33 | (##) DMA Configuration if you need to use DMA process |
<> | 144:ef7eb2e8f9f7 | 34 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream |
<> | 144:ef7eb2e8f9f7 | 35 | (+++) Enable the DMAx clock |
<> | 144:ef7eb2e8f9f7 | 36 | (+++) Configure the DMA handle parameters |
<> | 144:ef7eb2e8f9f7 | 37 | (+++) Configure the DMA Tx or Rx stream |
<> | 144:ef7eb2e8f9f7 | 38 | (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle |
<> | 144:ef7eb2e8f9f7 | 39 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS |
<> | 144:ef7eb2e8f9f7 | 42 | management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: |
<> | 144:ef7eb2e8f9f7 | 45 | (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
<> | 144:ef7eb2e8f9f7 | 46 | by calling the customized HAL_SPI_MspInit() API. |
<> | 144:ef7eb2e8f9f7 | 47 | [..] |
<> | 144:ef7eb2e8f9f7 | 48 | Circular mode restriction: |
<> | 144:ef7eb2e8f9f7 | 49 | (#) The DMA circular mode cannot be used when the SPI is configured in these modes: |
<> | 144:ef7eb2e8f9f7 | 50 | (##) Master 2Lines RxOnly |
<> | 144:ef7eb2e8f9f7 | 51 | (##) Master 1Line Rx |
<> | 144:ef7eb2e8f9f7 | 52 | (#) The CRC feature is not managed when the DMA circular mode is enabled |
<> | 144:ef7eb2e8f9f7 | 53 | (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs |
<> | 144:ef7eb2e8f9f7 | 54 | the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks |
<> | 144:ef7eb2e8f9f7 | 55 | [..] |
<> | 144:ef7eb2e8f9f7 | 56 | Master Receive mode restriction: |
<> | 144:ef7eb2e8f9f7 | 57 | (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or |
<> | 144:ef7eb2e8f9f7 | 58 | bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI |
<> | 144:ef7eb2e8f9f7 | 59 | does not initiate a new transfer the following procedure has to be respected: |
<> | 144:ef7eb2e8f9f7 | 60 | (##) HAL_SPI_DeInit() |
<> | 144:ef7eb2e8f9f7 | 61 | (##) HAL_SPI_Init() |
<> | 144:ef7eb2e8f9f7 | 62 | [..] |
<> | 144:ef7eb2e8f9f7 | 63 | Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, |
<> | 144:ef7eb2e8f9f7 | 64 | the following table resume the max SPI frequency reached with data size 8bits/16bits, |
<> | 144:ef7eb2e8f9f7 | 65 | according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | DataSize = SPI_DATASIZE_8BIT: |
<> | 144:ef7eb2e8f9f7 | 68 | +----------------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 69 | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | |
<> | 144:ef7eb2e8f9f7 | 70 | | Process | Tranfert mode |---------------------|----------------------|----------------------| |
<> | 144:ef7eb2e8f9f7 | 71 | | | | Master | Slave | Master | Slave | Master | Slave | |
<> | 144:ef7eb2e8f9f7 | 72 | |==============================================================================================| |
<> | 144:ef7eb2e8f9f7 | 73 | | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 74 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 75 | | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 76 | | R |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 77 | | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 78 | |=========|================|==========|==========|===========|==========|===========|==========| |
<> | 144:ef7eb2e8f9f7 | 79 | | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | |
<> | 144:ef7eb2e8f9f7 | 80 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 81 | | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | |
<> | 144:ef7eb2e8f9f7 | 82 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 83 | | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | |
<> | 144:ef7eb2e8f9f7 | 84 | |=========|================|==========|==========|===========|==========|===========|==========| |
<> | 144:ef7eb2e8f9f7 | 85 | | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | |
<> | 144:ef7eb2e8f9f7 | 86 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 87 | | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | |
<> | 144:ef7eb2e8f9f7 | 88 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 89 | | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| |
<> | 144:ef7eb2e8f9f7 | 90 | +----------------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | DataSize = SPI_DATASIZE_16BIT: |
<> | 144:ef7eb2e8f9f7 | 93 | +----------------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 94 | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | |
<> | 144:ef7eb2e8f9f7 | 95 | | Process | Tranfert mode |---------------------|----------------------|----------------------| |
<> | 144:ef7eb2e8f9f7 | 96 | | | | Master | Slave | Master | Slave | Master | Slave | |
<> | 144:ef7eb2e8f9f7 | 97 | |==============================================================================================| |
<> | 144:ef7eb2e8f9f7 | 98 | | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 99 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 100 | | / | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 101 | | R |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 102 | | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 103 | |=========|================|==========|==========|===========|==========|===========|==========| |
<> | 144:ef7eb2e8f9f7 | 104 | | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | |
<> | 144:ef7eb2e8f9f7 | 105 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 106 | | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | |
<> | 144:ef7eb2e8f9f7 | 107 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 108 | | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | |
<> | 144:ef7eb2e8f9f7 | 109 | |=========|================|==========|==========|===========|==========|===========|==========| |
<> | 144:ef7eb2e8f9f7 | 110 | | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | |
<> | 144:ef7eb2e8f9f7 | 111 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 112 | | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | |
<> | 144:ef7eb2e8f9f7 | 113 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
<> | 144:ef7eb2e8f9f7 | 114 | | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| |
<> | 144:ef7eb2e8f9f7 | 115 | +----------------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 116 | @note The max SPI frequency depend on SPI data size (8bits, 16bits), |
<> | 144:ef7eb2e8f9f7 | 117 | SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). |
<> | 144:ef7eb2e8f9f7 | 118 | @note |
<> | 144:ef7eb2e8f9f7 | 119 | (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() |
<> | 144:ef7eb2e8f9f7 | 120 | (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 121 | (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 124 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 125 | * @attention |
<> | 144:ef7eb2e8f9f7 | 126 | * |
<> | 144:ef7eb2e8f9f7 | 127 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 128 | * |
<> | 144:ef7eb2e8f9f7 | 129 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 130 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 131 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 132 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 133 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 134 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 135 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 136 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 137 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 138 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 139 | * |
<> | 144:ef7eb2e8f9f7 | 140 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 141 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 142 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 143 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 144 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 145 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 146 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 147 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 148 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 149 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 150 | * |
<> | 144:ef7eb2e8f9f7 | 151 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 152 | */ |
<> | 144:ef7eb2e8f9f7 | 153 | |
<> | 144:ef7eb2e8f9f7 | 154 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 155 | #include "stm32f2xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | /** @addtogroup STM32F2xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 158 | * @{ |
<> | 144:ef7eb2e8f9f7 | 159 | */ |
<> | 144:ef7eb2e8f9f7 | 160 | /** @defgroup SPI SPI |
<> | 144:ef7eb2e8f9f7 | 161 | * @brief SPI HAL module driver |
<> | 144:ef7eb2e8f9f7 | 162 | * @{ |
<> | 144:ef7eb2e8f9f7 | 163 | */ |
<> | 144:ef7eb2e8f9f7 | 164 | #ifdef HAL_SPI_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 167 | /* Private defines -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 168 | /** @defgroup SPI_Private_Constants SPI Private Constants |
<> | 144:ef7eb2e8f9f7 | 169 | * @{ |
<> | 144:ef7eb2e8f9f7 | 170 | */ |
<> | 144:ef7eb2e8f9f7 | 171 | #define SPI_DEFAULT_TIMEOUT 100U |
<> | 144:ef7eb2e8f9f7 | 172 | /** |
<> | 144:ef7eb2e8f9f7 | 173 | * @} |
<> | 144:ef7eb2e8f9f7 | 174 | */ |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /* Private macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 177 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 178 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 179 | /** @addtogroup SPI_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 180 | * @{ |
<> | 144:ef7eb2e8f9f7 | 181 | */ |
<> | 144:ef7eb2e8f9f7 | 182 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 183 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 184 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 185 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 186 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 187 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 188 | static void SPI_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 189 | static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 190 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 191 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 192 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 193 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 194 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 195 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 196 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 197 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 198 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 199 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 200 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 201 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 202 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 203 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 204 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 205 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 206 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 207 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 208 | static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 209 | /** |
<> | 144:ef7eb2e8f9f7 | 210 | * @} |
<> | 144:ef7eb2e8f9f7 | 211 | */ |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 214 | /** @defgroup SPI_Exported_Functions SPI Exported Functions |
<> | 144:ef7eb2e8f9f7 | 215 | * @{ |
<> | 144:ef7eb2e8f9f7 | 216 | */ |
<> | 144:ef7eb2e8f9f7 | 217 | |
<> | 144:ef7eb2e8f9f7 | 218 | /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 219 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 220 | * |
<> | 144:ef7eb2e8f9f7 | 221 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 222 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 223 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 224 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 225 | [..] This subsection provides a set of functions allowing to initialize and |
<> | 144:ef7eb2e8f9f7 | 226 | de-initialize the SPIx peripheral: |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | (+) User must implement HAL_SPI_MspInit() function in which he configures |
<> | 144:ef7eb2e8f9f7 | 229 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
<> | 144:ef7eb2e8f9f7 | 230 | |
<> | 144:ef7eb2e8f9f7 | 231 | (+) Call the function HAL_SPI_Init() to configure the selected device with |
<> | 144:ef7eb2e8f9f7 | 232 | the selected configuration: |
<> | 144:ef7eb2e8f9f7 | 233 | (++) Mode |
<> | 144:ef7eb2e8f9f7 | 234 | (++) Direction |
<> | 144:ef7eb2e8f9f7 | 235 | (++) Data Size |
<> | 144:ef7eb2e8f9f7 | 236 | (++) Clock Polarity and Phase |
<> | 144:ef7eb2e8f9f7 | 237 | (++) NSS Management |
<> | 144:ef7eb2e8f9f7 | 238 | (++) BaudRate Prescaler |
<> | 144:ef7eb2e8f9f7 | 239 | (++) FirstBit |
<> | 144:ef7eb2e8f9f7 | 240 | (++) TIMode |
<> | 144:ef7eb2e8f9f7 | 241 | (++) CRC Calculation |
<> | 144:ef7eb2e8f9f7 | 242 | (++) CRC Polynomial if CRC enabled |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | (+) Call the function HAL_SPI_DeInit() to restore the default configuration |
<> | 144:ef7eb2e8f9f7 | 245 | of the selected SPIx peripheral. |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 248 | * @{ |
<> | 144:ef7eb2e8f9f7 | 249 | */ |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | /** |
<> | 144:ef7eb2e8f9f7 | 252 | * @brief Initialize the SPI according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 253 | * in the SPI_InitTypeDef and initialize the associated handle. |
<> | 144:ef7eb2e8f9f7 | 254 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 255 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 256 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 257 | */ |
<> | 144:ef7eb2e8f9f7 | 258 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | /* Check the SPI handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 261 | if(hspi == NULL) |
<> | 144:ef7eb2e8f9f7 | 262 | { |
<> | 144:ef7eb2e8f9f7 | 263 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 264 | } |
<> | 144:ef7eb2e8f9f7 | 265 | |
<> | 144:ef7eb2e8f9f7 | 266 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 267 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
<> | 144:ef7eb2e8f9f7 | 268 | assert_param(IS_SPI_MODE(hspi->Init.Mode)); |
<> | 144:ef7eb2e8f9f7 | 269 | assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 270 | assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); |
<> | 144:ef7eb2e8f9f7 | 271 | assert_param(IS_SPI_NSS(hspi->Init.NSS)); |
<> | 144:ef7eb2e8f9f7 | 272 | assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); |
<> | 144:ef7eb2e8f9f7 | 273 | assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); |
<> | 144:ef7eb2e8f9f7 | 274 | assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); |
<> | 144:ef7eb2e8f9f7 | 275 | if(hspi->Init.TIMode == SPI_TIMODE_DISABLE) |
<> | 144:ef7eb2e8f9f7 | 276 | { |
<> | 144:ef7eb2e8f9f7 | 277 | assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); |
<> | 144:ef7eb2e8f9f7 | 278 | assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); |
<> | 144:ef7eb2e8f9f7 | 279 | } |
<> | 144:ef7eb2e8f9f7 | 280 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 281 | assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); |
<> | 144:ef7eb2e8f9f7 | 282 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 283 | { |
<> | 144:ef7eb2e8f9f7 | 284 | assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); |
<> | 144:ef7eb2e8f9f7 | 285 | } |
<> | 144:ef7eb2e8f9f7 | 286 | #else |
<> | 144:ef7eb2e8f9f7 | 287 | hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
<> | 144:ef7eb2e8f9f7 | 288 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 289 | |
<> | 144:ef7eb2e8f9f7 | 290 | if(hspi->State == HAL_SPI_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 291 | { |
<> | 144:ef7eb2e8f9f7 | 292 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 293 | hspi->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | /* Init the low level hardware : GPIO, CLOCK, NVIC... */ |
<> | 144:ef7eb2e8f9f7 | 296 | HAL_SPI_MspInit(hspi); |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | hspi->State = HAL_SPI_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 300 | |
<> | 144:ef7eb2e8f9f7 | 301 | /* Disable the selected SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 302 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 303 | |
<> | 144:ef7eb2e8f9f7 | 304 | /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ |
<> | 144:ef7eb2e8f9f7 | 305 | /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, |
<> | 144:ef7eb2e8f9f7 | 306 | Communication speed, First bit and CRC calculation state */ |
<> | 144:ef7eb2e8f9f7 | 307 | WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | |
<> | 144:ef7eb2e8f9f7 | 308 | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | |
<> | 144:ef7eb2e8f9f7 | 309 | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | /* Configure : NSS management */ |
<> | 144:ef7eb2e8f9f7 | 312 | WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 315 | /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ |
<> | 144:ef7eb2e8f9f7 | 316 | /* Configure : CRC Polynomial */ |
<> | 144:ef7eb2e8f9f7 | 317 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 318 | { |
<> | 144:ef7eb2e8f9f7 | 319 | WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); |
<> | 144:ef7eb2e8f9f7 | 320 | } |
<> | 144:ef7eb2e8f9f7 | 321 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 322 | |
<> | 144:ef7eb2e8f9f7 | 323 | #if defined(SPI_I2SCFGR_I2SMOD) |
<> | 144:ef7eb2e8f9f7 | 324 | /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ |
<> | 144:ef7eb2e8f9f7 | 325 | CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); |
<> | 144:ef7eb2e8f9f7 | 326 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 327 | |
<> | 144:ef7eb2e8f9f7 | 328 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 329 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 332 | } |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /** |
<> | 144:ef7eb2e8f9f7 | 335 | * @brief De Initialize the SPI peripheral. |
<> | 144:ef7eb2e8f9f7 | 336 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 337 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 338 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 339 | */ |
<> | 144:ef7eb2e8f9f7 | 340 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 341 | { |
<> | 144:ef7eb2e8f9f7 | 342 | /* Check the SPI handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 343 | if(hspi == NULL) |
<> | 144:ef7eb2e8f9f7 | 344 | { |
<> | 144:ef7eb2e8f9f7 | 345 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 346 | } |
<> | 144:ef7eb2e8f9f7 | 347 | |
<> | 144:ef7eb2e8f9f7 | 348 | /* Check SPI Instance parameter */ |
<> | 144:ef7eb2e8f9f7 | 349 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
<> | 144:ef7eb2e8f9f7 | 350 | |
<> | 144:ef7eb2e8f9f7 | 351 | hspi->State = HAL_SPI_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | /* Disable the SPI Peripheral Clock */ |
<> | 144:ef7eb2e8f9f7 | 354 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
<> | 144:ef7eb2e8f9f7 | 357 | HAL_SPI_MspDeInit(hspi); |
<> | 144:ef7eb2e8f9f7 | 358 | |
<> | 144:ef7eb2e8f9f7 | 359 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 360 | hspi->State = HAL_SPI_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 361 | |
<> | 144:ef7eb2e8f9f7 | 362 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 363 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 366 | } |
<> | 144:ef7eb2e8f9f7 | 367 | |
<> | 144:ef7eb2e8f9f7 | 368 | /** |
<> | 144:ef7eb2e8f9f7 | 369 | * @brief Initialize the SPI MSP. |
<> | 144:ef7eb2e8f9f7 | 370 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 371 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 372 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 373 | */ |
<> | 144:ef7eb2e8f9f7 | 374 | __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 375 | { |
<> | 144:ef7eb2e8f9f7 | 376 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 377 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 378 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 379 | the HAL_SPI_MspInit should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 380 | */ |
<> | 144:ef7eb2e8f9f7 | 381 | } |
<> | 144:ef7eb2e8f9f7 | 382 | |
<> | 144:ef7eb2e8f9f7 | 383 | /** |
<> | 144:ef7eb2e8f9f7 | 384 | * @brief De-Initialize the SPI MSP. |
<> | 144:ef7eb2e8f9f7 | 385 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 386 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 387 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 388 | */ |
<> | 144:ef7eb2e8f9f7 | 389 | __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 390 | { |
<> | 144:ef7eb2e8f9f7 | 391 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 392 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 393 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 394 | the HAL_SPI_MspDeInit should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 395 | */ |
<> | 144:ef7eb2e8f9f7 | 396 | } |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | /** |
<> | 144:ef7eb2e8f9f7 | 399 | * @} |
<> | 144:ef7eb2e8f9f7 | 400 | */ |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /** @defgroup SPI_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 403 | * @brief Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 404 | * |
<> | 144:ef7eb2e8f9f7 | 405 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 406 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 407 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 408 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 409 | [..] |
<> | 144:ef7eb2e8f9f7 | 410 | This subsection provides a set of functions allowing to manage the SPI |
<> | 144:ef7eb2e8f9f7 | 411 | data transfers. |
<> | 144:ef7eb2e8f9f7 | 412 | |
<> | 144:ef7eb2e8f9f7 | 413 | [..] The SPI supports master and slave mode : |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | (#) There are two modes of transfer: |
<> | 144:ef7eb2e8f9f7 | 416 | (++) Blocking mode: The communication is performed in polling mode. |
<> | 144:ef7eb2e8f9f7 | 417 | The HAL status of all data processing is returned by the same function |
<> | 144:ef7eb2e8f9f7 | 418 | after finishing transfer. |
<> | 144:ef7eb2e8f9f7 | 419 | (++) No-Blocking mode: The communication is performed using Interrupts |
<> | 144:ef7eb2e8f9f7 | 420 | or DMA, These APIs return the HAL status. |
<> | 144:ef7eb2e8f9f7 | 421 | The end of the data processing will be indicated through the |
<> | 144:ef7eb2e8f9f7 | 422 | dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when |
<> | 144:ef7eb2e8f9f7 | 423 | using DMA mode. |
<> | 144:ef7eb2e8f9f7 | 424 | The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks |
<> | 144:ef7eb2e8f9f7 | 425 | will be executed respectively at the end of the transmit or Receive process |
<> | 144:ef7eb2e8f9f7 | 426 | The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) |
<> | 144:ef7eb2e8f9f7 | 429 | exist for 1Line (simplex) and 2Lines (full duplex) modes. |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 432 | * @{ |
<> | 144:ef7eb2e8f9f7 | 433 | */ |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | /** |
<> | 144:ef7eb2e8f9f7 | 436 | * @brief Transmit an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 437 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 438 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 439 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 440 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 441 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 442 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 443 | */ |
<> | 144:ef7eb2e8f9f7 | 444 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 445 | { |
<> | 144:ef7eb2e8f9f7 | 446 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 447 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 448 | |
<> | 144:ef7eb2e8f9f7 | 449 | /* Check Direction parameter */ |
<> | 144:ef7eb2e8f9f7 | 450 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 451 | |
<> | 144:ef7eb2e8f9f7 | 452 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 453 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 454 | |
<> | 144:ef7eb2e8f9f7 | 455 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 456 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 457 | |
<> | 144:ef7eb2e8f9f7 | 458 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 459 | { |
<> | 144:ef7eb2e8f9f7 | 460 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 461 | goto error; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | |
<> | 144:ef7eb2e8f9f7 | 464 | if((pData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 465 | { |
<> | 144:ef7eb2e8f9f7 | 466 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 467 | goto error; |
<> | 144:ef7eb2e8f9f7 | 468 | } |
<> | 144:ef7eb2e8f9f7 | 469 | |
<> | 144:ef7eb2e8f9f7 | 470 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 471 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 472 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 473 | hspi->pTxBuffPtr = (uint8_t *)pData; |
<> | 144:ef7eb2e8f9f7 | 474 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 475 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 476 | |
<> | 144:ef7eb2e8f9f7 | 477 | /*Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 478 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 479 | hspi->RxXferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 480 | hspi->RxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 481 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 482 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 483 | |
<> | 144:ef7eb2e8f9f7 | 484 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 485 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 486 | { |
<> | 144:ef7eb2e8f9f7 | 487 | SPI_1LINE_TX(hspi); |
<> | 144:ef7eb2e8f9f7 | 488 | } |
<> | 144:ef7eb2e8f9f7 | 489 | |
<> | 144:ef7eb2e8f9f7 | 490 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 491 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 492 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 493 | { |
<> | 144:ef7eb2e8f9f7 | 494 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 495 | } |
<> | 144:ef7eb2e8f9f7 | 496 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 497 | |
<> | 144:ef7eb2e8f9f7 | 498 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 499 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 500 | { |
<> | 144:ef7eb2e8f9f7 | 501 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 502 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 503 | } |
<> | 144:ef7eb2e8f9f7 | 504 | |
<> | 144:ef7eb2e8f9f7 | 505 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 506 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
<> | 144:ef7eb2e8f9f7 | 507 | { |
<> | 144:ef7eb2e8f9f7 | 508 | if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) |
<> | 144:ef7eb2e8f9f7 | 509 | { |
<> | 144:ef7eb2e8f9f7 | 510 | hspi->Instance->DR = *((uint16_t *)pData); |
<> | 144:ef7eb2e8f9f7 | 511 | pData += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 512 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 513 | } |
<> | 144:ef7eb2e8f9f7 | 514 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 515 | while (hspi->TxXferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 516 | { |
<> | 144:ef7eb2e8f9f7 | 517 | /* Wait until TXE flag is set to send data */ |
<> | 144:ef7eb2e8f9f7 | 518 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) |
<> | 144:ef7eb2e8f9f7 | 519 | { |
<> | 144:ef7eb2e8f9f7 | 520 | hspi->Instance->DR = *((uint16_t *)pData); |
<> | 144:ef7eb2e8f9f7 | 521 | pData += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 522 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 523 | } |
<> | 144:ef7eb2e8f9f7 | 524 | else |
<> | 144:ef7eb2e8f9f7 | 525 | { |
<> | 144:ef7eb2e8f9f7 | 526 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 527 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 528 | { |
<> | 144:ef7eb2e8f9f7 | 529 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 530 | goto error; |
<> | 144:ef7eb2e8f9f7 | 531 | } |
<> | 144:ef7eb2e8f9f7 | 532 | } |
<> | 144:ef7eb2e8f9f7 | 533 | } |
<> | 144:ef7eb2e8f9f7 | 534 | } |
<> | 144:ef7eb2e8f9f7 | 535 | /* Transmit data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 536 | else |
<> | 144:ef7eb2e8f9f7 | 537 | { |
<> | 144:ef7eb2e8f9f7 | 538 | if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) |
<> | 144:ef7eb2e8f9f7 | 539 | { |
<> | 144:ef7eb2e8f9f7 | 540 | *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); |
<> | 144:ef7eb2e8f9f7 | 541 | pData += sizeof(uint8_t); |
<> | 144:ef7eb2e8f9f7 | 542 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 543 | } |
<> | 144:ef7eb2e8f9f7 | 544 | while (hspi->TxXferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 545 | { |
<> | 144:ef7eb2e8f9f7 | 546 | /* Wait until TXE flag is set to send data */ |
<> | 144:ef7eb2e8f9f7 | 547 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) |
<> | 144:ef7eb2e8f9f7 | 548 | { |
<> | 144:ef7eb2e8f9f7 | 549 | *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); |
<> | 144:ef7eb2e8f9f7 | 550 | pData += sizeof(uint8_t); |
<> | 144:ef7eb2e8f9f7 | 551 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 552 | } |
<> | 144:ef7eb2e8f9f7 | 553 | else |
<> | 144:ef7eb2e8f9f7 | 554 | { |
<> | 144:ef7eb2e8f9f7 | 555 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 556 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 557 | { |
<> | 144:ef7eb2e8f9f7 | 558 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 559 | goto error; |
<> | 144:ef7eb2e8f9f7 | 560 | } |
<> | 144:ef7eb2e8f9f7 | 561 | } |
<> | 144:ef7eb2e8f9f7 | 562 | } |
<> | 144:ef7eb2e8f9f7 | 563 | } |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | /* Wait until TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 566 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 567 | { |
<> | 144:ef7eb2e8f9f7 | 568 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 569 | goto error; |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | /* Check Busy flag */ |
<> | 144:ef7eb2e8f9f7 | 573 | if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 574 | { |
<> | 144:ef7eb2e8f9f7 | 575 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 576 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 577 | goto error; |
<> | 144:ef7eb2e8f9f7 | 578 | } |
<> | 144:ef7eb2e8f9f7 | 579 | |
<> | 144:ef7eb2e8f9f7 | 580 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 581 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 582 | { |
<> | 144:ef7eb2e8f9f7 | 583 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 584 | } |
<> | 144:ef7eb2e8f9f7 | 585 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 586 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 587 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 588 | { |
<> | 144:ef7eb2e8f9f7 | 589 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 590 | } |
<> | 144:ef7eb2e8f9f7 | 591 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 592 | |
<> | 144:ef7eb2e8f9f7 | 593 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 594 | { |
<> | 144:ef7eb2e8f9f7 | 595 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 596 | } |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | error: |
<> | 144:ef7eb2e8f9f7 | 599 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 600 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 601 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 602 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 603 | } |
<> | 144:ef7eb2e8f9f7 | 604 | |
<> | 144:ef7eb2e8f9f7 | 605 | /** |
<> | 144:ef7eb2e8f9f7 | 606 | * @brief Receive an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 607 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 608 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 609 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 610 | * @param Size: amount of data to be received |
<> | 144:ef7eb2e8f9f7 | 611 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 612 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 613 | */ |
<> | 144:ef7eb2e8f9f7 | 614 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 615 | { |
<> | 144:ef7eb2e8f9f7 | 616 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 617 | __IO uint16_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 618 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 619 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 620 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
<> | 144:ef7eb2e8f9f7 | 623 | { |
<> | 144:ef7eb2e8f9f7 | 624 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 625 | /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ |
<> | 144:ef7eb2e8f9f7 | 626 | return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); |
<> | 144:ef7eb2e8f9f7 | 627 | } |
<> | 144:ef7eb2e8f9f7 | 628 | |
<> | 144:ef7eb2e8f9f7 | 629 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 630 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 631 | |
<> | 144:ef7eb2e8f9f7 | 632 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 633 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 634 | |
<> | 144:ef7eb2e8f9f7 | 635 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 636 | { |
<> | 144:ef7eb2e8f9f7 | 637 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 638 | goto error; |
<> | 144:ef7eb2e8f9f7 | 639 | } |
<> | 144:ef7eb2e8f9f7 | 640 | |
<> | 144:ef7eb2e8f9f7 | 641 | if((pData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 642 | { |
<> | 144:ef7eb2e8f9f7 | 643 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 644 | goto error; |
<> | 144:ef7eb2e8f9f7 | 645 | } |
<> | 144:ef7eb2e8f9f7 | 646 | |
<> | 144:ef7eb2e8f9f7 | 647 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 648 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 649 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 650 | hspi->pRxBuffPtr = (uint8_t *)pData; |
<> | 144:ef7eb2e8f9f7 | 651 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 652 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | /*Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 655 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 656 | hspi->TxXferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 657 | hspi->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 658 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 659 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 660 | |
<> | 144:ef7eb2e8f9f7 | 661 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 662 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 663 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 664 | { |
<> | 144:ef7eb2e8f9f7 | 665 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 666 | /* this is done to handle the CRCNEXT before the latest data */ |
<> | 144:ef7eb2e8f9f7 | 667 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 668 | } |
<> | 144:ef7eb2e8f9f7 | 669 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 670 | |
<> | 144:ef7eb2e8f9f7 | 671 | /* Configure communication direction: 1Line */ |
<> | 144:ef7eb2e8f9f7 | 672 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 673 | { |
<> | 144:ef7eb2e8f9f7 | 674 | SPI_1LINE_RX(hspi); |
<> | 144:ef7eb2e8f9f7 | 675 | } |
<> | 144:ef7eb2e8f9f7 | 676 | |
<> | 144:ef7eb2e8f9f7 | 677 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 678 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 679 | { |
<> | 144:ef7eb2e8f9f7 | 680 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 681 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 682 | } |
<> | 144:ef7eb2e8f9f7 | 683 | |
<> | 144:ef7eb2e8f9f7 | 684 | /* Receive data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 685 | if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 686 | { |
<> | 144:ef7eb2e8f9f7 | 687 | /* Transfer loop */ |
<> | 144:ef7eb2e8f9f7 | 688 | while(hspi->RxXferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 689 | { |
<> | 144:ef7eb2e8f9f7 | 690 | /* Check the RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 691 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) |
<> | 144:ef7eb2e8f9f7 | 692 | { |
<> | 144:ef7eb2e8f9f7 | 693 | /* read the received data */ |
<> | 144:ef7eb2e8f9f7 | 694 | (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 695 | pData += sizeof(uint8_t); |
<> | 144:ef7eb2e8f9f7 | 696 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 697 | } |
<> | 144:ef7eb2e8f9f7 | 698 | else |
<> | 144:ef7eb2e8f9f7 | 699 | { |
<> | 144:ef7eb2e8f9f7 | 700 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 701 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 702 | { |
<> | 144:ef7eb2e8f9f7 | 703 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 704 | goto error; |
<> | 144:ef7eb2e8f9f7 | 705 | } |
<> | 144:ef7eb2e8f9f7 | 706 | } |
<> | 144:ef7eb2e8f9f7 | 707 | } |
<> | 144:ef7eb2e8f9f7 | 708 | } |
<> | 144:ef7eb2e8f9f7 | 709 | else |
<> | 144:ef7eb2e8f9f7 | 710 | { |
<> | 144:ef7eb2e8f9f7 | 711 | /* Transfer loop */ |
<> | 144:ef7eb2e8f9f7 | 712 | while(hspi->RxXferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 713 | { |
<> | 144:ef7eb2e8f9f7 | 714 | /* Check the RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 715 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) |
<> | 144:ef7eb2e8f9f7 | 716 | { |
<> | 144:ef7eb2e8f9f7 | 717 | *((uint16_t*)pData) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 718 | pData += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 719 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 720 | } |
<> | 144:ef7eb2e8f9f7 | 721 | else |
<> | 144:ef7eb2e8f9f7 | 722 | { |
<> | 144:ef7eb2e8f9f7 | 723 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 724 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 725 | { |
<> | 144:ef7eb2e8f9f7 | 726 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 727 | goto error; |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | } |
<> | 144:ef7eb2e8f9f7 | 730 | } |
<> | 144:ef7eb2e8f9f7 | 731 | } |
<> | 144:ef7eb2e8f9f7 | 732 | |
<> | 144:ef7eb2e8f9f7 | 733 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 734 | /* Handle the CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 735 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 736 | { |
<> | 144:ef7eb2e8f9f7 | 737 | /* freeze the CRC before the latest data */ |
<> | 144:ef7eb2e8f9f7 | 738 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 739 | |
<> | 144:ef7eb2e8f9f7 | 740 | /* Read the latest data */ |
<> | 144:ef7eb2e8f9f7 | 741 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 742 | { |
<> | 144:ef7eb2e8f9f7 | 743 | /* the latest data has not been received */ |
<> | 144:ef7eb2e8f9f7 | 744 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 745 | goto error; |
<> | 144:ef7eb2e8f9f7 | 746 | } |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | /* Receive last data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 749 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
<> | 144:ef7eb2e8f9f7 | 750 | { |
<> | 144:ef7eb2e8f9f7 | 751 | *((uint16_t*)pData) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 752 | } |
<> | 144:ef7eb2e8f9f7 | 753 | /* Receive last data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 754 | else |
<> | 144:ef7eb2e8f9f7 | 755 | { |
<> | 144:ef7eb2e8f9f7 | 756 | (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 757 | } |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | /* Wait the CRC data */ |
<> | 144:ef7eb2e8f9f7 | 760 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 761 | { |
<> | 144:ef7eb2e8f9f7 | 762 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 763 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 764 | goto error; |
<> | 144:ef7eb2e8f9f7 | 765 | } |
<> | 144:ef7eb2e8f9f7 | 766 | |
<> | 144:ef7eb2e8f9f7 | 767 | /* Read CRC to Flush DR and RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 768 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 769 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 770 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 771 | } |
<> | 144:ef7eb2e8f9f7 | 772 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 773 | |
<> | 144:ef7eb2e8f9f7 | 774 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 775 | { |
<> | 144:ef7eb2e8f9f7 | 776 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 777 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 778 | } |
<> | 144:ef7eb2e8f9f7 | 779 | |
<> | 144:ef7eb2e8f9f7 | 780 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 781 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 782 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
<> | 144:ef7eb2e8f9f7 | 783 | { |
<> | 144:ef7eb2e8f9f7 | 784 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 785 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 786 | } |
<> | 144:ef7eb2e8f9f7 | 787 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 788 | |
<> | 144:ef7eb2e8f9f7 | 789 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 790 | { |
<> | 144:ef7eb2e8f9f7 | 791 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 792 | } |
<> | 144:ef7eb2e8f9f7 | 793 | |
<> | 144:ef7eb2e8f9f7 | 794 | error : |
<> | 144:ef7eb2e8f9f7 | 795 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 796 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 797 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 798 | } |
<> | 144:ef7eb2e8f9f7 | 799 | |
<> | 144:ef7eb2e8f9f7 | 800 | /** |
<> | 144:ef7eb2e8f9f7 | 801 | * @brief Transmit and Receive an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 802 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 803 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 804 | * @param pTxData: pointer to transmission data buffer |
<> | 144:ef7eb2e8f9f7 | 805 | * @param pRxData: pointer to reception data buffer |
<> | 144:ef7eb2e8f9f7 | 806 | * @param Size: amount of data to be sent and received |
<> | 144:ef7eb2e8f9f7 | 807 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 808 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 809 | */ |
<> | 144:ef7eb2e8f9f7 | 810 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | uint32_t tmp = 0U, tmp1 = 0U; |
<> | 144:ef7eb2e8f9f7 | 813 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 814 | __IO uint16_t tmpreg1 = 0U; |
<> | 144:ef7eb2e8f9f7 | 815 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 816 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 817 | /* Variable used to alternate Rx and Tx during transfer */ |
<> | 144:ef7eb2e8f9f7 | 818 | uint32_t txallowed = 1U; |
<> | 144:ef7eb2e8f9f7 | 819 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 820 | |
<> | 144:ef7eb2e8f9f7 | 821 | /* Check Direction parameter */ |
<> | 144:ef7eb2e8f9f7 | 822 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 823 | |
<> | 144:ef7eb2e8f9f7 | 824 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 825 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 826 | |
<> | 144:ef7eb2e8f9f7 | 827 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 828 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 829 | |
<> | 144:ef7eb2e8f9f7 | 830 | tmp = hspi->State; |
<> | 144:ef7eb2e8f9f7 | 831 | tmp1 = hspi->Init.Mode; |
<> | 144:ef7eb2e8f9f7 | 832 | |
<> | 144:ef7eb2e8f9f7 | 833 | if(!((tmp == HAL_SPI_STATE_READY) || \ |
<> | 144:ef7eb2e8f9f7 | 834 | ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) |
<> | 144:ef7eb2e8f9f7 | 835 | { |
<> | 144:ef7eb2e8f9f7 | 836 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 837 | goto error; |
<> | 144:ef7eb2e8f9f7 | 838 | } |
<> | 144:ef7eb2e8f9f7 | 839 | |
<> | 144:ef7eb2e8f9f7 | 840 | if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 841 | { |
<> | 144:ef7eb2e8f9f7 | 842 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 843 | goto error; |
<> | 144:ef7eb2e8f9f7 | 844 | } |
<> | 144:ef7eb2e8f9f7 | 845 | |
<> | 144:ef7eb2e8f9f7 | 846 | /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ |
<> | 144:ef7eb2e8f9f7 | 847 | if(hspi->State == HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 848 | { |
<> | 144:ef7eb2e8f9f7 | 849 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
<> | 144:ef7eb2e8f9f7 | 850 | } |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 853 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 854 | hspi->pRxBuffPtr = (uint8_t *)pRxData; |
<> | 144:ef7eb2e8f9f7 | 855 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 856 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 857 | hspi->pTxBuffPtr = (uint8_t *)pTxData; |
<> | 144:ef7eb2e8f9f7 | 858 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 859 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 860 | |
<> | 144:ef7eb2e8f9f7 | 861 | /*Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 862 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 863 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 864 | |
<> | 144:ef7eb2e8f9f7 | 865 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 866 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 867 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 868 | { |
<> | 144:ef7eb2e8f9f7 | 869 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 870 | } |
<> | 144:ef7eb2e8f9f7 | 871 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 872 | |
<> | 144:ef7eb2e8f9f7 | 873 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 874 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 875 | { |
<> | 144:ef7eb2e8f9f7 | 876 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 877 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 878 | } |
<> | 144:ef7eb2e8f9f7 | 879 | |
<> | 144:ef7eb2e8f9f7 | 880 | /* Transmit and Receive data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 881 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
<> | 144:ef7eb2e8f9f7 | 882 | { |
<> | 144:ef7eb2e8f9f7 | 883 | if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) |
<> | 144:ef7eb2e8f9f7 | 884 | { |
<> | 144:ef7eb2e8f9f7 | 885 | hspi->Instance->DR = *((uint16_t *)pTxData); |
<> | 144:ef7eb2e8f9f7 | 886 | pTxData += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 887 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 888 | } |
<> | 144:ef7eb2e8f9f7 | 889 | while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) |
<> | 144:ef7eb2e8f9f7 | 890 | { |
<> | 144:ef7eb2e8f9f7 | 891 | /* Check TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 892 | if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) |
<> | 144:ef7eb2e8f9f7 | 893 | { |
<> | 144:ef7eb2e8f9f7 | 894 | hspi->Instance->DR = *((uint16_t *)pTxData); |
<> | 144:ef7eb2e8f9f7 | 895 | pTxData += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 896 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 897 | /* Next Data is a reception (Rx). Tx not allowed */ |
<> | 144:ef7eb2e8f9f7 | 898 | txallowed = 0U; |
<> | 144:ef7eb2e8f9f7 | 899 | |
<> | 144:ef7eb2e8f9f7 | 900 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 901 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 902 | if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 903 | { |
<> | 144:ef7eb2e8f9f7 | 904 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 905 | } |
<> | 144:ef7eb2e8f9f7 | 906 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 907 | } |
<> | 144:ef7eb2e8f9f7 | 908 | |
<> | 144:ef7eb2e8f9f7 | 909 | /* Check RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 910 | if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) |
<> | 144:ef7eb2e8f9f7 | 911 | { |
<> | 144:ef7eb2e8f9f7 | 912 | *((uint16_t *)pRxData) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 913 | pRxData += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 914 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 915 | /* Next Data is a Transmission (Tx). Tx is allowed */ |
<> | 144:ef7eb2e8f9f7 | 916 | txallowed = 1U; |
<> | 144:ef7eb2e8f9f7 | 917 | } |
<> | 144:ef7eb2e8f9f7 | 918 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 919 | { |
<> | 144:ef7eb2e8f9f7 | 920 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 921 | goto error; |
<> | 144:ef7eb2e8f9f7 | 922 | } |
<> | 144:ef7eb2e8f9f7 | 923 | } |
<> | 144:ef7eb2e8f9f7 | 924 | } |
<> | 144:ef7eb2e8f9f7 | 925 | /* Transmit and Receive data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 926 | else |
<> | 144:ef7eb2e8f9f7 | 927 | { |
<> | 144:ef7eb2e8f9f7 | 928 | if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) |
<> | 144:ef7eb2e8f9f7 | 929 | { |
<> | 144:ef7eb2e8f9f7 | 930 | *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData); |
<> | 144:ef7eb2e8f9f7 | 931 | pTxData += sizeof(uint8_t); |
<> | 144:ef7eb2e8f9f7 | 932 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 933 | } |
<> | 144:ef7eb2e8f9f7 | 934 | while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) |
<> | 144:ef7eb2e8f9f7 | 935 | { |
<> | 144:ef7eb2e8f9f7 | 936 | /* check TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 937 | if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) |
<> | 144:ef7eb2e8f9f7 | 938 | { |
<> | 144:ef7eb2e8f9f7 | 939 | *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); |
<> | 144:ef7eb2e8f9f7 | 940 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 941 | /* Next Data is a reception (Rx). Tx not allowed */ |
<> | 144:ef7eb2e8f9f7 | 942 | txallowed = 0U; |
<> | 144:ef7eb2e8f9f7 | 943 | |
<> | 144:ef7eb2e8f9f7 | 944 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 945 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 946 | if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 947 | { |
<> | 144:ef7eb2e8f9f7 | 948 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 949 | } |
<> | 144:ef7eb2e8f9f7 | 950 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 951 | } |
<> | 144:ef7eb2e8f9f7 | 952 | |
<> | 144:ef7eb2e8f9f7 | 953 | /* Wait until RXNE flag is reset */ |
<> | 144:ef7eb2e8f9f7 | 954 | if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) |
<> | 144:ef7eb2e8f9f7 | 955 | { |
<> | 144:ef7eb2e8f9f7 | 956 | (*(uint8_t *)pRxData++) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 957 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 958 | /* Next Data is a Transmission (Tx). Tx is allowed */ |
<> | 144:ef7eb2e8f9f7 | 959 | txallowed = 1U; |
<> | 144:ef7eb2e8f9f7 | 960 | } |
<> | 144:ef7eb2e8f9f7 | 961 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 962 | { |
<> | 144:ef7eb2e8f9f7 | 963 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 964 | goto error; |
<> | 144:ef7eb2e8f9f7 | 965 | } |
<> | 144:ef7eb2e8f9f7 | 966 | } |
<> | 144:ef7eb2e8f9f7 | 967 | } |
<> | 144:ef7eb2e8f9f7 | 968 | |
<> | 144:ef7eb2e8f9f7 | 969 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 970 | /* Read CRC from DR to close CRC calculation process */ |
<> | 144:ef7eb2e8f9f7 | 971 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 972 | { |
<> | 144:ef7eb2e8f9f7 | 973 | /* Wait until TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 974 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 975 | { |
<> | 144:ef7eb2e8f9f7 | 976 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 977 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 978 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 979 | goto error; |
<> | 144:ef7eb2e8f9f7 | 980 | } |
<> | 144:ef7eb2e8f9f7 | 981 | /* Read CRC */ |
<> | 144:ef7eb2e8f9f7 | 982 | tmpreg1 = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 983 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 984 | UNUSED(tmpreg1); |
<> | 144:ef7eb2e8f9f7 | 985 | } |
<> | 144:ef7eb2e8f9f7 | 986 | |
<> | 144:ef7eb2e8f9f7 | 987 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 988 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
<> | 144:ef7eb2e8f9f7 | 989 | { |
<> | 144:ef7eb2e8f9f7 | 990 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 991 | /* Clear CRC Flag */ |
<> | 144:ef7eb2e8f9f7 | 992 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 995 | } |
<> | 144:ef7eb2e8f9f7 | 996 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 997 | |
<> | 144:ef7eb2e8f9f7 | 998 | /* Wait until TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 999 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1000 | { |
<> | 144:ef7eb2e8f9f7 | 1001 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1002 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1003 | } |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | /* Check Busy flag */ |
<> | 144:ef7eb2e8f9f7 | 1006 | if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1007 | { |
<> | 144:ef7eb2e8f9f7 | 1008 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1009 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 1010 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1011 | } |
<> | 144:ef7eb2e8f9f7 | 1012 | |
<> | 144:ef7eb2e8f9f7 | 1013 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 1014 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 1015 | { |
<> | 144:ef7eb2e8f9f7 | 1016 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1017 | } |
<> | 144:ef7eb2e8f9f7 | 1018 | |
<> | 144:ef7eb2e8f9f7 | 1019 | error : |
<> | 144:ef7eb2e8f9f7 | 1020 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1021 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1022 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1023 | } |
<> | 144:ef7eb2e8f9f7 | 1024 | |
<> | 144:ef7eb2e8f9f7 | 1025 | /** |
<> | 144:ef7eb2e8f9f7 | 1026 | * @brief Transmit an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 1027 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1028 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1029 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1030 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1031 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1032 | */ |
<> | 144:ef7eb2e8f9f7 | 1033 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1034 | { |
<> | 144:ef7eb2e8f9f7 | 1035 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1036 | |
<> | 144:ef7eb2e8f9f7 | 1037 | /* Check Direction parameter */ |
<> | 144:ef7eb2e8f9f7 | 1038 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1039 | |
<> | 144:ef7eb2e8f9f7 | 1040 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1041 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1042 | |
<> | 144:ef7eb2e8f9f7 | 1043 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1044 | { |
<> | 144:ef7eb2e8f9f7 | 1045 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1046 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1047 | } |
<> | 144:ef7eb2e8f9f7 | 1048 | |
<> | 144:ef7eb2e8f9f7 | 1049 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1050 | { |
<> | 144:ef7eb2e8f9f7 | 1051 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1052 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1053 | } |
<> | 144:ef7eb2e8f9f7 | 1054 | |
<> | 144:ef7eb2e8f9f7 | 1055 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 1056 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 1057 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1058 | hspi->pTxBuffPtr = (uint8_t *)pData; |
<> | 144:ef7eb2e8f9f7 | 1059 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1060 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1061 | |
<> | 144:ef7eb2e8f9f7 | 1062 | /* Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 1063 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1064 | hspi->RxXferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 1065 | hspi->RxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1066 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1067 | |
<> | 144:ef7eb2e8f9f7 | 1068 | /* Set the function for IT treatment */ |
<> | 144:ef7eb2e8f9f7 | 1069 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
<> | 144:ef7eb2e8f9f7 | 1070 | { |
<> | 144:ef7eb2e8f9f7 | 1071 | hspi->TxISR = SPI_TxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1072 | } |
<> | 144:ef7eb2e8f9f7 | 1073 | else |
<> | 144:ef7eb2e8f9f7 | 1074 | { |
<> | 144:ef7eb2e8f9f7 | 1075 | hspi->TxISR = SPI_TxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1076 | } |
<> | 144:ef7eb2e8f9f7 | 1077 | |
<> | 144:ef7eb2e8f9f7 | 1078 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1079 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1080 | { |
<> | 144:ef7eb2e8f9f7 | 1081 | SPI_1LINE_TX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1082 | } |
<> | 144:ef7eb2e8f9f7 | 1083 | |
<> | 144:ef7eb2e8f9f7 | 1084 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1085 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1086 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1087 | { |
<> | 144:ef7eb2e8f9f7 | 1088 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1089 | } |
<> | 144:ef7eb2e8f9f7 | 1090 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1091 | |
<> | 144:ef7eb2e8f9f7 | 1092 | if (hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 1093 | { |
<> | 144:ef7eb2e8f9f7 | 1094 | /* Enable TXE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1095 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); |
<> | 144:ef7eb2e8f9f7 | 1096 | } |
<> | 144:ef7eb2e8f9f7 | 1097 | else |
<> | 144:ef7eb2e8f9f7 | 1098 | { |
<> | 144:ef7eb2e8f9f7 | 1099 | /* Enable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1100 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1101 | } |
<> | 144:ef7eb2e8f9f7 | 1102 | |
<> | 144:ef7eb2e8f9f7 | 1103 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1104 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1105 | { |
<> | 144:ef7eb2e8f9f7 | 1106 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1107 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1108 | } |
<> | 144:ef7eb2e8f9f7 | 1109 | |
<> | 144:ef7eb2e8f9f7 | 1110 | error : |
<> | 144:ef7eb2e8f9f7 | 1111 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1112 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1113 | } |
<> | 144:ef7eb2e8f9f7 | 1114 | |
<> | 144:ef7eb2e8f9f7 | 1115 | /** |
<> | 144:ef7eb2e8f9f7 | 1116 | * @brief Receive an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 1117 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1118 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1119 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1120 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1121 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1122 | */ |
<> | 144:ef7eb2e8f9f7 | 1123 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1124 | { |
<> | 144:ef7eb2e8f9f7 | 1125 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1126 | |
<> | 144:ef7eb2e8f9f7 | 1127 | if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) |
<> | 144:ef7eb2e8f9f7 | 1128 | { |
<> | 144:ef7eb2e8f9f7 | 1129 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1130 | /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ |
<> | 144:ef7eb2e8f9f7 | 1131 | return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); |
<> | 144:ef7eb2e8f9f7 | 1132 | } |
<> | 144:ef7eb2e8f9f7 | 1133 | |
<> | 144:ef7eb2e8f9f7 | 1134 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1135 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1136 | |
<> | 144:ef7eb2e8f9f7 | 1137 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1138 | { |
<> | 144:ef7eb2e8f9f7 | 1139 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1140 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1141 | } |
<> | 144:ef7eb2e8f9f7 | 1142 | |
<> | 144:ef7eb2e8f9f7 | 1143 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1144 | { |
<> | 144:ef7eb2e8f9f7 | 1145 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1146 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1147 | } |
<> | 144:ef7eb2e8f9f7 | 1148 | |
<> | 144:ef7eb2e8f9f7 | 1149 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 1150 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1151 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1152 | hspi->pRxBuffPtr = (uint8_t *)pData; |
<> | 144:ef7eb2e8f9f7 | 1153 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1154 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1155 | |
<> | 144:ef7eb2e8f9f7 | 1156 | /* Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 1157 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1158 | hspi->TxXferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 1159 | hspi->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1160 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1161 | |
<> | 144:ef7eb2e8f9f7 | 1162 | /* Set the function for IT treatment */ |
<> | 144:ef7eb2e8f9f7 | 1163 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
<> | 144:ef7eb2e8f9f7 | 1164 | { |
<> | 144:ef7eb2e8f9f7 | 1165 | hspi->RxISR = SPI_RxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1166 | } |
<> | 144:ef7eb2e8f9f7 | 1167 | else |
<> | 144:ef7eb2e8f9f7 | 1168 | { |
<> | 144:ef7eb2e8f9f7 | 1169 | hspi->RxISR = SPI_RxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1170 | } |
<> | 144:ef7eb2e8f9f7 | 1171 | |
<> | 144:ef7eb2e8f9f7 | 1172 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1173 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1174 | { |
<> | 144:ef7eb2e8f9f7 | 1175 | SPI_1LINE_RX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1176 | } |
<> | 144:ef7eb2e8f9f7 | 1177 | |
<> | 144:ef7eb2e8f9f7 | 1178 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1179 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1180 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1181 | { |
<> | 144:ef7eb2e8f9f7 | 1182 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1183 | } |
<> | 144:ef7eb2e8f9f7 | 1184 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1185 | |
<> | 144:ef7eb2e8f9f7 | 1186 | /* Enable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1187 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1188 | |
<> | 144:ef7eb2e8f9f7 | 1189 | /* Note : The SPI must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1190 | to avoid the risk of SPI interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1191 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1192 | |
<> | 144:ef7eb2e8f9f7 | 1193 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1194 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1195 | { |
<> | 144:ef7eb2e8f9f7 | 1196 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1197 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1198 | } |
<> | 144:ef7eb2e8f9f7 | 1199 | |
<> | 144:ef7eb2e8f9f7 | 1200 | error : |
<> | 144:ef7eb2e8f9f7 | 1201 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1202 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1203 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1204 | } |
<> | 144:ef7eb2e8f9f7 | 1205 | |
<> | 144:ef7eb2e8f9f7 | 1206 | /** |
<> | 144:ef7eb2e8f9f7 | 1207 | * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 1208 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1209 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1210 | * @param pTxData: pointer to transmission data buffer |
<> | 144:ef7eb2e8f9f7 | 1211 | * @param pRxData: pointer to reception data buffer |
<> | 144:ef7eb2e8f9f7 | 1212 | * @param Size: amount of data to be sent and received |
<> | 144:ef7eb2e8f9f7 | 1213 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1214 | */ |
<> | 144:ef7eb2e8f9f7 | 1215 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1216 | { |
<> | 144:ef7eb2e8f9f7 | 1217 | uint32_t tmp = 0U, tmp1 = 0U; |
<> | 144:ef7eb2e8f9f7 | 1218 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1219 | |
<> | 144:ef7eb2e8f9f7 | 1220 | /* Check Direction parameter */ |
<> | 144:ef7eb2e8f9f7 | 1221 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1222 | |
<> | 144:ef7eb2e8f9f7 | 1223 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1224 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1225 | |
<> | 144:ef7eb2e8f9f7 | 1226 | tmp = hspi->State; |
<> | 144:ef7eb2e8f9f7 | 1227 | tmp1 = hspi->Init.Mode; |
<> | 144:ef7eb2e8f9f7 | 1228 | |
<> | 144:ef7eb2e8f9f7 | 1229 | if(!((tmp == HAL_SPI_STATE_READY) || \ |
<> | 144:ef7eb2e8f9f7 | 1230 | ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) |
<> | 144:ef7eb2e8f9f7 | 1231 | { |
<> | 144:ef7eb2e8f9f7 | 1232 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1233 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1234 | } |
<> | 144:ef7eb2e8f9f7 | 1235 | |
<> | 144:ef7eb2e8f9f7 | 1236 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1237 | { |
<> | 144:ef7eb2e8f9f7 | 1238 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1239 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1240 | } |
<> | 144:ef7eb2e8f9f7 | 1241 | |
<> | 144:ef7eb2e8f9f7 | 1242 | /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ |
<> | 144:ef7eb2e8f9f7 | 1243 | if(hspi->State == HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1244 | { |
<> | 144:ef7eb2e8f9f7 | 1245 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
<> | 144:ef7eb2e8f9f7 | 1246 | } |
<> | 144:ef7eb2e8f9f7 | 1247 | |
<> | 144:ef7eb2e8f9f7 | 1248 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 1249 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1250 | hspi->pTxBuffPtr = (uint8_t *)pTxData; |
<> | 144:ef7eb2e8f9f7 | 1251 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1252 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1253 | hspi->pRxBuffPtr = (uint8_t *)pRxData; |
<> | 144:ef7eb2e8f9f7 | 1254 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1255 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1256 | |
<> | 144:ef7eb2e8f9f7 | 1257 | /* Set the function for IT treatment */ |
<> | 144:ef7eb2e8f9f7 | 1258 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
<> | 144:ef7eb2e8f9f7 | 1259 | { |
<> | 144:ef7eb2e8f9f7 | 1260 | hspi->RxISR = SPI_2linesRxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1261 | hspi->TxISR = SPI_2linesTxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1262 | } |
<> | 144:ef7eb2e8f9f7 | 1263 | else |
<> | 144:ef7eb2e8f9f7 | 1264 | { |
<> | 144:ef7eb2e8f9f7 | 1265 | hspi->RxISR = SPI_2linesRxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1266 | hspi->TxISR = SPI_2linesTxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1267 | } |
<> | 144:ef7eb2e8f9f7 | 1268 | |
<> | 144:ef7eb2e8f9f7 | 1269 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1270 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1271 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1272 | { |
<> | 144:ef7eb2e8f9f7 | 1273 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1274 | } |
<> | 144:ef7eb2e8f9f7 | 1275 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1276 | |
<> | 144:ef7eb2e8f9f7 | 1277 | /* Enable TXE, RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1278 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1279 | |
<> | 144:ef7eb2e8f9f7 | 1280 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1281 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1282 | { |
<> | 144:ef7eb2e8f9f7 | 1283 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1284 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1285 | } |
<> | 144:ef7eb2e8f9f7 | 1286 | |
<> | 144:ef7eb2e8f9f7 | 1287 | error : |
<> | 144:ef7eb2e8f9f7 | 1288 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1289 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1290 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1291 | } |
<> | 144:ef7eb2e8f9f7 | 1292 | |
<> | 144:ef7eb2e8f9f7 | 1293 | /** |
<> | 144:ef7eb2e8f9f7 | 1294 | * @brief Transmit an amount of data in non-blocking mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 1295 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1296 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1297 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1298 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1299 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1300 | */ |
<> | 144:ef7eb2e8f9f7 | 1301 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1302 | { |
<> | 144:ef7eb2e8f9f7 | 1303 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1304 | |
<> | 144:ef7eb2e8f9f7 | 1305 | /* Check Direction parameter */ |
<> | 144:ef7eb2e8f9f7 | 1306 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1307 | |
<> | 144:ef7eb2e8f9f7 | 1308 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1309 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1310 | |
<> | 144:ef7eb2e8f9f7 | 1311 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1312 | { |
<> | 144:ef7eb2e8f9f7 | 1313 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1314 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1315 | } |
<> | 144:ef7eb2e8f9f7 | 1316 | |
<> | 144:ef7eb2e8f9f7 | 1317 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1318 | { |
<> | 144:ef7eb2e8f9f7 | 1319 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1320 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1321 | } |
<> | 144:ef7eb2e8f9f7 | 1322 | |
<> | 144:ef7eb2e8f9f7 | 1323 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 1324 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 1325 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1326 | hspi->pTxBuffPtr = (uint8_t *)pData; |
<> | 144:ef7eb2e8f9f7 | 1327 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1328 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1329 | |
<> | 144:ef7eb2e8f9f7 | 1330 | /* Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 1331 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1332 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1333 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1334 | hspi->RxXferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 1335 | hspi->RxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1336 | |
<> | 144:ef7eb2e8f9f7 | 1337 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1338 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1339 | { |
<> | 144:ef7eb2e8f9f7 | 1340 | SPI_1LINE_TX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1341 | } |
<> | 144:ef7eb2e8f9f7 | 1342 | |
<> | 144:ef7eb2e8f9f7 | 1343 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1344 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1345 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1346 | { |
<> | 144:ef7eb2e8f9f7 | 1347 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1348 | } |
<> | 144:ef7eb2e8f9f7 | 1349 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1350 | |
<> | 144:ef7eb2e8f9f7 | 1351 | /* Set the SPI TxDMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1352 | hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 1353 | |
<> | 144:ef7eb2e8f9f7 | 1354 | /* Set the SPI TxDMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1355 | hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 1356 | |
<> | 144:ef7eb2e8f9f7 | 1357 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1358 | hspi->hdmatx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1359 | |
<> | 144:ef7eb2e8f9f7 | 1360 | /* Set the DMA AbortCpltCallback */ |
<> | 144:ef7eb2e8f9f7 | 1361 | hspi->hdmatx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1362 | |
<> | 144:ef7eb2e8f9f7 | 1363 | /* Enable the Tx DMA Stream */ |
<> | 144:ef7eb2e8f9f7 | 1364 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1365 | |
<> | 144:ef7eb2e8f9f7 | 1366 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1367 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1368 | { |
<> | 144:ef7eb2e8f9f7 | 1369 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1370 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1371 | } |
<> | 144:ef7eb2e8f9f7 | 1372 | |
<> | 144:ef7eb2e8f9f7 | 1373 | /* Enable the SPI Error Interrupt Bit */ |
<> | 144:ef7eb2e8f9f7 | 1374 | SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
<> | 144:ef7eb2e8f9f7 | 1375 | |
<> | 144:ef7eb2e8f9f7 | 1376 | /* Enable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1377 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1378 | |
<> | 144:ef7eb2e8f9f7 | 1379 | error : |
<> | 144:ef7eb2e8f9f7 | 1380 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1381 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1382 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1383 | } |
<> | 144:ef7eb2e8f9f7 | 1384 | |
<> | 144:ef7eb2e8f9f7 | 1385 | /** |
<> | 144:ef7eb2e8f9f7 | 1386 | * @brief Receive an amount of data in non-blocking mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 1387 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1388 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1389 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1390 | * @note When the CRC feature is enabled the pData Length must be Size + 1. |
<> | 144:ef7eb2e8f9f7 | 1391 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1392 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1393 | */ |
<> | 144:ef7eb2e8f9f7 | 1394 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1395 | { |
<> | 144:ef7eb2e8f9f7 | 1396 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1397 | |
<> | 144:ef7eb2e8f9f7 | 1398 | if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) |
<> | 144:ef7eb2e8f9f7 | 1399 | { |
<> | 144:ef7eb2e8f9f7 | 1400 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1401 | /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ |
<> | 144:ef7eb2e8f9f7 | 1402 | return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); |
<> | 144:ef7eb2e8f9f7 | 1403 | } |
<> | 144:ef7eb2e8f9f7 | 1404 | |
<> | 144:ef7eb2e8f9f7 | 1405 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1406 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1407 | |
<> | 144:ef7eb2e8f9f7 | 1408 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1409 | { |
<> | 144:ef7eb2e8f9f7 | 1410 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1411 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1412 | } |
<> | 144:ef7eb2e8f9f7 | 1413 | |
<> | 144:ef7eb2e8f9f7 | 1414 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1415 | { |
<> | 144:ef7eb2e8f9f7 | 1416 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1417 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1418 | } |
<> | 144:ef7eb2e8f9f7 | 1419 | |
<> | 144:ef7eb2e8f9f7 | 1420 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 1421 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1422 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1423 | hspi->pRxBuffPtr = (uint8_t *)pData; |
<> | 144:ef7eb2e8f9f7 | 1424 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1425 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1426 | |
<> | 144:ef7eb2e8f9f7 | 1427 | /*Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 1428 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1429 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1430 | hspi->TxXferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 1431 | hspi->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1432 | |
<> | 144:ef7eb2e8f9f7 | 1433 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1434 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1435 | { |
<> | 144:ef7eb2e8f9f7 | 1436 | SPI_1LINE_RX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1437 | } |
<> | 144:ef7eb2e8f9f7 | 1438 | |
<> | 144:ef7eb2e8f9f7 | 1439 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1440 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1441 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1442 | { |
<> | 144:ef7eb2e8f9f7 | 1443 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1444 | } |
<> | 144:ef7eb2e8f9f7 | 1445 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1446 | |
<> | 144:ef7eb2e8f9f7 | 1447 | /* Set the SPI RxDMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1448 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1449 | |
<> | 144:ef7eb2e8f9f7 | 1450 | /* Set the SPI Rx DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1451 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1452 | |
<> | 144:ef7eb2e8f9f7 | 1453 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1454 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1455 | |
<> | 144:ef7eb2e8f9f7 | 1456 | /* Set the DMA AbortCpltCallback */ |
<> | 144:ef7eb2e8f9f7 | 1457 | hspi->hdmarx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1458 | |
<> | 144:ef7eb2e8f9f7 | 1459 | /* Enable the Rx DMA Stream */ |
<> | 144:ef7eb2e8f9f7 | 1460 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1461 | |
<> | 144:ef7eb2e8f9f7 | 1462 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1463 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1464 | { |
<> | 144:ef7eb2e8f9f7 | 1465 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1466 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1467 | } |
<> | 144:ef7eb2e8f9f7 | 1468 | |
<> | 144:ef7eb2e8f9f7 | 1469 | /* Enable the SPI Error Interrupt Bit */ |
<> | 144:ef7eb2e8f9f7 | 1470 | SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
<> | 144:ef7eb2e8f9f7 | 1471 | |
<> | 144:ef7eb2e8f9f7 | 1472 | /* Enable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1473 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1474 | |
<> | 144:ef7eb2e8f9f7 | 1475 | error: |
<> | 144:ef7eb2e8f9f7 | 1476 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1477 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1478 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1479 | } |
<> | 144:ef7eb2e8f9f7 | 1480 | |
<> | 144:ef7eb2e8f9f7 | 1481 | /** |
<> | 144:ef7eb2e8f9f7 | 1482 | * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 1483 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1484 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1485 | * @param pTxData: pointer to transmission data buffer |
<> | 144:ef7eb2e8f9f7 | 1486 | * @param pRxData: pointer to reception data buffer |
<> | 144:ef7eb2e8f9f7 | 1487 | * @note When the CRC feature is enabled the pRxData Length must be Size + 1 |
<> | 144:ef7eb2e8f9f7 | 1488 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1489 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1490 | */ |
<> | 144:ef7eb2e8f9f7 | 1491 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1492 | { |
<> | 144:ef7eb2e8f9f7 | 1493 | uint32_t tmp = 0U, tmp1 = 0U; |
<> | 144:ef7eb2e8f9f7 | 1494 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1495 | |
<> | 144:ef7eb2e8f9f7 | 1496 | /* Check Direction parameter */ |
<> | 144:ef7eb2e8f9f7 | 1497 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1498 | |
<> | 144:ef7eb2e8f9f7 | 1499 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1500 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1501 | |
<> | 144:ef7eb2e8f9f7 | 1502 | tmp = hspi->State; |
<> | 144:ef7eb2e8f9f7 | 1503 | tmp1 = hspi->Init.Mode; |
<> | 144:ef7eb2e8f9f7 | 1504 | if(!((tmp == HAL_SPI_STATE_READY) || |
<> | 144:ef7eb2e8f9f7 | 1505 | ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) |
<> | 144:ef7eb2e8f9f7 | 1506 | { |
<> | 144:ef7eb2e8f9f7 | 1507 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1508 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1509 | } |
<> | 144:ef7eb2e8f9f7 | 1510 | |
<> | 144:ef7eb2e8f9f7 | 1511 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1512 | { |
<> | 144:ef7eb2e8f9f7 | 1513 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1514 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1515 | } |
<> | 144:ef7eb2e8f9f7 | 1516 | |
<> | 144:ef7eb2e8f9f7 | 1517 | /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ |
<> | 144:ef7eb2e8f9f7 | 1518 | if(hspi->State == HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1519 | { |
<> | 144:ef7eb2e8f9f7 | 1520 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
<> | 144:ef7eb2e8f9f7 | 1521 | } |
<> | 144:ef7eb2e8f9f7 | 1522 | |
<> | 144:ef7eb2e8f9f7 | 1523 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 1524 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1525 | hspi->pTxBuffPtr = (uint8_t*)pTxData; |
<> | 144:ef7eb2e8f9f7 | 1526 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1527 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1528 | hspi->pRxBuffPtr = (uint8_t*)pRxData; |
<> | 144:ef7eb2e8f9f7 | 1529 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1530 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1531 | |
<> | 144:ef7eb2e8f9f7 | 1532 | /* Init field not used in handle to zero */ |
<> | 144:ef7eb2e8f9f7 | 1533 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1534 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1535 | |
<> | 144:ef7eb2e8f9f7 | 1536 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1537 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1538 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1539 | { |
<> | 144:ef7eb2e8f9f7 | 1540 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1541 | } |
<> | 144:ef7eb2e8f9f7 | 1542 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1543 | |
<> | 144:ef7eb2e8f9f7 | 1544 | /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1545 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 1546 | { |
<> | 144:ef7eb2e8f9f7 | 1547 | /* Set the SPI Rx DMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1548 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1549 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1550 | } |
<> | 144:ef7eb2e8f9f7 | 1551 | else |
<> | 144:ef7eb2e8f9f7 | 1552 | { |
<> | 144:ef7eb2e8f9f7 | 1553 | /* Set the SPI Tx/Rx DMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1554 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1555 | hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1556 | } |
<> | 144:ef7eb2e8f9f7 | 1557 | |
<> | 144:ef7eb2e8f9f7 | 1558 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1559 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1560 | |
<> | 144:ef7eb2e8f9f7 | 1561 | /* Set the DMA AbortCpltCallback */ |
<> | 144:ef7eb2e8f9f7 | 1562 | hspi->hdmarx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1563 | |
<> | 144:ef7eb2e8f9f7 | 1564 | /* Enable the Rx DMA Stream */ |
<> | 144:ef7eb2e8f9f7 | 1565 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1566 | |
<> | 144:ef7eb2e8f9f7 | 1567 | /* Enable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1568 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1569 | |
<> | 144:ef7eb2e8f9f7 | 1570 | /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing |
<> | 144:ef7eb2e8f9f7 | 1571 | is performed in DMA reception complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1572 | hspi->hdmatx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1573 | hspi->hdmatx->XferCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1574 | hspi->hdmatx->XferErrorCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1575 | hspi->hdmatx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1576 | |
<> | 144:ef7eb2e8f9f7 | 1577 | /* Enable the Tx DMA Stream */ |
<> | 144:ef7eb2e8f9f7 | 1578 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1579 | |
<> | 144:ef7eb2e8f9f7 | 1580 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1581 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1582 | { |
<> | 144:ef7eb2e8f9f7 | 1583 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1584 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1585 | } |
<> | 144:ef7eb2e8f9f7 | 1586 | /* Enable the SPI Error Interrupt Bit */ |
<> | 144:ef7eb2e8f9f7 | 1587 | SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
<> | 144:ef7eb2e8f9f7 | 1588 | |
<> | 144:ef7eb2e8f9f7 | 1589 | /* Enable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1590 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1591 | |
<> | 144:ef7eb2e8f9f7 | 1592 | error : |
<> | 144:ef7eb2e8f9f7 | 1593 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1594 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1595 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1596 | } |
<> | 144:ef7eb2e8f9f7 | 1597 | |
<> | 144:ef7eb2e8f9f7 | 1598 | /** |
<> | 144:ef7eb2e8f9f7 | 1599 | * @brief Stop the DMA Transfer. |
<> | 144:ef7eb2e8f9f7 | 1600 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1601 | * the configuration information for the specified SPI module. |
<> | 144:ef7eb2e8f9f7 | 1602 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1603 | */ |
<> | 144:ef7eb2e8f9f7 | 1604 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1605 | { |
<> | 144:ef7eb2e8f9f7 | 1606 | /* The Lock is not implemented on this API to allow the user application |
<> | 144:ef7eb2e8f9f7 | 1607 | to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): |
<> | 144:ef7eb2e8f9f7 | 1608 | when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated |
<> | 144:ef7eb2e8f9f7 | 1609 | and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 1610 | */ |
<> | 144:ef7eb2e8f9f7 | 1611 | |
<> | 144:ef7eb2e8f9f7 | 1612 | /* Abort the SPI DMA tx Stream */ |
<> | 144:ef7eb2e8f9f7 | 1613 | if(hspi->hdmatx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1614 | { |
<> | 144:ef7eb2e8f9f7 | 1615 | HAL_DMA_Abort(hspi->hdmatx); |
<> | 144:ef7eb2e8f9f7 | 1616 | } |
<> | 144:ef7eb2e8f9f7 | 1617 | /* Abort the SPI DMA rx Stream */ |
<> | 144:ef7eb2e8f9f7 | 1618 | if(hspi->hdmarx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1619 | { |
<> | 144:ef7eb2e8f9f7 | 1620 | HAL_DMA_Abort(hspi->hdmarx); |
<> | 144:ef7eb2e8f9f7 | 1621 | } |
<> | 144:ef7eb2e8f9f7 | 1622 | |
<> | 144:ef7eb2e8f9f7 | 1623 | /* Disable the SPI DMA Tx & Rx requests */ |
<> | 144:ef7eb2e8f9f7 | 1624 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1625 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1626 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1627 | } |
<> | 144:ef7eb2e8f9f7 | 1628 | |
<> | 144:ef7eb2e8f9f7 | 1629 | /** |
<> | 144:ef7eb2e8f9f7 | 1630 | * @brief Handle SPI interrupt request. |
<> | 144:ef7eb2e8f9f7 | 1631 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1632 | * the configuration information for the specified SPI module. |
<> | 144:ef7eb2e8f9f7 | 1633 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1634 | */ |
<> | 144:ef7eb2e8f9f7 | 1635 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1636 | { |
<> | 144:ef7eb2e8f9f7 | 1637 | uint32_t itsource = hspi->Instance->CR2; |
<> | 144:ef7eb2e8f9f7 | 1638 | uint32_t itflag = hspi->Instance->SR; |
<> | 144:ef7eb2e8f9f7 | 1639 | |
<> | 144:ef7eb2e8f9f7 | 1640 | /* SPI in mode Receiver ----------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1641 | if(((itflag & SPI_FLAG_OVR) == RESET) && |
<> | 144:ef7eb2e8f9f7 | 1642 | ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1643 | { |
<> | 144:ef7eb2e8f9f7 | 1644 | hspi->RxISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 1645 | return; |
<> | 144:ef7eb2e8f9f7 | 1646 | } |
<> | 144:ef7eb2e8f9f7 | 1647 | |
<> | 144:ef7eb2e8f9f7 | 1648 | /* SPI in mode Transmitter -------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1649 | if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1650 | { |
<> | 144:ef7eb2e8f9f7 | 1651 | hspi->TxISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 1652 | return; |
<> | 144:ef7eb2e8f9f7 | 1653 | } |
<> | 144:ef7eb2e8f9f7 | 1654 | |
<> | 144:ef7eb2e8f9f7 | 1655 | /* SPI in Error Treatment --------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1656 | if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1657 | { |
<> | 144:ef7eb2e8f9f7 | 1658 | /* SPI Overrun error interrupt occurred ----------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1659 | if((itflag & SPI_FLAG_OVR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1660 | { |
<> | 144:ef7eb2e8f9f7 | 1661 | if(hspi->State != HAL_SPI_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 1662 | { |
<> | 144:ef7eb2e8f9f7 | 1663 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 1664 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1665 | } |
<> | 144:ef7eb2e8f9f7 | 1666 | else |
<> | 144:ef7eb2e8f9f7 | 1667 | { |
<> | 144:ef7eb2e8f9f7 | 1668 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1669 | return; |
<> | 144:ef7eb2e8f9f7 | 1670 | } |
<> | 144:ef7eb2e8f9f7 | 1671 | } |
<> | 144:ef7eb2e8f9f7 | 1672 | |
<> | 144:ef7eb2e8f9f7 | 1673 | /* SPI Mode Fault error interrupt occurred -------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1674 | if((itflag & SPI_FLAG_MODF) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1675 | { |
<> | 144:ef7eb2e8f9f7 | 1676 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); |
<> | 144:ef7eb2e8f9f7 | 1677 | __HAL_SPI_CLEAR_MODFFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1678 | } |
<> | 144:ef7eb2e8f9f7 | 1679 | |
<> | 144:ef7eb2e8f9f7 | 1680 | /* SPI Frame error interrupt occurred ------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1681 | if((itflag & SPI_FLAG_FRE) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1682 | { |
<> | 144:ef7eb2e8f9f7 | 1683 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); |
<> | 144:ef7eb2e8f9f7 | 1684 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1685 | } |
<> | 144:ef7eb2e8f9f7 | 1686 | |
<> | 144:ef7eb2e8f9f7 | 1687 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 1688 | { |
<> | 144:ef7eb2e8f9f7 | 1689 | /* Disable all interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1690 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); |
<> | 144:ef7eb2e8f9f7 | 1691 | |
<> | 144:ef7eb2e8f9f7 | 1692 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1693 | /* Disable the SPI DMA requests if enabled */ |
<> | 144:ef7eb2e8f9f7 | 1694 | if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) |
<> | 144:ef7eb2e8f9f7 | 1695 | { |
<> | 144:ef7eb2e8f9f7 | 1696 | CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); |
<> | 144:ef7eb2e8f9f7 | 1697 | |
<> | 144:ef7eb2e8f9f7 | 1698 | /* Abort the SPI DMA Rx channel */ |
<> | 144:ef7eb2e8f9f7 | 1699 | if(hspi->hdmarx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1700 | { |
<> | 144:ef7eb2e8f9f7 | 1701 | /* Set the SPI DMA Abort callback : |
<> | 144:ef7eb2e8f9f7 | 1702 | will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ |
<> | 144:ef7eb2e8f9f7 | 1703 | hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; |
<> | 144:ef7eb2e8f9f7 | 1704 | HAL_DMA_Abort_IT(hspi->hdmarx); |
<> | 144:ef7eb2e8f9f7 | 1705 | } |
<> | 144:ef7eb2e8f9f7 | 1706 | /* Abort the SPI DMA Tx channel */ |
<> | 144:ef7eb2e8f9f7 | 1707 | if(hspi->hdmatx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1708 | { |
<> | 144:ef7eb2e8f9f7 | 1709 | /* Set the SPI DMA Abort callback : |
<> | 144:ef7eb2e8f9f7 | 1710 | will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ |
<> | 144:ef7eb2e8f9f7 | 1711 | hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; |
<> | 144:ef7eb2e8f9f7 | 1712 | HAL_DMA_Abort_IT(hspi->hdmatx); |
<> | 144:ef7eb2e8f9f7 | 1713 | } |
<> | 144:ef7eb2e8f9f7 | 1714 | } |
<> | 144:ef7eb2e8f9f7 | 1715 | else |
<> | 144:ef7eb2e8f9f7 | 1716 | { |
<> | 144:ef7eb2e8f9f7 | 1717 | /* Call user error callback */ |
<> | 144:ef7eb2e8f9f7 | 1718 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1719 | } |
<> | 144:ef7eb2e8f9f7 | 1720 | } |
<> | 144:ef7eb2e8f9f7 | 1721 | return; |
<> | 144:ef7eb2e8f9f7 | 1722 | } |
<> | 144:ef7eb2e8f9f7 | 1723 | } |
<> | 144:ef7eb2e8f9f7 | 1724 | |
<> | 144:ef7eb2e8f9f7 | 1725 | /** |
<> | 144:ef7eb2e8f9f7 | 1726 | * @brief Tx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1727 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1728 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1729 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1730 | */ |
<> | 144:ef7eb2e8f9f7 | 1731 | __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1732 | { |
<> | 144:ef7eb2e8f9f7 | 1733 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1734 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1735 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1736 | the HAL_SPI_TxCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1737 | */ |
<> | 144:ef7eb2e8f9f7 | 1738 | } |
<> | 144:ef7eb2e8f9f7 | 1739 | |
<> | 144:ef7eb2e8f9f7 | 1740 | /** |
<> | 144:ef7eb2e8f9f7 | 1741 | * @brief Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1742 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1743 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1744 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1745 | */ |
<> | 144:ef7eb2e8f9f7 | 1746 | __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1747 | { |
<> | 144:ef7eb2e8f9f7 | 1748 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1749 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1750 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1751 | the HAL_SPI_RxCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1752 | */ |
<> | 144:ef7eb2e8f9f7 | 1753 | } |
<> | 144:ef7eb2e8f9f7 | 1754 | |
<> | 144:ef7eb2e8f9f7 | 1755 | /** |
<> | 144:ef7eb2e8f9f7 | 1756 | * @brief Tx and Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1757 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1758 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1759 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1760 | */ |
<> | 144:ef7eb2e8f9f7 | 1761 | __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1762 | { |
<> | 144:ef7eb2e8f9f7 | 1763 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1764 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1765 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1766 | the HAL_SPI_TxRxCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1767 | */ |
<> | 144:ef7eb2e8f9f7 | 1768 | } |
<> | 144:ef7eb2e8f9f7 | 1769 | |
<> | 144:ef7eb2e8f9f7 | 1770 | /** |
<> | 144:ef7eb2e8f9f7 | 1771 | * @brief Tx Half Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1772 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1773 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1774 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1775 | */ |
<> | 144:ef7eb2e8f9f7 | 1776 | __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1777 | { |
<> | 144:ef7eb2e8f9f7 | 1778 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1779 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1780 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1781 | the HAL_SPI_TxHalfCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1782 | */ |
<> | 144:ef7eb2e8f9f7 | 1783 | } |
<> | 144:ef7eb2e8f9f7 | 1784 | |
<> | 144:ef7eb2e8f9f7 | 1785 | /** |
<> | 144:ef7eb2e8f9f7 | 1786 | * @brief Rx Half Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1787 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1788 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1789 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1790 | */ |
<> | 144:ef7eb2e8f9f7 | 1791 | __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1792 | { |
<> | 144:ef7eb2e8f9f7 | 1793 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1794 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1795 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1796 | the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1797 | */ |
<> | 144:ef7eb2e8f9f7 | 1798 | } |
<> | 144:ef7eb2e8f9f7 | 1799 | |
<> | 144:ef7eb2e8f9f7 | 1800 | /** |
<> | 144:ef7eb2e8f9f7 | 1801 | * @brief Tx and Rx Half Transfer callback. |
<> | 144:ef7eb2e8f9f7 | 1802 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1803 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1804 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1805 | */ |
<> | 144:ef7eb2e8f9f7 | 1806 | __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1807 | { |
<> | 144:ef7eb2e8f9f7 | 1808 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1809 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1810 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1811 | the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1812 | */ |
<> | 144:ef7eb2e8f9f7 | 1813 | } |
<> | 144:ef7eb2e8f9f7 | 1814 | |
<> | 144:ef7eb2e8f9f7 | 1815 | /** |
<> | 144:ef7eb2e8f9f7 | 1816 | * @brief SPI error callback. |
<> | 144:ef7eb2e8f9f7 | 1817 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1818 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1819 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1820 | */ |
<> | 144:ef7eb2e8f9f7 | 1821 | __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1822 | { |
<> | 144:ef7eb2e8f9f7 | 1823 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1824 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1825 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1826 | the HAL_SPI_ErrorCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1827 | */ |
<> | 144:ef7eb2e8f9f7 | 1828 | /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes |
<> | 144:ef7eb2e8f9f7 | 1829 | and user can use HAL_SPI_GetError() API to check the latest error occurred |
<> | 144:ef7eb2e8f9f7 | 1830 | */ |
<> | 144:ef7eb2e8f9f7 | 1831 | } |
<> | 144:ef7eb2e8f9f7 | 1832 | |
<> | 144:ef7eb2e8f9f7 | 1833 | /** |
<> | 144:ef7eb2e8f9f7 | 1834 | * @} |
<> | 144:ef7eb2e8f9f7 | 1835 | */ |
<> | 144:ef7eb2e8f9f7 | 1836 | |
<> | 144:ef7eb2e8f9f7 | 1837 | /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 1838 | * @brief SPI control functions |
<> | 144:ef7eb2e8f9f7 | 1839 | * |
<> | 144:ef7eb2e8f9f7 | 1840 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1841 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1842 | ##### Peripheral State and Errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1843 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1844 | [..] |
<> | 144:ef7eb2e8f9f7 | 1845 | This subsection provides a set of functions allowing to control the SPI. |
<> | 144:ef7eb2e8f9f7 | 1846 | (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral |
<> | 144:ef7eb2e8f9f7 | 1847 | (+) HAL_SPI_GetError() check in run-time Errors occurring during communication |
<> | 144:ef7eb2e8f9f7 | 1848 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1849 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1850 | */ |
<> | 144:ef7eb2e8f9f7 | 1851 | |
<> | 144:ef7eb2e8f9f7 | 1852 | /** |
<> | 144:ef7eb2e8f9f7 | 1853 | * @brief Return the SPI handle state. |
<> | 144:ef7eb2e8f9f7 | 1854 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1855 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1856 | * @retval SPI state |
<> | 144:ef7eb2e8f9f7 | 1857 | */ |
<> | 144:ef7eb2e8f9f7 | 1858 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1859 | { |
<> | 144:ef7eb2e8f9f7 | 1860 | /* Return SPI handle state */ |
<> | 144:ef7eb2e8f9f7 | 1861 | return hspi->State; |
<> | 144:ef7eb2e8f9f7 | 1862 | } |
<> | 144:ef7eb2e8f9f7 | 1863 | |
<> | 144:ef7eb2e8f9f7 | 1864 | /** |
<> | 144:ef7eb2e8f9f7 | 1865 | * @brief Return the SPI error code. |
<> | 144:ef7eb2e8f9f7 | 1866 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1867 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1868 | * @retval SPI error code in bitmap format |
<> | 144:ef7eb2e8f9f7 | 1869 | */ |
<> | 144:ef7eb2e8f9f7 | 1870 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1871 | { |
<> | 144:ef7eb2e8f9f7 | 1872 | /* Return SPI ErrorCode */ |
<> | 144:ef7eb2e8f9f7 | 1873 | return hspi->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1874 | } |
<> | 144:ef7eb2e8f9f7 | 1875 | |
<> | 144:ef7eb2e8f9f7 | 1876 | /** |
<> | 144:ef7eb2e8f9f7 | 1877 | * @} |
<> | 144:ef7eb2e8f9f7 | 1878 | */ |
<> | 144:ef7eb2e8f9f7 | 1879 | |
<> | 144:ef7eb2e8f9f7 | 1880 | /** |
<> | 144:ef7eb2e8f9f7 | 1881 | * @} |
<> | 144:ef7eb2e8f9f7 | 1882 | */ |
<> | 144:ef7eb2e8f9f7 | 1883 | |
<> | 144:ef7eb2e8f9f7 | 1884 | /** @addtogroup SPI_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 1885 | * @brief Private functions |
<> | 144:ef7eb2e8f9f7 | 1886 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1887 | */ |
<> | 144:ef7eb2e8f9f7 | 1888 | |
<> | 144:ef7eb2e8f9f7 | 1889 | /** |
<> | 144:ef7eb2e8f9f7 | 1890 | * @brief DMA SPI transmit process complete callback. |
<> | 144:ef7eb2e8f9f7 | 1891 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1892 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1893 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1894 | */ |
<> | 144:ef7eb2e8f9f7 | 1895 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1896 | { |
<> | 144:ef7eb2e8f9f7 | 1897 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1898 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1899 | |
<> | 144:ef7eb2e8f9f7 | 1900 | /* Init tickstart for timeout managment*/ |
<> | 144:ef7eb2e8f9f7 | 1901 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1902 | |
<> | 144:ef7eb2e8f9f7 | 1903 | /* DMA Normal Mode */ |
<> | 144:ef7eb2e8f9f7 | 1904 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
<> | 144:ef7eb2e8f9f7 | 1905 | { |
<> | 144:ef7eb2e8f9f7 | 1906 | /* Disable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1907 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1908 | |
<> | 144:ef7eb2e8f9f7 | 1909 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 1910 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1911 | { |
<> | 144:ef7eb2e8f9f7 | 1912 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 1913 | } |
<> | 144:ef7eb2e8f9f7 | 1914 | |
<> | 144:ef7eb2e8f9f7 | 1915 | /* Clear overrun flag in 2 Lines communication mode because received data is not read */ |
<> | 144:ef7eb2e8f9f7 | 1916 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 1917 | { |
<> | 144:ef7eb2e8f9f7 | 1918 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1919 | } |
<> | 144:ef7eb2e8f9f7 | 1920 | |
<> | 144:ef7eb2e8f9f7 | 1921 | hspi->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1922 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1923 | |
<> | 144:ef7eb2e8f9f7 | 1924 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 1925 | { |
<> | 144:ef7eb2e8f9f7 | 1926 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1927 | return; |
<> | 144:ef7eb2e8f9f7 | 1928 | } |
<> | 144:ef7eb2e8f9f7 | 1929 | } |
<> | 144:ef7eb2e8f9f7 | 1930 | HAL_SPI_TxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1931 | } |
<> | 144:ef7eb2e8f9f7 | 1932 | |
<> | 144:ef7eb2e8f9f7 | 1933 | /** |
<> | 144:ef7eb2e8f9f7 | 1934 | * @brief DMA SPI receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 1935 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1936 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1937 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1938 | */ |
<> | 144:ef7eb2e8f9f7 | 1939 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1940 | { |
<> | 144:ef7eb2e8f9f7 | 1941 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1942 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1943 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1944 | __IO uint16_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 1945 | |
<> | 144:ef7eb2e8f9f7 | 1946 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 1947 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1948 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1949 | |
<> | 144:ef7eb2e8f9f7 | 1950 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
<> | 144:ef7eb2e8f9f7 | 1951 | { |
<> | 144:ef7eb2e8f9f7 | 1952 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1953 | /* CRC handling */ |
<> | 144:ef7eb2e8f9f7 | 1954 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1955 | { |
<> | 144:ef7eb2e8f9f7 | 1956 | /* Wait until RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 1957 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1958 | { |
<> | 144:ef7eb2e8f9f7 | 1959 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 1960 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 1961 | } |
<> | 144:ef7eb2e8f9f7 | 1962 | /* Read CRC */ |
<> | 144:ef7eb2e8f9f7 | 1963 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1964 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 1965 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 1966 | } |
<> | 144:ef7eb2e8f9f7 | 1967 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1968 | |
<> | 144:ef7eb2e8f9f7 | 1969 | /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ |
<> | 144:ef7eb2e8f9f7 | 1970 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1971 | |
<> | 144:ef7eb2e8f9f7 | 1972 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 1973 | { |
<> | 144:ef7eb2e8f9f7 | 1974 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1975 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1976 | } |
<> | 144:ef7eb2e8f9f7 | 1977 | |
<> | 144:ef7eb2e8f9f7 | 1978 | hspi->RxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1979 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1980 | |
<> | 144:ef7eb2e8f9f7 | 1981 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 1982 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 1983 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
<> | 144:ef7eb2e8f9f7 | 1984 | { |
<> | 144:ef7eb2e8f9f7 | 1985 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 1986 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1987 | } |
<> | 144:ef7eb2e8f9f7 | 1988 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 1989 | |
<> | 144:ef7eb2e8f9f7 | 1990 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 1991 | { |
<> | 144:ef7eb2e8f9f7 | 1992 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1993 | return; |
<> | 144:ef7eb2e8f9f7 | 1994 | } |
<> | 144:ef7eb2e8f9f7 | 1995 | } |
<> | 144:ef7eb2e8f9f7 | 1996 | HAL_SPI_RxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1997 | } |
<> | 144:ef7eb2e8f9f7 | 1998 | |
<> | 144:ef7eb2e8f9f7 | 1999 | /** |
<> | 144:ef7eb2e8f9f7 | 2000 | * @brief DMA SPI transmit receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 2001 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2002 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2003 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2004 | */ |
<> | 144:ef7eb2e8f9f7 | 2005 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2006 | { |
<> | 144:ef7eb2e8f9f7 | 2007 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2008 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2009 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2010 | __IO int16_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 2011 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2012 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 2013 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2014 | |
<> | 144:ef7eb2e8f9f7 | 2015 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
<> | 144:ef7eb2e8f9f7 | 2016 | { |
<> | 144:ef7eb2e8f9f7 | 2017 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2018 | /* CRC handling */ |
<> | 144:ef7eb2e8f9f7 | 2019 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2020 | { |
<> | 144:ef7eb2e8f9f7 | 2021 | /* Wait the CRC data */ |
<> | 144:ef7eb2e8f9f7 | 2022 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2023 | { |
<> | 144:ef7eb2e8f9f7 | 2024 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 2025 | } |
<> | 144:ef7eb2e8f9f7 | 2026 | /* Read CRC to Flush DR and RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 2027 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2028 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2029 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2030 | } |
<> | 144:ef7eb2e8f9f7 | 2031 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2032 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2033 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2034 | { |
<> | 144:ef7eb2e8f9f7 | 2035 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 2036 | } |
<> | 144:ef7eb2e8f9f7 | 2037 | |
<> | 144:ef7eb2e8f9f7 | 2038 | /* Disable Rx/Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 2039 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 2040 | |
<> | 144:ef7eb2e8f9f7 | 2041 | hspi->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 2042 | hspi->RxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 2043 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2044 | |
<> | 144:ef7eb2e8f9f7 | 2045 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2046 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2047 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
<> | 144:ef7eb2e8f9f7 | 2048 | { |
<> | 144:ef7eb2e8f9f7 | 2049 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 2050 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2051 | } |
<> | 144:ef7eb2e8f9f7 | 2052 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2053 | |
<> | 144:ef7eb2e8f9f7 | 2054 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2055 | { |
<> | 144:ef7eb2e8f9f7 | 2056 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2057 | return; |
<> | 144:ef7eb2e8f9f7 | 2058 | } |
<> | 144:ef7eb2e8f9f7 | 2059 | } |
<> | 144:ef7eb2e8f9f7 | 2060 | HAL_SPI_TxRxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2061 | } |
<> | 144:ef7eb2e8f9f7 | 2062 | |
<> | 144:ef7eb2e8f9f7 | 2063 | /** |
<> | 144:ef7eb2e8f9f7 | 2064 | * @brief DMA SPI half transmit process complete callback. |
<> | 144:ef7eb2e8f9f7 | 2065 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2066 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2067 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2068 | */ |
<> | 144:ef7eb2e8f9f7 | 2069 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2070 | { |
<> | 144:ef7eb2e8f9f7 | 2071 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2072 | |
<> | 144:ef7eb2e8f9f7 | 2073 | HAL_SPI_TxHalfCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2074 | } |
<> | 144:ef7eb2e8f9f7 | 2075 | |
<> | 144:ef7eb2e8f9f7 | 2076 | /** |
<> | 144:ef7eb2e8f9f7 | 2077 | * @brief DMA SPI half receive process complete callback |
<> | 144:ef7eb2e8f9f7 | 2078 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2079 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2080 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2081 | */ |
<> | 144:ef7eb2e8f9f7 | 2082 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2083 | { |
<> | 144:ef7eb2e8f9f7 | 2084 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2085 | |
<> | 144:ef7eb2e8f9f7 | 2086 | HAL_SPI_RxHalfCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2087 | } |
<> | 144:ef7eb2e8f9f7 | 2088 | |
<> | 144:ef7eb2e8f9f7 | 2089 | /** |
<> | 144:ef7eb2e8f9f7 | 2090 | * @brief DMA SPI half transmit receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 2091 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2092 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2093 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2094 | */ |
<> | 144:ef7eb2e8f9f7 | 2095 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2096 | { |
<> | 144:ef7eb2e8f9f7 | 2097 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2098 | |
<> | 144:ef7eb2e8f9f7 | 2099 | HAL_SPI_TxRxHalfCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2100 | } |
<> | 144:ef7eb2e8f9f7 | 2101 | |
<> | 144:ef7eb2e8f9f7 | 2102 | /** |
<> | 144:ef7eb2e8f9f7 | 2103 | * @brief DMA SPI communication error callback. |
<> | 144:ef7eb2e8f9f7 | 2104 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2105 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2106 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2107 | */ |
<> | 144:ef7eb2e8f9f7 | 2108 | static void SPI_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2109 | { |
<> | 144:ef7eb2e8f9f7 | 2110 | SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2111 | |
<> | 144:ef7eb2e8f9f7 | 2112 | /* Stop the disable DMA transfer on SPI side */ |
<> | 144:ef7eb2e8f9f7 | 2113 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 2114 | |
<> | 144:ef7eb2e8f9f7 | 2115 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2116 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2117 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2118 | } |
<> | 144:ef7eb2e8f9f7 | 2119 | |
<> | 144:ef7eb2e8f9f7 | 2120 | /** |
<> | 144:ef7eb2e8f9f7 | 2121 | * @brief DMA SPI communication abort callback, when initiated by HAL services on Error |
<> | 144:ef7eb2e8f9f7 | 2122 | * (To be called at end of DMA Abort procedure following error occurrence). |
<> | 144:ef7eb2e8f9f7 | 2123 | * @param hdma DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2124 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2125 | */ |
<> | 144:ef7eb2e8f9f7 | 2126 | static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2127 | { |
<> | 144:ef7eb2e8f9f7 | 2128 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2129 | hspi->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 2130 | hspi->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 2131 | |
<> | 144:ef7eb2e8f9f7 | 2132 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2133 | } |
<> | 144:ef7eb2e8f9f7 | 2134 | |
<> | 144:ef7eb2e8f9f7 | 2135 | /** |
<> | 144:ef7eb2e8f9f7 | 2136 | * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2137 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2138 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2139 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2140 | */ |
<> | 144:ef7eb2e8f9f7 | 2141 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2142 | { |
<> | 144:ef7eb2e8f9f7 | 2143 | /* Receive data in 8bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2144 | *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2145 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2146 | |
<> | 144:ef7eb2e8f9f7 | 2147 | /* check end of the reception */ |
<> | 144:ef7eb2e8f9f7 | 2148 | if(hspi->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2149 | { |
<> | 144:ef7eb2e8f9f7 | 2150 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2151 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2152 | { |
<> | 144:ef7eb2e8f9f7 | 2153 | hspi->RxISR = SPI_2linesRxISR_8BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2154 | return; |
<> | 144:ef7eb2e8f9f7 | 2155 | } |
<> | 144:ef7eb2e8f9f7 | 2156 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2157 | |
<> | 144:ef7eb2e8f9f7 | 2158 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2159 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2160 | |
<> | 144:ef7eb2e8f9f7 | 2161 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2162 | { |
<> | 144:ef7eb2e8f9f7 | 2163 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2164 | } |
<> | 144:ef7eb2e8f9f7 | 2165 | } |
<> | 144:ef7eb2e8f9f7 | 2166 | } |
<> | 144:ef7eb2e8f9f7 | 2167 | |
<> | 144:ef7eb2e8f9f7 | 2168 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2169 | /** |
<> | 144:ef7eb2e8f9f7 | 2170 | * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2171 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2172 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2173 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2174 | */ |
<> | 144:ef7eb2e8f9f7 | 2175 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2176 | { |
<> | 144:ef7eb2e8f9f7 | 2177 | __IO uint8_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 2178 | |
<> | 144:ef7eb2e8f9f7 | 2179 | /* Read data register to flush CRC */ |
<> | 144:ef7eb2e8f9f7 | 2180 | tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2181 | |
<> | 144:ef7eb2e8f9f7 | 2182 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2183 | |
<> | 144:ef7eb2e8f9f7 | 2184 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2185 | |
<> | 144:ef7eb2e8f9f7 | 2186 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2187 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2188 | |
<> | 144:ef7eb2e8f9f7 | 2189 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2190 | { |
<> | 144:ef7eb2e8f9f7 | 2191 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2192 | } |
<> | 144:ef7eb2e8f9f7 | 2193 | } |
<> | 144:ef7eb2e8f9f7 | 2194 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2195 | |
<> | 144:ef7eb2e8f9f7 | 2196 | /** |
<> | 144:ef7eb2e8f9f7 | 2197 | * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2198 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2199 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2200 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2201 | */ |
<> | 144:ef7eb2e8f9f7 | 2202 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2203 | { |
<> | 144:ef7eb2e8f9f7 | 2204 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 2205 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2206 | |
<> | 144:ef7eb2e8f9f7 | 2207 | /* check the end of the transmission */ |
<> | 144:ef7eb2e8f9f7 | 2208 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2209 | { |
<> | 144:ef7eb2e8f9f7 | 2210 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2211 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2212 | { |
<> | 144:ef7eb2e8f9f7 | 2213 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2214 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2215 | return; |
<> | 144:ef7eb2e8f9f7 | 2216 | } |
<> | 144:ef7eb2e8f9f7 | 2217 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2218 | |
<> | 144:ef7eb2e8f9f7 | 2219 | /* Disable TXE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2220 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2221 | |
<> | 144:ef7eb2e8f9f7 | 2222 | if(hspi->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2223 | { |
<> | 144:ef7eb2e8f9f7 | 2224 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2225 | } |
<> | 144:ef7eb2e8f9f7 | 2226 | } |
<> | 144:ef7eb2e8f9f7 | 2227 | } |
<> | 144:ef7eb2e8f9f7 | 2228 | |
<> | 144:ef7eb2e8f9f7 | 2229 | /** |
<> | 144:ef7eb2e8f9f7 | 2230 | * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2231 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2232 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2233 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2234 | */ |
<> | 144:ef7eb2e8f9f7 | 2235 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2236 | { |
<> | 144:ef7eb2e8f9f7 | 2237 | /* Receive data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2238 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2239 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2240 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2241 | |
<> | 144:ef7eb2e8f9f7 | 2242 | if(hspi->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2243 | { |
<> | 144:ef7eb2e8f9f7 | 2244 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2245 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2246 | { |
<> | 144:ef7eb2e8f9f7 | 2247 | hspi->RxISR = SPI_2linesRxISR_16BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2248 | return; |
<> | 144:ef7eb2e8f9f7 | 2249 | } |
<> | 144:ef7eb2e8f9f7 | 2250 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2251 | |
<> | 144:ef7eb2e8f9f7 | 2252 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2253 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 2254 | |
<> | 144:ef7eb2e8f9f7 | 2255 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2256 | { |
<> | 144:ef7eb2e8f9f7 | 2257 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2258 | } |
<> | 144:ef7eb2e8f9f7 | 2259 | } |
<> | 144:ef7eb2e8f9f7 | 2260 | } |
<> | 144:ef7eb2e8f9f7 | 2261 | |
<> | 144:ef7eb2e8f9f7 | 2262 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2263 | /** |
<> | 144:ef7eb2e8f9f7 | 2264 | * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2265 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2266 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2267 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2268 | */ |
<> | 144:ef7eb2e8f9f7 | 2269 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2270 | { |
<> | 144:ef7eb2e8f9f7 | 2271 | /* Receive data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2272 | __IO uint16_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 2273 | |
<> | 144:ef7eb2e8f9f7 | 2274 | /* Read data register to flush CRC */ |
<> | 144:ef7eb2e8f9f7 | 2275 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2276 | |
<> | 144:ef7eb2e8f9f7 | 2277 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2278 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2279 | |
<> | 144:ef7eb2e8f9f7 | 2280 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2281 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 2282 | |
<> | 144:ef7eb2e8f9f7 | 2283 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2284 | } |
<> | 144:ef7eb2e8f9f7 | 2285 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2286 | |
<> | 144:ef7eb2e8f9f7 | 2287 | /** |
<> | 144:ef7eb2e8f9f7 | 2288 | * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2289 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2290 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2291 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2292 | */ |
<> | 144:ef7eb2e8f9f7 | 2293 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2294 | { |
<> | 144:ef7eb2e8f9f7 | 2295 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2296 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 2297 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2298 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2299 | |
<> | 144:ef7eb2e8f9f7 | 2300 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2301 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2302 | { |
<> | 144:ef7eb2e8f9f7 | 2303 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2304 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2305 | { |
<> | 144:ef7eb2e8f9f7 | 2306 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2307 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2308 | return; |
<> | 144:ef7eb2e8f9f7 | 2309 | } |
<> | 144:ef7eb2e8f9f7 | 2310 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2311 | |
<> | 144:ef7eb2e8f9f7 | 2312 | /* Disable TXE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2313 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2314 | |
<> | 144:ef7eb2e8f9f7 | 2315 | if(hspi->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2316 | { |
<> | 144:ef7eb2e8f9f7 | 2317 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2318 | } |
<> | 144:ef7eb2e8f9f7 | 2319 | } |
<> | 144:ef7eb2e8f9f7 | 2320 | } |
<> | 144:ef7eb2e8f9f7 | 2321 | |
<> | 144:ef7eb2e8f9f7 | 2322 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2323 | /** |
<> | 144:ef7eb2e8f9f7 | 2324 | * @brief Manage the CRC 8-bit receive in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2325 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2326 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2327 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2328 | */ |
<> | 144:ef7eb2e8f9f7 | 2329 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2330 | { |
<> | 144:ef7eb2e8f9f7 | 2331 | __IO uint8_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 2332 | |
<> | 144:ef7eb2e8f9f7 | 2333 | /* Read data register to flush CRC */ |
<> | 144:ef7eb2e8f9f7 | 2334 | tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2335 | |
<> | 144:ef7eb2e8f9f7 | 2336 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2337 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2338 | |
<> | 144:ef7eb2e8f9f7 | 2339 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2340 | } |
<> | 144:ef7eb2e8f9f7 | 2341 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2342 | |
<> | 144:ef7eb2e8f9f7 | 2343 | /** |
<> | 144:ef7eb2e8f9f7 | 2344 | * @brief Manage the receive 8-bit in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2345 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2346 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2347 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2348 | */ |
<> | 144:ef7eb2e8f9f7 | 2349 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2350 | { |
<> | 144:ef7eb2e8f9f7 | 2351 | *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2352 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2353 | |
<> | 144:ef7eb2e8f9f7 | 2354 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2355 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2356 | if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 2357 | { |
<> | 144:ef7eb2e8f9f7 | 2358 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2359 | } |
<> | 144:ef7eb2e8f9f7 | 2360 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2361 | |
<> | 144:ef7eb2e8f9f7 | 2362 | if(hspi->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2363 | { |
<> | 144:ef7eb2e8f9f7 | 2364 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2365 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2366 | { |
<> | 144:ef7eb2e8f9f7 | 2367 | hspi->RxISR = SPI_RxISR_8BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2368 | return; |
<> | 144:ef7eb2e8f9f7 | 2369 | } |
<> | 144:ef7eb2e8f9f7 | 2370 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2371 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2372 | } |
<> | 144:ef7eb2e8f9f7 | 2373 | } |
<> | 144:ef7eb2e8f9f7 | 2374 | |
<> | 144:ef7eb2e8f9f7 | 2375 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2376 | /** |
<> | 144:ef7eb2e8f9f7 | 2377 | * @brief Manage the CRC 16-bit receive in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2378 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2379 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2380 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2381 | */ |
<> | 144:ef7eb2e8f9f7 | 2382 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2383 | { |
<> | 144:ef7eb2e8f9f7 | 2384 | __IO uint16_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 2385 | |
<> | 144:ef7eb2e8f9f7 | 2386 | /* Read data register to flush CRC */ |
<> | 144:ef7eb2e8f9f7 | 2387 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2388 | |
<> | 144:ef7eb2e8f9f7 | 2389 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2390 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2391 | |
<> | 144:ef7eb2e8f9f7 | 2392 | /* Disable RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2393 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2394 | |
<> | 144:ef7eb2e8f9f7 | 2395 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2396 | } |
<> | 144:ef7eb2e8f9f7 | 2397 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2398 | |
<> | 144:ef7eb2e8f9f7 | 2399 | /** |
<> | 144:ef7eb2e8f9f7 | 2400 | * @brief Manage the 16-bit receive in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2401 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2402 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2403 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2404 | */ |
<> | 144:ef7eb2e8f9f7 | 2405 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2406 | { |
<> | 144:ef7eb2e8f9f7 | 2407 | *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2408 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2409 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2410 | |
<> | 144:ef7eb2e8f9f7 | 2411 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2412 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2413 | if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 2414 | { |
<> | 144:ef7eb2e8f9f7 | 2415 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2416 | } |
<> | 144:ef7eb2e8f9f7 | 2417 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2418 | |
<> | 144:ef7eb2e8f9f7 | 2419 | if(hspi->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2420 | { |
<> | 144:ef7eb2e8f9f7 | 2421 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2422 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2423 | { |
<> | 144:ef7eb2e8f9f7 | 2424 | hspi->RxISR = SPI_RxISR_16BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2425 | return; |
<> | 144:ef7eb2e8f9f7 | 2426 | } |
<> | 144:ef7eb2e8f9f7 | 2427 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2428 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2429 | } |
<> | 144:ef7eb2e8f9f7 | 2430 | } |
<> | 144:ef7eb2e8f9f7 | 2431 | |
<> | 144:ef7eb2e8f9f7 | 2432 | /** |
<> | 144:ef7eb2e8f9f7 | 2433 | * @brief Handle the data 8-bit transmit in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2434 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2435 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2436 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2437 | */ |
<> | 144:ef7eb2e8f9f7 | 2438 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2439 | { |
<> | 144:ef7eb2e8f9f7 | 2440 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 2441 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2442 | |
<> | 144:ef7eb2e8f9f7 | 2443 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2444 | { |
<> | 144:ef7eb2e8f9f7 | 2445 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2446 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2447 | { |
<> | 144:ef7eb2e8f9f7 | 2448 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2449 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2450 | } |
<> | 144:ef7eb2e8f9f7 | 2451 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2452 | SPI_CloseTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2453 | } |
<> | 144:ef7eb2e8f9f7 | 2454 | } |
<> | 144:ef7eb2e8f9f7 | 2455 | |
<> | 144:ef7eb2e8f9f7 | 2456 | /** |
<> | 144:ef7eb2e8f9f7 | 2457 | * @brief Handle the data 16-bit transmit in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2458 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2459 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2460 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2461 | */ |
<> | 144:ef7eb2e8f9f7 | 2462 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2463 | { |
<> | 144:ef7eb2e8f9f7 | 2464 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2465 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 2466 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2467 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2468 | |
<> | 144:ef7eb2e8f9f7 | 2469 | if(hspi->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2470 | { |
<> | 144:ef7eb2e8f9f7 | 2471 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2472 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2473 | { |
<> | 144:ef7eb2e8f9f7 | 2474 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2475 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2476 | } |
<> | 144:ef7eb2e8f9f7 | 2477 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2478 | SPI_CloseTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2479 | } |
<> | 144:ef7eb2e8f9f7 | 2480 | } |
<> | 144:ef7eb2e8f9f7 | 2481 | |
<> | 144:ef7eb2e8f9f7 | 2482 | /** |
<> | 144:ef7eb2e8f9f7 | 2483 | * @brief Handle SPI Communication Timeout. |
<> | 144:ef7eb2e8f9f7 | 2484 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2485 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2486 | * @param Flag: SPI flag to check |
<> | 144:ef7eb2e8f9f7 | 2487 | * @param State: flag state to check |
<> | 144:ef7eb2e8f9f7 | 2488 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2489 | * @param Tickstart: tick start value |
<> | 144:ef7eb2e8f9f7 | 2490 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2491 | */ |
<> | 144:ef7eb2e8f9f7 | 2492 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 2493 | { |
<> | 144:ef7eb2e8f9f7 | 2494 | while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State) |
<> | 144:ef7eb2e8f9f7 | 2495 | { |
<> | 144:ef7eb2e8f9f7 | 2496 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 2497 | { |
<> | 144:ef7eb2e8f9f7 | 2498 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 2499 | { |
<> | 144:ef7eb2e8f9f7 | 2500 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
<> | 144:ef7eb2e8f9f7 | 2501 | on both master and slave sides in order to resynchronize the master |
<> | 144:ef7eb2e8f9f7 | 2502 | and slave for their respective CRC calculation */ |
<> | 144:ef7eb2e8f9f7 | 2503 | |
<> | 144:ef7eb2e8f9f7 | 2504 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
<> | 144:ef7eb2e8f9f7 | 2505 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2506 | |
<> | 144:ef7eb2e8f9f7 | 2507 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 2508 | { |
<> | 144:ef7eb2e8f9f7 | 2509 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 2510 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 2511 | } |
<> | 144:ef7eb2e8f9f7 | 2512 | |
<> | 144:ef7eb2e8f9f7 | 2513 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 2514 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2515 | { |
<> | 144:ef7eb2e8f9f7 | 2516 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 2517 | } |
<> | 144:ef7eb2e8f9f7 | 2518 | |
<> | 144:ef7eb2e8f9f7 | 2519 | hspi->State= HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2520 | |
<> | 144:ef7eb2e8f9f7 | 2521 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2522 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 2523 | |
<> | 144:ef7eb2e8f9f7 | 2524 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2525 | } |
<> | 144:ef7eb2e8f9f7 | 2526 | } |
<> | 144:ef7eb2e8f9f7 | 2527 | } |
<> | 144:ef7eb2e8f9f7 | 2528 | |
<> | 144:ef7eb2e8f9f7 | 2529 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2530 | } |
<> | 144:ef7eb2e8f9f7 | 2531 | /** |
<> | 144:ef7eb2e8f9f7 | 2532 | * @brief Handle to check BSY flag before start a new transaction. |
<> | 144:ef7eb2e8f9f7 | 2533 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2534 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2535 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2536 | * @param Tickstart: tick start value |
<> | 144:ef7eb2e8f9f7 | 2537 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2538 | */ |
<> | 144:ef7eb2e8f9f7 | 2539 | static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 2540 | { |
<> | 144:ef7eb2e8f9f7 | 2541 | /* Control the BSY flag */ |
<> | 144:ef7eb2e8f9f7 | 2542 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2543 | { |
<> | 144:ef7eb2e8f9f7 | 2544 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 2545 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2546 | } |
<> | 144:ef7eb2e8f9f7 | 2547 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2548 | } |
<> | 144:ef7eb2e8f9f7 | 2549 | |
<> | 144:ef7eb2e8f9f7 | 2550 | /** |
<> | 144:ef7eb2e8f9f7 | 2551 | * @brief Handle the end of the RXTX transaction. |
<> | 144:ef7eb2e8f9f7 | 2552 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2553 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2554 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2555 | */ |
<> | 144:ef7eb2e8f9f7 | 2556 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2557 | { |
<> | 144:ef7eb2e8f9f7 | 2558 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2559 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000); |
<> | 144:ef7eb2e8f9f7 | 2560 | /* Init tickstart for timeout managment*/ |
<> | 144:ef7eb2e8f9f7 | 2561 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2562 | |
<> | 144:ef7eb2e8f9f7 | 2563 | /* Disable ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2564 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); |
<> | 144:ef7eb2e8f9f7 | 2565 | |
<> | 144:ef7eb2e8f9f7 | 2566 | /* Wait until TXE flag is set */ |
<> | 144:ef7eb2e8f9f7 | 2567 | do |
<> | 144:ef7eb2e8f9f7 | 2568 | { |
<> | 144:ef7eb2e8f9f7 | 2569 | if(count-- == 0) |
<> | 144:ef7eb2e8f9f7 | 2570 | { |
<> | 144:ef7eb2e8f9f7 | 2571 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 2572 | break; |
<> | 144:ef7eb2e8f9f7 | 2573 | } |
<> | 144:ef7eb2e8f9f7 | 2574 | } |
<> | 144:ef7eb2e8f9f7 | 2575 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
<> | 144:ef7eb2e8f9f7 | 2576 | |
<> | 144:ef7eb2e8f9f7 | 2577 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2578 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2579 | { |
<> | 144:ef7eb2e8f9f7 | 2580 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 2581 | } |
<> | 144:ef7eb2e8f9f7 | 2582 | |
<> | 144:ef7eb2e8f9f7 | 2583 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 2584 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 2585 | { |
<> | 144:ef7eb2e8f9f7 | 2586 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2587 | } |
<> | 144:ef7eb2e8f9f7 | 2588 | |
<> | 144:ef7eb2e8f9f7 | 2589 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2590 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2591 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2592 | { |
<> | 144:ef7eb2e8f9f7 | 2593 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2594 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 2595 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2596 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2597 | } |
<> | 144:ef7eb2e8f9f7 | 2598 | else |
<> | 144:ef7eb2e8f9f7 | 2599 | { |
<> | 144:ef7eb2e8f9f7 | 2600 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2601 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2602 | { |
<> | 144:ef7eb2e8f9f7 | 2603 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 2604 | { |
<> | 144:ef7eb2e8f9f7 | 2605 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2606 | HAL_SPI_RxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2607 | } |
<> | 144:ef7eb2e8f9f7 | 2608 | else |
<> | 144:ef7eb2e8f9f7 | 2609 | { |
<> | 144:ef7eb2e8f9f7 | 2610 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2611 | HAL_SPI_TxRxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2612 | } |
<> | 144:ef7eb2e8f9f7 | 2613 | } |
<> | 144:ef7eb2e8f9f7 | 2614 | else |
<> | 144:ef7eb2e8f9f7 | 2615 | { |
<> | 144:ef7eb2e8f9f7 | 2616 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2617 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2618 | } |
<> | 144:ef7eb2e8f9f7 | 2619 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2620 | } |
<> | 144:ef7eb2e8f9f7 | 2621 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2622 | } |
<> | 144:ef7eb2e8f9f7 | 2623 | |
<> | 144:ef7eb2e8f9f7 | 2624 | /** |
<> | 144:ef7eb2e8f9f7 | 2625 | * @brief Handle the end of the RX transaction. |
<> | 144:ef7eb2e8f9f7 | 2626 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2627 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2628 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2629 | */ |
<> | 144:ef7eb2e8f9f7 | 2630 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2631 | { |
<> | 144:ef7eb2e8f9f7 | 2632 | /* Disable RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2633 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2634 | |
<> | 144:ef7eb2e8f9f7 | 2635 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2636 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 2637 | { |
<> | 144:ef7eb2e8f9f7 | 2638 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 2639 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 2640 | } |
<> | 144:ef7eb2e8f9f7 | 2641 | |
<> | 144:ef7eb2e8f9f7 | 2642 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 2643 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 2644 | { |
<> | 144:ef7eb2e8f9f7 | 2645 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2646 | } |
<> | 144:ef7eb2e8f9f7 | 2647 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2648 | |
<> | 144:ef7eb2e8f9f7 | 2649 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2650 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2651 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2652 | { |
<> | 144:ef7eb2e8f9f7 | 2653 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
<> | 144:ef7eb2e8f9f7 | 2654 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2655 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2656 | } |
<> | 144:ef7eb2e8f9f7 | 2657 | else |
<> | 144:ef7eb2e8f9f7 | 2658 | { |
<> | 144:ef7eb2e8f9f7 | 2659 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2660 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2661 | { |
<> | 144:ef7eb2e8f9f7 | 2662 | HAL_SPI_RxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2663 | } |
<> | 144:ef7eb2e8f9f7 | 2664 | else |
<> | 144:ef7eb2e8f9f7 | 2665 | { |
<> | 144:ef7eb2e8f9f7 | 2666 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2667 | } |
<> | 144:ef7eb2e8f9f7 | 2668 | #if (USE_SPI_CRC != 0U) |
<> | 144:ef7eb2e8f9f7 | 2669 | } |
<> | 144:ef7eb2e8f9f7 | 2670 | #endif /* USE_SPI_CRC */ |
<> | 144:ef7eb2e8f9f7 | 2671 | } |
<> | 144:ef7eb2e8f9f7 | 2672 | |
<> | 144:ef7eb2e8f9f7 | 2673 | /** |
<> | 144:ef7eb2e8f9f7 | 2674 | * @brief Handle the end of the TX transaction. |
<> | 144:ef7eb2e8f9f7 | 2675 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2676 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2677 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2678 | */ |
<> | 144:ef7eb2e8f9f7 | 2679 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2680 | { |
<> | 144:ef7eb2e8f9f7 | 2681 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2682 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000); |
<> | 144:ef7eb2e8f9f7 | 2683 | |
<> | 144:ef7eb2e8f9f7 | 2684 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 2685 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2686 | |
<> | 144:ef7eb2e8f9f7 | 2687 | /* Wait until TXE flag is set */ |
<> | 144:ef7eb2e8f9f7 | 2688 | do |
<> | 144:ef7eb2e8f9f7 | 2689 | { |
<> | 144:ef7eb2e8f9f7 | 2690 | if(count-- == 0) |
<> | 144:ef7eb2e8f9f7 | 2691 | { |
<> | 144:ef7eb2e8f9f7 | 2692 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 2693 | break; |
<> | 144:ef7eb2e8f9f7 | 2694 | } |
<> | 144:ef7eb2e8f9f7 | 2695 | } |
<> | 144:ef7eb2e8f9f7 | 2696 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
<> | 144:ef7eb2e8f9f7 | 2697 | |
<> | 144:ef7eb2e8f9f7 | 2698 | /* Disable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2699 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2700 | |
<> | 144:ef7eb2e8f9f7 | 2701 | /* Check Busy flag */ |
<> | 144:ef7eb2e8f9f7 | 2702 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2703 | { |
<> | 144:ef7eb2e8f9f7 | 2704 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
<> | 144:ef7eb2e8f9f7 | 2705 | } |
<> | 144:ef7eb2e8f9f7 | 2706 | |
<> | 144:ef7eb2e8f9f7 | 2707 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 2708 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 2709 | { |
<> | 144:ef7eb2e8f9f7 | 2710 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2711 | } |
<> | 144:ef7eb2e8f9f7 | 2712 | |
<> | 144:ef7eb2e8f9f7 | 2713 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2714 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2715 | { |
<> | 144:ef7eb2e8f9f7 | 2716 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2717 | } |
<> | 144:ef7eb2e8f9f7 | 2718 | else |
<> | 144:ef7eb2e8f9f7 | 2719 | { |
<> | 144:ef7eb2e8f9f7 | 2720 | HAL_SPI_TxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2721 | } |
<> | 144:ef7eb2e8f9f7 | 2722 | } |
<> | 144:ef7eb2e8f9f7 | 2723 | |
<> | 144:ef7eb2e8f9f7 | 2724 | /** |
<> | 144:ef7eb2e8f9f7 | 2725 | * @} |
<> | 144:ef7eb2e8f9f7 | 2726 | */ |
<> | 144:ef7eb2e8f9f7 | 2727 | |
<> | 144:ef7eb2e8f9f7 | 2728 | #endif /* HAL_SPI_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 2729 | |
<> | 144:ef7eb2e8f9f7 | 2730 | /** |
<> | 144:ef7eb2e8f9f7 | 2731 | * @} |
<> | 144:ef7eb2e8f9f7 | 2732 | */ |
<> | 144:ef7eb2e8f9f7 | 2733 | |
<> | 144:ef7eb2e8f9f7 | 2734 | /** |
<> | 144:ef7eb2e8f9f7 | 2735 | * @} |
<> | 144:ef7eb2e8f9f7 | 2736 | */ |
<> | 144:ef7eb2e8f9f7 | 2737 | |
<> | 144:ef7eb2e8f9f7 | 2738 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |