mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
56:05912f50f004 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f0xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.3.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f0xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
<> 144:ef7eb2e8f9f7 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
<> 144:ef7eb2e8f9f7 25 * configure the system clock before to branch to main program.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * 3. This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 28 *=============================================================================
<> 144:ef7eb2e8f9f7 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
<> 144:ef7eb2e8f9f7 30 * | (external 8 MHz clock) | (internal 48 MHz)
<> 144:ef7eb2e8f9f7 31 * | 2- PLL_HSE_XTAL |
<> 144:ef7eb2e8f9f7 32 * | (external 8 MHz xtal) |
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * SYSCLK(MHz) | 48 | 48
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * AHBCLK (MHz) | 48 | 48
<> 144:ef7eb2e8f9f7 37 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * APB1CLK (MHz) | 48 | 48
<> 144:ef7eb2e8f9f7 39 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 * USB capable (48 MHz precise clock) | YES | YES
<> 144:ef7eb2e8f9f7 41 *=============================================================================
<> 144:ef7eb2e8f9f7 42 ******************************************************************************
<> 144:ef7eb2e8f9f7 43 * @attention
<> 144:ef7eb2e8f9f7 44 *
<> 144:ef7eb2e8f9f7 45 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 48 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 49 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 50 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 53 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 55 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 56 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /** @addtogroup stm32f0xx_system
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** @addtogroup STM32F0xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #include "stm32f0xx.h"
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /**
<> 144:ef7eb2e8f9f7 87 * @}
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /**
<> 144:ef7eb2e8f9f7 95 * @}
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @addtogroup STM32F0xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
<> 144:ef7eb2e8f9f7 103 This value can be provided and adapted by the user application. */
<> 144:ef7eb2e8f9f7 104 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
<> 144:ef7eb2e8f9f7 108 This value can be provided and adapted by the user application. */
<> 144:ef7eb2e8f9f7 109 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #if !defined (HSI48_VALUE)
<> 144:ef7eb2e8f9f7 112 #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
<> 144:ef7eb2e8f9f7 113 This value can be provided and adapted by the user application. */
<> 144:ef7eb2e8f9f7 114 #endif /* HSI48_VALUE */
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @addtogroup STM32F0xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 124 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
<> 144:ef7eb2e8f9f7 125 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F0xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 135 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 136 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 137 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 138 Note: If you use this function to configure the system clock there is no need to
<> 144:ef7eb2e8f9f7 139 call the 2 first functions listed above, since SystemCoreClock variable is
<> 144:ef7eb2e8f9f7 140 updated automatically.
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 uint32_t SystemCoreClock = 48000000;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
<> 144:ef7eb2e8f9f7 145 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @}
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 156 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 157 #endif
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @}
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @addtogroup STM32F0xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 172 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
<> 144:ef7eb2e8f9f7 173 * @param None
<> 144:ef7eb2e8f9f7 174 * @retval None
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 void SystemInit(void)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 179 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 180 RCC->CR |= (uint32_t)0x00000001U;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 #if defined (STM32F051x8) || defined (STM32F058x8)
<> 144:ef7eb2e8f9f7 183 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
<> 144:ef7eb2e8f9f7 184 RCC->CFGR &= (uint32_t)0xF8FFB80CU;
<> 144:ef7eb2e8f9f7 185 #else
<> 144:ef7eb2e8f9f7 186 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
<> 144:ef7eb2e8f9f7 187 RCC->CFGR &= (uint32_t)0x08FFB80CU;
<> 144:ef7eb2e8f9f7 188 #endif /* STM32F051x8 or STM32F058x8 */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 191 RCC->CR &= (uint32_t)0xFEF6FFFFU;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 194 RCC->CR &= (uint32_t)0xFFFBFFFFU;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
<> 144:ef7eb2e8f9f7 197 RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Reset PREDIV[3:0] bits */
<> 144:ef7eb2e8f9f7 200 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #if defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 203 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
<> 144:ef7eb2e8f9f7 204 RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
<> 144:ef7eb2e8f9f7 205 #elif defined (STM32F071xB)
<> 144:ef7eb2e8f9f7 206 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
<> 144:ef7eb2e8f9f7 207 RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
<> 144:ef7eb2e8f9f7 208 #elif defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 209 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
<> 144:ef7eb2e8f9f7 210 RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
<> 144:ef7eb2e8f9f7 211 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 212 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
<> 144:ef7eb2e8f9f7 213 RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
<> 144:ef7eb2e8f9f7 214 #elif defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 215 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
<> 144:ef7eb2e8f9f7 216 RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
<> 144:ef7eb2e8f9f7 217 #elif defined (STM32F042x6) || defined (STM32F048xx)
<> 144:ef7eb2e8f9f7 218 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
<> 144:ef7eb2e8f9f7 219 RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
<> 144:ef7eb2e8f9f7 220 #elif defined (STM32F070x6) || defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 221 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
<> 144:ef7eb2e8f9f7 222 RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
<> 144:ef7eb2e8f9f7 223 /* Set default USB clock to PLLCLK, since there is no HSI48 */
<> 144:ef7eb2e8f9f7 224 RCC->CFGR3 |= (uint32_t)0x00000080U;
<> 144:ef7eb2e8f9f7 225 #else
<> 144:ef7eb2e8f9f7 226 #warning "No target selected"
<> 144:ef7eb2e8f9f7 227 #endif
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Reset HSI14 bit */
<> 144:ef7eb2e8f9f7 230 RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 233 RCC->CIR = 0x00000000U;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
<> 144:ef7eb2e8f9f7 236 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Configure the Cube driver */
<> 144:ef7eb2e8f9f7 239 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
<> 144:ef7eb2e8f9f7 240 HAL_Init();
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Configure the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 243 AHB/APBx prescalers and Flash settings */
<> 144:ef7eb2e8f9f7 244 SetSysClock();
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 250 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 251 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 252 * other parameters.
<> 144:ef7eb2e8f9f7 253 *
<> 144:ef7eb2e8f9f7 254 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 255 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 256 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 259 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 260 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 261 *
<> 144:ef7eb2e8f9f7 262 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 265 *
<> 144:ef7eb2e8f9f7 266 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 267 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 268 *
<> 144:ef7eb2e8f9f7 269 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 270 * 8 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 271 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 274 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 275 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 276 * have wrong result.
<> 144:ef7eb2e8f9f7 277 *
<> 144:ef7eb2e8f9f7 278 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 279 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 280 *
<> 144:ef7eb2e8f9f7 281 * @param None
<> 144:ef7eb2e8f9f7 282 * @retval None
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284 void SystemCoreClockUpdate (void)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 289 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 switch (tmp)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 294 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 295 break;
<> 144:ef7eb2e8f9f7 296 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 297 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 298 break;
<> 144:ef7eb2e8f9f7 299 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 300 /* Get PLL clock source and multiplication factor ----------------------*/
<> 144:ef7eb2e8f9f7 301 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 144:ef7eb2e8f9f7 302 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
<> 144:ef7eb2e8f9f7 303 pllmull = ( pllmull >> 18) + 2;
<> 144:ef7eb2e8f9f7 304 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 309 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 312 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 315 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 318 else
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
<> 144:ef7eb2e8f9f7 321 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
<> 144:ef7eb2e8f9f7 322 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 323 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 324 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 325 #else
<> 144:ef7eb2e8f9f7 326 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 327 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
<> 144:ef7eb2e8f9f7 328 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
<> 144:ef7eb2e8f9f7 329 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
<> 144:ef7eb2e8f9f7 330 STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332 break;
<> 144:ef7eb2e8f9f7 333 default: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 334 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 335 break;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337 /* Compute HCLK clock frequency ----------------*/
<> 144:ef7eb2e8f9f7 338 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 339 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 340 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 341 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 346 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 347 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 348 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 349 * @param None
<> 144:ef7eb2e8f9f7 350 * @retval None
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 355 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 356 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 357 #endif
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 360 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 361 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 362 #endif
<> 144:ef7eb2e8f9f7 363 {
<> 144:ef7eb2e8f9f7 364 /* 3- If fail start with HSI clock */
<> 144:ef7eb2e8f9f7 365 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 while(1)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 // Output clock on MCO pin(PA8) for debugging purpose
<> 144:ef7eb2e8f9f7 376 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 380 /******************************************************************************/
<> 144:ef7eb2e8f9f7 381 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 382 /******************************************************************************/
<> 144:ef7eb2e8f9f7 383 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
<> 144:ef7eb2e8f9f7 386 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
<> 144:ef7eb2e8f9f7 387 //Select HSI as system clock source to allow modification of the PLL configuration
<> 144:ef7eb2e8f9f7 388 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
<> 144:ef7eb2e8f9f7 389 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
<> 144:ef7eb2e8f9f7 390 if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 return 0; // FAIL
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 // Select HSE oscillator as PLL source
<> 144:ef7eb2e8f9f7 397 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 398 if (bypass == 0) {
<> 144:ef7eb2e8f9f7 399 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
<> 144:ef7eb2e8f9f7 400 } else {
<> 144:ef7eb2e8f9f7 401 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 404 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 405 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
<> 144:ef7eb2e8f9f7 406 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
<> 144:ef7eb2e8f9f7 407 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
<> 144:ef7eb2e8f9f7 408 return 0; // FAIL
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
<> 144:ef7eb2e8f9f7 412 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
<> 144:ef7eb2e8f9f7 413 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
<> 144:ef7eb2e8f9f7 414 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
<> 144:ef7eb2e8f9f7 415 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
<> 144:ef7eb2e8f9f7 416 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
<> 144:ef7eb2e8f9f7 417 return 0; // FAIL
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 return 1; // OK
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 #endif
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /******************************************************************************/
<> 144:ef7eb2e8f9f7 427 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 428 /******************************************************************************/
<> 144:ef7eb2e8f9f7 429 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 432 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
<> 144:ef7eb2e8f9f7 435 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
<> 144:ef7eb2e8f9f7 436 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 437 RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 438 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 439 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
<> 144:ef7eb2e8f9f7 440 RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 441 RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
<> 144:ef7eb2e8f9f7 442 RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 443 RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 444 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 445 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
<> 144:ef7eb2e8f9f7 446 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
<> 144:ef7eb2e8f9f7 447 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
<> 144:ef7eb2e8f9f7 448 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
<> 144:ef7eb2e8f9f7 449 return 0; // FAIL
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
<> 144:ef7eb2e8f9f7 453 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
<> 144:ef7eb2e8f9f7 454 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
<> 144:ef7eb2e8f9f7 455 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
<> 144:ef7eb2e8f9f7 456 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
<> 144:ef7eb2e8f9f7 457 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
<> 144:ef7eb2e8f9f7 458 return 0; // FAIL
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 return 1; // OK
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Used for the different timeouts in the HAL */
<> 144:ef7eb2e8f9f7 467 void SysTick_Handler(void)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 HAL_IncTick();
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @}
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 485