mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

hal/spi_api.h@181:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
181:57724642e740
Parent:
170:19eb464bc2be
Child:
184:08ed48f1de7f
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1
<> 149:156823d33999 2 /** \addtogroup hal */
<> 149:156823d33999 3 /** @{*/
<> 144:ef7eb2e8f9f7 4 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 5 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 8 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 9 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 14 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 16 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 17 * limitations under the License.
<> 144:ef7eb2e8f9f7 18 */
<> 144:ef7eb2e8f9f7 19 #ifndef MBED_SPI_API_H
<> 144:ef7eb2e8f9f7 20 #define MBED_SPI_API_H
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #include "device.h"
<> 149:156823d33999 23 #include "hal/dma_api.h"
<> 149:156823d33999 24 #include "hal/buffer.h"
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #define SPI_EVENT_ERROR (1 << 1)
<> 144:ef7eb2e8f9f7 29 #define SPI_EVENT_COMPLETE (1 << 2)
<> 144:ef7eb2e8f9f7 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
<> 144:ef7eb2e8f9f7 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #define SPI_FILL_WORD (0xFFFF)
Kojto 170:19eb464bc2be 36 #define SPI_FILL_CHAR (0xFF)
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 39 /** Asynch SPI HAL structure
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41 typedef struct {
<> 144:ef7eb2e8f9f7 42 struct spi_s spi; /**< Target specific SPI structure */
<> 144:ef7eb2e8f9f7 43 struct buffer_s tx_buff; /**< Tx buffer */
<> 144:ef7eb2e8f9f7 44 struct buffer_s rx_buff; /**< Rx buffer */
<> 144:ef7eb2e8f9f7 45 } spi_t;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #else
<> 144:ef7eb2e8f9f7 48 /** Non-asynch SPI HAL structure
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50 typedef struct spi_s spi_t;
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #endif
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 55 extern "C" {
<> 144:ef7eb2e8f9f7 56 #endif
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /**
<> 144:ef7eb2e8f9f7 59 * \defgroup hal_GeneralSPI SPI Configuration Functions
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** Initialize the SPI peripheral
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
<> 144:ef7eb2e8f9f7 66 * @param[out] obj The SPI object to initialize
<> 144:ef7eb2e8f9f7 67 * @param[in] mosi The pin to use for MOSI
<> 144:ef7eb2e8f9f7 68 * @param[in] miso The pin to use for MISO
<> 144:ef7eb2e8f9f7 69 * @param[in] sclk The pin to use for SCLK
<> 144:ef7eb2e8f9f7 70 * @param[in] ssel The pin to use for SSEL
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** Release a SPI object
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * TODO: spi_free is currently unimplemented
<> 144:ef7eb2e8f9f7 77 * This will require reference counting at the C++ level to be safe
<> 144:ef7eb2e8f9f7 78 *
<> 144:ef7eb2e8f9f7 79 * Return the pins owned by the SPI object to their reset state
<> 144:ef7eb2e8f9f7 80 * Disable the SPI peripheral
<> 144:ef7eb2e8f9f7 81 * Disable the SPI clock
<> 144:ef7eb2e8f9f7 82 * @param[in] obj The SPI object to deinitialize
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 void spi_free(spi_t *obj);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** Configure the SPI format
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
<> 144:ef7eb2e8f9f7 89 * The default bit order is MSB.
<> 144:ef7eb2e8f9f7 90 * @param[in,out] obj The SPI object to configure
<> 144:ef7eb2e8f9f7 91 * @param[in] bits The number of bits per frame
<> 144:ef7eb2e8f9f7 92 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
<> 144:ef7eb2e8f9f7 93 * @param[in] slave Zero for master mode or non-zero for slave mode
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 void spi_format(spi_t *obj, int bits, int mode, int slave);
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** Set the SPI baud rate
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
<> 144:ef7eb2e8f9f7 100 * Configures the SPI peripheral's baud rate
<> 144:ef7eb2e8f9f7 101 * @param[in,out] obj The SPI object to configure
<> 144:ef7eb2e8f9f7 102 * @param[in] hz The baud rate in Hz
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 void spi_frequency(spi_t *obj, int hz);
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**@}*/
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** Write a byte out in master mode and receive a value
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * @param[in] obj The SPI peripheral to use for sending
<> 144:ef7eb2e8f9f7 115 * @param[in] value The value to send
<> 144:ef7eb2e8f9f7 116 * @return Returns the value received during send
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 int spi_master_write(spi_t *obj, int value);
<> 144:ef7eb2e8f9f7 119
AnnaBridge 167:e84263d55307 120 /** Write a block out in master mode and receive a value
AnnaBridge 167:e84263d55307 121 *
AnnaBridge 167:e84263d55307 122 * The total number of bytes sent and recieved will be the maximum of
AnnaBridge 167:e84263d55307 123 * tx_length and rx_length. The bytes written will be padded with the
AnnaBridge 167:e84263d55307 124 * value 0xff.
AnnaBridge 167:e84263d55307 125 *
Kojto 170:19eb464bc2be 126 * @param[in] obj The SPI peripheral to use for sending
Kojto 170:19eb464bc2be 127 * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
Kojto 170:19eb464bc2be 128 * @param[in] tx_length Number of bytes to write, may be zero
Kojto 170:19eb464bc2be 129 * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
Kojto 170:19eb464bc2be 130 * @param[in] rx_length Number of bytes to read, may be zero
Kojto 170:19eb464bc2be 131 * @param[in] write_fill Default data transmitted while performing a read
AnnaBridge 167:e84263d55307 132 * @returns
AnnaBridge 167:e84263d55307 133 * The number of bytes written and read from the device. This is
AnnaBridge 167:e84263d55307 134 * maximum of tx_length and rx_length.
AnnaBridge 167:e84263d55307 135 */
Kojto 170:19eb464bc2be 136 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
AnnaBridge 167:e84263d55307 137
<> 144:ef7eb2e8f9f7 138 /** Check if a value is available to read
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 141 * @return non-zero if a value is available
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 int spi_slave_receive(spi_t *obj);
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** Get a received value out of the SPI receive buffer in slave mode
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 * Blocks until a value is available
<> 144:ef7eb2e8f9f7 148 * @param[in] obj The SPI peripheral to read
<> 144:ef7eb2e8f9f7 149 * @return The value received
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 int spi_slave_read(spi_t *obj);
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** Write a value to the SPI peripheral in slave mode
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 * Blocks until the SPI peripheral can be written to
<> 144:ef7eb2e8f9f7 156 * @param[in] obj The SPI peripheral to write
<> 144:ef7eb2e8f9f7 157 * @param[in] value The value to write
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 void spi_slave_write(spi_t *obj, int value);
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** Checks if the specified SPI peripheral is in use
<> 144:ef7eb2e8f9f7 162 *
<> 144:ef7eb2e8f9f7 163 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 164 * @return non-zero if the peripheral is currently transmitting
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 int spi_busy(spi_t *obj);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /** Get the module number
<> 144:ef7eb2e8f9f7 169 *
<> 144:ef7eb2e8f9f7 170 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 171 * @return The module number
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 uint8_t spi_get_module(spi_t *obj);
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /**@}*/
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
<> 144:ef7eb2e8f9f7 184 *
<> 144:ef7eb2e8f9f7 185 * @param[in] obj The SPI object that holds the transfer information
<> 144:ef7eb2e8f9f7 186 * @param[in] tx The transmit buffer
<> 144:ef7eb2e8f9f7 187 * @param[in] tx_length The number of bytes to transmit
<> 144:ef7eb2e8f9f7 188 * @param[in] rx The receive buffer
<> 144:ef7eb2e8f9f7 189 * @param[in] rx_length The number of bytes to receive
<> 144:ef7eb2e8f9f7 190 * @param[in] bit_width The bit width of buffer words
<> 144:ef7eb2e8f9f7 191 * @param[in] event The logical OR of events to be registered
<> 144:ef7eb2e8f9f7 192 * @param[in] handler SPI interrupt handler
<> 144:ef7eb2e8f9f7 193 * @param[in] hint A suggestion for how to use DMA with this transfer
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** The asynchronous IRQ handler
<> 144:ef7eb2e8f9f7 198 *
<> 144:ef7eb2e8f9f7 199 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
<> 144:ef7eb2e8f9f7 200 * conditions, such as buffer overflows or transfer complete.
<> 144:ef7eb2e8f9f7 201 * @param[in] obj The SPI object that holds the transfer information
<> 144:ef7eb2e8f9f7 202 * @return Event flags if a transfer termination condition was met; otherwise 0.
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 uint32_t spi_irq_handler_asynch(spi_t *obj);
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** Attempts to determine if the SPI peripheral is already in use
<> 144:ef7eb2e8f9f7 207 *
<> 144:ef7eb2e8f9f7 208 * If a temporary DMA channel has been allocated, peripheral is in use.
<> 144:ef7eb2e8f9f7 209 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
<> 144:ef7eb2e8f9f7 210 * channel were allocated.
<> 144:ef7eb2e8f9f7 211 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
<> 144:ef7eb2e8f9f7 212 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
<> 144:ef7eb2e8f9f7 213 * there are any bytes in the FIFOs.
<> 144:ef7eb2e8f9f7 214 * @param[in] obj The SPI object to check for activity
<> 144:ef7eb2e8f9f7 215 * @return Non-zero if the SPI port is active or zero if it is not.
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217 uint8_t spi_active(spi_t *obj);
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /** Abort an SPI transfer
<> 144:ef7eb2e8f9f7 220 *
<> 144:ef7eb2e8f9f7 221 * @param obj The SPI peripheral to stop
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223 void spi_abort_asynch(spi_t *obj);
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #endif
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**@}*/
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232 #endif // __cplusplus
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #endif // SPI_DEVICE
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 #endif // MBED_SPI_API_H
<> 149:156823d33999 237
<> 149:156823d33999 238 /** @}*/