NXP LPC1768 Ethernet driver for lwip and CMSIS-RTOS

Dependents:   EthernetInterface EthernetInterface EthernetInterface_RSF EthernetInterface ... more

Legacy Networking Libraries

This is an mbed 2 networking library. For mbed 5, the networking libraries have been revised to better support additional network stacks and thread safety here.

This library is based on the code of the NXP LPC port of the Lightweight TCP/IP Stack

Copyright(C) 2011, NXP Semiconductor
All rights reserved.

Software that is described herein is for illustrative purposes only
which provides customers with programming information regarding the
products. This software is supplied "AS IS" without any warranties.
NXP Semiconductors assumes no responsibility or liability for the
use of the software, conveys no license or title under any patent,
copyright, or mask work right to the product. NXP Semiconductors
reserves the right to make changes in the software without
notification. NXP Semiconductors also make no representation or
warranty that such application will be suitable for the specified
use without further testing or modification.
Committer:
mbed_official
Date:
Thu May 26 09:00:26 2016 +0100
Revision:
33:9de8bd8ca1c8
Parent:
10:ab9330955226
Synchronized with git revision 745ebbf4557f0f3964f73063c1d88ddbcda0ed22

Full URL: https://github.com/mbedmicro/mbed/commit/745ebbf4557f0f3964f73063c1d88ddbcda0ed22/

Synch - fix lwip-eth path

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 10:ab9330955226 1 /**********************************************************************
mbed_official 10:ab9330955226 2 * $Id$ lpc_phy_dp83848.c 2011-11-20
mbed_official 10:ab9330955226 3 *//**
mbed_official 10:ab9330955226 4 * @file lpc_phy_dp83848.c
mbed_official 10:ab9330955226 5 * @brief DP83848C PHY status and control.
mbed_official 10:ab9330955226 6 * @version 1.0
mbed_official 10:ab9330955226 7 * @date 20 Nov. 2011
mbed_official 10:ab9330955226 8 * @author NXP MCU SW Application Team
mbed_official 10:ab9330955226 9 *
mbed_official 10:ab9330955226 10 * Copyright(C) 2011, NXP Semiconductor
mbed_official 10:ab9330955226 11 * All rights reserved.
mbed_official 10:ab9330955226 12 *
mbed_official 10:ab9330955226 13 ***********************************************************************
mbed_official 10:ab9330955226 14 * Software that is described herein is for illustrative purposes only
mbed_official 10:ab9330955226 15 * which provides customers with programming information regarding the
mbed_official 10:ab9330955226 16 * products. This software is supplied "AS IS" without any warranties.
mbed_official 10:ab9330955226 17 * NXP Semiconductors assumes no responsibility or liability for the
mbed_official 10:ab9330955226 18 * use of the software, conveys no license or title under any patent,
mbed_official 10:ab9330955226 19 * copyright, or mask work right to the product. NXP Semiconductors
mbed_official 10:ab9330955226 20 * reserves the right to make changes in the software without
mbed_official 10:ab9330955226 21 * notification. NXP Semiconductors also make no representation or
mbed_official 10:ab9330955226 22 * warranty that such application will be suitable for the specified
mbed_official 10:ab9330955226 23 * use without further testing or modification.
mbed_official 10:ab9330955226 24 **********************************************************************/
mbed_official 10:ab9330955226 25
mbed_official 10:ab9330955226 26 #include "lwip/opt.h"
mbed_official 10:ab9330955226 27 #include "lwip/err.h"
mbed_official 10:ab9330955226 28 #include "lwip/tcpip.h"
mbed_official 10:ab9330955226 29 #include "lwip/snmp.h"
mbed_official 10:ab9330955226 30 #include "lpc_emac_config.h"
mbed_official 10:ab9330955226 31 #include "lpc_phy.h"
mbed_official 10:ab9330955226 32 #include "lpc17xx_emac.h"
mbed_official 10:ab9330955226 33
mbed_official 10:ab9330955226 34 /** @defgroup dp83848_phy PHY status and control for the DP83848.
mbed_official 10:ab9330955226 35 * @ingroup lwip_phy
mbed_official 10:ab9330955226 36 *
mbed_official 10:ab9330955226 37 * Various functions for controlling and monitoring the status of the
mbed_official 10:ab9330955226 38 * DP83848 PHY. In polled (standalone) systems, the PHY state must be
mbed_official 10:ab9330955226 39 * monitored as part of the application. In a threaded (RTOS) system,
mbed_official 10:ab9330955226 40 * the PHY state is monitored by the PHY handler thread. The MAC
mbed_official 10:ab9330955226 41 * driver will not transmit unless the PHY link is active.
mbed_official 10:ab9330955226 42 * @{
mbed_official 10:ab9330955226 43 */
mbed_official 10:ab9330955226 44
mbed_official 10:ab9330955226 45 /** \brief DP83848 PHY register offsets */
mbed_official 10:ab9330955226 46 #define DP8_BMCR_REG 0x0 /**< Basic Mode Control Register */
mbed_official 10:ab9330955226 47 #define DP8_BMSR_REG 0x1 /**< Basic Mode Status Reg */
mbed_official 10:ab9330955226 48 #define DP8_IDR1_REG 0x2 /**< Basic Mode Status Reg */
mbed_official 10:ab9330955226 49 #define DP8_IDR2_REG 0x3 /**< Basic Mode Status Reg */
mbed_official 10:ab9330955226 50 #define DP8_ANADV_REG 0x4 /**< Auto_Neg Advt Reg */
mbed_official 10:ab9330955226 51 #define DP8_ANLPA_REG 0x5 /**< Auto_neg Link Partner Ability Reg */
mbed_official 10:ab9330955226 52 #define DP8_ANEEXP_REG 0x6 /**< Auto-neg Expansion Reg */
mbed_official 10:ab9330955226 53 #define DP8_PHY_STAT_REG 0x10 /**< PHY Status Register */
mbed_official 10:ab9330955226 54 #define DP8_PHY_INT_CTL_REG 0x11 /**< PHY Interrupt Control Register */
mbed_official 10:ab9330955226 55 #define DP8_PHY_RBR_REG 0x17 /**< PHY RMII and Bypass Register */
mbed_official 10:ab9330955226 56 #define DP8_PHY_STS_REG 0x19 /**< PHY Status Register */
mbed_official 10:ab9330955226 57
mbed_official 10:ab9330955226 58 #define DP8_PHY_SCSR_REG 0x1f /**< PHY Special Control/Status Register (LAN8720) */
mbed_official 10:ab9330955226 59
mbed_official 10:ab9330955226 60 /** \brief DP83848 Control register definitions */
mbed_official 10:ab9330955226 61 #define DP8_RESET (1 << 15) /**< 1= S/W Reset */
mbed_official 10:ab9330955226 62 #define DP8_LOOPBACK (1 << 14) /**< 1=loopback Enabled */
mbed_official 10:ab9330955226 63 #define DP8_SPEED_SELECT (1 << 13) /**< 1=Select 100MBps */
mbed_official 10:ab9330955226 64 #define DP8_AUTONEG (1 << 12) /**< 1=Enable auto-negotiation */
mbed_official 10:ab9330955226 65 #define DP8_POWER_DOWN (1 << 11) /**< 1=Power down PHY */
mbed_official 10:ab9330955226 66 #define DP8_ISOLATE (1 << 10) /**< 1=Isolate PHY */
mbed_official 10:ab9330955226 67 #define DP8_RESTART_AUTONEG (1 << 9) /**< 1=Restart auto-negoatiation */
mbed_official 10:ab9330955226 68 #define DP8_DUPLEX_MODE (1 << 8) /**< 1=Full duplex mode */
mbed_official 10:ab9330955226 69 #define DP8_COLLISION_TEST (1 << 7) /**< 1=Perform collsion test */
mbed_official 10:ab9330955226 70
mbed_official 10:ab9330955226 71 /** \brief DP83848 Status register definitions */
mbed_official 10:ab9330955226 72 #define DP8_100BASE_T4 (1 << 15) /**< T4 mode */
mbed_official 10:ab9330955226 73 #define DP8_100BASE_TX_FD (1 << 14) /**< 100MBps full duplex */
mbed_official 10:ab9330955226 74 #define DP8_100BASE_TX_HD (1 << 13) /**< 100MBps half duplex */
mbed_official 10:ab9330955226 75 #define DP8_10BASE_T_FD (1 << 12) /**< 100Bps full duplex */
mbed_official 10:ab9330955226 76 #define DP8_10BASE_T_HD (1 << 11) /**< 10MBps half duplex */
mbed_official 10:ab9330955226 77 #define DP8_MF_PREAMB_SUPPR (1 << 6) /**< Preamble suppress */
mbed_official 10:ab9330955226 78 #define DP8_AUTONEG_COMP (1 << 5) /**< Auto-negotation complete */
mbed_official 10:ab9330955226 79 #define DP8_RMT_FAULT (1 << 4) /**< Fault */
mbed_official 10:ab9330955226 80 #define DP8_AUTONEG_ABILITY (1 << 3) /**< Auto-negotation supported */
mbed_official 10:ab9330955226 81 #define DP8_LINK_STATUS (1 << 2) /**< 1=Link active */
mbed_official 10:ab9330955226 82 #define DP8_JABBER_DETECT (1 << 1) /**< Jabber detect */
mbed_official 10:ab9330955226 83 #define DP8_EXTEND_CAPAB (1 << 0) /**< Supports extended capabilities */
mbed_official 10:ab9330955226 84
mbed_official 10:ab9330955226 85 /** \brief DP83848 PHY RBR MII dode definitions */
mbed_official 10:ab9330955226 86 #define DP8_RBR_RMII_MODE (1 << 5) /**< Use RMII mode */
mbed_official 10:ab9330955226 87
mbed_official 10:ab9330955226 88 /** \brief DP83848 PHY status definitions */
mbed_official 10:ab9330955226 89 #define DP8_REMOTEFAULT (1 << 6) /**< Remote fault */
mbed_official 10:ab9330955226 90 #define DP8_FULLDUPLEX (1 << 2) /**< 1=full duplex */
mbed_official 10:ab9330955226 91 #define DP8_SPEED10MBPS (1 << 1) /**< 1=10MBps speed */
mbed_official 10:ab9330955226 92 #define DP8_VALID_LINK (1 << 0) /**< 1=Link active */
mbed_official 10:ab9330955226 93
mbed_official 10:ab9330955226 94 /** \brief DP83848 PHY ID register definitions */
mbed_official 10:ab9330955226 95 #define DP8_PHYID1_OUI 0x2000 /**< Expected PHY ID1 */
mbed_official 10:ab9330955226 96 #define DP8_PHYID2_OUI 0x5c90 /**< Expected PHY ID2 */
mbed_official 10:ab9330955226 97
mbed_official 10:ab9330955226 98 /** \brief LAN8720 PHY Special Control/Status Register */
mbed_official 10:ab9330955226 99 #define PHY_SCSR_100MBIT 0x0008 /**< Speed: 1=100 MBit, 0=10Mbit */
mbed_official 10:ab9330955226 100 #define PHY_SCSR_DUPLEX 0x0010 /**< PHY Duplex Mask */
mbed_official 10:ab9330955226 101
mbed_official 10:ab9330955226 102 /** \brief Link status bits */
mbed_official 10:ab9330955226 103 #define LNK_STAT_VALID 0x01
mbed_official 10:ab9330955226 104 #define LNK_STAT_FULLDUPLEX 0x02
mbed_official 10:ab9330955226 105 #define LNK_STAT_SPEED10MPS 0x04
mbed_official 10:ab9330955226 106
mbed_official 10:ab9330955226 107 /** \brief PHY ID definitions */
mbed_official 10:ab9330955226 108 #define DP83848C_ID 0x20005C90 /**< PHY Identifier - DP83848C */
mbed_official 10:ab9330955226 109 #define LAN8720_ID 0x0007C0F0 /**< PHY Identifier - LAN8720 */
mbed_official 10:ab9330955226 110
mbed_official 10:ab9330955226 111 /** \brief PHY status structure used to indicate current status of PHY.
mbed_official 10:ab9330955226 112 */
mbed_official 10:ab9330955226 113 typedef struct {
mbed_official 10:ab9330955226 114 u32_t phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
mbed_official 10:ab9330955226 115 u32_t phy_full_duplex:1; /**< Half/full duplex connection speed flag. */
mbed_official 10:ab9330955226 116 u32_t phy_link_active:1; /**< Phy link active flag. */
mbed_official 10:ab9330955226 117 } PHY_STATUS_TYPE;
mbed_official 10:ab9330955226 118
mbed_official 10:ab9330955226 119 /** \brief PHY update flags */
mbed_official 10:ab9330955226 120 static PHY_STATUS_TYPE physts;
mbed_official 10:ab9330955226 121
mbed_official 10:ab9330955226 122 /** \brief Last PHY update flags, used for determing if something has changed */
mbed_official 10:ab9330955226 123 static PHY_STATUS_TYPE olddphysts;
mbed_official 10:ab9330955226 124
mbed_official 10:ab9330955226 125 /** \brief PHY update counter for state machine */
mbed_official 10:ab9330955226 126 static s32_t phyustate;
mbed_official 10:ab9330955226 127
mbed_official 10:ab9330955226 128 /** \brief Holds the PHY ID */
mbed_official 10:ab9330955226 129 static u32_t phy_id;
mbed_official 10:ab9330955226 130
mbed_official 10:ab9330955226 131 /** \brief Temporary holder of link status for LAN7420 */
mbed_official 10:ab9330955226 132 static u32_t phy_lan7420_sts_tmp;
mbed_official 10:ab9330955226 133
mbed_official 10:ab9330955226 134 /* Write a value via the MII link (non-blocking) */
mbed_official 10:ab9330955226 135 void lpc_mii_write_noblock(u32_t PhyReg, u32_t Value)
mbed_official 10:ab9330955226 136 {
mbed_official 10:ab9330955226 137 /* Write value at PHY address and register */
mbed_official 10:ab9330955226 138 LPC_EMAC->MADR = (LPC_PHYDEF_PHYADDR << 8) | PhyReg;
mbed_official 10:ab9330955226 139 LPC_EMAC->MWTD = Value;
mbed_official 10:ab9330955226 140 }
mbed_official 10:ab9330955226 141
mbed_official 10:ab9330955226 142 /* Write a value via the MII link (blocking) */
mbed_official 10:ab9330955226 143 err_t lpc_mii_write(u32_t PhyReg, u32_t Value)
mbed_official 10:ab9330955226 144 {
mbed_official 10:ab9330955226 145 u32_t mst = 250;
mbed_official 10:ab9330955226 146 err_t sts = ERR_OK;
mbed_official 10:ab9330955226 147
mbed_official 10:ab9330955226 148 /* Write value at PHY address and register */
mbed_official 10:ab9330955226 149 lpc_mii_write_noblock(PhyReg, Value);
mbed_official 10:ab9330955226 150
mbed_official 10:ab9330955226 151 /* Wait for unbusy status */
mbed_official 10:ab9330955226 152 while (mst > 0) {
mbed_official 10:ab9330955226 153 sts = LPC_EMAC->MIND;
mbed_official 10:ab9330955226 154 if ((sts & EMAC_MIND_BUSY) == 0)
mbed_official 10:ab9330955226 155 mst = 0;
mbed_official 10:ab9330955226 156 else {
mbed_official 10:ab9330955226 157 mst--;
mbed_official 10:ab9330955226 158 osDelay(1);
mbed_official 10:ab9330955226 159 }
mbed_official 10:ab9330955226 160 }
mbed_official 10:ab9330955226 161
mbed_official 10:ab9330955226 162 if (sts != 0)
mbed_official 10:ab9330955226 163 sts = ERR_TIMEOUT;
mbed_official 10:ab9330955226 164
mbed_official 10:ab9330955226 165 return sts;
mbed_official 10:ab9330955226 166 }
mbed_official 10:ab9330955226 167
mbed_official 10:ab9330955226 168 /* Reads current MII link busy status */
mbed_official 10:ab9330955226 169 u32_t lpc_mii_is_busy(void)
mbed_official 10:ab9330955226 170 {
mbed_official 10:ab9330955226 171 return (u32_t) (LPC_EMAC->MIND & EMAC_MIND_BUSY);
mbed_official 10:ab9330955226 172 }
mbed_official 10:ab9330955226 173
mbed_official 10:ab9330955226 174 /* Starts a read operation via the MII link (non-blocking) */
mbed_official 10:ab9330955226 175 u32_t lpc_mii_read_data(void)
mbed_official 10:ab9330955226 176 {
mbed_official 10:ab9330955226 177 u32_t data = LPC_EMAC->MRDD;
mbed_official 10:ab9330955226 178 LPC_EMAC->MCMD = 0;
mbed_official 10:ab9330955226 179
mbed_official 10:ab9330955226 180 return data;
mbed_official 10:ab9330955226 181 }
mbed_official 10:ab9330955226 182
mbed_official 10:ab9330955226 183 /* Starts a read operation via the MII link (non-blocking) */
mbed_official 10:ab9330955226 184 void lpc_mii_read_noblock(u32_t PhyReg)
mbed_official 10:ab9330955226 185 {
mbed_official 10:ab9330955226 186 /* Read value at PHY address and register */
mbed_official 10:ab9330955226 187 LPC_EMAC->MADR = (LPC_PHYDEF_PHYADDR << 8) | PhyReg;
mbed_official 10:ab9330955226 188 LPC_EMAC->MCMD = EMAC_MCMD_READ;
mbed_official 10:ab9330955226 189 }
mbed_official 10:ab9330955226 190
mbed_official 10:ab9330955226 191 /* Read a value via the MII link (blocking) */
mbed_official 10:ab9330955226 192 err_t lpc_mii_read(u32_t PhyReg, u32_t *data)
mbed_official 10:ab9330955226 193 {
mbed_official 10:ab9330955226 194 u32_t mst = 250;
mbed_official 10:ab9330955226 195 err_t sts = ERR_OK;
mbed_official 10:ab9330955226 196
mbed_official 10:ab9330955226 197 /* Read value at PHY address and register */
mbed_official 10:ab9330955226 198 lpc_mii_read_noblock(PhyReg);
mbed_official 10:ab9330955226 199
mbed_official 10:ab9330955226 200 /* Wait for unbusy status */
mbed_official 10:ab9330955226 201 while (mst > 0) {
mbed_official 10:ab9330955226 202 sts = LPC_EMAC->MIND & ~EMAC_MIND_MII_LINK_FAIL;
mbed_official 10:ab9330955226 203 if ((sts & EMAC_MIND_BUSY) == 0) {
mbed_official 10:ab9330955226 204 mst = 0;
mbed_official 10:ab9330955226 205 *data = LPC_EMAC->MRDD;
mbed_official 10:ab9330955226 206 } else {
mbed_official 10:ab9330955226 207 mst--;
mbed_official 10:ab9330955226 208 osDelay(1);
mbed_official 10:ab9330955226 209 }
mbed_official 10:ab9330955226 210 }
mbed_official 10:ab9330955226 211
mbed_official 10:ab9330955226 212 LPC_EMAC->MCMD = 0;
mbed_official 10:ab9330955226 213
mbed_official 10:ab9330955226 214 if (sts != 0)
mbed_official 10:ab9330955226 215 sts = ERR_TIMEOUT;
mbed_official 10:ab9330955226 216
mbed_official 10:ab9330955226 217 return sts;
mbed_official 10:ab9330955226 218 }
mbed_official 10:ab9330955226 219
mbed_official 10:ab9330955226 220
mbed_official 10:ab9330955226 221
mbed_official 10:ab9330955226 222 /** \brief Update PHY status from passed value
mbed_official 10:ab9330955226 223 *
mbed_official 10:ab9330955226 224 * This function updates the current PHY status based on the
mbed_official 10:ab9330955226 225 * passed PHY status word. The PHY status indicate if the link
mbed_official 10:ab9330955226 226 * is active, the connection speed, and duplex.
mbed_official 10:ab9330955226 227 *
mbed_official 10:ab9330955226 228 * \param[in] netif NETIF structure
mbed_official 10:ab9330955226 229 * \param[in] linksts Status word from PHY
mbed_official 10:ab9330955226 230 * \return 1 if the status has changed, otherwise 0
mbed_official 10:ab9330955226 231 */
mbed_official 10:ab9330955226 232 static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts)
mbed_official 10:ab9330955226 233 {
mbed_official 10:ab9330955226 234 s32_t changed = 0;
mbed_official 10:ab9330955226 235
mbed_official 10:ab9330955226 236 /* Update link active status */
mbed_official 10:ab9330955226 237 if (linksts & LNK_STAT_VALID)
mbed_official 10:ab9330955226 238 physts.phy_link_active = 1;
mbed_official 10:ab9330955226 239 else
mbed_official 10:ab9330955226 240 physts.phy_link_active = 0;
mbed_official 10:ab9330955226 241
mbed_official 10:ab9330955226 242 /* Full or half duplex */
mbed_official 10:ab9330955226 243 if (linksts & LNK_STAT_FULLDUPLEX)
mbed_official 10:ab9330955226 244 physts.phy_full_duplex = 1;
mbed_official 10:ab9330955226 245 else
mbed_official 10:ab9330955226 246 physts.phy_full_duplex = 0;
mbed_official 10:ab9330955226 247
mbed_official 10:ab9330955226 248 /* Configure 100MBit/10MBit mode. */
mbed_official 10:ab9330955226 249 if (linksts & LNK_STAT_SPEED10MPS)
mbed_official 10:ab9330955226 250 physts.phy_speed_100mbs = 0;
mbed_official 10:ab9330955226 251 else
mbed_official 10:ab9330955226 252 physts.phy_speed_100mbs = 1;
mbed_official 10:ab9330955226 253
mbed_official 10:ab9330955226 254 if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
mbed_official 10:ab9330955226 255 changed = 1;
mbed_official 10:ab9330955226 256 if (physts.phy_speed_100mbs) {
mbed_official 10:ab9330955226 257 /* 100MBit mode. */
mbed_official 10:ab9330955226 258 lpc_emac_set_speed(1);
mbed_official 10:ab9330955226 259
mbed_official 10:ab9330955226 260 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
mbed_official 10:ab9330955226 261 }
mbed_official 10:ab9330955226 262 else {
mbed_official 10:ab9330955226 263 /* 10MBit mode. */
mbed_official 10:ab9330955226 264 lpc_emac_set_speed(0);
mbed_official 10:ab9330955226 265
mbed_official 10:ab9330955226 266 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
mbed_official 10:ab9330955226 267 }
mbed_official 10:ab9330955226 268
mbed_official 10:ab9330955226 269 olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
mbed_official 10:ab9330955226 270 }
mbed_official 10:ab9330955226 271
mbed_official 10:ab9330955226 272 if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
mbed_official 10:ab9330955226 273 changed = 1;
mbed_official 10:ab9330955226 274 if (physts.phy_full_duplex)
mbed_official 10:ab9330955226 275 lpc_emac_set_duplex(1);
mbed_official 10:ab9330955226 276 else
mbed_official 10:ab9330955226 277 lpc_emac_set_duplex(0);
mbed_official 10:ab9330955226 278
mbed_official 10:ab9330955226 279 olddphysts.phy_full_duplex = physts.phy_full_duplex;
mbed_official 10:ab9330955226 280 }
mbed_official 10:ab9330955226 281
mbed_official 10:ab9330955226 282 if (physts.phy_link_active != olddphysts.phy_link_active) {
mbed_official 10:ab9330955226 283 changed = 1;
mbed_official 10:ab9330955226 284 #if NO_SYS == 1
mbed_official 10:ab9330955226 285 if (physts.phy_link_active)
mbed_official 10:ab9330955226 286 netif_set_link_up(netif);
mbed_official 10:ab9330955226 287 else
mbed_official 10:ab9330955226 288 netif_set_link_down(netif);
mbed_official 10:ab9330955226 289 #else
mbed_official 10:ab9330955226 290 if (physts.phy_link_active)
mbed_official 10:ab9330955226 291 tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
mbed_official 10:ab9330955226 292 (void*) netif, 1);
mbed_official 10:ab9330955226 293 else
mbed_official 10:ab9330955226 294 tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
mbed_official 10:ab9330955226 295 (void*) netif, 1);
mbed_official 10:ab9330955226 296 #endif
mbed_official 10:ab9330955226 297
mbed_official 10:ab9330955226 298 olddphysts.phy_link_active = physts.phy_link_active;
mbed_official 10:ab9330955226 299 }
mbed_official 10:ab9330955226 300
mbed_official 10:ab9330955226 301 return changed;
mbed_official 10:ab9330955226 302 }
mbed_official 10:ab9330955226 303
mbed_official 10:ab9330955226 304 /** \brief Initialize the DP83848 PHY.
mbed_official 10:ab9330955226 305 *
mbed_official 10:ab9330955226 306 * This function initializes the DP83848 PHY. It will block until
mbed_official 10:ab9330955226 307 * complete. This function is called as part of the EMAC driver
mbed_official 10:ab9330955226 308 * initialization. Configuration of the PHY at startup is
mbed_official 10:ab9330955226 309 * controlled by setting up configuration defines in lpc_phy.h.
mbed_official 10:ab9330955226 310 *
mbed_official 10:ab9330955226 311 * \param[in] netif NETIF structure
mbed_official 10:ab9330955226 312 * \param[in] rmii If set, configures the PHY for RMII mode
mbed_official 10:ab9330955226 313 * \return ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
mbed_official 10:ab9330955226 314 */
mbed_official 10:ab9330955226 315 err_t lpc_phy_init(struct netif *netif, int rmii)
mbed_official 10:ab9330955226 316 {
mbed_official 10:ab9330955226 317 u32_t tmp;
mbed_official 10:ab9330955226 318 s32_t i;
mbed_official 10:ab9330955226 319
mbed_official 10:ab9330955226 320 physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 0;
mbed_official 10:ab9330955226 321 physts.phy_full_duplex = olddphysts.phy_full_duplex = 0;
mbed_official 10:ab9330955226 322 physts.phy_link_active = olddphysts.phy_link_active = 0;
mbed_official 10:ab9330955226 323 phyustate = 0;
mbed_official 10:ab9330955226 324
mbed_official 10:ab9330955226 325 /* Only first read and write are checked for failure */
mbed_official 10:ab9330955226 326 /* Put the DP83848C in reset mode and wait for completion */
mbed_official 10:ab9330955226 327 if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
mbed_official 10:ab9330955226 328 return ERR_TIMEOUT;
mbed_official 10:ab9330955226 329 i = 400;
mbed_official 10:ab9330955226 330 while (i > 0) {
mbed_official 10:ab9330955226 331 osDelay(1); /* 1 ms */
mbed_official 10:ab9330955226 332 if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
mbed_official 10:ab9330955226 333 return ERR_TIMEOUT;
mbed_official 10:ab9330955226 334
mbed_official 10:ab9330955226 335 if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
mbed_official 10:ab9330955226 336 i = -1;
mbed_official 10:ab9330955226 337 else
mbed_official 10:ab9330955226 338 i--;
mbed_official 10:ab9330955226 339 }
mbed_official 10:ab9330955226 340 /* Timeout? */
mbed_official 10:ab9330955226 341 if (i == 0)
mbed_official 10:ab9330955226 342 return ERR_TIMEOUT;
mbed_official 10:ab9330955226 343
mbed_official 10:ab9330955226 344 // read PHY ID
mbed_official 10:ab9330955226 345 lpc_mii_read(DP8_IDR1_REG, &tmp);
mbed_official 10:ab9330955226 346 phy_id = (tmp << 16);
mbed_official 10:ab9330955226 347 lpc_mii_read(DP8_IDR2_REG, &tmp);
mbed_official 10:ab9330955226 348 phy_id |= (tmp & 0XFFF0);
mbed_official 10:ab9330955226 349
mbed_official 10:ab9330955226 350 /* Setup link based on configuration options */
mbed_official 10:ab9330955226 351 #if PHY_USE_AUTONEG==1
mbed_official 10:ab9330955226 352 tmp = DP8_AUTONEG;
mbed_official 10:ab9330955226 353 #else
mbed_official 10:ab9330955226 354 tmp = 0;
mbed_official 10:ab9330955226 355 #endif
mbed_official 10:ab9330955226 356 #if PHY_USE_100MBS==1
mbed_official 10:ab9330955226 357 tmp |= DP8_SPEED_SELECT;
mbed_official 10:ab9330955226 358 #endif
mbed_official 10:ab9330955226 359 #if PHY_USE_FULL_DUPLEX==1
mbed_official 10:ab9330955226 360 tmp |= DP8_DUPLEX_MODE;
mbed_official 10:ab9330955226 361 #endif
mbed_official 10:ab9330955226 362 lpc_mii_write(DP8_BMCR_REG, tmp);
mbed_official 10:ab9330955226 363
mbed_official 10:ab9330955226 364 /* Enable RMII mode for PHY */
mbed_official 10:ab9330955226 365 if (rmii)
mbed_official 10:ab9330955226 366 lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
mbed_official 10:ab9330955226 367
mbed_official 10:ab9330955226 368 /* The link is not set active at this point, but will be detected
mbed_official 10:ab9330955226 369 later */
mbed_official 10:ab9330955226 370
mbed_official 10:ab9330955226 371 return ERR_OK;
mbed_official 10:ab9330955226 372 }
mbed_official 10:ab9330955226 373
mbed_official 10:ab9330955226 374 /* Phy status update state machine */
mbed_official 10:ab9330955226 375 s32_t lpc_phy_sts_sm(struct netif *netif)
mbed_official 10:ab9330955226 376 {
mbed_official 10:ab9330955226 377 s32_t changed = 0;
mbed_official 10:ab9330955226 378 u32_t data = 0;
mbed_official 10:ab9330955226 379 u32_t tmp;
mbed_official 10:ab9330955226 380
mbed_official 10:ab9330955226 381 switch (phyustate) {
mbed_official 10:ab9330955226 382 default:
mbed_official 10:ab9330955226 383 case 0:
mbed_official 10:ab9330955226 384 if (phy_id == DP83848C_ID) {
mbed_official 10:ab9330955226 385 lpc_mii_read_noblock(DP8_PHY_STAT_REG);
mbed_official 10:ab9330955226 386 phyustate = 2;
mbed_official 10:ab9330955226 387 }
mbed_official 10:ab9330955226 388 else if (phy_id == LAN8720_ID) {
mbed_official 10:ab9330955226 389 lpc_mii_read_noblock(DP8_PHY_SCSR_REG);
mbed_official 10:ab9330955226 390 phyustate = 1;
mbed_official 10:ab9330955226 391 }
mbed_official 10:ab9330955226 392 break;
mbed_official 10:ab9330955226 393
mbed_official 10:ab9330955226 394 case 1:
mbed_official 10:ab9330955226 395 if (phy_id == LAN8720_ID) {
mbed_official 10:ab9330955226 396 tmp = lpc_mii_read_data();
mbed_official 10:ab9330955226 397 // we get speed and duplex here.
mbed_official 10:ab9330955226 398 phy_lan7420_sts_tmp = (tmp & PHY_SCSR_DUPLEX) ? LNK_STAT_FULLDUPLEX : 0;
mbed_official 10:ab9330955226 399 phy_lan7420_sts_tmp |= (tmp & PHY_SCSR_100MBIT) ? 0 : LNK_STAT_SPEED10MPS;
mbed_official 10:ab9330955226 400
mbed_official 10:ab9330955226 401 //read the status register to get link status
mbed_official 10:ab9330955226 402 lpc_mii_read_noblock(DP8_BMSR_REG);
mbed_official 10:ab9330955226 403 phyustate = 2;
mbed_official 10:ab9330955226 404 }
mbed_official 10:ab9330955226 405 break;
mbed_official 10:ab9330955226 406
mbed_official 10:ab9330955226 407 case 2:
mbed_official 10:ab9330955226 408 /* Wait for read status state */
mbed_official 10:ab9330955226 409 if (!lpc_mii_is_busy()) {
mbed_official 10:ab9330955226 410 /* Update PHY status */
mbed_official 10:ab9330955226 411 tmp = lpc_mii_read_data();
mbed_official 10:ab9330955226 412
mbed_official 10:ab9330955226 413 if (phy_id == DP83848C_ID) {
mbed_official 10:ab9330955226 414 // STS register contains all needed status bits
mbed_official 10:ab9330955226 415 data = (tmp & DP8_VALID_LINK) ? LNK_STAT_VALID : 0;
mbed_official 10:ab9330955226 416 data |= (tmp & DP8_FULLDUPLEX) ? LNK_STAT_FULLDUPLEX : 0;
mbed_official 10:ab9330955226 417 data |= (tmp & DP8_SPEED10MBPS) ? LNK_STAT_SPEED10MPS : 0;
mbed_official 10:ab9330955226 418 }
mbed_official 10:ab9330955226 419 else if (phy_id == LAN8720_ID) {
mbed_official 10:ab9330955226 420 // we only get the link status here.
mbed_official 10:ab9330955226 421 phy_lan7420_sts_tmp |= (tmp & DP8_LINK_STATUS) ? LNK_STAT_VALID : 0;
mbed_official 10:ab9330955226 422 data = phy_lan7420_sts_tmp;
mbed_official 10:ab9330955226 423 }
mbed_official 10:ab9330955226 424
mbed_official 10:ab9330955226 425 changed = lpc_update_phy_sts(netif, data);
mbed_official 10:ab9330955226 426 phyustate = 0;
mbed_official 10:ab9330955226 427 }
mbed_official 10:ab9330955226 428 break;
mbed_official 10:ab9330955226 429 }
mbed_official 10:ab9330955226 430
mbed_official 10:ab9330955226 431 return changed;
mbed_official 10:ab9330955226 432 }
mbed_official 10:ab9330955226 433
mbed_official 10:ab9330955226 434 /**
mbed_official 10:ab9330955226 435 * @}
mbed_official 10:ab9330955226 436 */
mbed_official 10:ab9330955226 437
mbed_official 10:ab9330955226 438 /* --------------------------------- End Of File ------------------------------ */