mbed official / lwip-eth

NXP LPC1768 Ethernet driver for lwip and CMSIS-RTOS

Dependents:   EthernetInterface EthernetInterface EthernetInterface_RSF EthernetInterface ... more

Legacy Networking Libraries

This is an mbed 2 networking library. For mbed 5, the networking libraries have been revised to better support additional network stacks and thread safety here.

This library is based on the code of the NXP LPC port of the Lightweight TCP/IP Stack

Copyright(C) 2011, NXP Semiconductor
All rights reserved.

Software that is described herein is for illustrative purposes only
which provides customers with programming information regarding the
products. This software is supplied "AS IS" without any warranties.
NXP Semiconductors assumes no responsibility or liability for the
use of the software, conveys no license or title under any patent,
copyright, or mask work right to the product. NXP Semiconductors
reserves the right to make changes in the software without
notification. NXP Semiconductors also make no representation or
warranty that such application will be suitable for the specified
use without further testing or modification.

arch/TARGET_NXP/lpc17xx_emac.h@33:9de8bd8ca1c8, 2016-05-26 (annotated)

Committer:
mbed_official
Date:
Thu May 26 09:00:26 2016 +0100
Revision:
33:9de8bd8ca1c8
Synchronized with git revision 745ebbf4557f0f3964f73063c1d88ddbcda0ed22



Full URL: https://github.com/mbedmicro/mbed/commit/745ebbf4557f0f3964f73063c1d88ddbcda0ed22/



Synch - fix lwip-eth path

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 33:9de8bd8ca1c8 1 /**********************************************************************
mbed_official 33:9de8bd8ca1c8 2 * $Id$ lpc17xx_emac.h 2010-05-21
mbed_official 33:9de8bd8ca1c8 3 *//**
mbed_official 33:9de8bd8ca1c8 4 * @file lpc17xx_emac.h
mbed_official 33:9de8bd8ca1c8 5 * @brief Contains all macro definitions and function prototypes
mbed_official 33:9de8bd8ca1c8 6 * support for Ethernet MAC firmware library on LPC17xx
mbed_official 33:9de8bd8ca1c8 7 * @version 2.0
mbed_official 33:9de8bd8ca1c8 8 * @date 21. May. 2010
mbed_official 33:9de8bd8ca1c8 9 * @author NXP MCU SW Application Team
mbed_official 33:9de8bd8ca1c8 10 *
mbed_official 33:9de8bd8ca1c8 11 * Copyright(C) 2010, NXP Semiconductor
mbed_official 33:9de8bd8ca1c8 12 * All rights reserved.
mbed_official 33:9de8bd8ca1c8 13 *
mbed_official 33:9de8bd8ca1c8 14 ***********************************************************************
mbed_official 33:9de8bd8ca1c8 15 * Software that is described herein is for illustrative purposes only
mbed_official 33:9de8bd8ca1c8 16 * which provides customers with programming information regarding the
mbed_official 33:9de8bd8ca1c8 17 * products. This software is supplied "AS IS" without any warranties.
mbed_official 33:9de8bd8ca1c8 18 * NXP Semiconductors assumes no responsibility or liability for the
mbed_official 33:9de8bd8ca1c8 19 * use of the software, conveys no license or title under any patent,
mbed_official 33:9de8bd8ca1c8 20 * copyright, or mask work right to the product. NXP Semiconductors
mbed_official 33:9de8bd8ca1c8 21 * reserves the right to make changes in the software without
mbed_official 33:9de8bd8ca1c8 22 * notification. NXP Semiconductors also make no representation or
mbed_official 33:9de8bd8ca1c8 23 * warranty that such application will be suitable for the specified
mbed_official 33:9de8bd8ca1c8 24 * use without further testing or modification.
mbed_official 33:9de8bd8ca1c8 25 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 26
mbed_official 33:9de8bd8ca1c8 27 /* Peripheral group ----------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
mbed_official 33:9de8bd8ca1c8 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
mbed_official 33:9de8bd8ca1c8 30 * @{
mbed_official 33:9de8bd8ca1c8 31 */
mbed_official 33:9de8bd8ca1c8 32
mbed_official 33:9de8bd8ca1c8 33 #ifndef LPC17XX_EMAC_H_
mbed_official 33:9de8bd8ca1c8 34 #define LPC17XX_EMAC_H_
mbed_official 33:9de8bd8ca1c8 35
mbed_official 33:9de8bd8ca1c8 36 /* Includes ------------------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 37 #include "cmsis.h"
mbed_official 33:9de8bd8ca1c8 38
mbed_official 33:9de8bd8ca1c8 39 #ifdef __cplusplus
mbed_official 33:9de8bd8ca1c8 40 extern "C"
mbed_official 33:9de8bd8ca1c8 41 {
mbed_official 33:9de8bd8ca1c8 42 #endif
mbed_official 33:9de8bd8ca1c8 43
mbed_official 33:9de8bd8ca1c8 44 #define MCB_LPC_1768
mbed_official 33:9de8bd8ca1c8 45 //#define IAR_LPC_1768
mbed_official 33:9de8bd8ca1c8 46
mbed_official 33:9de8bd8ca1c8 47 /* Public Macros -------------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
mbed_official 33:9de8bd8ca1c8 49 * @{
mbed_official 33:9de8bd8ca1c8 50 */
mbed_official 33:9de8bd8ca1c8 51
mbed_official 33:9de8bd8ca1c8 52
mbed_official 33:9de8bd8ca1c8 53 /* EMAC PHY status type definitions */
mbed_official 33:9de8bd8ca1c8 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
mbed_official 33:9de8bd8ca1c8 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
mbed_official 33:9de8bd8ca1c8 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
mbed_official 33:9de8bd8ca1c8 57
mbed_official 33:9de8bd8ca1c8 58 /* EMAC PHY device Speed definitions */
mbed_official 33:9de8bd8ca1c8 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
mbed_official 33:9de8bd8ca1c8 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
mbed_official 33:9de8bd8ca1c8 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
mbed_official 33:9de8bd8ca1c8 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
mbed_official 33:9de8bd8ca1c8 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
mbed_official 33:9de8bd8ca1c8 64
mbed_official 33:9de8bd8ca1c8 65 /**
mbed_official 33:9de8bd8ca1c8 66 * @}
mbed_official 33:9de8bd8ca1c8 67 */
mbed_official 33:9de8bd8ca1c8 68 /* Private Macros ------------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
mbed_official 33:9de8bd8ca1c8 70 * @{
mbed_official 33:9de8bd8ca1c8 71 */
mbed_official 33:9de8bd8ca1c8 72
mbed_official 33:9de8bd8ca1c8 73
mbed_official 33:9de8bd8ca1c8 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
mbed_official 33:9de8bd8ca1c8 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
mbed_official 33:9de8bd8ca1c8 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
mbed_official 33:9de8bd8ca1c8 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
mbed_official 33:9de8bd8ca1c8 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
mbed_official 33:9de8bd8ca1c8 79
mbed_official 33:9de8bd8ca1c8 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
mbed_official 33:9de8bd8ca1c8 81 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 82 * Macro defines for MAC Configuration Register 1
mbed_official 33:9de8bd8ca1c8 83 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
mbed_official 33:9de8bd8ca1c8 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
mbed_official 33:9de8bd8ca1c8 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
mbed_official 33:9de8bd8ca1c8 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
mbed_official 33:9de8bd8ca1c8 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
mbed_official 33:9de8bd8ca1c8 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
mbed_official 33:9de8bd8ca1c8 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
mbed_official 33:9de8bd8ca1c8 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
mbed_official 33:9de8bd8ca1c8 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
mbed_official 33:9de8bd8ca1c8 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
mbed_official 33:9de8bd8ca1c8 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
mbed_official 33:9de8bd8ca1c8 95
mbed_official 33:9de8bd8ca1c8 96 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 97 * Macro defines for MAC Configuration Register 2
mbed_official 33:9de8bd8ca1c8 98 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
mbed_official 33:9de8bd8ca1c8 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
mbed_official 33:9de8bd8ca1c8 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
mbed_official 33:9de8bd8ca1c8 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
mbed_official 33:9de8bd8ca1c8 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
mbed_official 33:9de8bd8ca1c8 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
mbed_official 33:9de8bd8ca1c8 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
mbed_official 33:9de8bd8ca1c8 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
mbed_official 33:9de8bd8ca1c8 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
mbed_official 33:9de8bd8ca1c8 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
mbed_official 33:9de8bd8ca1c8 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
mbed_official 33:9de8bd8ca1c8 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
mbed_official 33:9de8bd8ca1c8 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
mbed_official 33:9de8bd8ca1c8 112
mbed_official 33:9de8bd8ca1c8 113 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
mbed_official 33:9de8bd8ca1c8 115 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 116 /** Programmable field representing the nibble time offset of the minimum possible period
mbed_official 33:9de8bd8ca1c8 117 * between the end of any transmitted packet to the beginning of the next */
mbed_official 33:9de8bd8ca1c8 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
mbed_official 33:9de8bd8ca1c8 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
mbed_official 33:9de8bd8ca1c8 120 * offset of the minimum possible period between the end of any transmitted packet to the
mbed_official 33:9de8bd8ca1c8 121 * beginning of the next */
mbed_official 33:9de8bd8ca1c8 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
mbed_official 33:9de8bd8ca1c8 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
mbed_official 33:9de8bd8ca1c8 124 * offset of the minimum possible period between the end of any transmitted packet to the
mbed_official 33:9de8bd8ca1c8 125 * beginning of the next */
mbed_official 33:9de8bd8ca1c8 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
mbed_official 33:9de8bd8ca1c8 127
mbed_official 33:9de8bd8ca1c8 128 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
mbed_official 33:9de8bd8ca1c8 130 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
mbed_official 33:9de8bd8ca1c8 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
mbed_official 33:9de8bd8ca1c8 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
mbed_official 33:9de8bd8ca1c8 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
mbed_official 33:9de8bd8ca1c8 135 /** Programmable field representing the optional carrierSense window referenced in
mbed_official 33:9de8bd8ca1c8 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
mbed_official 33:9de8bd8ca1c8 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
mbed_official 33:9de8bd8ca1c8 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
mbed_official 33:9de8bd8ca1c8 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
mbed_official 33:9de8bd8ca1c8 140
mbed_official 33:9de8bd8ca1c8 141 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 142 * Macro defines for Collision Window/Retry Register
mbed_official 33:9de8bd8ca1c8 143 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 144 /** Programmable field specifying the number of retransmission attempts following a collision before
mbed_official 33:9de8bd8ca1c8 145 * aborting the packet due to excessive collisions */
mbed_official 33:9de8bd8ca1c8 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
mbed_official 33:9de8bd8ca1c8 147 /** Programmable field representing the slot time or collision window during which collisions occur
mbed_official 33:9de8bd8ca1c8 148 * in properly configured networks */
mbed_official 33:9de8bd8ca1c8 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
mbed_official 33:9de8bd8ca1c8 150 /** Default value for Collision Window / Retry register */
mbed_official 33:9de8bd8ca1c8 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
mbed_official 33:9de8bd8ca1c8 152
mbed_official 33:9de8bd8ca1c8 153 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 154 * Macro defines for Maximum Frame Register
mbed_official 33:9de8bd8ca1c8 155 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 156 /** Represents a maximum receive frame of 1536 octets */
mbed_official 33:9de8bd8ca1c8 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
mbed_official 33:9de8bd8ca1c8 158
mbed_official 33:9de8bd8ca1c8 159 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 160 * Macro defines for PHY Support Register
mbed_official 33:9de8bd8ca1c8 161 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
mbed_official 33:9de8bd8ca1c8 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
mbed_official 33:9de8bd8ca1c8 164
mbed_official 33:9de8bd8ca1c8 165 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 166 * Macro defines for Test Register
mbed_official 33:9de8bd8ca1c8 167 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
mbed_official 33:9de8bd8ca1c8 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
mbed_official 33:9de8bd8ca1c8 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
mbed_official 33:9de8bd8ca1c8 171
mbed_official 33:9de8bd8ca1c8 172 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 173 * Macro defines for MII Management Configuration Register
mbed_official 33:9de8bd8ca1c8 174 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
mbed_official 33:9de8bd8ca1c8 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
mbed_official 33:9de8bd8ca1c8 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
mbed_official 33:9de8bd8ca1c8 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
mbed_official 33:9de8bd8ca1c8 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
mbed_official 33:9de8bd8ca1c8 180
mbed_official 33:9de8bd8ca1c8 181 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 182 * Macro defines for MII Management Command Register
mbed_official 33:9de8bd8ca1c8 183 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
mbed_official 33:9de8bd8ca1c8 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
mbed_official 33:9de8bd8ca1c8 186
mbed_official 33:9de8bd8ca1c8 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
mbed_official 33:9de8bd8ca1c8 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
mbed_official 33:9de8bd8ca1c8 189
mbed_official 33:9de8bd8ca1c8 190 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 191 * Macro defines for MII Management Address Register
mbed_official 33:9de8bd8ca1c8 192 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
mbed_official 33:9de8bd8ca1c8 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
mbed_official 33:9de8bd8ca1c8 195
mbed_official 33:9de8bd8ca1c8 196 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 197 * Macro defines for MII Management Write Data Register
mbed_official 33:9de8bd8ca1c8 198 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
mbed_official 33:9de8bd8ca1c8 200
mbed_official 33:9de8bd8ca1c8 201 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 202 * Macro defines for MII Management Read Data Register
mbed_official 33:9de8bd8ca1c8 203 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
mbed_official 33:9de8bd8ca1c8 205
mbed_official 33:9de8bd8ca1c8 206 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 207 * Macro defines for MII Management Indicators Register
mbed_official 33:9de8bd8ca1c8 208 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
mbed_official 33:9de8bd8ca1c8 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
mbed_official 33:9de8bd8ca1c8 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
mbed_official 33:9de8bd8ca1c8 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
mbed_official 33:9de8bd8ca1c8 213
mbed_official 33:9de8bd8ca1c8 214 /* Station Address 0 Register */
mbed_official 33:9de8bd8ca1c8 215 /* Station Address 1 Register */
mbed_official 33:9de8bd8ca1c8 216 /* Station Address 2 Register */
mbed_official 33:9de8bd8ca1c8 217
mbed_official 33:9de8bd8ca1c8 218
mbed_official 33:9de8bd8ca1c8 219 /* Control register definitions --------------------------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 220 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 221 * Macro defines for Command Register
mbed_official 33:9de8bd8ca1c8 222 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
mbed_official 33:9de8bd8ca1c8 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
mbed_official 33:9de8bd8ca1c8 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
mbed_official 33:9de8bd8ca1c8 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
mbed_official 33:9de8bd8ca1c8 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
mbed_official 33:9de8bd8ca1c8 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
mbed_official 33:9de8bd8ca1c8 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
mbed_official 33:9de8bd8ca1c8 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
mbed_official 33:9de8bd8ca1c8 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
mbed_official 33:9de8bd8ca1c8 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
mbed_official 33:9de8bd8ca1c8 233
mbed_official 33:9de8bd8ca1c8 234 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 235 * Macro defines for Status Register
mbed_official 33:9de8bd8ca1c8 236 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
mbed_official 33:9de8bd8ca1c8 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
mbed_official 33:9de8bd8ca1c8 239
mbed_official 33:9de8bd8ca1c8 240 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 241 * Macro defines for Transmit Status Vector 0 Register
mbed_official 33:9de8bd8ca1c8 242 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
mbed_official 33:9de8bd8ca1c8 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
mbed_official 33:9de8bd8ca1c8 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
mbed_official 33:9de8bd8ca1c8 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
mbed_official 33:9de8bd8ca1c8 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
mbed_official 33:9de8bd8ca1c8 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
mbed_official 33:9de8bd8ca1c8 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
mbed_official 33:9de8bd8ca1c8 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
mbed_official 33:9de8bd8ca1c8 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
mbed_official 33:9de8bd8ca1c8 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
mbed_official 33:9de8bd8ca1c8 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
mbed_official 33:9de8bd8ca1c8 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
mbed_official 33:9de8bd8ca1c8 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
mbed_official 33:9de8bd8ca1c8 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
mbed_official 33:9de8bd8ca1c8 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
mbed_official 33:9de8bd8ca1c8 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
mbed_official 33:9de8bd8ca1c8 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
mbed_official 33:9de8bd8ca1c8 260
mbed_official 33:9de8bd8ca1c8 261 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 262 * Macro defines for Transmit Status Vector 1 Register
mbed_official 33:9de8bd8ca1c8 263 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
mbed_official 33:9de8bd8ca1c8 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
mbed_official 33:9de8bd8ca1c8 266
mbed_official 33:9de8bd8ca1c8 267 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 268 * Macro defines for Receive Status Vector Register
mbed_official 33:9de8bd8ca1c8 269 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
mbed_official 33:9de8bd8ca1c8 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
mbed_official 33:9de8bd8ca1c8 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
mbed_official 33:9de8bd8ca1c8 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
mbed_official 33:9de8bd8ca1c8 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
mbed_official 33:9de8bd8ca1c8 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
mbed_official 33:9de8bd8ca1c8 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
mbed_official 33:9de8bd8ca1c8 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
mbed_official 33:9de8bd8ca1c8 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
mbed_official 33:9de8bd8ca1c8 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
mbed_official 33:9de8bd8ca1c8 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
mbed_official 33:9de8bd8ca1c8 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
mbed_official 33:9de8bd8ca1c8 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
mbed_official 33:9de8bd8ca1c8 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
mbed_official 33:9de8bd8ca1c8 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
mbed_official 33:9de8bd8ca1c8 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
mbed_official 33:9de8bd8ca1c8 286
mbed_official 33:9de8bd8ca1c8 287 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 288 * Macro defines for Flow Control Counter Register
mbed_official 33:9de8bd8ca1c8 289 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
mbed_official 33:9de8bd8ca1c8 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
mbed_official 33:9de8bd8ca1c8 292
mbed_official 33:9de8bd8ca1c8 293 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 294 * Macro defines for Flow Control Status Register
mbed_official 33:9de8bd8ca1c8 295 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
mbed_official 33:9de8bd8ca1c8 297
mbed_official 33:9de8bd8ca1c8 298
mbed_official 33:9de8bd8ca1c8 299 /* Receive filter register definitions -------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 300 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 301 * Macro defines for Receive Filter Control Register
mbed_official 33:9de8bd8ca1c8 302 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
mbed_official 33:9de8bd8ca1c8 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
mbed_official 33:9de8bd8ca1c8 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
mbed_official 33:9de8bd8ca1c8 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
mbed_official 33:9de8bd8ca1c8 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
mbed_official 33:9de8bd8ca1c8 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
mbed_official 33:9de8bd8ca1c8 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
mbed_official 33:9de8bd8ca1c8 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
mbed_official 33:9de8bd8ca1c8 311
mbed_official 33:9de8bd8ca1c8 312 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 313 * Macro defines for Receive Filter WoL Status/Clear Registers
mbed_official 33:9de8bd8ca1c8 314 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
mbed_official 33:9de8bd8ca1c8 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
mbed_official 33:9de8bd8ca1c8 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
mbed_official 33:9de8bd8ca1c8 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
mbed_official 33:9de8bd8ca1c8 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
mbed_official 33:9de8bd8ca1c8 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
mbed_official 33:9de8bd8ca1c8 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
mbed_official 33:9de8bd8ca1c8 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
mbed_official 33:9de8bd8ca1c8 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
mbed_official 33:9de8bd8ca1c8 324
mbed_official 33:9de8bd8ca1c8 325
mbed_official 33:9de8bd8ca1c8 326 /* Module control register definitions ---------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 327 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
mbed_official 33:9de8bd8ca1c8 329 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
mbed_official 33:9de8bd8ca1c8 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
mbed_official 33:9de8bd8ca1c8 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
mbed_official 33:9de8bd8ca1c8 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
mbed_official 33:9de8bd8ca1c8 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
mbed_official 33:9de8bd8ca1c8 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
mbed_official 33:9de8bd8ca1c8 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
mbed_official 33:9de8bd8ca1c8 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
mbed_official 33:9de8bd8ca1c8 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
mbed_official 33:9de8bd8ca1c8 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
mbed_official 33:9de8bd8ca1c8 340
mbed_official 33:9de8bd8ca1c8 341 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 342 * Macro defines for Power Down Register
mbed_official 33:9de8bd8ca1c8 343 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
mbed_official 33:9de8bd8ca1c8 345
mbed_official 33:9de8bd8ca1c8 346 /* Descriptor and status formats ---------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 347 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 348 * Macro defines for RX Descriptor Control Word
mbed_official 33:9de8bd8ca1c8 349 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
mbed_official 33:9de8bd8ca1c8 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
mbed_official 33:9de8bd8ca1c8 352
mbed_official 33:9de8bd8ca1c8 353 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 354 * Macro defines for RX Status Hash CRC Word
mbed_official 33:9de8bd8ca1c8 355 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
mbed_official 33:9de8bd8ca1c8 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
mbed_official 33:9de8bd8ca1c8 358
mbed_official 33:9de8bd8ca1c8 359 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 360 * Macro defines for RX Status Information Word
mbed_official 33:9de8bd8ca1c8 361 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
mbed_official 33:9de8bd8ca1c8 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
mbed_official 33:9de8bd8ca1c8 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
mbed_official 33:9de8bd8ca1c8 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
mbed_official 33:9de8bd8ca1c8 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
mbed_official 33:9de8bd8ca1c8 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
mbed_official 33:9de8bd8ca1c8 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
mbed_official 33:9de8bd8ca1c8 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
mbed_official 33:9de8bd8ca1c8 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
mbed_official 33:9de8bd8ca1c8 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
mbed_official 33:9de8bd8ca1c8 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
mbed_official 33:9de8bd8ca1c8 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
mbed_official 33:9de8bd8ca1c8 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
mbed_official 33:9de8bd8ca1c8 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
mbed_official 33:9de8bd8ca1c8 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
mbed_official 33:9de8bd8ca1c8 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
mbed_official 33:9de8bd8ca1c8 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
mbed_official 33:9de8bd8ca1c8 379
mbed_official 33:9de8bd8ca1c8 380 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 381 * Macro defines for TX Descriptor Control Word
mbed_official 33:9de8bd8ca1c8 382 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
mbed_official 33:9de8bd8ca1c8 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
mbed_official 33:9de8bd8ca1c8 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
mbed_official 33:9de8bd8ca1c8 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
mbed_official 33:9de8bd8ca1c8 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
mbed_official 33:9de8bd8ca1c8 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
mbed_official 33:9de8bd8ca1c8 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
mbed_official 33:9de8bd8ca1c8 390
mbed_official 33:9de8bd8ca1c8 391 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 392 * Macro defines for TX Status Information Word
mbed_official 33:9de8bd8ca1c8 393 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
mbed_official 33:9de8bd8ca1c8 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
mbed_official 33:9de8bd8ca1c8 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
mbed_official 33:9de8bd8ca1c8 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
mbed_official 33:9de8bd8ca1c8 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
mbed_official 33:9de8bd8ca1c8 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
mbed_official 33:9de8bd8ca1c8 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
mbed_official 33:9de8bd8ca1c8 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
mbed_official 33:9de8bd8ca1c8 402
mbed_official 33:9de8bd8ca1c8 403 #ifdef MCB_LPC_1768
mbed_official 33:9de8bd8ca1c8 404 /* DP83848C PHY definition ------------------------------------------------------------ */
mbed_official 33:9de8bd8ca1c8 405
mbed_official 33:9de8bd8ca1c8 406 /** PHY device reset time out definition */
mbed_official 33:9de8bd8ca1c8 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
mbed_official 33:9de8bd8ca1c8 408
mbed_official 33:9de8bd8ca1c8 409 /* ENET Device Revision ID */
mbed_official 33:9de8bd8ca1c8 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
mbed_official 33:9de8bd8ca1c8 411
mbed_official 33:9de8bd8ca1c8 412 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 413 * Macro defines for DP83848C PHY Registers
mbed_official 33:9de8bd8ca1c8 414 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
mbed_official 33:9de8bd8ca1c8 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
mbed_official 33:9de8bd8ca1c8 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
mbed_official 33:9de8bd8ca1c8 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
mbed_official 33:9de8bd8ca1c8 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
mbed_official 33:9de8bd8ca1c8 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
mbed_official 33:9de8bd8ca1c8 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
mbed_official 33:9de8bd8ca1c8 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
mbed_official 33:9de8bd8ca1c8 423 #define EMAC_PHY_REG_LPNPA 0x08
mbed_official 33:9de8bd8ca1c8 424
mbed_official 33:9de8bd8ca1c8 425 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 426 * Macro defines for PHY Extended Registers
mbed_official 33:9de8bd8ca1c8 427 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
mbed_official 33:9de8bd8ca1c8 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
mbed_official 33:9de8bd8ca1c8 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
mbed_official 33:9de8bd8ca1c8 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
mbed_official 33:9de8bd8ca1c8 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
mbed_official 33:9de8bd8ca1c8 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
mbed_official 33:9de8bd8ca1c8 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
mbed_official 33:9de8bd8ca1c8 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
mbed_official 33:9de8bd8ca1c8 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
mbed_official 33:9de8bd8ca1c8 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
mbed_official 33:9de8bd8ca1c8 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
mbed_official 33:9de8bd8ca1c8 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
mbed_official 33:9de8bd8ca1c8 440
mbed_official 33:9de8bd8ca1c8 441 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 442 * Macro defines for PHY Basic Mode Control Register
mbed_official 33:9de8bd8ca1c8 443 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
mbed_official 33:9de8bd8ca1c8 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
mbed_official 33:9de8bd8ca1c8 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
mbed_official 33:9de8bd8ca1c8 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
mbed_official 33:9de8bd8ca1c8 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
mbed_official 33:9de8bd8ca1c8 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
mbed_official 33:9de8bd8ca1c8 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
mbed_official 33:9de8bd8ca1c8 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
mbed_official 33:9de8bd8ca1c8 452
mbed_official 33:9de8bd8ca1c8 453 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 454 * Macro defines for PHY Basic Mode Status Status Register
mbed_official 33:9de8bd8ca1c8 455 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
mbed_official 33:9de8bd8ca1c8 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
mbed_official 33:9de8bd8ca1c8 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
mbed_official 33:9de8bd8ca1c8 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
mbed_official 33:9de8bd8ca1c8 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
mbed_official 33:9de8bd8ca1c8 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
mbed_official 33:9de8bd8ca1c8 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
mbed_official 33:9de8bd8ca1c8 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
mbed_official 33:9de8bd8ca1c8 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
mbed_official 33:9de8bd8ca1c8 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
mbed_official 33:9de8bd8ca1c8 466
mbed_official 33:9de8bd8ca1c8 467 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 468 * Macro defines for PHY Status Register
mbed_official 33:9de8bd8ca1c8 469 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
mbed_official 33:9de8bd8ca1c8 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
mbed_official 33:9de8bd8ca1c8 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
mbed_official 33:9de8bd8ca1c8 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
mbed_official 33:9de8bd8ca1c8 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
mbed_official 33:9de8bd8ca1c8 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
mbed_official 33:9de8bd8ca1c8 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
mbed_official 33:9de8bd8ca1c8 477
mbed_official 33:9de8bd8ca1c8 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
mbed_official 33:9de8bd8ca1c8 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
mbed_official 33:9de8bd8ca1c8 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
mbed_official 33:9de8bd8ca1c8 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
mbed_official 33:9de8bd8ca1c8 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
mbed_official 33:9de8bd8ca1c8 483
mbed_official 33:9de8bd8ca1c8 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
mbed_official 33:9de8bd8ca1c8 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
mbed_official 33:9de8bd8ca1c8 486
mbed_official 33:9de8bd8ca1c8 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
mbed_official 33:9de8bd8ca1c8 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
mbed_official 33:9de8bd8ca1c8 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
mbed_official 33:9de8bd8ca1c8 490
mbed_official 33:9de8bd8ca1c8 491 #elif defined(IAR_LPC_1768)
mbed_official 33:9de8bd8ca1c8 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
mbed_official 33:9de8bd8ca1c8 493 /** PHY device reset time out definition */
mbed_official 33:9de8bd8ca1c8 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
mbed_official 33:9de8bd8ca1c8 495
mbed_official 33:9de8bd8ca1c8 496 /* ENET Device Revision ID */
mbed_official 33:9de8bd8ca1c8 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
mbed_official 33:9de8bd8ca1c8 498
mbed_official 33:9de8bd8ca1c8 499 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 500 * Macro defines for KSZ8721BL PHY Registers
mbed_official 33:9de8bd8ca1c8 501 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
mbed_official 33:9de8bd8ca1c8 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
mbed_official 33:9de8bd8ca1c8 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
mbed_official 33:9de8bd8ca1c8 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
mbed_official 33:9de8bd8ca1c8 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
mbed_official 33:9de8bd8ca1c8 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
mbed_official 33:9de8bd8ca1c8 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
mbed_official 33:9de8bd8ca1c8 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
mbed_official 33:9de8bd8ca1c8 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
mbed_official 33:9de8bd8ca1c8 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
mbed_official 33:9de8bd8ca1c8 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
mbed_official 33:9de8bd8ca1c8 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
mbed_official 33:9de8bd8ca1c8 514
mbed_official 33:9de8bd8ca1c8 515 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 516 * Macro defines for PHY Basic Mode Control Register
mbed_official 33:9de8bd8ca1c8 517 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
mbed_official 33:9de8bd8ca1c8 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
mbed_official 33:9de8bd8ca1c8 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
mbed_official 33:9de8bd8ca1c8 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
mbed_official 33:9de8bd8ca1c8 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
mbed_official 33:9de8bd8ca1c8 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
mbed_official 33:9de8bd8ca1c8 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
mbed_official 33:9de8bd8ca1c8 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
mbed_official 33:9de8bd8ca1c8 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
mbed_official 33:9de8bd8ca1c8 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
mbed_official 33:9de8bd8ca1c8 528
mbed_official 33:9de8bd8ca1c8 529 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 530 * Macro defines for PHY Basic Mode Status Register
mbed_official 33:9de8bd8ca1c8 531 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
mbed_official 33:9de8bd8ca1c8 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
mbed_official 33:9de8bd8ca1c8 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
mbed_official 33:9de8bd8ca1c8 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
mbed_official 33:9de8bd8ca1c8 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
mbed_official 33:9de8bd8ca1c8 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
mbed_official 33:9de8bd8ca1c8 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
mbed_official 33:9de8bd8ca1c8 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
mbed_official 33:9de8bd8ca1c8 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
mbed_official 33:9de8bd8ca1c8 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
mbed_official 33:9de8bd8ca1c8 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
mbed_official 33:9de8bd8ca1c8 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
mbed_official 33:9de8bd8ca1c8 544
mbed_official 33:9de8bd8ca1c8 545 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 546 * Macro defines for PHY Identifier
mbed_official 33:9de8bd8ca1c8 547 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 548 /* PHY Identifier 1 bitmap definitions */
mbed_official 33:9de8bd8ca1c8 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
mbed_official 33:9de8bd8ca1c8 550
mbed_official 33:9de8bd8ca1c8 551 /* PHY Identifier 2 bitmap definitions */
mbed_official 33:9de8bd8ca1c8 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
mbed_official 33:9de8bd8ca1c8 553
mbed_official 33:9de8bd8ca1c8 554 /*********************************************************************//**
mbed_official 33:9de8bd8ca1c8 555 * Macro defines for Auto-Negotiation Advertisement
mbed_official 33:9de8bd8ca1c8 556 **********************************************************************/
mbed_official 33:9de8bd8ca1c8 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
mbed_official 33:9de8bd8ca1c8 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
mbed_official 33:9de8bd8ca1c8 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
mbed_official 33:9de8bd8ca1c8 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
mbed_official 33:9de8bd8ca1c8 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
mbed_official 33:9de8bd8ca1c8 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
mbed_official 33:9de8bd8ca1c8 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
mbed_official 33:9de8bd8ca1c8 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
mbed_official 33:9de8bd8ca1c8 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
mbed_official 33:9de8bd8ca1c8 566
mbed_official 33:9de8bd8ca1c8 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
mbed_official 33:9de8bd8ca1c8 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
mbed_official 33:9de8bd8ca1c8 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
mbed_official 33:9de8bd8ca1c8 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
mbed_official 33:9de8bd8ca1c8 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
mbed_official 33:9de8bd8ca1c8 572
mbed_official 33:9de8bd8ca1c8 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
mbed_official 33:9de8bd8ca1c8 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
mbed_official 33:9de8bd8ca1c8 575
mbed_official 33:9de8bd8ca1c8 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
mbed_official 33:9de8bd8ca1c8 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
mbed_official 33:9de8bd8ca1c8 578 #endif
mbed_official 33:9de8bd8ca1c8 579
mbed_official 33:9de8bd8ca1c8 580 /**
mbed_official 33:9de8bd8ca1c8 581 * @}
mbed_official 33:9de8bd8ca1c8 582 */
mbed_official 33:9de8bd8ca1c8 583
mbed_official 33:9de8bd8ca1c8 584
mbed_official 33:9de8bd8ca1c8 585 /* Public Types --------------------------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 586 /** @defgroup EMAC_Public_Types EMAC Public Types
mbed_official 33:9de8bd8ca1c8 587 * @{
mbed_official 33:9de8bd8ca1c8 588 */
mbed_official 33:9de8bd8ca1c8 589
mbed_official 33:9de8bd8ca1c8 590 /* Descriptor and status formats ---------------------------------------------- */
mbed_official 33:9de8bd8ca1c8 591
mbed_official 33:9de8bd8ca1c8 592 /**
mbed_official 33:9de8bd8ca1c8 593 * @brief RX Descriptor structure type definition
mbed_official 33:9de8bd8ca1c8 594 */
mbed_official 33:9de8bd8ca1c8 595 typedef struct {
mbed_official 33:9de8bd8ca1c8 596 uint32_t Packet; /**< Receive Packet Descriptor */
mbed_official 33:9de8bd8ca1c8 597 uint32_t Ctrl; /**< Receive Control Descriptor */
mbed_official 33:9de8bd8ca1c8 598 } RX_Desc;
mbed_official 33:9de8bd8ca1c8 599
mbed_official 33:9de8bd8ca1c8 600 /**
mbed_official 33:9de8bd8ca1c8 601 * @brief RX Status structure type definition
mbed_official 33:9de8bd8ca1c8 602 */
mbed_official 33:9de8bd8ca1c8 603 typedef struct {
mbed_official 33:9de8bd8ca1c8 604 uint32_t Info; /**< Receive Information Status */
mbed_official 33:9de8bd8ca1c8 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
mbed_official 33:9de8bd8ca1c8 606 } RX_Stat;
mbed_official 33:9de8bd8ca1c8 607
mbed_official 33:9de8bd8ca1c8 608 /**
mbed_official 33:9de8bd8ca1c8 609 * @brief TX Descriptor structure type definition
mbed_official 33:9de8bd8ca1c8 610 */
mbed_official 33:9de8bd8ca1c8 611 typedef struct {
mbed_official 33:9de8bd8ca1c8 612 uint32_t Packet; /**< Transmit Packet Descriptor */
mbed_official 33:9de8bd8ca1c8 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
mbed_official 33:9de8bd8ca1c8 614 } TX_Desc;
mbed_official 33:9de8bd8ca1c8 615
mbed_official 33:9de8bd8ca1c8 616 /**
mbed_official 33:9de8bd8ca1c8 617 * @brief TX Status structure type definition
mbed_official 33:9de8bd8ca1c8 618 */
mbed_official 33:9de8bd8ca1c8 619 typedef struct {
mbed_official 33:9de8bd8ca1c8 620 uint32_t Info; /**< Transmit Information Status */
mbed_official 33:9de8bd8ca1c8 621 } TX_Stat;
mbed_official 33:9de8bd8ca1c8 622
mbed_official 33:9de8bd8ca1c8 623
mbed_official 33:9de8bd8ca1c8 624 /**
mbed_official 33:9de8bd8ca1c8 625 * @brief TX Data Buffer structure definition
mbed_official 33:9de8bd8ca1c8 626 */
mbed_official 33:9de8bd8ca1c8 627 typedef struct {
mbed_official 33:9de8bd8ca1c8 628 uint32_t ulDataLen; /**< Data length */
mbed_official 33:9de8bd8ca1c8 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
mbed_official 33:9de8bd8ca1c8 630 } EMAC_PACKETBUF_Type;
mbed_official 33:9de8bd8ca1c8 631
mbed_official 33:9de8bd8ca1c8 632 /**
mbed_official 33:9de8bd8ca1c8 633 * @brief EMAC configuration structure definition
mbed_official 33:9de8bd8ca1c8 634 */
mbed_official 33:9de8bd8ca1c8 635 typedef struct {
mbed_official 33:9de8bd8ca1c8 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
mbed_official 33:9de8bd8ca1c8 637 - EMAC_MODE_AUTO
mbed_official 33:9de8bd8ca1c8 638 - EMAC_MODE_10M_FULL
mbed_official 33:9de8bd8ca1c8 639 - EMAC_MODE_10M_HALF
mbed_official 33:9de8bd8ca1c8 640 - EMAC_MODE_100M_FULL
mbed_official 33:9de8bd8ca1c8 641 - EMAC_MODE_100M_HALF
mbed_official 33:9de8bd8ca1c8 642 */
mbed_official 33:9de8bd8ca1c8 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
mbed_official 33:9de8bd8ca1c8 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
mbed_official 33:9de8bd8ca1c8 645 */
mbed_official 33:9de8bd8ca1c8 646 } EMAC_CFG_Type;
mbed_official 33:9de8bd8ca1c8 647
mbed_official 33:9de8bd8ca1c8 648 /** Ethernet block power/clock control bit*/
mbed_official 33:9de8bd8ca1c8 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
mbed_official 33:9de8bd8ca1c8 650
mbed_official 33:9de8bd8ca1c8 651 #ifdef __cplusplus
mbed_official 33:9de8bd8ca1c8 652 }
mbed_official 33:9de8bd8ca1c8 653 #endif
mbed_official 33:9de8bd8ca1c8 654
mbed_official 33:9de8bd8ca1c8 655 #endif /* LPC17XX_EMAC_H_ */
mbed_official 33:9de8bd8ca1c8 656
mbed_official 33:9de8bd8ca1c8 657 /**
mbed_official 33:9de8bd8ca1c8 658 * @}
mbed_official 33:9de8bd8ca1c8 659 */
mbed_official 33:9de8bd8ca1c8 660
mbed_official 33:9de8bd8ca1c8 661 /* --------------------------------- End Of File ------------------------------ */