demo of Murata wifi chip as TCP client.
Dependencies: SNICInterface mbed-rtos mbed
Fork of murataDemo by
Intro
this program demonstrates how to use TCP on the Murata Wifi chip. It will connect to a server and send a message, the server will then send a reply. The reply will be printed out to the terminal on the microcontroller.
Instructions
- Make sure you have both the wifi device and the computer running the server on the same network / wifi router.
- Change the hard coded IP in the microcontroller code to match that of the laptop running the python server.
- Run the python2 script below on the computer
- Have a console hooked up to the microcontroller and watch as messages are sent back and forth between the server (python) and the client (murata).
- Run the microcontroller code on the device.
For ease of use numbers have been appended to the end of the messages being sent back and forth.
Python Server
Please run this python2.7 code on your computer. Make sure to change the IP Address in the microcontroller code to match the IP of your computer.
import socket
s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
s.bind(('', 7))
s.listen(1)
x = 0
while True:
conn, addr = s.accept()
print 'Connected b'TCP data from server: 'y', addr
while True:
# receive data from board
data = conn.recv(1024)
# check received data
if not data:
break
# print received data
print("TCP data from microcontroller: '"+data+"'")
# send data to board with counter to differentiate messages
conn.sendall("HelloFromPython!: "+str(x)+"\n\r")
x+=1
# close the port
conn.close()
PowerControl/EthernetPowerControl.cpp@22:e567f0d4b05d, 2014-07-15 (annotated)
- Committer:
- kishino
- Date:
- Tue Jul 15 09:56:43 2014 +0000
- Revision:
- 22:e567f0d4b05d
- Parent:
- 16:ed9b9c28f860
The platform-dependent code was modified to implemented in ifdef.; The process of debug log output was changed to macro.;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| kishino | 22:e567f0d4b05d | 1 | #if defined(TARGET_LPC1768) |
| kishino | 16:ed9b9c28f860 | 2 | #include "EthernetPowerControl.h" |
| kishino | 16:ed9b9c28f860 | 3 | |
| kishino | 16:ed9b9c28f860 | 4 | static void write_PHY (unsigned int PhyReg, unsigned short Value) { |
| kishino | 16:ed9b9c28f860 | 5 | /* Write a data 'Value' to PHY register 'PhyReg'. */ |
| kishino | 16:ed9b9c28f860 | 6 | unsigned int tout; |
| kishino | 16:ed9b9c28f860 | 7 | /* Hardware MII Management for LPC176x devices. */ |
| kishino | 16:ed9b9c28f860 | 8 | LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; |
| kishino | 16:ed9b9c28f860 | 9 | LPC_EMAC->MWTD = Value; |
| kishino | 16:ed9b9c28f860 | 10 | |
| kishino | 16:ed9b9c28f860 | 11 | /* Wait utill operation completed */ |
| kishino | 16:ed9b9c28f860 | 12 | for (tout = 0; tout < MII_WR_TOUT; tout++) { |
| kishino | 16:ed9b9c28f860 | 13 | if ((LPC_EMAC->MIND & MIND_BUSY) == 0) { |
| kishino | 16:ed9b9c28f860 | 14 | break; |
| kishino | 16:ed9b9c28f860 | 15 | } |
| kishino | 16:ed9b9c28f860 | 16 | } |
| kishino | 16:ed9b9c28f860 | 17 | } |
| kishino | 16:ed9b9c28f860 | 18 | |
| kishino | 16:ed9b9c28f860 | 19 | static unsigned short read_PHY (unsigned int PhyReg) { |
| kishino | 16:ed9b9c28f860 | 20 | /* Read a PHY register 'PhyReg'. */ |
| kishino | 16:ed9b9c28f860 | 21 | unsigned int tout, val; |
| kishino | 16:ed9b9c28f860 | 22 | |
| kishino | 16:ed9b9c28f860 | 23 | LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; |
| kishino | 16:ed9b9c28f860 | 24 | LPC_EMAC->MCMD = MCMD_READ; |
| kishino | 16:ed9b9c28f860 | 25 | |
| kishino | 16:ed9b9c28f860 | 26 | /* Wait until operation completed */ |
| kishino | 16:ed9b9c28f860 | 27 | for (tout = 0; tout < MII_RD_TOUT; tout++) { |
| kishino | 16:ed9b9c28f860 | 28 | if ((LPC_EMAC->MIND & MIND_BUSY) == 0) { |
| kishino | 16:ed9b9c28f860 | 29 | break; |
| kishino | 16:ed9b9c28f860 | 30 | } |
| kishino | 16:ed9b9c28f860 | 31 | } |
| kishino | 16:ed9b9c28f860 | 32 | LPC_EMAC->MCMD = 0; |
| kishino | 16:ed9b9c28f860 | 33 | val = LPC_EMAC->MRDD; |
| kishino | 16:ed9b9c28f860 | 34 | |
| kishino | 16:ed9b9c28f860 | 35 | return (val); |
| kishino | 16:ed9b9c28f860 | 36 | } |
| kishino | 16:ed9b9c28f860 | 37 | |
| kishino | 16:ed9b9c28f860 | 38 | void EMAC_Init() |
| kishino | 16:ed9b9c28f860 | 39 | { |
| kishino | 16:ed9b9c28f860 | 40 | unsigned int tout,regv; |
| kishino | 16:ed9b9c28f860 | 41 | /* Power Up the EMAC controller. */ |
| kishino | 16:ed9b9c28f860 | 42 | Peripheral_PowerUp(LPC1768_PCONP_PCENET); |
| kishino | 16:ed9b9c28f860 | 43 | |
| kishino | 16:ed9b9c28f860 | 44 | LPC_PINCON->PINSEL2 = 0x50150105; |
| kishino | 16:ed9b9c28f860 | 45 | LPC_PINCON->PINSEL3 &= ~0x0000000F; |
| kishino | 16:ed9b9c28f860 | 46 | LPC_PINCON->PINSEL3 |= 0x00000005; |
| kishino | 16:ed9b9c28f860 | 47 | |
| kishino | 16:ed9b9c28f860 | 48 | /* Reset all EMAC internal modules. */ |
| kishino | 16:ed9b9c28f860 | 49 | LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | |
| kishino | 16:ed9b9c28f860 | 50 | MAC1_SIM_RES | MAC1_SOFT_RES; |
| kishino | 16:ed9b9c28f860 | 51 | LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; |
| kishino | 16:ed9b9c28f860 | 52 | |
| kishino | 16:ed9b9c28f860 | 53 | /* A short delay after reset. */ |
| kishino | 16:ed9b9c28f860 | 54 | for (tout = 100; tout; tout--); |
| kishino | 16:ed9b9c28f860 | 55 | |
| kishino | 16:ed9b9c28f860 | 56 | /* Initialize MAC control registers. */ |
| kishino | 16:ed9b9c28f860 | 57 | LPC_EMAC->MAC1 = MAC1_PASS_ALL; |
| kishino | 16:ed9b9c28f860 | 58 | LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; |
| kishino | 16:ed9b9c28f860 | 59 | LPC_EMAC->MAXF = ETH_MAX_FLEN; |
| kishino | 16:ed9b9c28f860 | 60 | LPC_EMAC->CLRT = CLRT_DEF; |
| kishino | 16:ed9b9c28f860 | 61 | LPC_EMAC->IPGR = IPGR_DEF; |
| kishino | 16:ed9b9c28f860 | 62 | |
| kishino | 16:ed9b9c28f860 | 63 | /* Enable Reduced MII interface. */ |
| kishino | 16:ed9b9c28f860 | 64 | LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; |
| kishino | 16:ed9b9c28f860 | 65 | |
| kishino | 16:ed9b9c28f860 | 66 | /* Reset Reduced MII Logic. */ |
| kishino | 16:ed9b9c28f860 | 67 | LPC_EMAC->SUPP = SUPP_RES_RMII; |
| kishino | 16:ed9b9c28f860 | 68 | for (tout = 100; tout; tout--); |
| kishino | 16:ed9b9c28f860 | 69 | LPC_EMAC->SUPP = 0; |
| kishino | 16:ed9b9c28f860 | 70 | |
| kishino | 16:ed9b9c28f860 | 71 | /* Put the DP83848C in reset mode */ |
| kishino | 16:ed9b9c28f860 | 72 | write_PHY (PHY_REG_BMCR, 0x8000); |
| kishino | 16:ed9b9c28f860 | 73 | |
| kishino | 16:ed9b9c28f860 | 74 | /* Wait for hardware reset to end. */ |
| kishino | 16:ed9b9c28f860 | 75 | for (tout = 0; tout < 0x100000; tout++) { |
| kishino | 16:ed9b9c28f860 | 76 | regv = read_PHY (PHY_REG_BMCR); |
| kishino | 16:ed9b9c28f860 | 77 | if (!(regv & 0x8000)) { |
| kishino | 16:ed9b9c28f860 | 78 | /* Reset complete */ |
| kishino | 16:ed9b9c28f860 | 79 | break; |
| kishino | 16:ed9b9c28f860 | 80 | } |
| kishino | 16:ed9b9c28f860 | 81 | } |
| kishino | 16:ed9b9c28f860 | 82 | } |
| kishino | 16:ed9b9c28f860 | 83 | |
| kishino | 16:ed9b9c28f860 | 84 | |
| kishino | 16:ed9b9c28f860 | 85 | void PHY_PowerDown() |
| kishino | 16:ed9b9c28f860 | 86 | { |
| kishino | 16:ed9b9c28f860 | 87 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| kishino | 16:ed9b9c28f860 | 88 | EMAC_Init(); //init EMAC if it is not already init'd |
| kishino | 16:ed9b9c28f860 | 89 | |
| kishino | 16:ed9b9c28f860 | 90 | unsigned int regv; |
| kishino | 16:ed9b9c28f860 | 91 | regv = read_PHY(PHY_REG_BMCR); |
| kishino | 16:ed9b9c28f860 | 92 | write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN)); |
| kishino | 16:ed9b9c28f860 | 93 | regv = read_PHY(PHY_REG_BMCR); |
| kishino | 16:ed9b9c28f860 | 94 | |
| kishino | 16:ed9b9c28f860 | 95 | //shouldn't need the EMAC now. |
| kishino | 16:ed9b9c28f860 | 96 | Peripheral_PowerDown(LPC1768_PCONP_PCENET); |
| kishino | 16:ed9b9c28f860 | 97 | |
| kishino | 16:ed9b9c28f860 | 98 | //and turn off the PHY OSC |
| kishino | 16:ed9b9c28f860 | 99 | LPC_GPIO1->FIODIR |= 0x8000000; |
| kishino | 16:ed9b9c28f860 | 100 | LPC_GPIO1->FIOCLR = 0x8000000; |
| kishino | 16:ed9b9c28f860 | 101 | } |
| kishino | 16:ed9b9c28f860 | 102 | |
| kishino | 16:ed9b9c28f860 | 103 | void PHY_PowerUp() |
| kishino | 16:ed9b9c28f860 | 104 | { |
| kishino | 16:ed9b9c28f860 | 105 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| kishino | 16:ed9b9c28f860 | 106 | EMAC_Init(); //init EMAC if it is not already init'd |
| kishino | 16:ed9b9c28f860 | 107 | |
| kishino | 16:ed9b9c28f860 | 108 | LPC_GPIO1->FIODIR |= 0x8000000; |
| kishino | 16:ed9b9c28f860 | 109 | LPC_GPIO1->FIOSET = 0x8000000; |
| kishino | 16:ed9b9c28f860 | 110 | |
| kishino | 16:ed9b9c28f860 | 111 | //wait for osc to be stable |
| kishino | 16:ed9b9c28f860 | 112 | wait_ms(200); |
| kishino | 16:ed9b9c28f860 | 113 | |
| kishino | 16:ed9b9c28f860 | 114 | unsigned int regv; |
| kishino | 16:ed9b9c28f860 | 115 | regv = read_PHY(PHY_REG_BMCR); |
| kishino | 16:ed9b9c28f860 | 116 | write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN)); |
| kishino | 16:ed9b9c28f860 | 117 | regv = read_PHY(PHY_REG_BMCR); |
| kishino | 16:ed9b9c28f860 | 118 | } |
| kishino | 16:ed9b9c28f860 | 119 | |
| kishino | 16:ed9b9c28f860 | 120 | void PHY_EnergyDetect_Enable() |
| kishino | 16:ed9b9c28f860 | 121 | { |
| kishino | 16:ed9b9c28f860 | 122 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| kishino | 16:ed9b9c28f860 | 123 | EMAC_Init(); //init EMAC if it is not already init'd |
| kishino | 16:ed9b9c28f860 | 124 | |
| kishino | 16:ed9b9c28f860 | 125 | unsigned int regv; |
| kishino | 16:ed9b9c28f860 | 126 | regv = read_PHY(PHY_REG_EDCR); |
| kishino | 16:ed9b9c28f860 | 127 | write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE)); |
| kishino | 16:ed9b9c28f860 | 128 | regv = read_PHY(PHY_REG_EDCR); |
| kishino | 16:ed9b9c28f860 | 129 | } |
| kishino | 16:ed9b9c28f860 | 130 | |
| kishino | 16:ed9b9c28f860 | 131 | void PHY_EnergyDetect_Disable() |
| kishino | 16:ed9b9c28f860 | 132 | { |
| kishino | 16:ed9b9c28f860 | 133 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| kishino | 16:ed9b9c28f860 | 134 | EMAC_Init(); //init EMAC if it is not already init'd |
| kishino | 16:ed9b9c28f860 | 135 | unsigned int regv; |
| kishino | 16:ed9b9c28f860 | 136 | regv = read_PHY(PHY_REG_EDCR); |
| kishino | 16:ed9b9c28f860 | 137 | write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE)); |
| kishino | 16:ed9b9c28f860 | 138 | regv = read_PHY(PHY_REG_EDCR); |
| kishino | 22:e567f0d4b05d | 139 | } |
| kishino | 22:e567f0d4b05d | 140 | #endif |
Austin Blackstone
