Austin Blackstone / Mbed 2 deprecated murataDemo

demo of the murata wifi chip. This demo tries to connect to an open wifi access point and prints out all the relevant information about the connection. It then scans all wifi access points nearby and reports their information.

Dependencies:   SNICInterface mbed-rtos mbed

Fork of SNIC-xively-jumpstart-demo by muRata

PowerControl/EthernetPowerControl.h@16:ed9b9c28f860, 2014-05-30 (annotated)

Committer:
kishino
Date:
Fri May 30 08:32:20 2014 +0000
Revision:
16:ed9b9c28f860
Xively demo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kishino 16:ed9b9c28f860 1 /* mbed PowerControl Library
kishino 16:ed9b9c28f860 2 * Copyright (c) 2010 Michael Wei
kishino 16:ed9b9c28f860 3 */
kishino 16:ed9b9c28f860 4
kishino 16:ed9b9c28f860 5 #ifndef MBED_POWERCONTROL_ETH_H
kishino 16:ed9b9c28f860 6 #define MBED_POWERCONTROL_ETH_H
kishino 16:ed9b9c28f860 7
kishino 16:ed9b9c28f860 8 #include "mbed.h"
kishino 16:ed9b9c28f860 9 #include "PowerControl.h"
kishino 16:ed9b9c28f860 10
kishino 16:ed9b9c28f860 11 #define PHY_REG_BMCR_POWERDOWN 0xB
kishino 16:ed9b9c28f860 12 #define PHY_REG_EDCR_ENABLE 0xF
kishino 16:ed9b9c28f860 13
kishino 16:ed9b9c28f860 14
kishino 16:ed9b9c28f860 15 void EMAC_Init();
kishino 16:ed9b9c28f860 16 static unsigned short read_PHY (unsigned int PhyReg);
kishino 16:ed9b9c28f860 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
kishino 16:ed9b9c28f860 18
kishino 16:ed9b9c28f860 19 void PHY_PowerDown(void);
kishino 16:ed9b9c28f860 20 void PHY_PowerUp(void);
kishino 16:ed9b9c28f860 21 void PHY_EnergyDetect_Enable(void);
kishino 16:ed9b9c28f860 22 void PHY_EnergyDetect_Disable(void);
kishino 16:ed9b9c28f860 23
kishino 16:ed9b9c28f860 24 //From NXP Sample Code .... Probably from KEIL sample code
kishino 16:ed9b9c28f860 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
kishino 16:ed9b9c28f860 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
kishino 16:ed9b9c28f860 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
kishino 16:ed9b9c28f860 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
kishino 16:ed9b9c28f860 29
kishino 16:ed9b9c28f860 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
kishino 16:ed9b9c28f860 31
kishino 16:ed9b9c28f860 32 /* EMAC variables located in 16K Ethernet SRAM */
kishino 16:ed9b9c28f860 33 #define RX_DESC_BASE 0x20080000
kishino 16:ed9b9c28f860 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
kishino 16:ed9b9c28f860 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
kishino 16:ed9b9c28f860 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
kishino 16:ed9b9c28f860 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
kishino 16:ed9b9c28f860 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
kishino 16:ed9b9c28f860 39
kishino 16:ed9b9c28f860 40 /* RX and TX descriptor and status definitions. */
kishino 16:ed9b9c28f860 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
kishino 16:ed9b9c28f860 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
kishino 16:ed9b9c28f860 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
kishino 16:ed9b9c28f860 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
kishino 16:ed9b9c28f860 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
kishino 16:ed9b9c28f860 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
kishino 16:ed9b9c28f860 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
kishino 16:ed9b9c28f860 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
kishino 16:ed9b9c28f860 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
kishino 16:ed9b9c28f860 50
kishino 16:ed9b9c28f860 51 /* MAC Configuration Register 1 */
kishino 16:ed9b9c28f860 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
kishino 16:ed9b9c28f860 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
kishino 16:ed9b9c28f860 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
kishino 16:ed9b9c28f860 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
kishino 16:ed9b9c28f860 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
kishino 16:ed9b9c28f860 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
kishino 16:ed9b9c28f860 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
kishino 16:ed9b9c28f860 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
kishino 16:ed9b9c28f860 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
kishino 16:ed9b9c28f860 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
kishino 16:ed9b9c28f860 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
kishino 16:ed9b9c28f860 63
kishino 16:ed9b9c28f860 64 /* MAC Configuration Register 2 */
kishino 16:ed9b9c28f860 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
kishino 16:ed9b9c28f860 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
kishino 16:ed9b9c28f860 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
kishino 16:ed9b9c28f860 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
kishino 16:ed9b9c28f860 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
kishino 16:ed9b9c28f860 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
kishino 16:ed9b9c28f860 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
kishino 16:ed9b9c28f860 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
kishino 16:ed9b9c28f860 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
kishino 16:ed9b9c28f860 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
kishino 16:ed9b9c28f860 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
kishino 16:ed9b9c28f860 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
kishino 16:ed9b9c28f860 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
kishino 16:ed9b9c28f860 78
kishino 16:ed9b9c28f860 79 /* Back-to-Back Inter-Packet-Gap Register */
kishino 16:ed9b9c28f860 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
kishino 16:ed9b9c28f860 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
kishino 16:ed9b9c28f860 82
kishino 16:ed9b9c28f860 83 /* Non Back-to-Back Inter-Packet-Gap Register */
kishino 16:ed9b9c28f860 84 #define IPGR_DEF 0x00000012 /* Recommended value */
kishino 16:ed9b9c28f860 85
kishino 16:ed9b9c28f860 86 /* Collision Window/Retry Register */
kishino 16:ed9b9c28f860 87 #define CLRT_DEF 0x0000370F /* Default value */
kishino 16:ed9b9c28f860 88
kishino 16:ed9b9c28f860 89 /* PHY Support Register */
kishino 16:ed9b9c28f860 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
kishino 16:ed9b9c28f860 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
kishino 16:ed9b9c28f860 92
kishino 16:ed9b9c28f860 93 /* Test Register */
kishino 16:ed9b9c28f860 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
kishino 16:ed9b9c28f860 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
kishino 16:ed9b9c28f860 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
kishino 16:ed9b9c28f860 97
kishino 16:ed9b9c28f860 98 /* MII Management Configuration Register */
kishino 16:ed9b9c28f860 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
kishino 16:ed9b9c28f860 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
kishino 16:ed9b9c28f860 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
kishino 16:ed9b9c28f860 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
kishino 16:ed9b9c28f860 103
kishino 16:ed9b9c28f860 104 /* MII Management Command Register */
kishino 16:ed9b9c28f860 105 #define MCMD_READ 0x00000001 /* MII Read */
kishino 16:ed9b9c28f860 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
kishino 16:ed9b9c28f860 107
kishino 16:ed9b9c28f860 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
kishino 16:ed9b9c28f860 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
kishino 16:ed9b9c28f860 110
kishino 16:ed9b9c28f860 111 /* MII Management Address Register */
kishino 16:ed9b9c28f860 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
kishino 16:ed9b9c28f860 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
kishino 16:ed9b9c28f860 114
kishino 16:ed9b9c28f860 115 /* MII Management Indicators Register */
kishino 16:ed9b9c28f860 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
kishino 16:ed9b9c28f860 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
kishino 16:ed9b9c28f860 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
kishino 16:ed9b9c28f860 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
kishino 16:ed9b9c28f860 120
kishino 16:ed9b9c28f860 121 /* Command Register */
kishino 16:ed9b9c28f860 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
kishino 16:ed9b9c28f860 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
kishino 16:ed9b9c28f860 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
kishino 16:ed9b9c28f860 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
kishino 16:ed9b9c28f860 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
kishino 16:ed9b9c28f860 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
kishino 16:ed9b9c28f860 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
kishino 16:ed9b9c28f860 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
kishino 16:ed9b9c28f860 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
kishino 16:ed9b9c28f860 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
kishino 16:ed9b9c28f860 132
kishino 16:ed9b9c28f860 133 /* Status Register */
kishino 16:ed9b9c28f860 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
kishino 16:ed9b9c28f860 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
kishino 16:ed9b9c28f860 136
kishino 16:ed9b9c28f860 137 /* Transmit Status Vector 0 Register */
kishino 16:ed9b9c28f860 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
kishino 16:ed9b9c28f860 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
kishino 16:ed9b9c28f860 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
kishino 16:ed9b9c28f860 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
kishino 16:ed9b9c28f860 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
kishino 16:ed9b9c28f860 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
kishino 16:ed9b9c28f860 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
kishino 16:ed9b9c28f860 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
kishino 16:ed9b9c28f860 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
kishino 16:ed9b9c28f860 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
kishino 16:ed9b9c28f860 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
kishino 16:ed9b9c28f860 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
kishino 16:ed9b9c28f860 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
kishino 16:ed9b9c28f860 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
kishino 16:ed9b9c28f860 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
kishino 16:ed9b9c28f860 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
kishino 16:ed9b9c28f860 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
kishino 16:ed9b9c28f860 155
kishino 16:ed9b9c28f860 156 /* Transmit Status Vector 1 Register */
kishino 16:ed9b9c28f860 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
kishino 16:ed9b9c28f860 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
kishino 16:ed9b9c28f860 159
kishino 16:ed9b9c28f860 160 /* Receive Status Vector Register */
kishino 16:ed9b9c28f860 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
kishino 16:ed9b9c28f860 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
kishino 16:ed9b9c28f860 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
kishino 16:ed9b9c28f860 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
kishino 16:ed9b9c28f860 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
kishino 16:ed9b9c28f860 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
kishino 16:ed9b9c28f860 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
kishino 16:ed9b9c28f860 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
kishino 16:ed9b9c28f860 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
kishino 16:ed9b9c28f860 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
kishino 16:ed9b9c28f860 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
kishino 16:ed9b9c28f860 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
kishino 16:ed9b9c28f860 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
kishino 16:ed9b9c28f860 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
kishino 16:ed9b9c28f860 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
kishino 16:ed9b9c28f860 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
kishino 16:ed9b9c28f860 177
kishino 16:ed9b9c28f860 178 /* Flow Control Counter Register */
kishino 16:ed9b9c28f860 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
kishino 16:ed9b9c28f860 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
kishino 16:ed9b9c28f860 181
kishino 16:ed9b9c28f860 182 /* Flow Control Status Register */
kishino 16:ed9b9c28f860 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
kishino 16:ed9b9c28f860 184
kishino 16:ed9b9c28f860 185 /* Receive Filter Control Register */
kishino 16:ed9b9c28f860 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
kishino 16:ed9b9c28f860 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
kishino 16:ed9b9c28f860 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
kishino 16:ed9b9c28f860 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
kishino 16:ed9b9c28f860 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
kishino 16:ed9b9c28f860 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
kishino 16:ed9b9c28f860 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
kishino 16:ed9b9c28f860 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
kishino 16:ed9b9c28f860 194
kishino 16:ed9b9c28f860 195 /* Receive Filter WoL Status/Clear Registers */
kishino 16:ed9b9c28f860 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
kishino 16:ed9b9c28f860 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
kishino 16:ed9b9c28f860 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
kishino 16:ed9b9c28f860 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
kishino 16:ed9b9c28f860 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
kishino 16:ed9b9c28f860 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
kishino 16:ed9b9c28f860 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
kishino 16:ed9b9c28f860 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
kishino 16:ed9b9c28f860 204
kishino 16:ed9b9c28f860 205 /* Interrupt Status/Enable/Clear/Set Registers */
kishino 16:ed9b9c28f860 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
kishino 16:ed9b9c28f860 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
kishino 16:ed9b9c28f860 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
kishino 16:ed9b9c28f860 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
kishino 16:ed9b9c28f860 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
kishino 16:ed9b9c28f860 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
kishino 16:ed9b9c28f860 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
kishino 16:ed9b9c28f860 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
kishino 16:ed9b9c28f860 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
kishino 16:ed9b9c28f860 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
kishino 16:ed9b9c28f860 216
kishino 16:ed9b9c28f860 217 /* Power Down Register */
kishino 16:ed9b9c28f860 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
kishino 16:ed9b9c28f860 219
kishino 16:ed9b9c28f860 220 /* RX Descriptor Control Word */
kishino 16:ed9b9c28f860 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
kishino 16:ed9b9c28f860 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
kishino 16:ed9b9c28f860 223
kishino 16:ed9b9c28f860 224 /* RX Status Hash CRC Word */
kishino 16:ed9b9c28f860 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
kishino 16:ed9b9c28f860 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
kishino 16:ed9b9c28f860 227
kishino 16:ed9b9c28f860 228 /* RX Status Information Word */
kishino 16:ed9b9c28f860 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
kishino 16:ed9b9c28f860 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
kishino 16:ed9b9c28f860 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
kishino 16:ed9b9c28f860 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
kishino 16:ed9b9c28f860 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
kishino 16:ed9b9c28f860 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
kishino 16:ed9b9c28f860 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
kishino 16:ed9b9c28f860 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
kishino 16:ed9b9c28f860 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
kishino 16:ed9b9c28f860 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
kishino 16:ed9b9c28f860 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
kishino 16:ed9b9c28f860 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
kishino 16:ed9b9c28f860 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
kishino 16:ed9b9c28f860 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
kishino 16:ed9b9c28f860 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
kishino 16:ed9b9c28f860 244
kishino 16:ed9b9c28f860 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
kishino 16:ed9b9c28f860 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
kishino 16:ed9b9c28f860 247
kishino 16:ed9b9c28f860 248 /* TX Descriptor Control Word */
kishino 16:ed9b9c28f860 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
kishino 16:ed9b9c28f860 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
kishino 16:ed9b9c28f860 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
kishino 16:ed9b9c28f860 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
kishino 16:ed9b9c28f860 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
kishino 16:ed9b9c28f860 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
kishino 16:ed9b9c28f860 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
kishino 16:ed9b9c28f860 256
kishino 16:ed9b9c28f860 257 /* TX Status Information Word */
kishino 16:ed9b9c28f860 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
kishino 16:ed9b9c28f860 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
kishino 16:ed9b9c28f860 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
kishino 16:ed9b9c28f860 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
kishino 16:ed9b9c28f860 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
kishino 16:ed9b9c28f860 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
kishino 16:ed9b9c28f860 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
kishino 16:ed9b9c28f860 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
kishino 16:ed9b9c28f860 266
kishino 16:ed9b9c28f860 267 /* DP83848C PHY Registers */
kishino 16:ed9b9c28f860 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
kishino 16:ed9b9c28f860 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
kishino 16:ed9b9c28f860 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
kishino 16:ed9b9c28f860 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
kishino 16:ed9b9c28f860 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
kishino 16:ed9b9c28f860 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
kishino 16:ed9b9c28f860 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
kishino 16:ed9b9c28f860 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
kishino 16:ed9b9c28f860 276
kishino 16:ed9b9c28f860 277 /* PHY Extended Registers */
kishino 16:ed9b9c28f860 278 #define PHY_REG_STS 0x10 /* Status Register */
kishino 16:ed9b9c28f860 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
kishino 16:ed9b9c28f860 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
kishino 16:ed9b9c28f860 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
kishino 16:ed9b9c28f860 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
kishino 16:ed9b9c28f860 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
kishino 16:ed9b9c28f860 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
kishino 16:ed9b9c28f860 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
kishino 16:ed9b9c28f860 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
kishino 16:ed9b9c28f860 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
kishino 16:ed9b9c28f860 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
kishino 16:ed9b9c28f860 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
kishino 16:ed9b9c28f860 290
kishino 16:ed9b9c28f860 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
kishino 16:ed9b9c28f860 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
kishino 16:ed9b9c28f860 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
kishino 16:ed9b9c28f860 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
kishino 16:ed9b9c28f860 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
kishino 16:ed9b9c28f860 296
kishino 16:ed9b9c28f860 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
kishino 16:ed9b9c28f860 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
kishino 16:ed9b9c28f860 299 #endif