Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
170:19eb464bc2be 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 12 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 13 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 * 3. Neither the name of ARM Limited nor the names of its contributors
<> 144:ef7eb2e8f9f7 15 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 16 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 28 *******************************************************************************
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 32 #include <math.h>
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 35 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 36 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 37 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 38 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 static inline int ssp_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 41 static inline int ssp_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 44 // determine the SPI to use
<> 144:ef7eb2e8f9f7 45 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 46 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 47 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 48 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 49 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 50 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 51 obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 52 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 // enable power and clocking
<> 144:ef7eb2e8f9f7 55 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 56 case SPI_0: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock
<> 144:ef7eb2e8f9f7 57 case SPI_1: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break;
<> 144:ef7eb2e8f9f7 58 }
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 // set default format and frequency
<> 144:ef7eb2e8f9f7 61 if (ssel == NC) {
<> 144:ef7eb2e8f9f7 62 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
<> 144:ef7eb2e8f9f7 63 } else {
<> 144:ef7eb2e8f9f7 64 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66 spi_frequency(obj, 1000000);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 // enable the ssp channel
<> 144:ef7eb2e8f9f7 69 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 // pin out the spi pins
<> 144:ef7eb2e8f9f7 72 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 73 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 74 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 75 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 76 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 77 }
<> 144:ef7eb2e8f9f7 78 }
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 void spi_free(spi_t *obj) {}
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 83 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 84 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 87 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // set it up
<> 144:ef7eb2e8f9f7 90 int DSS = bits - 1; // DSS (data select size)
<> 144:ef7eb2e8f9f7 91 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
<> 144:ef7eb2e8f9f7 92 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 int FRF = 0; // FRF (frame format) = SPI
<> 144:ef7eb2e8f9f7 95 uint32_t tmp = obj->spi->CR0;
<> 144:ef7eb2e8f9f7 96 tmp &= ~(0xFFFF);
<> 144:ef7eb2e8f9f7 97 tmp |= DSS << 0
<> 144:ef7eb2e8f9f7 98 | FRF << 4
<> 144:ef7eb2e8f9f7 99 | SPO << 6
<> 144:ef7eb2e8f9f7 100 | SPH << 7;
<> 144:ef7eb2e8f9f7 101 obj->spi->CR0 = tmp;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 tmp = obj->spi->CR1;
<> 144:ef7eb2e8f9f7 104 tmp &= ~(0xD);
<> 144:ef7eb2e8f9f7 105 tmp |= 0 << 0 // LBM - loop back mode - off
<> 144:ef7eb2e8f9f7 106 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
<> 144:ef7eb2e8f9f7 107 | 0 << 3; // SOD - slave output disable - na
<> 144:ef7eb2e8f9f7 108 obj->spi->CR1 = tmp;
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 114 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // setup the spi clock diveder to /1
<> 144:ef7eb2e8f9f7 117 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 118 case SPI_0:
<> 144:ef7eb2e8f9f7 119 CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
<> 144:ef7eb2e8f9f7 120 break;
<> 144:ef7eb2e8f9f7 121 case SPI_1:
<> 144:ef7eb2e8f9f7 122 CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
<> 144:ef7eb2e8f9f7 123 break;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 uint32_t HCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 int prescaler;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
<> 144:ef7eb2e8f9f7 131 int prescale_hz = HCLK / prescaler;
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 // calculate the divider
<> 144:ef7eb2e8f9f7 134 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 // check we can support the divider
<> 144:ef7eb2e8f9f7 137 if (divider < 256) {
<> 144:ef7eb2e8f9f7 138 // prescaler
<> 144:ef7eb2e8f9f7 139 obj->spi->CPSR = prescaler;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 // divider
<> 144:ef7eb2e8f9f7 142 obj->spi->CR0 &= ~(0xFFFF << 8);
<> 144:ef7eb2e8f9f7 143 obj->spi->CR0 |= (divider - 1) << 8;
<> 144:ef7eb2e8f9f7 144 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 145 return;
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148 error("Couldn't setup requested SPI frequency");
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 static inline int ssp_disable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 152 return obj->spi->CR1 &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 static inline int ssp_enable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 156 return obj->spi->CR1 |= (1 << 1);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 static inline int ssp_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 160 return obj->spi->SR & (1 << 2);
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 static inline int ssp_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 164 return obj->spi->SR & (1 << 1);
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 static inline void ssp_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 168 while (!ssp_writeable(obj));
<> 144:ef7eb2e8f9f7 169 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 static inline int ssp_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 173 while (!ssp_readable(obj));
<> 144:ef7eb2e8f9f7 174 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 static inline int ssp_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 178 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 182 ssp_write(obj, value);
<> 144:ef7eb2e8f9f7 183 return ssp_read(obj);
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
Kojto 170:19eb464bc2be 186 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 187 char *rx_buffer, int rx_length, char write_fill) {
AnnaBridge 167:e84263d55307 188 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 189
AnnaBridge 167:e84263d55307 190 for (int i = 0; i < total; i++) {
Kojto 170:19eb464bc2be 191 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 167:e84263d55307 192 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 193 if (i < rx_length) {
AnnaBridge 167:e84263d55307 194 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 195 }
AnnaBridge 167:e84263d55307 196 }
AnnaBridge 167:e84263d55307 197
AnnaBridge 167:e84263d55307 198 return total;
AnnaBridge 167:e84263d55307 199 }
AnnaBridge 167:e84263d55307 200
<> 144:ef7eb2e8f9f7 201 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 202 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 206 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 210 while (ssp_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 211 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 215 return ssp_busy(obj);
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217