Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC81X/serial_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
149:156823d33999 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 // math.h required for floating point operations for baud rate calculation
<> 144:ef7eb2e8f9f7 17 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 18 #include <math.h>
<> 144:ef7eb2e8f9f7 19 #include <string.h>
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 22 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 23 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 24 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 /******************************************************************************
<> 144:ef7eb2e8f9f7 27 * INITIALIZATION
<> 144:ef7eb2e8f9f7 28 ******************************************************************************/
<> 144:ef7eb2e8f9f7 29 #define UART_NUM 3
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 static const SWM_Map SWM_UART_TX[] = {
<> 144:ef7eb2e8f9f7 32 {0, 0},
<> 144:ef7eb2e8f9f7 33 {1, 8},
<> 144:ef7eb2e8f9f7 34 {2, 16},
<> 144:ef7eb2e8f9f7 35 };
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 static const SWM_Map SWM_UART_RX[] = {
<> 144:ef7eb2e8f9f7 38 {0, 8},
<> 144:ef7eb2e8f9f7 39 {1, 16},
<> 144:ef7eb2e8f9f7 40 {2, 24},
<> 144:ef7eb2e8f9f7 41 };
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 static const SWM_Map SWM_UART_RTS[] = {
<> 144:ef7eb2e8f9f7 44 {0, 16},
<> 144:ef7eb2e8f9f7 45 {1, 24},
<> 144:ef7eb2e8f9f7 46 {3, 0},
<> 144:ef7eb2e8f9f7 47 };
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 static const SWM_Map SWM_UART_CTS[] = {
<> 144:ef7eb2e8f9f7 50 {0, 24},
<> 144:ef7eb2e8f9f7 51 {2, 0},
<> 144:ef7eb2e8f9f7 52 {3, 8}
<> 144:ef7eb2e8f9f7 53 };
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 // bit flags for used UARTs
<> 144:ef7eb2e8f9f7 56 static unsigned char uart_used = 0;
<> 144:ef7eb2e8f9f7 57 static int get_available_uart(void) {
<> 144:ef7eb2e8f9f7 58 int i;
<> 144:ef7eb2e8f9f7 59 for (i=0; i<3; i++) {
<> 144:ef7eb2e8f9f7 60 if ((uart_used & (1 << i)) == 0)
<> 144:ef7eb2e8f9f7 61 return i;
<> 144:ef7eb2e8f9f7 62 }
<> 144:ef7eb2e8f9f7 63 return -1;
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #define UART_EN (0x01<<0)
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #define CTS_DELTA (0x01<<5)
<> 144:ef7eb2e8f9f7 69 #define RXBRK (0x01<<10)
<> 144:ef7eb2e8f9f7 70 #define DELTA_RXBRK (0x01<<11)
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define RXRDY (0x01<<0)
<> 144:ef7eb2e8f9f7 73 #define TXRDY (0x01<<2)
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 #define TXBRKEN (0x01<<1)
<> 144:ef7eb2e8f9f7 76 #define CTSEN (0x01<<9)
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 static uint32_t UARTSysClk;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 static uint32_t serial_irq_ids[UART_NUM] = {0};
<> 144:ef7eb2e8f9f7 81 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 int stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 84 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 void serial_init(serial_t *obj, PinName tx, PinName rx) {
<> 144:ef7eb2e8f9f7 87 int is_stdio_uart = 0;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 int uart_n = get_available_uart();
<> 144:ef7eb2e8f9f7 90 if (uart_n == -1) {
<> 144:ef7eb2e8f9f7 91 error("No available UART");
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93 obj->index = uart_n;
<> 144:ef7eb2e8f9f7 94 obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n));
<> 144:ef7eb2e8f9f7 95 uart_used |= (1 << uart_n);
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 98 uint32_t regVal;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 swm = &SWM_UART_TX[uart_n];
<> 144:ef7eb2e8f9f7 101 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 102 LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset);
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 swm = &SWM_UART_RX[uart_n];
<> 144:ef7eb2e8f9f7 105 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 106 LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset);
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* uart clock divided by 1 */
<> 144:ef7eb2e8f9f7 109 LPC_SYSCON->UARTCLKDIV = 1;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* disable uart interrupts */
<> 144:ef7eb2e8f9f7 112 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Enable UART clock */
<> 144:ef7eb2e8f9f7 115 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Peripheral reset control to UART, a "1" bring it out of reset. */
<> 144:ef7eb2e8f9f7 118 LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
<> 144:ef7eb2e8f9f7 119 LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 // Derive UART Clock from MainClock
<> 144:ef7eb2e8f9f7 122 UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // set default baud rate and format
<> 144:ef7eb2e8f9f7 125 serial_baud (obj, 9600);
<> 144:ef7eb2e8f9f7 126 serial_format(obj, 8, ParityNone, 1);
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Clear all status bits. */
<> 144:ef7eb2e8f9f7 129 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* enable uart interrupts */
<> 144:ef7eb2e8f9f7 132 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Enable UART interrupt */
<> 144:ef7eb2e8f9f7 135 // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Enable UART */
<> 144:ef7eb2e8f9f7 138 obj->uart->CFG |= UART_EN;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if (is_stdio_uart) {
<> 144:ef7eb2e8f9f7 143 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 144 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 void serial_free(serial_t *obj) {
<> 144:ef7eb2e8f9f7 149 uart_used &= ~(1 << obj->index);
<> 144:ef7eb2e8f9f7 150 serial_irq_ids[obj->index] = 0;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 // serial_baud
<> 144:ef7eb2e8f9f7 154 // set the baud rate, taking in to account the current SystemFrequency
<> 144:ef7eb2e8f9f7 155 void serial_baud(serial_t *obj, int baudrate) {
<> 144:ef7eb2e8f9f7 156 /* Integer divider:
<> 144:ef7eb2e8f9f7 157 BRG = UARTSysClk/(Baudrate * 16) - 1
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 Frational divider:
<> 144:ef7eb2e8f9f7 160 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 where
<> 144:ef7eb2e8f9f7 163 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
<> 144:ef7eb2e8f9f7 166 register is 0xFF.
<> 144:ef7eb2e8f9f7 167 (2) In ADD register value, depending on the value of UartSysClk,
<> 144:ef7eb2e8f9f7 168 baudrate, BRG register value, and SUB register value, be careful
<> 144:ef7eb2e8f9f7 169 about the order of multiplier and divider and make sure any
<> 144:ef7eb2e8f9f7 170 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
<> 144:ef7eb2e8f9f7 171 down below one(integer 0).
<> 144:ef7eb2e8f9f7 172 (3) ADD should be always less than SUB.
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 LPC_SYSCON->UARTFRGDIV = 0xFF;
<> 144:ef7eb2e8f9f7 177 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
<> 144:ef7eb2e8f9f7 178 (baudrate * (obj->uart->BRG + 1))
<> 144:ef7eb2e8f9f7 179 ) - (LPC_SYSCON->UARTFRGDIV + 1);
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 144:ef7eb2e8f9f7 184 // 0: 1 stop bits, 1: 2 stop bits
<> 144:ef7eb2e8f9f7 185 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
<> 144:ef7eb2e8f9f7 186 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
<> 144:ef7eb2e8f9f7 187 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
<> 144:ef7eb2e8f9f7 188 stop_bits -= 1;
<> 144:ef7eb2e8f9f7 189 data_bits -= 7;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 int paritysel;
<> 144:ef7eb2e8f9f7 192 switch (parity) {
<> 144:ef7eb2e8f9f7 193 case ParityNone: paritysel = 0; break;
<> 144:ef7eb2e8f9f7 194 case ParityEven: paritysel = 2; break;
<> 144:ef7eb2e8f9f7 195 case ParityOdd : paritysel = 3; break;
<> 144:ef7eb2e8f9f7 196 default:
<> 144:ef7eb2e8f9f7 197 break;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 // First disable the the usart as described in documentation and then enable while updating CFG
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 // 24.6.1 USART Configuration register
<> 144:ef7eb2e8f9f7 203 // Remark: If software needs to change configuration values, the following sequence should
<> 144:ef7eb2e8f9f7 204 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
<> 144:ef7eb2e8f9f7 205 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
<> 144:ef7eb2e8f9f7 206 // Write the new configuration value, with the ENABLE bit set to 1.
<> 144:ef7eb2e8f9f7 207 obj->uart->CFG &= ~(1 << 0);
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 obj->uart->CFG = (1 << 0) // this will enable the usart
<> 144:ef7eb2e8f9f7 210 | (data_bits << 2)
<> 144:ef7eb2e8f9f7 211 | (paritysel << 4)
<> 144:ef7eb2e8f9f7 212 | (stop_bits << 6);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /******************************************************************************
<> 144:ef7eb2e8f9f7 216 * INTERRUPTS HANDLING
<> 144:ef7eb2e8f9f7 217 ******************************************************************************/
<> 144:ef7eb2e8f9f7 218 static inline void uart_irq(uint32_t iir, uint32_t index) {
<> 144:ef7eb2e8f9f7 219 // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
<> 144:ef7eb2e8f9f7 220 SerialIrq irq_type;
<> 144:ef7eb2e8f9f7 221 switch (iir) {
<> 144:ef7eb2e8f9f7 222 case 1: irq_type = TxIrq; break;
<> 144:ef7eb2e8f9f7 223 case 2: irq_type = RxIrq; break;
<> 144:ef7eb2e8f9f7 224 default: return;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 if (serial_irq_ids[index] != 0)
<> 144:ef7eb2e8f9f7 228 irq_handler(serial_irq_ids[index], irq_type);
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
<> 144:ef7eb2e8f9f7 232 void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
<> 144:ef7eb2e8f9f7 233 void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 236 irq_handler = handler;
<> 144:ef7eb2e8f9f7 237 serial_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
<> 144:ef7eb2e8f9f7 241 IRQn_Type irq_n = (IRQn_Type)0;
<> 144:ef7eb2e8f9f7 242 uint32_t vector = 0;
<> 144:ef7eb2e8f9f7 243 switch ((int)obj->uart) {
<> 144:ef7eb2e8f9f7 244 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
<> 144:ef7eb2e8f9f7 245 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
<> 144:ef7eb2e8f9f7 246 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 if (enable) {
<> 144:ef7eb2e8f9f7 250 obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
<> 144:ef7eb2e8f9f7 251 NVIC_SetVector(irq_n, vector);
<> 144:ef7eb2e8f9f7 252 NVIC_EnableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 253 } else { // disable
<> 144:ef7eb2e8f9f7 254 int all_disabled = 0;
<> 144:ef7eb2e8f9f7 255 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
<> 144:ef7eb2e8f9f7 256 obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
<> 144:ef7eb2e8f9f7 257 all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
<> 144:ef7eb2e8f9f7 258 if (all_disabled)
<> 144:ef7eb2e8f9f7 259 NVIC_DisableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /******************************************************************************
<> 144:ef7eb2e8f9f7 264 * READ/WRITE
<> 144:ef7eb2e8f9f7 265 ******************************************************************************/
<> 144:ef7eb2e8f9f7 266 int serial_getc(serial_t *obj) {
<> 144:ef7eb2e8f9f7 267 while (!serial_readable(obj));
<> 144:ef7eb2e8f9f7 268 return obj->uart->RXDATA;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 void serial_putc(serial_t *obj, int c) {
<> 144:ef7eb2e8f9f7 272 while (!serial_writable(obj));
<> 144:ef7eb2e8f9f7 273 obj->uart->TXDATA = c;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 int serial_readable(serial_t *obj) {
<> 144:ef7eb2e8f9f7 277 return obj->uart->STAT & RXRDY;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 int serial_writable(serial_t *obj) {
<> 144:ef7eb2e8f9f7 281 return obj->uart->STAT & TXRDY;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 void serial_clear(serial_t *obj) {
<> 144:ef7eb2e8f9f7 285 // [TODO]
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 void serial_pinout_tx(PinName tx) {
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 void serial_break_set(serial_t *obj) {
<> 144:ef7eb2e8f9f7 293 obj->uart->CTRL |= TXBRKEN;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 void serial_break_clear(serial_t *obj) {
<> 144:ef7eb2e8f9f7 297 obj->uart->CTRL &= ~TXBRKEN;
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
<> 144:ef7eb2e8f9f7 301 const SWM_Map *swm_rts, *swm_cts;
<> 144:ef7eb2e8f9f7 302 uint32_t regVal_rts, regVal_cts;
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 swm_rts = &SWM_UART_RTS[obj->index];
<> 144:ef7eb2e8f9f7 305 swm_cts = &SWM_UART_CTS[obj->index];
<> 144:ef7eb2e8f9f7 306 regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
<> 144:ef7eb2e8f9f7 307 regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 if (FlowControlNone == type) {
<> 144:ef7eb2e8f9f7 310 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
<> 144:ef7eb2e8f9f7 311 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
<> 144:ef7eb2e8f9f7 312 obj->uart->CFG &= ~CTSEN;
<> 144:ef7eb2e8f9f7 313 return;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
<> 144:ef7eb2e8f9f7 316 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (rxflow << swm_rts->offset);
<> 144:ef7eb2e8f9f7 317 if (FlowControlRTS == type) {
<> 144:ef7eb2e8f9f7 318 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
<> 144:ef7eb2e8f9f7 319 obj->uart->CFG &= ~CTSEN;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
<> 144:ef7eb2e8f9f7 323 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (txflow << swm_cts->offset);
<> 144:ef7eb2e8f9f7 324 obj->uart->CFG |= CTSEN;
<> 144:ef7eb2e8f9f7 325 if (FlowControlCTS == type) {
<> 144:ef7eb2e8f9f7 326 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330