Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c@144:ef7eb2e8f9f7
Child:
151:5eaa88a5bcc7
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 19 #include "pwmout_api.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 // PWM implementation for the LPC43xx using State Configurable Timer (SCT)
<> 144:ef7eb2e8f9f7 25 // * PWM_0 to PWM_15 on mbed use CTOUT_0 to CTOUT_15 outputs on LPC43xx
<> 144:ef7eb2e8f9f7 26 // * Event 0 is PWM period, events 1 to PWM_EVENT_MAX are PWM channels
<> 144:ef7eb2e8f9f7 27 // * Default is unified 32-bit timer, but could be configured to use
<> 144:ef7eb2e8f9f7 28 // a 16-bit timer so a timer is available for other SCT functions
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 // configuration options
<> 144:ef7eb2e8f9f7 31 #define PWM_FREQ_BASE 1000000 // Base frequency 1 MHz = 1000000
<> 144:ef7eb2e8f9f7 32 #define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 // macros
<> 144:ef7eb2e8f9f7 35 #define PWM_SETCOUNT(x) (x - 1) // set count value
<> 144:ef7eb2e8f9f7 36 #define PWM_GETCOUNT(x) (x + 1) // get count value
<> 144:ef7eb2e8f9f7 37 #if (PWM_MODE == 0) // unified 32-bit counter, events 1 to 15
<> 144:ef7eb2e8f9f7 38 #define PWM_EVENT_MAX (CONFIG_SCT_nEV - 1) // Max PWM channels
<> 144:ef7eb2e8f9f7 39 #define PWM_CONFIG SCT_CONFIG_32BIT_COUNTER // default config
<> 144:ef7eb2e8f9f7 40 #define PWM_CTRL &LPC_SCT->CTRL_U // control register
<> 144:ef7eb2e8f9f7 41 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
<> 144:ef7eb2e8f9f7 42 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
<> 144:ef7eb2e8f9f7 43 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
<> 144:ef7eb2e8f9f7 44 #define PWM_EVT_MASK (1 << 12) // event control mask
<> 144:ef7eb2e8f9f7 45 #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
<> 144:ef7eb2e8f9f7 46 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].U // match register
<> 144:ef7eb2e8f9f7 47 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].U // 32-bit match reload register
<> 144:ef7eb2e8f9f7 48 #elif (PWM_MODE == 1) // 16-bit low counter, events 1 to 7
<> 144:ef7eb2e8f9f7 49 #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
<> 144:ef7eb2e8f9f7 50 #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
<> 144:ef7eb2e8f9f7 51 #define PWM_CTRL &LPC_SCT->CTRL_L // control register
<> 144:ef7eb2e8f9f7 52 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
<> 144:ef7eb2e8f9f7 53 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
<> 144:ef7eb2e8f9f7 54 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
<> 144:ef7eb2e8f9f7 55 #define PWM_EVT_MASK (1 << 12) // event control mask
<> 144:ef7eb2e8f9f7 56 #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
<> 144:ef7eb2e8f9f7 57 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].L // match register
<> 144:ef7eb2e8f9f7 58 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].L // 16-bit match reload register
<> 144:ef7eb2e8f9f7 59 #elif (PWM_MODE == 2) // 16-bit high counter, events 1 to 7
<> 144:ef7eb2e8f9f7 60 // [TODO] use events 8 to 15 on mode 2
<> 144:ef7eb2e8f9f7 61 #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
<> 144:ef7eb2e8f9f7 62 #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
<> 144:ef7eb2e8f9f7 63 #define PWM_CTRL &LPC_SCT->CTRL_H // control register
<> 144:ef7eb2e8f9f7 64 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
<> 144:ef7eb2e8f9f7 65 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
<> 144:ef7eb2e8f9f7 66 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
<> 144:ef7eb2e8f9f7 67 #define PWM_EVT_MASK ((1 << 4) | (1 << 12)) // event control mask
<> 144:ef7eb2e8f9f7 68 #define PWM_LIMIT &LPC_SCT->LIMIT_H // limit register
<> 144:ef7eb2e8f9f7 69 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].H // match register
<> 144:ef7eb2e8f9f7 70 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].H // 16-bit match reload register
<> 144:ef7eb2e8f9f7 71 #else
<> 144:ef7eb2e8f9f7 72 #error "PWM mode not implemented"
<> 144:ef7eb2e8f9f7 73 #endif
<> 144:ef7eb2e8f9f7 74 #define PWM_MR0 PWM_MR(0) // MR register 0 is for period
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 static uint8_t event = 0;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 // PORT ID, PWM ID, Pin function
<> 144:ef7eb2e8f9f7 79 static const PinMap PinMap_PWM[] = {
<> 144:ef7eb2e8f9f7 80 {P1_1, PWM_7, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 81 {P1_2, PWM_6, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 82 {P1_3, PWM_8, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 83 {P1_4, PWM_9, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 84 {P1_5, PWM_10, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 85 {P1_7, PWM_13, (SCU_PINIO_FAST | 2)},
<> 144:ef7eb2e8f9f7 86 {P1_8, PWM_12, (SCU_PINIO_FAST | 2)},
<> 144:ef7eb2e8f9f7 87 {P1_9, PWM_11, (SCU_PINIO_FAST | 2)},
<> 144:ef7eb2e8f9f7 88 {P1_10, PWM_14, (SCU_PINIO_FAST | 2)},
<> 144:ef7eb2e8f9f7 89 {P1_11, PWM_15, (SCU_PINIO_FAST | 2)},
<> 144:ef7eb2e8f9f7 90 {P2_7, PWM_1, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 91 {P2_8, PWM_0, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 92 {P2_9, PWM_3, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 93 {P2_10, PWM_2, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 94 {P2_11, PWM_5, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 95 {P2_12, PWM_4, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 96 {P4_1, PWM_1, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 97 {P4_2, PWM_0, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 98 {P4_3, PWM_3, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 99 {P4_4, PWM_2, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 100 {P4_5, PWM_5, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 101 {P4_6, PWM_4, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 102 {P6_5, PWM_6, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 103 {P6_12, PWM_7, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 104 {P7_0, PWM_14, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 105 {P7_1, PWM_15, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 106 {P7_4, PWM_13, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 107 {P7_5, PWM_12, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 108 {P7_6, PWM_11, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 109 {P7_7, PWM_8, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 110 {PA_4, PWM_9, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 111 {PB_0, PWM_10, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 112 {PB_1, PWM_6, (SCU_PINIO_FAST | 5)},
<> 144:ef7eb2e8f9f7 113 {PB_2, PWM_7, (SCU_PINIO_FAST | 5)},
<> 144:ef7eb2e8f9f7 114 {PB_3, PWM_8, (SCU_PINIO_FAST | 5)},
<> 144:ef7eb2e8f9f7 115 {PD_0, PWM_15, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 116 {PD_2, PWM_7, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 117 {PD_3, PWM_6, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 118 {PD_4, PWM_8, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 119 {PD_5, PWM_9, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 120 {PD_6, PWM_10, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 121 {PD_9, PWM_13, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 122 {PD_11, PWM_14, (SCU_PINIO_FAST | 6)},
<> 144:ef7eb2e8f9f7 123 {PD_12, PWM_10, (SCU_PINIO_FAST | 6)},
<> 144:ef7eb2e8f9f7 124 {PD_13, PWM_13, (SCU_PINIO_FAST | 6)},
<> 144:ef7eb2e8f9f7 125 {PD_14, PWM_11, (SCU_PINIO_FAST | 6)},
<> 144:ef7eb2e8f9f7 126 {PD_15, PWM_8, (SCU_PINIO_FAST | 6)},
<> 144:ef7eb2e8f9f7 127 {PD_16, PWM_12, (SCU_PINIO_FAST | 6)},
<> 144:ef7eb2e8f9f7 128 {PE_5, PWM_3, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 129 {PE_6, PWM_2, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 130 {PE_7, PWM_5, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 131 {PE_8, PWM_4, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 132 {PE_11, PWM_12, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 133 {PE_12, PWM_11, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 134 {PE_13, PWM_14, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 135 {PE_15, PWM_0, (SCU_PINIO_FAST | 1)},
<> 144:ef7eb2e8f9f7 136 {PF_9, PWM_1, (SCU_PINIO_FAST | 2)},
<> 144:ef7eb2e8f9f7 137 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 138 };
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 static unsigned int pwm_clock_mhz;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 static void _pwmout_dev_init() {
<> 144:ef7eb2e8f9f7 143 uint32_t i;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 // set SCT clock and config
<> 144:ef7eb2e8f9f7 146 LPC_CCU1->CLKCCU[CLK_MX_SCT].CFG = (1 << 0); // enable SCT clock in CCU1
<> 144:ef7eb2e8f9f7 147 LPC_SCT->CONFIG |= PWM_CONFIG; // set config options
<> 144:ef7eb2e8f9f7 148 *PWM_CTRL |= PWM_HALT; // set HALT bit to stop counter
<> 144:ef7eb2e8f9f7 149 // clear counter and set prescaler for desired freq
<> 144:ef7eb2e8f9f7 150 *PWM_CTRL |= PWM_CLEAR | PWM_PRE(SystemCoreClock / PWM_FREQ_BASE - 1);
<> 144:ef7eb2e8f9f7 151 pwm_clock_mhz = PWM_FREQ_BASE / 1000000;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 // configure SCT events
<> 144:ef7eb2e8f9f7 154 for (i = 0; i < PWM_EVENT_MAX; i++) {
<> 144:ef7eb2e8f9f7 155 *PWM_MATCH(i) = 0; // match register
<> 144:ef7eb2e8f9f7 156 *PWM_MR(i) = 0; // match reload register
<> 144:ef7eb2e8f9f7 157 LPC_SCT->EVENT[i].STATE = 0xFFFFFFFF; // event happens in all states
<> 144:ef7eb2e8f9f7 158 LPC_SCT->EVENT[i].CTRL = (i << 0) | PWM_EVT_MASK; // match condition only
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 *PWM_LIMIT = (1 << 0) ; // set event 0 as limit
<> 144:ef7eb2e8f9f7 161 // initialize period to 20ms: standard for servos, and fine for e.g. brightness control
<> 144:ef7eb2e8f9f7 162 *PWM_MR0 = PWM_SETCOUNT((uint32_t)(((20 * PWM_FREQ_BASE) / 1000000) * 1000));
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 // initialize SCT outputs
<> 144:ef7eb2e8f9f7 165 for (i = 0; i < CONFIG_SCT_nOU; i++) {
<> 144:ef7eb2e8f9f7 166 LPC_SCT->OUT[i].SET = (1 << 0); // event 0 will set SCTOUT_xx
<> 144:ef7eb2e8f9f7 167 LPC_SCT->OUT[i].CLR = 0; // set clear event when duty cycle
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169 LPC_SCT->OUTPUT = 0; // default outputs to clear
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 *PWM_CTRL &= ~PWM_HALT; // clear HALT bit to start counter
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 void pwmout_init(pwmout_t* obj, PinName pin) {
<> 144:ef7eb2e8f9f7 175 // determine the channel
<> 144:ef7eb2e8f9f7 176 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
<> 144:ef7eb2e8f9f7 177 MBED_ASSERT((pwm != (PWMName)NC) && (event < PWM_EVENT_MAX));
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 // init SCT clock and outputs on first PWM init
<> 144:ef7eb2e8f9f7 180 if (event == 0) {
<> 144:ef7eb2e8f9f7 181 _pwmout_dev_init();
<> 144:ef7eb2e8f9f7 182 }
<> 144:ef7eb2e8f9f7 183 // init PWM object
<> 144:ef7eb2e8f9f7 184 event++;
<> 144:ef7eb2e8f9f7 185 obj->pwm = pwm; // pwm output
<> 144:ef7eb2e8f9f7 186 obj->mr = event; // index of match reload register
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 // initial duty cycle is 0
<> 144:ef7eb2e8f9f7 189 pwmout_write(obj, 0);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 // Wire pinout
<> 144:ef7eb2e8f9f7 192 pinmap_pinout(pin, PinMap_PWM);
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 void pwmout_free(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 196 // [TODO]
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 void pwmout_write(pwmout_t* obj, float value) {
<> 144:ef7eb2e8f9f7 200 if (value < 0.0f) {
<> 144:ef7eb2e8f9f7 201 value = 0.0;
<> 144:ef7eb2e8f9f7 202 } else if (value > 1.0f) {
<> 144:ef7eb2e8f9f7 203 value = 1.0;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 // set new pulse width
<> 144:ef7eb2e8f9f7 207 uint32_t us = (uint32_t)((float)PWM_GETCOUNT(*PWM_MR0) * value) * pwm_clock_mhz;
<> 144:ef7eb2e8f9f7 208 pwmout_pulsewidth_us(obj, us);
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 float pwmout_read(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 212 float v = (float)PWM_GETCOUNT(*PWM_MR(obj->mr)) / (float)PWM_GETCOUNT(*PWM_MR0);
<> 144:ef7eb2e8f9f7 213 return (v > 1.0f) ? (1.0f) : (v);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 void pwmout_period(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 217 pwmout_period_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 void pwmout_period_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 221 pwmout_period_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 // Set the PWM period, keeping the duty cycle the same.
<> 144:ef7eb2e8f9f7 225 void pwmout_period_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 226 // calculate number of ticks
<> 144:ef7eb2e8f9f7 227 uint32_t ticks = pwm_clock_mhz * us;
<> 144:ef7eb2e8f9f7 228 uint32_t old_ticks = PWM_GETCOUNT(*PWM_MR0);
<> 144:ef7eb2e8f9f7 229 uint32_t i, v;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 // set new period
<> 144:ef7eb2e8f9f7 232 *PWM_MR0 = PWM_SETCOUNT(ticks);
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 // Scale pulse widths to preserve the duty ratio
<> 144:ef7eb2e8f9f7 235 for (i = 1; i < PWM_EVENT_MAX; i++) {
<> 144:ef7eb2e8f9f7 236 v = PWM_GETCOUNT(*PWM_MR(i));
<> 144:ef7eb2e8f9f7 237 if (v > 1) {
<> 144:ef7eb2e8f9f7 238 v = (v * ticks) / old_ticks;
<> 144:ef7eb2e8f9f7 239 *PWM_MR(i) = PWM_SETCOUNT(v);
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 245 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 249 pwmout_pulsewidth_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 253 // calculate number of ticks
<> 144:ef7eb2e8f9f7 254 uint32_t v = pwm_clock_mhz * us;
<> 144:ef7eb2e8f9f7 255 //MBED_ASSERT(PWM_GETCOUNT(*PWM_MR0) >= v);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 if (v > 0) {
<> 144:ef7eb2e8f9f7 258 // set new match register value and enable SCT output
<> 144:ef7eb2e8f9f7 259 *PWM_MR(obj->mr) = PWM_SETCOUNT(v);
<> 144:ef7eb2e8f9f7 260 LPC_SCT->OUT[obj->pwm].CLR = (1 << obj->mr); // on event will clear PWM_XX
<> 144:ef7eb2e8f9f7 261 } else {
<> 144:ef7eb2e8f9f7 262 // set match to zero and disable SCT output
<> 144:ef7eb2e8f9f7 263 *PWM_MR(obj->mr) = 0;
<> 144:ef7eb2e8f9f7 264 LPC_SCT->OUT[obj->pwm].CLR = 0;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266 }