Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
174:b96e65c34a4d 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <stddef.h>
<> 144:ef7eb2e8f9f7 17 #include "us_ticker_api.h"
<> 144:ef7eb2e8f9f7 18 #include "PeripheralNames.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 //New, using MRT instead of SCT, needed to free up SCT for PWM
<> 144:ef7eb2e8f9f7 21 //Ported from LPC824 libs
<> 144:ef7eb2e8f9f7 22 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 23 static int us_ticker_interrupt_inited = 0;
<> 144:ef7eb2e8f9f7 24 unsigned int ticker_fullcount_us;
<> 144:ef7eb2e8f9f7 25 unsigned long int ticker_expired_count_us = 0;
<> 144:ef7eb2e8f9f7 26 int MRT_Clock_MHz;
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #define US_TICKER_TIMER_IRQn MRT_IRQn
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 void us_ticker_init(void) {
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 if (us_ticker_inited)
<> 144:ef7eb2e8f9f7 33 return;
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 // Calculate MRT clock value (MRT has no prescaler)
<> 144:ef7eb2e8f9f7 38 MRT_Clock_MHz = (SystemCoreClock / 1000000);
<> 144:ef7eb2e8f9f7 39 // Calculate fullcounter value in us (MRT has 31 bits and clock is 30 MHz)
<> 144:ef7eb2e8f9f7 40 ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz;
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 // Enable the MRT clock
<> 144:ef7eb2e8f9f7 43 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 // Clear peripheral reset the MRT
<> 144:ef7eb2e8f9f7 46 LPC_SYSCON->PRESETCTRL |= (1 << 7);
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
<> 144:ef7eb2e8f9f7 49 LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
<> 144:ef7eb2e8f9f7 50 // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt
<> 144:ef7eb2e8f9f7 51 LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0);
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
<> 144:ef7eb2e8f9f7 54 LPC_MRT->INTVAL1 = 0x80000000UL;
<> 144:ef7eb2e8f9f7 55 // Disable ch1 interrupt, Mode 0 is Repeat Interrupt
<> 144:ef7eb2e8f9f7 56 LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0);
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 void us_ticker_interrupt_init(void) {
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 if (us_ticker_interrupt_inited)
<> 144:ef7eb2e8f9f7 62 return;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 us_ticker_interrupt_inited = 1;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 // Set MRT interrupt vector
<> 144:ef7eb2e8f9f7 67 NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
<> 144:ef7eb2e8f9f7 68 NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 //TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc)
<> 144:ef7eb2e8f9f7 72 uint32_t us_ticker_read() {
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 if (!us_ticker_inited)
<> 144:ef7eb2e8f9f7 75 us_ticker_init();
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 // Generate ticker value
<> 144:ef7eb2e8f9f7 78 // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
<> 144:ef7eb2e8f9f7 79 // Calculate expected value using current count and number of expired times to mimic a 32bit timer @ 1 MHz
<> 144:ef7eb2e8f9f7 80 //
<> 144:ef7eb2e8f9f7 81 // ticker_expired_count_us
<> 144:ef7eb2e8f9f7 82 // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and
<> 144:ef7eb2e8f9f7 83 // corrects that back to us counts.
<> 144:ef7eb2e8f9f7 84 //
<> 144:ef7eb2e8f9f7 85 // (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz
<> 144:ef7eb2e8f9f7 86 // The counter is a 31bit downcounter from 7FFFFFFF so correct to actual count-up value and correct
<> 144:ef7eb2e8f9f7 87 // for 30 counts per us.
<> 144:ef7eb2e8f9f7 88 //
<> 144:ef7eb2e8f9f7 89 // Added up these 2 parts result in current us time returned as 32 bits.
<> 144:ef7eb2e8f9f7 90 return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us;
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 //TIMER1 is used for Timestamped interrupts (Ticker(), Timeout())
<> 144:ef7eb2e8f9f7 94 void us_ticker_set_interrupt(timestamp_t timestamp) {
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 if (!us_ticker_interrupt_inited)
<> 144:ef7eb2e8f9f7 97 us_ticker_interrupt_init();
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
<> 144:ef7eb2e8f9f7 100 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
<> 144:ef7eb2e8f9f7 101 // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz.
<> 144:ef7eb2e8f9f7 102 // The calculated counter interval until the next timestamp will be truncated and an
<> 144:ef7eb2e8f9f7 103 // 'early' interrupt will be generated in case the max required count interval exceeds
<> 144:ef7eb2e8f9f7 104 // the available 31 bits space. However, the mbed us_ticker interrupt handler will
<> 144:ef7eb2e8f9f7 105 // check current time against the next scheduled timestamp and simply re-issue the
<> 144:ef7eb2e8f9f7 106 // same interrupt again when needed. The calculated counter interval will now be smaller.
<> 144:ef7eb2e8f9f7 107 LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // Enable interrupt
<> 144:ef7eb2e8f9f7 110 LPC_MRT->CTRL1 |= 1;
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
AnnaBridge 174:b96e65c34a4d 113 void us_ticker_fire_interrupt(void)
AnnaBridge 174:b96e65c34a4d 114 {
AnnaBridge 174:b96e65c34a4d 115 NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
AnnaBridge 174:b96e65c34a4d 116 }
AnnaBridge 174:b96e65c34a4d 117
<> 144:ef7eb2e8f9f7 118 //Disable Timestamped interrupts triggered by TIMER1
<> 144:ef7eb2e8f9f7 119 void us_ticker_disable_interrupt() {
<> 144:ef7eb2e8f9f7 120 //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
<> 144:ef7eb2e8f9f7 121 LPC_MRT->CTRL1 &= ~1;
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 void us_ticker_clear_interrupt() {
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
<> 144:ef7eb2e8f9f7 127 if (LPC_MRT->STAT1 & 1)
<> 144:ef7eb2e8f9f7 128 LPC_MRT->STAT1 = 1;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 //Timer0 for us counter (31 bits downcounter @ SystemCoreClock)
<> 144:ef7eb2e8f9f7 131 if (LPC_MRT->STAT0 & 1) {
<> 144:ef7eb2e8f9f7 132 LPC_MRT->STAT0 = 1;
<> 144:ef7eb2e8f9f7 133 // ticker_expired_count_us = (ticker_expired * 0x80000000UL) / MRT_Clock_MHz
<> 144:ef7eb2e8f9f7 134 // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and
<> 144:ef7eb2e8f9f7 135 // the multiplication/division corrects that back to us counts.
<> 144:ef7eb2e8f9f7 136 ticker_expired_count_us += ticker_fullcount_us;
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138 }