Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
149:156823d33999 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "pwmout_api.h"
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 20 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 // Ported from LPC824 and adapted.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #if DEVICE_PWMOUT
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #define PWM_IRQn SCT_IRQn
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 // Bit flags for used SCT Outputs
<> 144:ef7eb2e8f9f7 29 static unsigned char sct_used = 0;
<> 144:ef7eb2e8f9f7 30 static int sct_inited = 0;
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 // Find available output channel
<> 144:ef7eb2e8f9f7 33 // Max number of PWM outputs is 4 on LPC812
<> 144:ef7eb2e8f9f7 34 static int get_available_sct() {
<> 144:ef7eb2e8f9f7 35 int i;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 // Find available output channel 0..3
<> 144:ef7eb2e8f9f7 38 // Also need one Match register per channel
<> 144:ef7eb2e8f9f7 39 for (i = 0; i < CONFIG_SCT_nOU; i++) {
<> 144:ef7eb2e8f9f7 40 if ((sct_used & (1 << i)) == 0)
<> 144:ef7eb2e8f9f7 41 return i;
<> 144:ef7eb2e8f9f7 42 }
<> 144:ef7eb2e8f9f7 43 return -1;
<> 144:ef7eb2e8f9f7 44 }
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 // Any Port pin may be used for PWM.
<> 144:ef7eb2e8f9f7 47 // Max number of PWM outputs is 4
<> 144:ef7eb2e8f9f7 48 void pwmout_init(pwmout_t* obj, PinName pin) {
<> 144:ef7eb2e8f9f7 49 MBED_ASSERT(pin != (PinName)NC);
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 int sct_n = get_available_sct();
<> 144:ef7eb2e8f9f7 52 if (sct_n == -1) {
<> 144:ef7eb2e8f9f7 53 error("No available SCT Output");
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 sct_used |= (1 << sct_n);
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 obj->pwm = (LPC_SCT_TypeDef*)LPC_SCT;
<> 144:ef7eb2e8f9f7 59 obj->pwm_ch = sct_n;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 LPC_SCT_TypeDef* pwm = obj->pwm;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 // Init SCT on first use
<> 144:ef7eb2e8f9f7 64 if (! sct_inited) {
<> 144:ef7eb2e8f9f7 65 sct_inited = 1;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 // Enable the SCT clock
<> 144:ef7eb2e8f9f7 68 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 // Clear peripheral reset the SCT:
<> 144:ef7eb2e8f9f7 71 LPC_SYSCON->PRESETCTRL |= (1 << 8);
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 // Two 16-bit counters, autolimit (ie reset on Match_0)
<> 144:ef7eb2e8f9f7 74 pwm->CONFIG |= ((0x3 << 17) | 0x01);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 // halt and clear the counter
<> 144:ef7eb2e8f9f7 77 pwm->CTRL_U |= (1 << 2) | (1 << 3);
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 // System Clock (30 Mhz) -> Prescaler -> us_ticker (1 MHz)
<> 144:ef7eb2e8f9f7 80 pwm->CTRL_U &= ~(0x7F << 5);
<> 144:ef7eb2e8f9f7 81 pwm->CTRL_U |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5);
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 pwm->EVENT[0].CTRL = (1 << 12) | 0; // Event_0 on Match_0
<> 144:ef7eb2e8f9f7 84 pwm->EVENT[0].STATE = 0xFFFFFFFF; // All states
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 // unhalt the counter:
<> 144:ef7eb2e8f9f7 87 // - clearing bit 2 of the CTRL register
<> 144:ef7eb2e8f9f7 88 pwm->CTRL_U &= ~(1 << 2);
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 // LPC81x has only one SCT and 4 Outputs
<> 144:ef7eb2e8f9f7 93 // LPC82x has only one SCT and 6 Outputs
<> 144:ef7eb2e8f9f7 94 // LPC1549 has 4 SCTs and 16 Outputs
<> 144:ef7eb2e8f9f7 95 switch(sct_n) {
<> 144:ef7eb2e8f9f7 96 case 0:
<> 144:ef7eb2e8f9f7 97 // SCTx_OUT0
<> 144:ef7eb2e8f9f7 98 LPC_SWM->PINASSIGN[6] &= ~0xFF000000;
<> 144:ef7eb2e8f9f7 99 LPC_SWM->PINASSIGN[6] |= (pin << 24);
<> 144:ef7eb2e8f9f7 100 break;
<> 144:ef7eb2e8f9f7 101 case 1:
<> 144:ef7eb2e8f9f7 102 // SCTx_OUT1
<> 144:ef7eb2e8f9f7 103 LPC_SWM->PINASSIGN[7] &= ~0x000000FF;
<> 144:ef7eb2e8f9f7 104 LPC_SWM->PINASSIGN[7] |= (pin);
<> 144:ef7eb2e8f9f7 105 break;
<> 144:ef7eb2e8f9f7 106 case 2:
<> 144:ef7eb2e8f9f7 107 // SCTx_OUT2
<> 144:ef7eb2e8f9f7 108 LPC_SWM->PINASSIGN[7] &= ~0x0000FF00;
<> 144:ef7eb2e8f9f7 109 LPC_SWM->PINASSIGN[7] |= (pin << 8);
<> 144:ef7eb2e8f9f7 110 break;
<> 144:ef7eb2e8f9f7 111 case 3:
<> 144:ef7eb2e8f9f7 112 // SCTx_OUT3
<> 144:ef7eb2e8f9f7 113 LPC_SWM->PINASSIGN[7] &= ~0x00FF0000;
<> 144:ef7eb2e8f9f7 114 LPC_SWM->PINASSIGN[7] |= (pin << 16);
<> 144:ef7eb2e8f9f7 115 break;
<> 144:ef7eb2e8f9f7 116 default:
<> 144:ef7eb2e8f9f7 117 break;
<> 144:ef7eb2e8f9f7 118 }
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 pwm->EVENT[sct_n + 1].CTRL = (1 << 12) | (sct_n + 1); // Event_n on Match_n
<> 144:ef7eb2e8f9f7 121 pwm->EVENT[sct_n + 1].STATE = 0xFFFFFFFF; // All states
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 pwm->OUT[sct_n].SET = (1 << 0); // All PWM channels are SET on Event_0
<> 144:ef7eb2e8f9f7 124 pwm->OUT[sct_n].CLR = (1 << (sct_n + 1)); // PWM ch is CLRed on Event_(ch+1)
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 // default to 20ms: standard for servos, and fine for e.g. brightness control
<> 144:ef7eb2e8f9f7 127 pwmout_period_ms(obj, 20); // 20ms period
<> 144:ef7eb2e8f9f7 128 pwmout_write (obj, 0.0); // 0ms pulsewidth, dutycycle 0
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 void pwmout_free(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 132 // PWM channel is now free
<> 144:ef7eb2e8f9f7 133 sct_used &= ~(1 << obj->pwm_ch);
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 // Disable the SCT clock when all channels free
<> 144:ef7eb2e8f9f7 136 if (sct_used == 0) {
<> 144:ef7eb2e8f9f7 137 LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
<> 144:ef7eb2e8f9f7 138 sct_inited = 0;
<> 144:ef7eb2e8f9f7 139 };
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 // Set new dutycycle (0.0 .. 1.0)
<> 144:ef7eb2e8f9f7 143 void pwmout_write(pwmout_t* obj, float value) {
<> 144:ef7eb2e8f9f7 144 //value is new dutycycle
<> 144:ef7eb2e8f9f7 145 if (value < 0.0f) {
<> 144:ef7eb2e8f9f7 146 value = 0.0;
<> 144:ef7eb2e8f9f7 147 } else if (value > 1.0f) {
<> 144:ef7eb2e8f9f7 148 value = 1.0;
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 // Match_0 is PWM period. Compute new endtime of pulse for current channel
<> 144:ef7eb2e8f9f7 152 uint32_t t_off = (uint32_t)((float)(obj->pwm->MATCHREL[0].U) * value);
<> 144:ef7eb2e8f9f7 153 obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = t_off; // New endtime
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 // Clear OxRES (conflict resolution register) bit first, effect of simultaneous set and clear on output x
<> 144:ef7eb2e8f9f7 156 int offset = (obj->pwm_ch * 2);
<> 144:ef7eb2e8f9f7 157 obj->pwm->RES &= ~(0x3 << offset);
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 if (value == 0.0f) { // duty is 0%
<> 144:ef7eb2e8f9f7 160 // Clear output
<> 144:ef7eb2e8f9f7 161 obj->pwm->RES |= (0x2 << offset);
<> 144:ef7eb2e8f9f7 162 // Set CLR event to be same as SET event, makes output to be 0 (low)
<> 144:ef7eb2e8f9f7 163 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << 0);
<> 144:ef7eb2e8f9f7 164 } else {
<> 144:ef7eb2e8f9f7 165 // Set output
<> 144:ef7eb2e8f9f7 166 obj->pwm->RES |= (0x1 << offset);
<> 144:ef7eb2e8f9f7 167 // Use normal CLR event (current SCT ch + 1)
<> 144:ef7eb2e8f9f7 168 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << ((obj->pwm_ch) + 1));
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 // Get dutycycle (0.0 .. 1.0)
<> 144:ef7eb2e8f9f7 173 float pwmout_read(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 174 uint32_t t_period = obj->pwm->MATCHREL[0].U;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 //Sanity check
<> 144:ef7eb2e8f9f7 177 if (t_period == 0) {
<> 144:ef7eb2e8f9f7 178 return 0.0;
<> 144:ef7eb2e8f9f7 179 };
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U;
<> 144:ef7eb2e8f9f7 182 float v = (float)t_off/(float)t_period;
<> 144:ef7eb2e8f9f7 183 //Sanity check
<> 144:ef7eb2e8f9f7 184 return (v > 1.0f) ? (1.0f) : (v);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 // Set the PWM period, keeping the duty cycle the same (for this channel only!).
<> 144:ef7eb2e8f9f7 188 void pwmout_period(pwmout_t* obj, float seconds){
<> 144:ef7eb2e8f9f7 189 pwmout_period_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 // Set the PWM period, keeping the duty cycle the same (for this channel only!).
<> 144:ef7eb2e8f9f7 193 void pwmout_period_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 194 pwmout_period_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 // Set the PWM period, keeping the duty cycle the same (for this channel only!).
<> 144:ef7eb2e8f9f7 198 void pwmout_period_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 uint32_t t_period = obj->pwm->MATCHREL[0].U; // Current PWM period
<> 144:ef7eb2e8f9f7 201 obj->pwm->MATCHREL[0].U = (uint32_t)us; // New PWM period
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 // Sanity check
<> 144:ef7eb2e8f9f7 204 if (t_period == 0) {
<> 144:ef7eb2e8f9f7 205 return;
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207 else {
<> 144:ef7eb2e8f9f7 208 int cnt = sct_used;
<> 144:ef7eb2e8f9f7 209 int ch = 0;
<> 144:ef7eb2e8f9f7 210 // Update match period for exising PWM channels
<> 144:ef7eb2e8f9f7 211 do {
<> 144:ef7eb2e8f9f7 212 // Get current pulse width
<> 144:ef7eb2e8f9f7 213 uint32_t t_off = obj->pwm->MATCHREL[ch + 1].U;
<> 144:ef7eb2e8f9f7 214 // Get the duty
<> 144:ef7eb2e8f9f7 215 float v = (float)t_off/(float)t_period;
<> 144:ef7eb2e8f9f7 216 // Update pulse width for this channel
<> 144:ef7eb2e8f9f7 217 obj->pwm->MATCHREL[ch + 1].U = (uint32_t)((float)us * (float)v);
<> 144:ef7eb2e8f9f7 218 // Get next used SCT channel
<> 144:ef7eb2e8f9f7 219 cnt = cnt >> 1;
<> 144:ef7eb2e8f9f7 220 ch++;
<> 144:ef7eb2e8f9f7 221 } while (cnt != 0);
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 //Set pulsewidth
<> 144:ef7eb2e8f9f7 227 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 228 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 //Set pulsewidth
<> 144:ef7eb2e8f9f7 232 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms){
<> 144:ef7eb2e8f9f7 233 pwmout_pulsewidth_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 //Set pulsewidth
<> 144:ef7eb2e8f9f7 237 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 238 if (us == 0) { // pulse width is 0
<> 144:ef7eb2e8f9f7 239 // Set CLR event to be same as SET event, makes output to be 0 (low)
<> 144:ef7eb2e8f9f7 240 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << 0);
<> 144:ef7eb2e8f9f7 241 } else {
<> 144:ef7eb2e8f9f7 242 // Use normal CLR event (current SCT ch + 1)
<> 144:ef7eb2e8f9f7 243 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << ((obj->pwm_ch) + 1));
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245 //Should add Sanity check to make sure pulsewidth < period!
<> 144:ef7eb2e8f9f7 246 obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = (uint32_t)us; // New endtime for this channel
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 #endif