mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c
Dependents: Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay
Fork of mbed-dev by
targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c@177:619788de047e, 2017-11-07 (annotated)
- Committer:
- maxxir
- Date:
- Tue Nov 07 16:46:29 2017 +0000
- Revision:
- 177:619788de047e
- Parent:
- 174:b96e65c34a4d
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..; Used direct RTC register manipulation for STM32F1xx; rtc_read() && rtc_write() (native rtc_init() - works good); also added stub for non-working on STM32F1xx rtc_read_subseconds().
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | * |
<> | 144:ef7eb2e8f9f7 | 16 | * Ported to NXP LPC43XX by Micromint USA <support@micromint.com> |
<> | 144:ef7eb2e8f9f7 | 17 | */ |
<> | 144:ef7eb2e8f9f7 | 18 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 19 | #include "us_ticker_api.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "PeripheralNames.h" |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | #define US_TICKER_TIMER ((LPC_TIMER_T *)LPC_TIMER3_BASE) |
<> | 144:ef7eb2e8f9f7 | 23 | #define US_TICKER_TIMER_IRQn TIMER3_IRQn |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | int us_ticker_inited = 0; |
<> | 144:ef7eb2e8f9f7 | 26 | |
<> | 144:ef7eb2e8f9f7 | 27 | void us_ticker_init(void) { |
<> | 144:ef7eb2e8f9f7 | 28 | if (us_ticker_inited) return; |
<> | 144:ef7eb2e8f9f7 | 29 | us_ticker_inited = 1; |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | US_TICKER_TIMER->CTCR = 0x0; // timer mode |
<> | 144:ef7eb2e8f9f7 | 32 | uint32_t PCLK = SystemCoreClock; |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | US_TICKER_TIMER->TCR = 0x2; // reset |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) |
<> | 144:ef7eb2e8f9f7 | 37 | US_TICKER_TIMER->PR = prescale - 1; |
<> | 144:ef7eb2e8f9f7 | 38 | US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0 |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); |
<> | 144:ef7eb2e8f9f7 | 41 | NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
<> | 144:ef7eb2e8f9f7 | 42 | } |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | uint32_t us_ticker_read() { |
<> | 144:ef7eb2e8f9f7 | 45 | if (!us_ticker_inited) |
<> | 144:ef7eb2e8f9f7 | 46 | us_ticker_init(); |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | return US_TICKER_TIMER->TC; |
<> | 144:ef7eb2e8f9f7 | 49 | } |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
<> | 144:ef7eb2e8f9f7 | 52 | // set match value |
<> | 144:ef7eb2e8f9f7 | 53 | US_TICKER_TIMER->MR[0] = (uint32_t)timestamp; |
<> | 144:ef7eb2e8f9f7 | 54 | // enable match interrupt |
<> | 144:ef7eb2e8f9f7 | 55 | US_TICKER_TIMER->MCR |= 1; |
<> | 144:ef7eb2e8f9f7 | 56 | } |
<> | 144:ef7eb2e8f9f7 | 57 | |
AnnaBridge | 174:b96e65c34a4d | 58 | void us_ticker_fire_interrupt(void) |
AnnaBridge | 174:b96e65c34a4d | 59 | { |
AnnaBridge | 174:b96e65c34a4d | 60 | NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); |
AnnaBridge | 174:b96e65c34a4d | 61 | } |
AnnaBridge | 174:b96e65c34a4d | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | void us_ticker_disable_interrupt(void) { |
<> | 144:ef7eb2e8f9f7 | 64 | US_TICKER_TIMER->MCR &= ~1; |
<> | 144:ef7eb2e8f9f7 | 65 | } |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | void us_ticker_clear_interrupt(void) { |
<> | 144:ef7eb2e8f9f7 | 68 | US_TICKER_TIMER->IR = 1; |
<> | 144:ef7eb2e8f9f7 | 69 | } |