Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC11U6X/PeripheralNames.h@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
149:156823d33999 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #ifndef MBED_PERIPHERALNAMES_H
<> 144:ef7eb2e8f9f7 17 #define MBED_PERIPHERALNAMES_H
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 22 extern "C" {
<> 144:ef7eb2e8f9f7 23 #endif
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 typedef enum {
<> 144:ef7eb2e8f9f7 26 UART_0 = (int)LPC_USART0_BASE,
<> 144:ef7eb2e8f9f7 27 UART_1 = (int)LPC_USART1_BASE,
<> 144:ef7eb2e8f9f7 28 UART_2 = (int)LPC_USART2_BASE,
<> 144:ef7eb2e8f9f7 29 UART_3 = (int)LPC_USART3_BASE,
<> 144:ef7eb2e8f9f7 30 UART_4 = (int)LPC_USART4_BASE,
<> 144:ef7eb2e8f9f7 31 } UARTName;
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 typedef enum {
<> 144:ef7eb2e8f9f7 34 ADC_0 = 0,
<> 144:ef7eb2e8f9f7 35 ADC_1,
<> 144:ef7eb2e8f9f7 36 ADC_2,
<> 144:ef7eb2e8f9f7 37 ADC_3,
<> 144:ef7eb2e8f9f7 38 ADC_4,
<> 144:ef7eb2e8f9f7 39 ADC_5,
<> 144:ef7eb2e8f9f7 40 ADC_6,
<> 144:ef7eb2e8f9f7 41 ADC_7,
<> 144:ef7eb2e8f9f7 42 ADC_8,
<> 144:ef7eb2e8f9f7 43 ADC_9,
<> 144:ef7eb2e8f9f7 44 ADC_10,
<> 144:ef7eb2e8f9f7 45 ADC_11,
<> 144:ef7eb2e8f9f7 46 } ADCName;
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 typedef enum {
<> 144:ef7eb2e8f9f7 49 SPI_0 = (int)LPC_SSP0_BASE,
<> 144:ef7eb2e8f9f7 50 SPI_1 = (int)LPC_SSP1_BASE
<> 144:ef7eb2e8f9f7 51 } SPIName;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 typedef enum {
<> 144:ef7eb2e8f9f7 54 I2C_0 = (int)LPC_I2C0_BASE,
<> 144:ef7eb2e8f9f7 55 I2C_1 = (int)LPC_I2C1_BASE
<> 144:ef7eb2e8f9f7 56 } I2CName;
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 typedef enum {
<> 144:ef7eb2e8f9f7 59 SCT0_0 = 0,
<> 144:ef7eb2e8f9f7 60 SCT0_1,
<> 144:ef7eb2e8f9f7 61 SCT0_2,
<> 144:ef7eb2e8f9f7 62 SCT0_3,
<> 144:ef7eb2e8f9f7 63 SCT1_0,
<> 144:ef7eb2e8f9f7 64 SCT1_1,
<> 144:ef7eb2e8f9f7 65 SCT1_2,
<> 144:ef7eb2e8f9f7 66 SCT1_3,
<> 144:ef7eb2e8f9f7 67 } PWMName;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71 #endif
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #endif