Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file wdt_map.h
<> 149:156823d33999 4 * @brief WDT HW register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3283 $
<> 149:156823d33999 8 * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup wdt
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * <p>
<> 149:156823d33999 31 * Watchdog Timer HW register map description
<> 149:156823d33999 32 * </p>
<> 149:156823d33999 33 *
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 #if defined ( __CC_ARM )
<> 149:156823d33999 37 #pragma anon_unions
<> 149:156823d33999 38 #endif
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifndef WDT_MAP_H_
<> 149:156823d33999 41 #define WDT_MAP_H_
<> 149:156823d33999 42
<> 149:156823d33999 43 #include "architecture.h"
<> 149:156823d33999 44
<> 149:156823d33999 45 #ifdef REVB
<> 149:156823d33999 46 /** Watch Dog Timer Control HW Structure Overlay */
<> 149:156823d33999 47 typedef struct {
<> 149:156823d33999 48 __IO uint32_t LOAD; /**< Watchdog load value */
<> 149:156823d33999 49 __I uint32_t VALUE; /**< Watchdog current value */
<> 149:156823d33999 50 union {
<> 149:156823d33999 51 struct {
<> 149:156823d33999 52 __IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
<> 149:156823d33999 53 __IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
<> 149:156823d33999 54 __IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
<> 149:156823d33999 55 } BITS;
<> 149:156823d33999 56 __IO uint32_t WORD;
<> 149:156823d33999 57 } CONTROL;
<> 149:156823d33999 58 __IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
<> 149:156823d33999 59 __I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
<> 149:156823d33999 60 __I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
<> 149:156823d33999 61 union {
<> 149:156823d33999 62 struct {
<> 149:156823d33999 63 __IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
<> 149:156823d33999 64 __IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
<> 149:156823d33999 65 } BITS;
<> 149:156823d33999 66 __IO uint32_t WORD;
<> 149:156823d33999 67 } LOCK;
<> 149:156823d33999 68 __I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
<> 149:156823d33999 69 union {
<> 149:156823d33999 70 struct {
<> 149:156823d33999 71 __IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
<> 149:156823d33999 72 __IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
<> 149:156823d33999 73 __IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 74 } BITS;
<> 149:156823d33999 75 __IO uint32_t WORD;
<> 149:156823d33999 76 } TEST_OUT;
<> 149:156823d33999 77 union {
<> 149:156823d33999 78 struct {
<> 149:156823d33999 79 __IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
<> 149:156823d33999 80 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 81 } BITS;
<> 149:156823d33999 82 __IO uint32_t WORD;
<> 149:156823d33999 83 } PID_REG0;
<> 149:156823d33999 84 union {
<> 149:156823d33999 85 struct {
<> 149:156823d33999 86 __IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
<> 149:156823d33999 87 __IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
<> 149:156823d33999 88 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 89 } BITS;
<> 149:156823d33999 90 __IO uint32_t WORD;
<> 149:156823d33999 91 } PID_REG1;
<> 149:156823d33999 92 union {
<> 149:156823d33999 93 struct {
<> 149:156823d33999 94 __IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
<> 149:156823d33999 95 __IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
<> 149:156823d33999 96 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 97 } BITS;
<> 149:156823d33999 98 __IO uint32_t WORD;
<> 149:156823d33999 99 } PID_REG2;
<> 149:156823d33999 100 union {
<> 149:156823d33999 101 struct {
<> 149:156823d33999 102 __IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
<> 149:156823d33999 103 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 104 } BITS;
<> 149:156823d33999 105 __IO uint32_t WORD;
<> 149:156823d33999 106 } PID_REG3;
<> 149:156823d33999 107 union {
<> 149:156823d33999 108 struct {
<> 149:156823d33999 109 __IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
<> 149:156823d33999 110 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 111 } BITS;
<> 149:156823d33999 112 __IO uint32_t WORD;
<> 149:156823d33999 113 } PCELL_ID0;
<> 149:156823d33999 114 union {
<> 149:156823d33999 115 struct {
<> 149:156823d33999 116 __IO uint32_t ID :8; /**< These bits read back as 0xF0*/
<> 149:156823d33999 117 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 118 } BITS;
<> 149:156823d33999 119 __IO uint32_t WORD;
<> 149:156823d33999 120 } PCELL_ID1;
<> 149:156823d33999 121 union {
<> 149:156823d33999 122 struct {
<> 149:156823d33999 123 __IO uint32_t ID :8; /**< These bits read back as 0x05*/
<> 149:156823d33999 124 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 125 } BITS;
<> 149:156823d33999 126 __IO uint32_t WORD;
<> 149:156823d33999 127 } PCELL_ID2;
<> 149:156823d33999 128 union {
<> 149:156823d33999 129 struct {
<> 149:156823d33999 130 __IO uint32_t ID :8; /**< These bits read back as 0xB1*/
<> 149:156823d33999 131 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 149:156823d33999 132 } BITS;
<> 149:156823d33999 133 __IO uint32_t WORD;
<> 149:156823d33999 134 } PCELL_ID3;
<> 149:156823d33999 135 } WdtReg_t, *WdtReg_pt;
<> 149:156823d33999 136 #endif /* REVB */
<> 149:156823d33999 137
<> 149:156823d33999 138 #ifdef REVD
<> 149:156823d33999 139 typedef struct {
<> 149:156823d33999 140 __IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
<> 149:156823d33999 141 __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
<> 149:156823d33999 142 union {
<> 149:156823d33999 143 struct {
<> 149:156823d33999 144 __IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
<> 149:156823d33999 145 } BITS;
<> 149:156823d33999 146 __IO uint32_t WORD;
<> 149:156823d33999 147 } CONTROL; /* 0x4000A008 */
<> 149:156823d33999 148 __O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
<> 149:156823d33999 149 __O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
<> 149:156823d33999 150 union {
<> 149:156823d33999 151 struct {
<> 149:156823d33999 152 __I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
<> 149:156823d33999 153 __I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
<> 149:156823d33999 154 __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
<> 149:156823d33999 155 __IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
<> 149:156823d33999 156 } BITS;
<> 149:156823d33999 157 __IO uint32_t WORD;
<> 149:156823d33999 158 } STATUS; /* 0x4000A014 */
<> 149:156823d33999 159 } WdtReg_t, *WdtReg_pt;
<> 149:156823d33999 160 #endif /* REVD */
<> 149:156823d33999 161 #endif /* WDT_MAP_H_ */