mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c
Dependents: Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay
Fork of mbed-dev by
targets/TARGET_NXP/TARGET_LPC11U6X/sleep.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep.c@144:ef7eb2e8f9f7
- Child:
- 160:d5399cc887bb
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include "sleep_api.h" |
<> | 144:ef7eb2e8f9f7 | 17 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "mbed_interface.h" |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | #if DEVICE_SLEEP |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | void sleep(void) { |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | #if (DEVICE_SEMIHOST == 1) |
<> | 144:ef7eb2e8f9f7 | 25 | // ensure debug is disconnected |
<> | 144:ef7eb2e8f9f7 | 26 | mbed_interface_disconnect(); |
<> | 144:ef7eb2e8f9f7 | 27 | #endif |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | // PCON[PM] (bits 2:0) set to 0 |
<> | 144:ef7eb2e8f9f7 | 30 | LPC_PMU->PCON &= ~0x03; |
<> | 144:ef7eb2e8f9f7 | 31 | |
<> | 144:ef7eb2e8f9f7 | 32 | // SRC[SLEEPDEEP] set to 0 = sleep |
<> | 144:ef7eb2e8f9f7 | 33 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | // wait for interrupt |
<> | 144:ef7eb2e8f9f7 | 36 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 37 | } |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | void deepsleep(void) { |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #if (DEVICE_SEMIHOST == 1) |
<> | 144:ef7eb2e8f9f7 | 43 | // ensure debug is disconnected |
<> | 144:ef7eb2e8f9f7 | 44 | mbed_interface_disconnect(); |
<> | 144:ef7eb2e8f9f7 | 45 | #endif |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | // PCON[PM] (bits 2:0) set to 1 |
<> | 144:ef7eb2e8f9f7 | 48 | LPC_PMU->PCON &= ~0x03; |
<> | 144:ef7eb2e8f9f7 | 49 | LPC_PMU->PCON |= 0x01; |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | //According to user manual it is kinda picky about reserved bits, so we follow that nicely |
<> | 144:ef7eb2e8f9f7 | 52 | //Keep WDOSC and BOD in same state as they are now during deepsleep |
<> | 144:ef7eb2e8f9f7 | 53 | LPC_SYSCON->PDSLEEPCFG = 0x00000037 | (LPC_SYSCON->PDRUNCFG & (0x00000048)); |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | // Power up same as before powerdown |
<> | 144:ef7eb2e8f9f7 | 56 | LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG; |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | // All interrupts can wake |
<> | 144:ef7eb2e8f9f7 | 59 | LPC_SYSCON->STARTERP0 = 0xFF; |
<> | 144:ef7eb2e8f9f7 | 60 | LPC_SYSCON->STARTERP1 = 0xFFFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | // SRC[SLEEPDEEP] set to 1 = deep sleep |
<> | 144:ef7eb2e8f9f7 | 63 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | // wait for interrupt |
<> | 144:ef7eb2e8f9f7 | 66 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 67 | } |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | #endif |