Matthew Sims / mbed

Lab 1 Program C

Dependents:   Lab1C

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LPC11U24/core_cm0.h@40:976df7c37ad5, 2012-06-12 (annotated)

Committer:
emilmont
Date:
Tue Jun 12 18:23:44 2012 +0100
Revision:
40:976df7c37ad5
First build for the new build system

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /**************************************************************************//**
emilmont 40:976df7c37ad5 2 * @file core_cm0.h
emilmont 40:976df7c37ad5 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
emilmont 40:976df7c37ad5 4 * @version V3.01
emilmont 40:976df7c37ad5 5 * @date 06. March 2012
emilmont 40:976df7c37ad5 6 *
emilmont 40:976df7c37ad5 7 * @note
emilmont 40:976df7c37ad5 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 9 *
emilmont 40:976df7c37ad5 10 * @par
emilmont 40:976df7c37ad5 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 40:976df7c37ad5 12 * processor based microcontrollers. This file can be freely distributed
emilmont 40:976df7c37ad5 13 * within development tools that are supporting such ARM based processors.
emilmont 40:976df7c37ad5 14 *
emilmont 40:976df7c37ad5 15 * @par
emilmont 40:976df7c37ad5 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 40:976df7c37ad5 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 40:976df7c37ad5 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 40:976df7c37ad5 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 40:976df7c37ad5 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 40:976df7c37ad5 21 *
emilmont 40:976df7c37ad5 22 ******************************************************************************/
emilmont 40:976df7c37ad5 23 #if defined ( __ICCARM__ )
emilmont 40:976df7c37ad5 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 40:976df7c37ad5 25 #endif
emilmont 40:976df7c37ad5 26
emilmont 40:976df7c37ad5 27 #ifdef __cplusplus
emilmont 40:976df7c37ad5 28 extern "C" {
emilmont 40:976df7c37ad5 29 #endif
emilmont 40:976df7c37ad5 30
emilmont 40:976df7c37ad5 31 #ifndef __CORE_CM0_H_GENERIC
emilmont 40:976df7c37ad5 32 #define __CORE_CM0_H_GENERIC
emilmont 40:976df7c37ad5 33
emilmont 40:976df7c37ad5 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 40:976df7c37ad5 35 CMSIS violates the following MISRA-C:2004 rules:
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 40:976df7c37ad5 38 Function definitions in header files are used to allow 'inlining'.
emilmont 40:976df7c37ad5 39
emilmont 40:976df7c37ad5 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 40:976df7c37ad5 41 Unions are used for effective representation of core registers.
emilmont 40:976df7c37ad5 42
emilmont 40:976df7c37ad5 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 40:976df7c37ad5 44 Function-like macros are used to allow more efficient code.
emilmont 40:976df7c37ad5 45 */
emilmont 40:976df7c37ad5 46
emilmont 40:976df7c37ad5 47
emilmont 40:976df7c37ad5 48 /*******************************************************************************
emilmont 40:976df7c37ad5 49 * CMSIS definitions
emilmont 40:976df7c37ad5 50 ******************************************************************************/
emilmont 40:976df7c37ad5 51 /** \ingroup Cortex_M0
emilmont 40:976df7c37ad5 52 @{
emilmont 40:976df7c37ad5 53 */
emilmont 40:976df7c37ad5 54
emilmont 40:976df7c37ad5 55 /* CMSIS CM0 definitions */
emilmont 40:976df7c37ad5 56 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 40:976df7c37ad5 57 #define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
emilmont 40:976df7c37ad5 58 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
emilmont 40:976df7c37ad5 59 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 40:976df7c37ad5 60
emilmont 40:976df7c37ad5 61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 40:976df7c37ad5 62
emilmont 40:976df7c37ad5 63
emilmont 40:976df7c37ad5 64 #if defined ( __CC_ARM )
emilmont 40:976df7c37ad5 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 40:976df7c37ad5 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 40:976df7c37ad5 67 #define __STATIC_INLINE static __inline
emilmont 40:976df7c37ad5 68
emilmont 40:976df7c37ad5 69 #elif defined ( __ICCARM__ )
emilmont 40:976df7c37ad5 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 40:976df7c37ad5 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 40:976df7c37ad5 72 #define __STATIC_INLINE static inline
emilmont 40:976df7c37ad5 73
emilmont 40:976df7c37ad5 74 #elif defined ( __GNUC__ )
emilmont 40:976df7c37ad5 75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 40:976df7c37ad5 76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 40:976df7c37ad5 77 #define __STATIC_INLINE static inline
emilmont 40:976df7c37ad5 78
emilmont 40:976df7c37ad5 79 #elif defined ( __TASKING__ )
emilmont 40:976df7c37ad5 80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 40:976df7c37ad5 81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 40:976df7c37ad5 82 #define __STATIC_INLINE static inline
emilmont 40:976df7c37ad5 83
emilmont 40:976df7c37ad5 84 #endif
emilmont 40:976df7c37ad5 85
emilmont 40:976df7c37ad5 86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 40:976df7c37ad5 87 */
emilmont 40:976df7c37ad5 88 #define __FPU_USED 0
emilmont 40:976df7c37ad5 89
emilmont 40:976df7c37ad5 90 #if defined ( __CC_ARM )
emilmont 40:976df7c37ad5 91 #if defined __TARGET_FPU_VFP
emilmont 40:976df7c37ad5 92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 40:976df7c37ad5 93 #endif
emilmont 40:976df7c37ad5 94
emilmont 40:976df7c37ad5 95 #elif defined ( __ICCARM__ )
emilmont 40:976df7c37ad5 96 #if defined __ARMVFP__
emilmont 40:976df7c37ad5 97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 40:976df7c37ad5 98 #endif
emilmont 40:976df7c37ad5 99
emilmont 40:976df7c37ad5 100 #elif defined ( __GNUC__ )
emilmont 40:976df7c37ad5 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 40:976df7c37ad5 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 40:976df7c37ad5 103 #endif
emilmont 40:976df7c37ad5 104
emilmont 40:976df7c37ad5 105 #elif defined ( __TASKING__ )
emilmont 40:976df7c37ad5 106 /* add preprocessor checks */
emilmont 40:976df7c37ad5 107 #endif
emilmont 40:976df7c37ad5 108
emilmont 40:976df7c37ad5 109 #include <stdint.h> /* standard types definitions */
emilmont 40:976df7c37ad5 110 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 40:976df7c37ad5 111 #include <core_cmFunc.h> /* Core Function Access */
emilmont 40:976df7c37ad5 112
emilmont 40:976df7c37ad5 113 #endif /* __CORE_CM0_H_GENERIC */
emilmont 40:976df7c37ad5 114
emilmont 40:976df7c37ad5 115 #ifndef __CMSIS_GENERIC
emilmont 40:976df7c37ad5 116
emilmont 40:976df7c37ad5 117 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 40:976df7c37ad5 118 #define __CORE_CM0_H_DEPENDANT
emilmont 40:976df7c37ad5 119
emilmont 40:976df7c37ad5 120 /* check device defines and use defaults */
emilmont 40:976df7c37ad5 121 #if defined __CHECK_DEVICE_DEFINES
emilmont 40:976df7c37ad5 122 #ifndef __CM0_REV
emilmont 40:976df7c37ad5 123 #define __CM0_REV 0x0000
emilmont 40:976df7c37ad5 124 #warning "__CM0_REV not defined in device header file; using default!"
emilmont 40:976df7c37ad5 125 #endif
emilmont 40:976df7c37ad5 126
emilmont 40:976df7c37ad5 127 #ifndef __NVIC_PRIO_BITS
emilmont 40:976df7c37ad5 128 #define __NVIC_PRIO_BITS 2
emilmont 40:976df7c37ad5 129 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 40:976df7c37ad5 130 #endif
emilmont 40:976df7c37ad5 131
emilmont 40:976df7c37ad5 132 #ifndef __Vendor_SysTickConfig
emilmont 40:976df7c37ad5 133 #define __Vendor_SysTickConfig 0
emilmont 40:976df7c37ad5 134 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 40:976df7c37ad5 135 #endif
emilmont 40:976df7c37ad5 136 #endif
emilmont 40:976df7c37ad5 137
emilmont 40:976df7c37ad5 138 /* IO definitions (access restrictions to peripheral registers) */
emilmont 40:976df7c37ad5 139 /**
emilmont 40:976df7c37ad5 140 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 40:976df7c37ad5 141
emilmont 40:976df7c37ad5 142 <strong>IO Type Qualifiers</strong> are used
emilmont 40:976df7c37ad5 143 \li to specify the access to peripheral variables.
emilmont 40:976df7c37ad5 144 \li for automatic generation of peripheral register debug information.
emilmont 40:976df7c37ad5 145 */
emilmont 40:976df7c37ad5 146 #ifdef __cplusplus
emilmont 40:976df7c37ad5 147 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 40:976df7c37ad5 148 #else
emilmont 40:976df7c37ad5 149 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 40:976df7c37ad5 150 #endif
emilmont 40:976df7c37ad5 151 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 40:976df7c37ad5 152 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 40:976df7c37ad5 153
emilmont 40:976df7c37ad5 154 /*@} end of group Cortex_M0 */
emilmont 40:976df7c37ad5 155
emilmont 40:976df7c37ad5 156
emilmont 40:976df7c37ad5 157
emilmont 40:976df7c37ad5 158 /*******************************************************************************
emilmont 40:976df7c37ad5 159 * Register Abstraction
emilmont 40:976df7c37ad5 160 Core Register contain:
emilmont 40:976df7c37ad5 161 - Core Register
emilmont 40:976df7c37ad5 162 - Core NVIC Register
emilmont 40:976df7c37ad5 163 - Core SCB Register
emilmont 40:976df7c37ad5 164 - Core SysTick Register
emilmont 40:976df7c37ad5 165 ******************************************************************************/
emilmont 40:976df7c37ad5 166 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 40:976df7c37ad5 167 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 40:976df7c37ad5 168 */
emilmont 40:976df7c37ad5 169
emilmont 40:976df7c37ad5 170 /** \ingroup CMSIS_core_register
emilmont 40:976df7c37ad5 171 \defgroup CMSIS_CORE Status and Control Registers
emilmont 40:976df7c37ad5 172 \brief Core Register type definitions.
emilmont 40:976df7c37ad5 173 @{
emilmont 40:976df7c37ad5 174 */
emilmont 40:976df7c37ad5 175
emilmont 40:976df7c37ad5 176 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 40:976df7c37ad5 177 */
emilmont 40:976df7c37ad5 178 typedef union
emilmont 40:976df7c37ad5 179 {
emilmont 40:976df7c37ad5 180 struct
emilmont 40:976df7c37ad5 181 {
emilmont 40:976df7c37ad5 182 #if (__CORTEX_M != 0x04)
emilmont 40:976df7c37ad5 183 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 40:976df7c37ad5 184 #else
emilmont 40:976df7c37ad5 185 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 40:976df7c37ad5 186 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 40:976df7c37ad5 187 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 40:976df7c37ad5 188 #endif
emilmont 40:976df7c37ad5 189 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 40:976df7c37ad5 190 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 40:976df7c37ad5 191 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 40:976df7c37ad5 192 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 40:976df7c37ad5 193 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 40:976df7c37ad5 194 } b; /*!< Structure used for bit access */
emilmont 40:976df7c37ad5 195 uint32_t w; /*!< Type used for word access */
emilmont 40:976df7c37ad5 196 } APSR_Type;
emilmont 40:976df7c37ad5 197
emilmont 40:976df7c37ad5 198
emilmont 40:976df7c37ad5 199 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 40:976df7c37ad5 200 */
emilmont 40:976df7c37ad5 201 typedef union
emilmont 40:976df7c37ad5 202 {
emilmont 40:976df7c37ad5 203 struct
emilmont 40:976df7c37ad5 204 {
emilmont 40:976df7c37ad5 205 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 40:976df7c37ad5 206 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 40:976df7c37ad5 207 } b; /*!< Structure used for bit access */
emilmont 40:976df7c37ad5 208 uint32_t w; /*!< Type used for word access */
emilmont 40:976df7c37ad5 209 } IPSR_Type;
emilmont 40:976df7c37ad5 210
emilmont 40:976df7c37ad5 211
emilmont 40:976df7c37ad5 212 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 40:976df7c37ad5 213 */
emilmont 40:976df7c37ad5 214 typedef union
emilmont 40:976df7c37ad5 215 {
emilmont 40:976df7c37ad5 216 struct
emilmont 40:976df7c37ad5 217 {
emilmont 40:976df7c37ad5 218 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 40:976df7c37ad5 219 #if (__CORTEX_M != 0x04)
emilmont 40:976df7c37ad5 220 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 40:976df7c37ad5 221 #else
emilmont 40:976df7c37ad5 222 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 40:976df7c37ad5 223 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 40:976df7c37ad5 224 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 40:976df7c37ad5 225 #endif
emilmont 40:976df7c37ad5 226 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 40:976df7c37ad5 227 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 40:976df7c37ad5 228 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 40:976df7c37ad5 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 40:976df7c37ad5 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 40:976df7c37ad5 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 40:976df7c37ad5 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 40:976df7c37ad5 233 } b; /*!< Structure used for bit access */
emilmont 40:976df7c37ad5 234 uint32_t w; /*!< Type used for word access */
emilmont 40:976df7c37ad5 235 } xPSR_Type;
emilmont 40:976df7c37ad5 236
emilmont 40:976df7c37ad5 237
emilmont 40:976df7c37ad5 238 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 40:976df7c37ad5 239 */
emilmont 40:976df7c37ad5 240 typedef union
emilmont 40:976df7c37ad5 241 {
emilmont 40:976df7c37ad5 242 struct
emilmont 40:976df7c37ad5 243 {
emilmont 40:976df7c37ad5 244 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 40:976df7c37ad5 245 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 40:976df7c37ad5 246 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 40:976df7c37ad5 247 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 40:976df7c37ad5 248 } b; /*!< Structure used for bit access */
emilmont 40:976df7c37ad5 249 uint32_t w; /*!< Type used for word access */
emilmont 40:976df7c37ad5 250 } CONTROL_Type;
emilmont 40:976df7c37ad5 251
emilmont 40:976df7c37ad5 252 /*@} end of group CMSIS_CORE */
emilmont 40:976df7c37ad5 253
emilmont 40:976df7c37ad5 254
emilmont 40:976df7c37ad5 255 /** \ingroup CMSIS_core_register
emilmont 40:976df7c37ad5 256 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 40:976df7c37ad5 257 \brief Type definitions for the NVIC Registers
emilmont 40:976df7c37ad5 258 @{
emilmont 40:976df7c37ad5 259 */
emilmont 40:976df7c37ad5 260
emilmont 40:976df7c37ad5 261 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 40:976df7c37ad5 262 */
emilmont 40:976df7c37ad5 263 typedef struct
emilmont 40:976df7c37ad5 264 {
emilmont 40:976df7c37ad5 265 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 40:976df7c37ad5 266 uint32_t RESERVED0[31];
emilmont 40:976df7c37ad5 267 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 40:976df7c37ad5 268 uint32_t RSERVED1[31];
emilmont 40:976df7c37ad5 269 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 40:976df7c37ad5 270 uint32_t RESERVED2[31];
emilmont 40:976df7c37ad5 271 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 40:976df7c37ad5 272 uint32_t RESERVED3[31];
emilmont 40:976df7c37ad5 273 uint32_t RESERVED4[64];
emilmont 40:976df7c37ad5 274 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 40:976df7c37ad5 275 } NVIC_Type;
emilmont 40:976df7c37ad5 276
emilmont 40:976df7c37ad5 277 /*@} end of group CMSIS_NVIC */
emilmont 40:976df7c37ad5 278
emilmont 40:976df7c37ad5 279
emilmont 40:976df7c37ad5 280 /** \ingroup CMSIS_core_register
emilmont 40:976df7c37ad5 281 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 40:976df7c37ad5 282 \brief Type definitions for the System Control Block Registers
emilmont 40:976df7c37ad5 283 @{
emilmont 40:976df7c37ad5 284 */
emilmont 40:976df7c37ad5 285
emilmont 40:976df7c37ad5 286 /** \brief Structure type to access the System Control Block (SCB).
emilmont 40:976df7c37ad5 287 */
emilmont 40:976df7c37ad5 288 typedef struct
emilmont 40:976df7c37ad5 289 {
emilmont 40:976df7c37ad5 290 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 40:976df7c37ad5 291 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 40:976df7c37ad5 292 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 293 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 40:976df7c37ad5 294 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 40:976df7c37ad5 295 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 40:976df7c37ad5 296 uint32_t RESERVED1;
emilmont 40:976df7c37ad5 297 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 40:976df7c37ad5 298 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 40:976df7c37ad5 299 } SCB_Type;
emilmont 40:976df7c37ad5 300
emilmont 40:976df7c37ad5 301 /* SCB CPUID Register Definitions */
emilmont 40:976df7c37ad5 302 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 40:976df7c37ad5 303 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 40:976df7c37ad5 304
emilmont 40:976df7c37ad5 305 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 40:976df7c37ad5 306 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 40:976df7c37ad5 307
emilmont 40:976df7c37ad5 308 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 40:976df7c37ad5 309 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 40:976df7c37ad5 310
emilmont 40:976df7c37ad5 311 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 40:976df7c37ad5 312 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 40:976df7c37ad5 313
emilmont 40:976df7c37ad5 314 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 40:976df7c37ad5 315 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 40:976df7c37ad5 316
emilmont 40:976df7c37ad5 317 /* SCB Interrupt Control State Register Definitions */
emilmont 40:976df7c37ad5 318 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 40:976df7c37ad5 319 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 40:976df7c37ad5 320
emilmont 40:976df7c37ad5 321 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 40:976df7c37ad5 322 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 40:976df7c37ad5 323
emilmont 40:976df7c37ad5 324 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 40:976df7c37ad5 325 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 40:976df7c37ad5 326
emilmont 40:976df7c37ad5 327 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 40:976df7c37ad5 328 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 40:976df7c37ad5 329
emilmont 40:976df7c37ad5 330 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 40:976df7c37ad5 331 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 40:976df7c37ad5 332
emilmont 40:976df7c37ad5 333 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 40:976df7c37ad5 334 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 40:976df7c37ad5 335
emilmont 40:976df7c37ad5 336 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 40:976df7c37ad5 337 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 40:976df7c37ad5 338
emilmont 40:976df7c37ad5 339 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 40:976df7c37ad5 340 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 40:976df7c37ad5 341
emilmont 40:976df7c37ad5 342 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 40:976df7c37ad5 343 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 40:976df7c37ad5 344
emilmont 40:976df7c37ad5 345 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 40:976df7c37ad5 346 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 40:976df7c37ad5 347 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 40:976df7c37ad5 348
emilmont 40:976df7c37ad5 349 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 40:976df7c37ad5 350 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 40:976df7c37ad5 351
emilmont 40:976df7c37ad5 352 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 40:976df7c37ad5 353 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 40:976df7c37ad5 354
emilmont 40:976df7c37ad5 355 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 40:976df7c37ad5 356 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 40:976df7c37ad5 357
emilmont 40:976df7c37ad5 358 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 40:976df7c37ad5 359 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 40:976df7c37ad5 360
emilmont 40:976df7c37ad5 361 /* SCB System Control Register Definitions */
emilmont 40:976df7c37ad5 362 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 40:976df7c37ad5 363 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 40:976df7c37ad5 364
emilmont 40:976df7c37ad5 365 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 40:976df7c37ad5 366 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 40:976df7c37ad5 367
emilmont 40:976df7c37ad5 368 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 40:976df7c37ad5 369 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 40:976df7c37ad5 370
emilmont 40:976df7c37ad5 371 /* SCB Configuration Control Register Definitions */
emilmont 40:976df7c37ad5 372 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 40:976df7c37ad5 373 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 40:976df7c37ad5 374
emilmont 40:976df7c37ad5 375 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 40:976df7c37ad5 376 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 40:976df7c37ad5 377
emilmont 40:976df7c37ad5 378 /* SCB System Handler Control and State Register Definitions */
emilmont 40:976df7c37ad5 379 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 40:976df7c37ad5 380 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 40:976df7c37ad5 381
emilmont 40:976df7c37ad5 382 /*@} end of group CMSIS_SCB */
emilmont 40:976df7c37ad5 383
emilmont 40:976df7c37ad5 384
emilmont 40:976df7c37ad5 385 /** \ingroup CMSIS_core_register
emilmont 40:976df7c37ad5 386 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 40:976df7c37ad5 387 \brief Type definitions for the System Timer Registers.
emilmont 40:976df7c37ad5 388 @{
emilmont 40:976df7c37ad5 389 */
emilmont 40:976df7c37ad5 390
emilmont 40:976df7c37ad5 391 /** \brief Structure type to access the System Timer (SysTick).
emilmont 40:976df7c37ad5 392 */
emilmont 40:976df7c37ad5 393 typedef struct
emilmont 40:976df7c37ad5 394 {
emilmont 40:976df7c37ad5 395 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 40:976df7c37ad5 396 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 40:976df7c37ad5 397 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 40:976df7c37ad5 398 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 40:976df7c37ad5 399 } SysTick_Type;
emilmont 40:976df7c37ad5 400
emilmont 40:976df7c37ad5 401 /* SysTick Control / Status Register Definitions */
emilmont 40:976df7c37ad5 402 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 40:976df7c37ad5 403 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 40:976df7c37ad5 404
emilmont 40:976df7c37ad5 405 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 40:976df7c37ad5 406 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 40:976df7c37ad5 407
emilmont 40:976df7c37ad5 408 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 40:976df7c37ad5 409 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 40:976df7c37ad5 410
emilmont 40:976df7c37ad5 411 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 40:976df7c37ad5 412 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 40:976df7c37ad5 413
emilmont 40:976df7c37ad5 414 /* SysTick Reload Register Definitions */
emilmont 40:976df7c37ad5 415 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 40:976df7c37ad5 416 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 40:976df7c37ad5 417
emilmont 40:976df7c37ad5 418 /* SysTick Current Register Definitions */
emilmont 40:976df7c37ad5 419 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 40:976df7c37ad5 420 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 40:976df7c37ad5 421
emilmont 40:976df7c37ad5 422 /* SysTick Calibration Register Definitions */
emilmont 40:976df7c37ad5 423 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 40:976df7c37ad5 424 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 40:976df7c37ad5 425
emilmont 40:976df7c37ad5 426 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 40:976df7c37ad5 427 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 40:976df7c37ad5 428
emilmont 40:976df7c37ad5 429 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 40:976df7c37ad5 430 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 40:976df7c37ad5 431
emilmont 40:976df7c37ad5 432 /*@} end of group CMSIS_SysTick */
emilmont 40:976df7c37ad5 433
emilmont 40:976df7c37ad5 434
emilmont 40:976df7c37ad5 435 /** \ingroup CMSIS_core_register
emilmont 40:976df7c37ad5 436 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 40:976df7c37ad5 437 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 40:976df7c37ad5 438 are only accessible over DAP and not via processor. Therefore
emilmont 40:976df7c37ad5 439 they are not covered by the Cortex-M0 header file.
emilmont 40:976df7c37ad5 440 @{
emilmont 40:976df7c37ad5 441 */
emilmont 40:976df7c37ad5 442 /*@} end of group CMSIS_CoreDebug */
emilmont 40:976df7c37ad5 443
emilmont 40:976df7c37ad5 444
emilmont 40:976df7c37ad5 445 /** \ingroup CMSIS_core_register
emilmont 40:976df7c37ad5 446 \defgroup CMSIS_core_base Core Definitions
emilmont 40:976df7c37ad5 447 \brief Definitions for base addresses, unions, and structures.
emilmont 40:976df7c37ad5 448 @{
emilmont 40:976df7c37ad5 449 */
emilmont 40:976df7c37ad5 450
emilmont 40:976df7c37ad5 451 /* Memory mapping of Cortex-M0 Hardware */
emilmont 40:976df7c37ad5 452 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 40:976df7c37ad5 453 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 40:976df7c37ad5 454 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 40:976df7c37ad5 455 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 40:976df7c37ad5 456
emilmont 40:976df7c37ad5 457 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 40:976df7c37ad5 458 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 40:976df7c37ad5 459 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 40:976df7c37ad5 460
emilmont 40:976df7c37ad5 461
emilmont 40:976df7c37ad5 462 /*@} */
emilmont 40:976df7c37ad5 463
emilmont 40:976df7c37ad5 464
emilmont 40:976df7c37ad5 465
emilmont 40:976df7c37ad5 466 /*******************************************************************************
emilmont 40:976df7c37ad5 467 * Hardware Abstraction Layer
emilmont 40:976df7c37ad5 468 Core Function Interface contains:
emilmont 40:976df7c37ad5 469 - Core NVIC Functions
emilmont 40:976df7c37ad5 470 - Core SysTick Functions
emilmont 40:976df7c37ad5 471 - Core Register Access Functions
emilmont 40:976df7c37ad5 472 ******************************************************************************/
emilmont 40:976df7c37ad5 473 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 40:976df7c37ad5 474 */
emilmont 40:976df7c37ad5 475
emilmont 40:976df7c37ad5 476
emilmont 40:976df7c37ad5 477
emilmont 40:976df7c37ad5 478 /* ########################## NVIC functions #################################### */
emilmont 40:976df7c37ad5 479 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 40:976df7c37ad5 480 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 40:976df7c37ad5 481 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 40:976df7c37ad5 482 @{
emilmont 40:976df7c37ad5 483 */
emilmont 40:976df7c37ad5 484
emilmont 40:976df7c37ad5 485 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 40:976df7c37ad5 486 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 40:976df7c37ad5 487 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 40:976df7c37ad5 488 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 40:976df7c37ad5 489 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 40:976df7c37ad5 490
emilmont 40:976df7c37ad5 491
emilmont 40:976df7c37ad5 492 /** \brief Enable External Interrupt
emilmont 40:976df7c37ad5 493
emilmont 40:976df7c37ad5 494 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 40:976df7c37ad5 495
emilmont 40:976df7c37ad5 496 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 40:976df7c37ad5 497 */
emilmont 40:976df7c37ad5 498 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 40:976df7c37ad5 499 {
emilmont 40:976df7c37ad5 500 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 40:976df7c37ad5 501 }
emilmont 40:976df7c37ad5 502
emilmont 40:976df7c37ad5 503
emilmont 40:976df7c37ad5 504 /** \brief Disable External Interrupt
emilmont 40:976df7c37ad5 505
emilmont 40:976df7c37ad5 506 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 40:976df7c37ad5 507
emilmont 40:976df7c37ad5 508 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 40:976df7c37ad5 509 */
emilmont 40:976df7c37ad5 510 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 40:976df7c37ad5 511 {
emilmont 40:976df7c37ad5 512 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 40:976df7c37ad5 513 }
emilmont 40:976df7c37ad5 514
emilmont 40:976df7c37ad5 515
emilmont 40:976df7c37ad5 516 /** \brief Get Pending Interrupt
emilmont 40:976df7c37ad5 517
emilmont 40:976df7c37ad5 518 The function reads the pending register in the NVIC and returns the pending bit
emilmont 40:976df7c37ad5 519 for the specified interrupt.
emilmont 40:976df7c37ad5 520
emilmont 40:976df7c37ad5 521 \param [in] IRQn Interrupt number.
emilmont 40:976df7c37ad5 522
emilmont 40:976df7c37ad5 523 \return 0 Interrupt status is not pending.
emilmont 40:976df7c37ad5 524 \return 1 Interrupt status is pending.
emilmont 40:976df7c37ad5 525 */
emilmont 40:976df7c37ad5 526 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 40:976df7c37ad5 527 {
emilmont 40:976df7c37ad5 528 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 40:976df7c37ad5 529 }
emilmont 40:976df7c37ad5 530
emilmont 40:976df7c37ad5 531
emilmont 40:976df7c37ad5 532 /** \brief Set Pending Interrupt
emilmont 40:976df7c37ad5 533
emilmont 40:976df7c37ad5 534 The function sets the pending bit of an external interrupt.
emilmont 40:976df7c37ad5 535
emilmont 40:976df7c37ad5 536 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 40:976df7c37ad5 537 */
emilmont 40:976df7c37ad5 538 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 40:976df7c37ad5 539 {
emilmont 40:976df7c37ad5 540 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 40:976df7c37ad5 541 }
emilmont 40:976df7c37ad5 542
emilmont 40:976df7c37ad5 543
emilmont 40:976df7c37ad5 544 /** \brief Clear Pending Interrupt
emilmont 40:976df7c37ad5 545
emilmont 40:976df7c37ad5 546 The function clears the pending bit of an external interrupt.
emilmont 40:976df7c37ad5 547
emilmont 40:976df7c37ad5 548 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 40:976df7c37ad5 549 */
emilmont 40:976df7c37ad5 550 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 40:976df7c37ad5 551 {
emilmont 40:976df7c37ad5 552 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 40:976df7c37ad5 553 }
emilmont 40:976df7c37ad5 554
emilmont 40:976df7c37ad5 555
emilmont 40:976df7c37ad5 556 /** \brief Set Interrupt Priority
emilmont 40:976df7c37ad5 557
emilmont 40:976df7c37ad5 558 The function sets the priority of an interrupt.
emilmont 40:976df7c37ad5 559
emilmont 40:976df7c37ad5 560 \note The priority cannot be set for every core interrupt.
emilmont 40:976df7c37ad5 561
emilmont 40:976df7c37ad5 562 \param [in] IRQn Interrupt number.
emilmont 40:976df7c37ad5 563 \param [in] priority Priority to set.
emilmont 40:976df7c37ad5 564 */
emilmont 40:976df7c37ad5 565 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 40:976df7c37ad5 566 {
emilmont 40:976df7c37ad5 567 if(IRQn < 0) {
emilmont 40:976df7c37ad5 568 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 40:976df7c37ad5 569 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 40:976df7c37ad5 570 else {
emilmont 40:976df7c37ad5 571 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 40:976df7c37ad5 572 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 40:976df7c37ad5 573 }
emilmont 40:976df7c37ad5 574
emilmont 40:976df7c37ad5 575
emilmont 40:976df7c37ad5 576 /** \brief Get Interrupt Priority
emilmont 40:976df7c37ad5 577
emilmont 40:976df7c37ad5 578 The function reads the priority of an interrupt. The interrupt
emilmont 40:976df7c37ad5 579 number can be positive to specify an external (device specific)
emilmont 40:976df7c37ad5 580 interrupt, or negative to specify an internal (core) interrupt.
emilmont 40:976df7c37ad5 581
emilmont 40:976df7c37ad5 582
emilmont 40:976df7c37ad5 583 \param [in] IRQn Interrupt number.
emilmont 40:976df7c37ad5 584 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 40:976df7c37ad5 585 priority bits of the microcontroller.
emilmont 40:976df7c37ad5 586 */
emilmont 40:976df7c37ad5 587 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 40:976df7c37ad5 588 {
emilmont 40:976df7c37ad5 589
emilmont 40:976df7c37ad5 590 if(IRQn < 0) {
emilmont 40:976df7c37ad5 591 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 40:976df7c37ad5 592 else {
emilmont 40:976df7c37ad5 593 return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 40:976df7c37ad5 594 }
emilmont 40:976df7c37ad5 595
emilmont 40:976df7c37ad5 596
emilmont 40:976df7c37ad5 597 /** \brief System Reset
emilmont 40:976df7c37ad5 598
emilmont 40:976df7c37ad5 599 The function initiates a system reset request to reset the MCU.
emilmont 40:976df7c37ad5 600 */
emilmont 40:976df7c37ad5 601 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 40:976df7c37ad5 602 {
emilmont 40:976df7c37ad5 603 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 40:976df7c37ad5 604 buffered write are completed before reset */
emilmont 40:976df7c37ad5 605 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 40:976df7c37ad5 606 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 40:976df7c37ad5 607 __DSB(); /* Ensure completion of memory access */
emilmont 40:976df7c37ad5 608 while(1); /* wait until reset */
emilmont 40:976df7c37ad5 609 }
emilmont 40:976df7c37ad5 610
emilmont 40:976df7c37ad5 611 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 40:976df7c37ad5 612
emilmont 40:976df7c37ad5 613
emilmont 40:976df7c37ad5 614
emilmont 40:976df7c37ad5 615 /* ################################## SysTick function ############################################ */
emilmont 40:976df7c37ad5 616 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 40:976df7c37ad5 617 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 40:976df7c37ad5 618 \brief Functions that configure the System.
emilmont 40:976df7c37ad5 619 @{
emilmont 40:976df7c37ad5 620 */
emilmont 40:976df7c37ad5 621
emilmont 40:976df7c37ad5 622 #if (__Vendor_SysTickConfig == 0)
emilmont 40:976df7c37ad5 623
emilmont 40:976df7c37ad5 624 /** \brief System Tick Configuration
emilmont 40:976df7c37ad5 625
emilmont 40:976df7c37ad5 626 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 40:976df7c37ad5 627 Counter is in free running mode to generate periodic interrupts.
emilmont 40:976df7c37ad5 628
emilmont 40:976df7c37ad5 629 \param [in] ticks Number of ticks between two interrupts.
emilmont 40:976df7c37ad5 630
emilmont 40:976df7c37ad5 631 \return 0 Function succeeded.
emilmont 40:976df7c37ad5 632 \return 1 Function failed.
emilmont 40:976df7c37ad5 633
emilmont 40:976df7c37ad5 634 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 40:976df7c37ad5 635 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 40:976df7c37ad5 636 must contain a vendor-specific implementation of this function.
emilmont 40:976df7c37ad5 637
emilmont 40:976df7c37ad5 638 */
emilmont 40:976df7c37ad5 639 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 40:976df7c37ad5 640 {
emilmont 40:976df7c37ad5 641 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 40:976df7c37ad5 642
emilmont 40:976df7c37ad5 643 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont 40:976df7c37ad5 644 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 40:976df7c37ad5 645 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 40:976df7c37ad5 646 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 40:976df7c37ad5 647 SysTick_CTRL_TICKINT_Msk |
emilmont 40:976df7c37ad5 648 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 40:976df7c37ad5 649 return (0); /* Function successful */
emilmont 40:976df7c37ad5 650 }
emilmont 40:976df7c37ad5 651
emilmont 40:976df7c37ad5 652 #endif
emilmont 40:976df7c37ad5 653
emilmont 40:976df7c37ad5 654 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 40:976df7c37ad5 655
emilmont 40:976df7c37ad5 656
emilmont 40:976df7c37ad5 657
emilmont 40:976df7c37ad5 658
emilmont 40:976df7c37ad5 659 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 40:976df7c37ad5 660
emilmont 40:976df7c37ad5 661 #endif /* __CMSIS_GENERIC */
emilmont 40:976df7c37ad5 662
emilmont 40:976df7c37ad5 663 #ifdef __cplusplus
emilmont 40:976df7c37ad5 664 }
emilmont 40:976df7c37ad5 665 #endif