MARCUS NEVES CUNHA / QSPI_DISCO_F746NG

Implementation of the QSPI-Flash driver for the DISCO-STM32F746NG board. Allows usage of the MICRON 128Mb Quad-SPI Flash memory present on the board. Ported from library QSPI_DISCO_L476VG from ST.

Fork of QSPI_DISCO_F746NG by Sylvain Savon

QSPI_DISCO_F746NG.h@1:cff2435c21cf, 2017-08-01 (annotated)

Committer:
marcusncunha
Date:
Tue Aug 01 17:33:38 2017 +0000
Revision:
1:cff2435c21cf
Parent:
0:f391cd8f34c1 
1

Who changed what in which revision?

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capsavon 0:f391cd8f34c1 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
capsavon 0:f391cd8f34c1 2 *
capsavon 0:f391cd8f34c1 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
capsavon 0:f391cd8f34c1 4 * and associated documentation files (the "Software"), to deal in the Software without
capsavon 0:f391cd8f34c1 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
capsavon 0:f391cd8f34c1 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
capsavon 0:f391cd8f34c1 7 * Software is furnished to do so, subject to the following conditions:
capsavon 0:f391cd8f34c1 8 *
capsavon 0:f391cd8f34c1 9 * The above copyright notice and this permission notice shall be included in all copies or
capsavon 0:f391cd8f34c1 10 * substantial portions of the Software.
capsavon 0:f391cd8f34c1 11 *
capsavon 0:f391cd8f34c1 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
capsavon 0:f391cd8f34c1 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
capsavon 0:f391cd8f34c1 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
capsavon 0:f391cd8f34c1 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
capsavon 0:f391cd8f34c1 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
capsavon 0:f391cd8f34c1 17 */
capsavon 0:f391cd8f34c1 18
capsavon 0:f391cd8f34c1 19 #ifndef __QSPI_DISCO_F746NG_H
capsavon 0:f391cd8f34c1 20 #define __QSPI_DISCO_F746NG_H
capsavon 0:f391cd8f34c1 21
capsavon 0:f391cd8f34c1 22 #ifdef TARGET_DISCO_F746NG
capsavon 0:f391cd8f34c1 23
capsavon 0:f391cd8f34c1 24 #include "mbed.h"
capsavon 0:f391cd8f34c1 25 #include "stm32746g_discovery_qspi.h"
capsavon 0:f391cd8f34c1 26
capsavon 0:f391cd8f34c1 27 /*
capsavon 0:f391cd8f34c1 28 Class to drive the QSPI external memory (N25Q128A device)
capsavon 0:f391cd8f34c1 29 present on DISCO_F746NG board.
capsavon 0:f391cd8f34c1 30
capsavon 0:f391cd8f34c1 31 Usage:
marcusncunha 1:cff2435c21cf 32
marcusncunha 1:cff2435c21cf 33 #include "mbed.h"
marcusncunha 1:cff2435c21cf 34 #include "QSPI_DISCO_F746NG.h"
marcusncunha 1:cff2435c21cf 35
marcusncunha 1:cff2435c21cf 36 QSPI_DISCO_F746NG qspi;
marcusncunha 1:cff2435c21cf 37
marcusncunha 1:cff2435c21cf 38 #define BUFFER_SIZE ((uint32_t)32)
marcusncunha 1:cff2435c21cf 39 #define WRITE_READ_ADDR ((uint32_t)0x0050)
marcusncunha 1:cff2435c21cf 40
marcusncunha 1:cff2435c21cf 41 int main()
marcusncunha 1:cff2435c21cf 42 {
marcusncunha 1:cff2435c21cf 43 uint8_t WriteBuffer[BUFFER_SIZE] = "Hello World";
marcusncunha 1:cff2435c21cf 44 uint8_t ReadBuffer[BUFFER_SIZE];
marcusncunha 1:cff2435c21cf 45
marcusncunha 1:cff2435c21cf 46 qspi.Init();
marcusncunha 1:cff2435c21cf 47
marcusncunha 1:cff2435c21cf 48 // Erase memory
marcusncunha 1:cff2435c21cf 49 qspi.Erase_Block(WRITE_READ_ADDR);
marcusncunha 1:cff2435c21cf 50
marcusncunha 1:cff2435c21cf 51 // Write memory
marcusncunha 1:cff2435c21cf 52 qspi.Write(WriteBuffer, WRITE_READ_ADDR, 11);
marcusncunha 1:cff2435c21cf 53
marcusncunha 1:cff2435c21cf 54 // Read memory
marcusncunha 1:cff2435c21cf 55 qspi.Read(ReadBuffer, WRITE_READ_ADDR, 11);
marcusncunha 1:cff2435c21cf 56 ReadBuffer[11] = '\0';
marcusncunha 1:cff2435c21cf 57 printf("Buffer read [%s]\n", ReadBuffer);
marcusncunha 1:cff2435c21cf 58 }
marcusncunha 1:cff2435c21cf 59
capsavon 0:f391cd8f34c1 60 */
capsavon 0:f391cd8f34c1 61 class QSPI_DISCO_F746NG
capsavon 0:f391cd8f34c1 62 {
capsavon 0:f391cd8f34c1 63
capsavon 0:f391cd8f34c1 64 public:
capsavon 0:f391cd8f34c1 65 //! Constructor
capsavon 0:f391cd8f34c1 66 QSPI_DISCO_F746NG();
capsavon 0:f391cd8f34c1 67
capsavon 0:f391cd8f34c1 68 //! Destructor
capsavon 0:f391cd8f34c1 69 ~QSPI_DISCO_F746NG();
marcusncunha 1:cff2435c21cf 70
capsavon 0:f391cd8f34c1 71 /**
capsavon 0:f391cd8f34c1 72 * @brief Initializes the QSPI interface.
capsavon 0:f391cd8f34c1 73 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 74 */
capsavon 0:f391cd8f34c1 75 uint8_t Init(void);
capsavon 0:f391cd8f34c1 76
capsavon 0:f391cd8f34c1 77 /**
capsavon 0:f391cd8f34c1 78 * @brief De-Initializes the QSPI interface.
capsavon 0:f391cd8f34c1 79 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 80 */
capsavon 0:f391cd8f34c1 81 uint8_t DeInit(void);
capsavon 0:f391cd8f34c1 82
capsavon 0:f391cd8f34c1 83 /**
capsavon 0:f391cd8f34c1 84 * @brief Reads an amount of data from the QSPI memory.
capsavon 0:f391cd8f34c1 85 * @param pData: Pointer to data to be read
capsavon 0:f391cd8f34c1 86 * @param ReadAddr: Read start address
capsavon 0:f391cd8f34c1 87 * @param Size: Size of data to read
capsavon 0:f391cd8f34c1 88 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 89 */
capsavon 0:f391cd8f34c1 90 uint8_t Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
capsavon 0:f391cd8f34c1 91
capsavon 0:f391cd8f34c1 92 /**
capsavon 0:f391cd8f34c1 93 * @brief Writes an amount of data to the QSPI memory.
capsavon 0:f391cd8f34c1 94 * @param pData: Pointer to data to be written
capsavon 0:f391cd8f34c1 95 * @param WriteAddr: Write start address
capsavon 0:f391cd8f34c1 96 * @param Size: Size of data to write
capsavon 0:f391cd8f34c1 97 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 98 */
capsavon 0:f391cd8f34c1 99 uint8_t Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
capsavon 0:f391cd8f34c1 100
capsavon 0:f391cd8f34c1 101 /**
capsavon 0:f391cd8f34c1 102 * @brief Erases the specified block of the QSPI memory.
capsavon 0:f391cd8f34c1 103 * @param BlockAddress: Block address to erase
capsavon 0:f391cd8f34c1 104 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 105 */
capsavon 0:f391cd8f34c1 106 uint8_t Erase_Block(uint32_t BlockAddress);
capsavon 0:f391cd8f34c1 107
capsavon 0:f391cd8f34c1 108 /**
capsavon 0:f391cd8f34c1 109 * @brief Erases the entire QSPI memory.
capsavon 0:f391cd8f34c1 110 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 111 */
capsavon 0:f391cd8f34c1 112 uint8_t Erase_Chip(void);
capsavon 0:f391cd8f34c1 113
capsavon 0:f391cd8f34c1 114 /**
capsavon 0:f391cd8f34c1 115 * @brief Reads current status of the QSPI memory.
capsavon 0:f391cd8f34c1 116 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 117 */
capsavon 0:f391cd8f34c1 118 uint8_t GetStatus(void);
capsavon 0:f391cd8f34c1 119
capsavon 0:f391cd8f34c1 120 /**
capsavon 0:f391cd8f34c1 121 * @brief Return the configuration of the QSPI memory.
capsavon 0:f391cd8f34c1 122 * @param pInfo: pointer on the configuration structure
capsavon 0:f391cd8f34c1 123 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 124 */
capsavon 0:f391cd8f34c1 125 uint8_t GetInfo(QSPI_Info* pInfo);
capsavon 0:f391cd8f34c1 126
capsavon 0:f391cd8f34c1 127 /**
capsavon 0:f391cd8f34c1 128 * @brief Configure the QSPI in memory-mapped mode
capsavon 0:f391cd8f34c1 129 * @retval QSPI memory status
capsavon 0:f391cd8f34c1 130 */
capsavon 0:f391cd8f34c1 131 uint8_t EnableMemoryMappedMode(void);
capsavon 0:f391cd8f34c1 132
marcusncunha 1:cff2435c21cf 133 private:
capsavon 0:f391cd8f34c1 134
capsavon 0:f391cd8f34c1 135 };
capsavon 0:f391cd8f34c1 136
capsavon 0:f391cd8f34c1 137 #else
capsavon 0:f391cd8f34c1 138 #error "This class must be used with DISCO_F746NG board only."
capsavon 0:f391cd8f34c1 139 #endif // TARGET_DISCO_F746NG
capsavon 0:f391cd8f34c1 140
capsavon 0:f391cd8f34c1 141 #endif