marcus chiou / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c@636:cb7d56e6ff53, 2015-10-27 (annotated)

Committer:
marcusC
Date:
Tue Oct 27 07:54:54 2015 +0000
Revision:
636:cb7d56e6ff53
Parent:
499:d0e9408fd176 
Changed for DELTA_DFCM_NNN40; Do not initialize flash at mbed_sdk_init()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 445:3312ed629f01 1 /* mbed Microcontroller Library
mbed_official 445:3312ed629f01 2 * Copyright (c) 2006-2015 ARM Limited
mbed_official 445:3312ed629f01 3 *
mbed_official 445:3312ed629f01 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 445:3312ed629f01 5 * you may not use this file except in compliance with the License.
mbed_official 445:3312ed629f01 6 * You may obtain a copy of the License at
mbed_official 445:3312ed629f01 7 *
mbed_official 445:3312ed629f01 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 445:3312ed629f01 9 *
mbed_official 445:3312ed629f01 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 445:3312ed629f01 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 445:3312ed629f01 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 445:3312ed629f01 13 * See the License for the specific language governing permissions and
mbed_official 445:3312ed629f01 14 * limitations under the License.
mbed_official 445:3312ed629f01 15 */
mbed_official 445:3312ed629f01 16 #include "sleep_api.h"
mbed_official 445:3312ed629f01 17 #include "cmsis.h"
mbed_official 445:3312ed629f01 18
mbed_official 445:3312ed629f01 19 //Normal wait mode
mbed_official 445:3312ed629f01 20 void sleep(void)
mbed_official 445:3312ed629f01 21 {
mbed_official 445:3312ed629f01 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
mbed_official 445:3312ed629f01 23
mbed_official 445:3312ed629f01 24 //Normal sleep mode for ARM core:
mbed_official 445:3312ed629f01 25 SCB->SCR = 0;
mbed_official 445:3312ed629f01 26 __WFI();
mbed_official 445:3312ed629f01 27 }
mbed_official 445:3312ed629f01 28
mbed_official 445:3312ed629f01 29 //Very low-power stop mode
mbed_official 445:3312ed629f01 30 void deepsleep(void)
mbed_official 445:3312ed629f01 31 {
mbed_official 499:d0e9408fd176 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
mbed_official 499:d0e9408fd176 33 uint8_t ADC_HSC = 0;
mbed_official 499:d0e9408fd176 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
mbed_official 499:d0e9408fd176 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
mbed_official 499:d0e9408fd176 36 ADC_HSC = 1;
mbed_official 499:d0e9408fd176 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
mbed_official 499:d0e9408fd176 38 }
mbed_official 499:d0e9408fd176 39 }
mbed_official 499:d0e9408fd176 40
mbed_official 445:3312ed629f01 41 //Check if PLL/FLL is enabled:
mbed_official 445:3312ed629f01 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
mbed_official 445:3312ed629f01 43
mbed_official 445:3312ed629f01 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
mbed_official 445:3312ed629f01 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
mbed_official 445:3312ed629f01 46
mbed_official 445:3312ed629f01 47 //Deep sleep for ARM core:
mbed_official 445:3312ed629f01 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
mbed_official 445:3312ed629f01 49
mbed_official 445:3312ed629f01 50 __WFI();
mbed_official 445:3312ed629f01 51 //Switch back to PLL as clock source if needed
mbed_official 445:3312ed629f01 52 //The interrupt that woke up the device will run at reduced speed
mbed_official 445:3312ed629f01 53 if (PLL_FLL_en) {
mbed_official 489:119543c9f674 54
mbed_official 489:119543c9f674 55 #if defined (TARGET_K20D50M)
mbed_official 445:3312ed629f01 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
mbed_official 445:3312ed629f01 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
mbed_official 445:3312ed629f01 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
mbed_official 489:119543c9f674 59 #else
mbed_official 489:119543c9f674 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
mbed_official 489:119543c9f674 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
mbed_official 489:119543c9f674 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
mbed_official 489:119543c9f674 63 MCG->C6 = MCG_C6_VDIV0(0);
mbed_official 489:119543c9f674 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
mbed_official 489:119543c9f674 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
mbed_official 489:119543c9f674 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
mbed_official 489:119543c9f674 67 MCG->C5 = MCG_C5_PRDIV0(5);
mbed_official 489:119543c9f674 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
mbed_official 489:119543c9f674 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
mbed_official 489:119543c9f674 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
mbed_official 489:119543c9f674 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
mbed_official 489:119543c9f674 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
mbed_official 489:119543c9f674 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
mbed_official 489:119543c9f674 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
mbed_official 489:119543c9f674 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
mbed_official 489:119543c9f674 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
mbed_official 489:119543c9f674 77 #endif
mbed_official 445:3312ed629f01 78 }
mbed_official 499:d0e9408fd176 79
mbed_official 499:d0e9408fd176 80 if (ADC_HSC) {
mbed_official 499:d0e9408fd176 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
mbed_official 499:d0e9408fd176 82 }
mbed_official 445:3312ed629f01 83 }