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Kalman/Sonar/RF12B/RF_defs.h@1:6799c07fe510, 2012-11-07 (annotated)

Committer:: sv
Date:: Wed Nov 07 14:37:35 2012 +0000
Revision:: 1:6799c07fe510

Preliminary copy of 2012 code

Who changed what in which revision?

User	Revision	Line number	New contents of line
sv	1:6799c07fe510	1	/*
sv	1:6799c07fe510	2	* Open HR20
sv	1:6799c07fe510	3	*
sv	1:6799c07fe510	4	* target: ATmega169 @ 4 MHz in Honnywell Rondostat HR20E
sv	1:6799c07fe510	5	*
sv	1:6799c07fe510	6	* compiler: WinAVR-20071221
sv	1:6799c07fe510	7	* avr-libc 1.6.0
sv	1:6799c07fe510	8	* GCC 4.2.2
sv	1:6799c07fe510	9	*
sv	1:6799c07fe510	10	* copyright: 2008 Dario Carluccio (hr20-at-carluccio-dot-de)
sv	1:6799c07fe510	11	* 2008 Jiri Dobry (jdobry-at-centrum-dot-cz)
sv	1:6799c07fe510	12	* 2008 Mario Fischer (MarioFischer-at-gmx-dot-net)
sv	1:6799c07fe510	13	* 2007 Michael Smola (Michael-dot-Smola-at-gmx-dot-net)
sv	1:6799c07fe510	14	*
sv	1:6799c07fe510	15	* license: This program is free software; you can redistribute it and/or
sv	1:6799c07fe510	16	* modify it under the terms of the GNU Library General Public
sv	1:6799c07fe510	17	* License as published by the Free Software Foundation; either
sv	1:6799c07fe510	18	* version 2 of the License, or (at your option) any later version.
sv	1:6799c07fe510	19	*
sv	1:6799c07fe510	20	* This program is distributed in the hope that it will be useful,
sv	1:6799c07fe510	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
sv	1:6799c07fe510	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
sv	1:6799c07fe510	23	* GNU General Public License for more details.
sv	1:6799c07fe510	24	*
sv	1:6799c07fe510	25	* You should have received a copy of the GNU General Public License
sv	1:6799c07fe510	26	* along with this program. If not, see http:*www.gnu.org/licenses
sv	1:6799c07fe510	27	*/
sv	1:6799c07fe510	28
sv	1:6799c07fe510	29	/*
sv	1:6799c07fe510	30	* \file rfm.h
sv	1:6799c07fe510	31	* \brief functions to control the RFM12 Radio Transceiver Module
sv	1:6799c07fe510	32	* \author Mario Fischer <MarioFischer-at-gmx-dot-net>; Michael Smola <Michael-dot-Smola-at-gmx-dot-net>
sv	1:6799c07fe510	33	* \date $Date: 2010/04/17 17:57:02 $
sv	1:6799c07fe510	34	* $Rev: 260 $
sv	1:6799c07fe510	35	*/
sv	1:6799c07fe510	36
sv	1:6799c07fe510	37
sv	1:6799c07fe510	38	//#pragma once // multi-iclude prevention. gcc knows this pragma
sv	1:6799c07fe510	39	#ifndef rfm_H
sv	1:6799c07fe510	40	#define rfm_H
sv	1:6799c07fe510	41
sv	1:6799c07fe510	42
sv	1:6799c07fe510	43	#define RFM_SPI_16(OUTVAL) rfm_spi16(OUTVAL) //<! a function that gets a uint16_t (clocked out value) and returns a uint16_t (clocked in value)
sv	1:6799c07fe510	44
sv	1:6799c07fe510	45	#define RFM_CLK_OUTPUT 0
sv	1:6799c07fe510	46
sv	1:6799c07fe510	47	/*
sv	1:6799c07fe510	48	#define RFM_TESTPIN_INIT
sv	1:6799c07fe510	49	#define RFM_TESTPIN_ON
sv	1:6799c07fe510	50	#define RFM_TESTPIN_OFF
sv	1:6799c07fe510	51	#define RFM_TESTPIN_TOG
sv	1:6799c07fe510	52
sv	1:6799c07fe510	53	#define RFM_CONFIG_DISABLE 0x00 //<! RFM_CONFIG_*** are combinable flags, what the RFM shold do
sv	1:6799c07fe510	54	#define RFM_CONFIG_BROADCASTSTATUS 0x01 //<! Flag that enables the HR20's status broadcast every minute
sv	1:6799c07fe510	55
sv	1:6799c07fe510	56	#define RFM_CONFIG_ENABLEALL 0xff
sv	1:6799c07fe510	57	*/
sv	1:6799c07fe510	58
sv	1:6799c07fe510	59
sv	1:6799c07fe510	60	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	61	//
sv	1:6799c07fe510	62	// RFM status bits
sv	1:6799c07fe510	63	//
sv	1:6799c07fe510	64	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	65
sv	1:6799c07fe510	66	// Interrupt bits, latched ////////////////////////////////////////////////////
sv	1:6799c07fe510	67
sv	1:6799c07fe510	68	#define RFM_STATUS_FFIT 0x8000 // RX FIFO reached the progr. number of bits
sv	1:6799c07fe510	69	// Cleared by any FIFO read method
sv	1:6799c07fe510	70
sv	1:6799c07fe510	71	#define RFM_STATUS_RGIT 0x8000 // TX register is ready to receive
sv	1:6799c07fe510	72	// Cleared by TX write
sv	1:6799c07fe510	73
sv	1:6799c07fe510	74	#define RFM_STATUS_POR 0x4000 // Power On reset
sv	1:6799c07fe510	75	// Cleared by read status
sv	1:6799c07fe510	76
sv	1:6799c07fe510	77	#define RFM_STATUS_RGUR 0x2000 // TX register underrun, register over write
sv	1:6799c07fe510	78	// Cleared by read status
sv	1:6799c07fe510	79
sv	1:6799c07fe510	80	#define RFM_STATUS_FFOV 0x2000 // RX FIFO overflow
sv	1:6799c07fe510	81	// Cleared by read status
sv	1:6799c07fe510	82
sv	1:6799c07fe510	83	#define RFM_STATUS_WKUP 0x1000 // Wake up timer overflow
sv	1:6799c07fe510	84	// Cleared by read status
sv	1:6799c07fe510	85
sv	1:6799c07fe510	86	#define RFM_STATUS_EXT 0x0800 // Interupt changed to low
sv	1:6799c07fe510	87	// Cleared by read status
sv	1:6799c07fe510	88
sv	1:6799c07fe510	89	#define RFM_STATUS_LBD 0x0400 // Low battery detect
sv	1:6799c07fe510	90
sv	1:6799c07fe510	91	// Status bits ////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	92
sv	1:6799c07fe510	93	#define RFM_STATUS_FFEM 0x0200 // FIFO is empty
sv	1:6799c07fe510	94	#define RFM_STATUS_ATS 0x0100 // TX mode: Strong enough RF signal
sv	1:6799c07fe510	95	#define RFM_STATUS_RSSI 0x0100 // RX mode: signal strength above programmed limit
sv	1:6799c07fe510	96	#define RFM_STATUS_DQD 0x0080 // Data Quality detector output
sv	1:6799c07fe510	97	#define RFM_STATUS_CRL 0x0040 // Clock recovery lock
sv	1:6799c07fe510	98	#define RFM_STATUS_ATGL 0x0020 // Toggling in each AFC cycle
sv	1:6799c07fe510	99
sv	1:6799c07fe510	100	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	101	//
sv	1:6799c07fe510	102	// 1. Configuration Setting Command
sv	1:6799c07fe510	103	//
sv	1:6799c07fe510	104	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	105
sv	1:6799c07fe510	106	#define RFM_CONFIG 0x8000
sv	1:6799c07fe510	107
sv	1:6799c07fe510	108	#define RFM_CONFIG_EL 0x8080 // Enable TX Register
sv	1:6799c07fe510	109	#define RFM_CONFIG_EF 0x8040 // Enable RX FIFO buffer
sv	1:6799c07fe510	110	#define RFM_CONFIG_BAND_315 0x8000 // Frequency band
sv	1:6799c07fe510	111	#define RFM_CONFIG_BAND_433 0x8010
sv	1:6799c07fe510	112	#define RFM_CONFIG_BAND_868 0x8020
sv	1:6799c07fe510	113	#define RFM_CONFIG_BAND_915 0x8030
sv	1:6799c07fe510	114	#define RFM_CONFIG_X_8_5pf 0x8000 // Crystal Load Capacitor
sv	1:6799c07fe510	115	#define RFM_CONFIG_X_9_0pf 0x8001
sv	1:6799c07fe510	116	#define RFM_CONFIG_X_9_5pf 0x8002
sv	1:6799c07fe510	117	#define RFM_CONFIG_X_10_0pf 0x8003
sv	1:6799c07fe510	118	#define RFM_CONFIG_X_10_5pf 0x8004
sv	1:6799c07fe510	119	#define RFM_CONFIG_X_11_0pf 0x8005
sv	1:6799c07fe510	120	#define RFM_CONFIG_X_11_5pf 0x8006
sv	1:6799c07fe510	121	#define RFM_CONFIG_X_12_0pf 0x8007
sv	1:6799c07fe510	122	#define RFM_CONFIG_X_12_5pf 0x8008
sv	1:6799c07fe510	123	#define RFM_CONFIG_X_13_0pf 0x8009
sv	1:6799c07fe510	124	#define RFM_CONFIG_X_13_5pf 0x800A
sv	1:6799c07fe510	125	#define RFM_CONFIG_X_14_0pf 0x800B
sv	1:6799c07fe510	126	#define RFM_CONFIG_X_14_5pf 0x800C
sv	1:6799c07fe510	127	#define RFM_CONFIG_X_15_0pf 0x800D
sv	1:6799c07fe510	128	#define RFM_CONFIG_X_15_5pf 0x800E
sv	1:6799c07fe510	129	#define RFM_CONFIG_X_16_0pf 0x800F
sv	1:6799c07fe510	130
sv	1:6799c07fe510	131	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	132	//
sv	1:6799c07fe510	133	// 2. Power Management Command
sv	1:6799c07fe510	134	//
sv	1:6799c07fe510	135	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	136
sv	1:6799c07fe510	137	#define RFM_POWER_MANAGEMENT 0x8200
sv	1:6799c07fe510	138
sv	1:6799c07fe510	139	#define RFM_POWER_MANAGEMENT_ER 0x8280 // Enable receiver
sv	1:6799c07fe510	140	#define RFM_POWER_MANAGEMENT_EBB 0x8240 // Enable base band block
sv	1:6799c07fe510	141	#define RFM_POWER_MANAGEMENT_ET 0x8220 // Enable transmitter
sv	1:6799c07fe510	142	#define RFM_POWER_MANAGEMENT_ES 0x8210 // Enable synthesizer
sv	1:6799c07fe510	143	#define RFM_POWER_MANAGEMENT_EX 0x8208 // Enable crystal oscillator
sv	1:6799c07fe510	144	#define RFM_POWER_MANAGEMENT_EB 0x8204 // Enable low battery detector
sv	1:6799c07fe510	145	#define RFM_POWER_MANAGEMENT_EW 0x8202 // Enable wake-up timer
sv	1:6799c07fe510	146	#define RFM_POWER_MANAGEMENT_DC 0x8201 // Disable clock output of CLK pin
sv	1:6799c07fe510	147
sv	1:6799c07fe510	148	#ifndef RFM_CLK_OUTPUT
sv	1:6799c07fe510	149	#error RFM_CLK_OUTPUT must be defined to 0 or 1
sv	1:6799c07fe510	150	#endif
sv	1:6799c07fe510	151	#if RFM_CLK_OUTPUT
sv	1:6799c07fe510	152	#define RFM_TX_ON_PRE() RFM_SPI_16( \
sv	1:6799c07fe510	153	RFM_POWER_MANAGEMENT_ES \| \
sv	1:6799c07fe510	154	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	155	#define RFM_TX_ON() RFM_SPI_16( \
sv	1:6799c07fe510	156	RFM_POWER_MANAGEMENT_ET \| \
sv	1:6799c07fe510	157	RFM_POWER_MANAGEMENT_ES \| \
sv	1:6799c07fe510	158	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	159	#define RFM_RX_ON() RFM_SPI_16( \
sv	1:6799c07fe510	160	RFM_POWER_MANAGEMENT_ER \| \
sv	1:6799c07fe510	161	RFM_POWER_MANAGEMENT_EBB \| \
sv	1:6799c07fe510	162	RFM_POWER_MANAGEMENT_ES \| \
sv	1:6799c07fe510	163	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	164	#define RFM_OFF() RFM_SPI_16( \
sv	1:6799c07fe510	165	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	166	#else
sv	1:6799c07fe510	167	#define RFM_TX_ON_PRE() RFM_SPI_16( \
sv	1:6799c07fe510	168	RFM_POWER_MANAGEMENT_DC \| \
sv	1:6799c07fe510	169	RFM_POWER_MANAGEMENT_ES \| \
sv	1:6799c07fe510	170	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	171	#define RFM_TX_ON() RFM_SPI_16( \
sv	1:6799c07fe510	172	RFM_POWER_MANAGEMENT_DC \| \
sv	1:6799c07fe510	173	RFM_POWER_MANAGEMENT_ET \| \
sv	1:6799c07fe510	174	RFM_POWER_MANAGEMENT_ES \| \
sv	1:6799c07fe510	175	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	176	#define RFM_RX_ON() RFM_SPI_16( \
sv	1:6799c07fe510	177	RFM_POWER_MANAGEMENT_DC \| \
sv	1:6799c07fe510	178	RFM_POWER_MANAGEMENT_ER \| \
sv	1:6799c07fe510	179	RFM_POWER_MANAGEMENT_EBB \| \
sv	1:6799c07fe510	180	RFM_POWER_MANAGEMENT_ES \| \
sv	1:6799c07fe510	181	RFM_POWER_MANAGEMENT_EX )
sv	1:6799c07fe510	182	#define RFM_OFF() RFM_SPI_16(RFM_POWER_MANAGEMENT_DC)
sv	1:6799c07fe510	183	#endif
sv	1:6799c07fe510	184	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	185	//
sv	1:6799c07fe510	186	// 3. Frequency Setting Command
sv	1:6799c07fe510	187	//
sv	1:6799c07fe510	188	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	189
sv	1:6799c07fe510	190	#define RFM_FREQUENCY 0xA000
sv	1:6799c07fe510	191
sv	1:6799c07fe510	192	#define RFM_FREQ_315Band(v) (uint16_t)((v/10.0-31)*4000)
sv	1:6799c07fe510	193	#define RFM_FREQ_433Band(v) (uint16_t)((v/10.0-43)*4000)
sv	1:6799c07fe510	194	#define RFM_FREQ_868Band(v) (uint16_t)((v/20.0-43)*4000)
sv	1:6799c07fe510	195	#define RFM_FREQ_915Band(v) (uint16_t)((v/30.0-30)*4000)
sv	1:6799c07fe510	196
sv	1:6799c07fe510	197	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	198	//
sv	1:6799c07fe510	199	// 4. Data Rate Command
sv	1:6799c07fe510	200	//
sv	1:6799c07fe510	201	/////////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	202
sv	1:6799c07fe510	203	#define RFM_BAUD_RATE 9600
sv	1:6799c07fe510	204
sv	1:6799c07fe510	205	#define RFM_DATA_RATE 0xC600
sv	1:6799c07fe510	206
sv	1:6799c07fe510	207	#define RFM_DATA_RATE_CS 0xC680
sv	1:6799c07fe510	208	#define RFM_DATA_RATE_4800 0xC647
sv	1:6799c07fe510	209	#define RFM_DATA_RATE_9600 0xC623
sv	1:6799c07fe510	210	#define RFM_DATA_RATE_19200 0xC611
sv	1:6799c07fe510	211	#define RFM_DATA_RATE_38400 0xC608
sv	1:6799c07fe510	212	#define RFM_DATA_RATE_57600 0xC605
sv	1:6799c07fe510	213
sv	1:6799c07fe510	214	#define RFM_SET_DATARATE(baud) ( ((baud)<5400) ? (RFM_DATA_RATE_CS\|((43104/(baud))-1)) : (RFM_DATA_RATE\|((344828UL/(baud))-1)) )
sv	1:6799c07fe510	215
sv	1:6799c07fe510	216	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	217	//
sv	1:6799c07fe510	218	// 5. Receiver Control Command
sv	1:6799c07fe510	219	//
sv	1:6799c07fe510	220	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	221
sv	1:6799c07fe510	222	#define RFM_RX_CONTROL 0x9000
sv	1:6799c07fe510	223
sv	1:6799c07fe510	224	#define RFM_RX_CONTROL_P20_INT 0x9000 // Pin20 = ExternalInt
sv	1:6799c07fe510	225	#define RFM_RX_CONTROL_P20_VDI 0x9400 // Pin20 = VDI out
sv	1:6799c07fe510	226
sv	1:6799c07fe510	227	#define RFM_RX_CONTROL_VDI_FAST 0x9000 // fast VDI Response time
sv	1:6799c07fe510	228	#define RFM_RX_CONTROL_VDI_MED 0x9100 // medium
sv	1:6799c07fe510	229	#define RFM_RX_CONTROL_VDI_SLOW 0x9200 // slow
sv	1:6799c07fe510	230	#define RFM_RX_CONTROL_VDI_ON 0x9300 // Always on
sv	1:6799c07fe510	231
sv	1:6799c07fe510	232	#define RFM_RX_CONTROL_BW_400 0x9020 // bandwidth 400kHz
sv	1:6799c07fe510	233	#define RFM_RX_CONTROL_BW_340 0x9040 // bandwidth 340kHz
sv	1:6799c07fe510	234	#define RFM_RX_CONTROL_BW_270 0x9060 // bandwidth 270kHz
sv	1:6799c07fe510	235	#define RFM_RX_CONTROL_BW_200 0x9080 // bandwidth 200kHz
sv	1:6799c07fe510	236	#define RFM_RX_CONTROL_BW_134 0x90A0 // bandwidth 134kHz
sv	1:6799c07fe510	237	#define RFM_RX_CONTROL_BW_67 0x90C0 // bandwidth 67kHz
sv	1:6799c07fe510	238
sv	1:6799c07fe510	239	#define RFM_RX_CONTROL_GAIN_0 0x9000 // LNA gain 0db
sv	1:6799c07fe510	240	#define RFM_RX_CONTROL_GAIN_6 0x9008 // LNA gain -6db
sv	1:6799c07fe510	241	#define RFM_RX_CONTROL_GAIN_14 0x9010 // LNA gain -14db
sv	1:6799c07fe510	242	#define RFM_RX_CONTROL_GAIN_20 0x9018 // LNA gain -20db
sv	1:6799c07fe510	243
sv	1:6799c07fe510	244	#define RFM_RX_CONTROL_RSSI_103 0x9000 // DRSSI threshold -103dbm
sv	1:6799c07fe510	245	#define RFM_RX_CONTROL_RSSI_97 0x9001 // DRSSI threshold -97dbm
sv	1:6799c07fe510	246	#define RFM_RX_CONTROL_RSSI_91 0x9002 // DRSSI threshold -91dbm
sv	1:6799c07fe510	247	#define RFM_RX_CONTROL_RSSI_85 0x9003 // DRSSI threshold -85dbm
sv	1:6799c07fe510	248	#define RFM_RX_CONTROL_RSSI_79 0x9004 // DRSSI threshold -79dbm
sv	1:6799c07fe510	249	#define RFM_RX_CONTROL_RSSI_73 0x9005 // DRSSI threshold -73dbm
sv	1:6799c07fe510	250	//#define RFM_RX_CONTROL_RSSI_67 0x9006 // DRSSI threshold -67dbm // RF12B reserved
sv	1:6799c07fe510	251	//#define RFM_RX_CONTROL_RSSI_61 0x9007 // DRSSI threshold -61dbm // RF12B reserved
sv	1:6799c07fe510	252
sv	1:6799c07fe510	253	#define RFM_RX_CONTROL_BW(baud) (((baud)<8000) ? \
sv	1:6799c07fe510	254	RFM_RX_CONTROL_BW_67 : \
sv	1:6799c07fe510	255	( \
sv	1:6799c07fe510	256	((baud)<30000) ? \
sv	1:6799c07fe510	257	RFM_RX_CONTROL_BW_134 : \
sv	1:6799c07fe510	258	RFM_RX_CONTROL_BW_200 \
sv	1:6799c07fe510	259	))
sv	1:6799c07fe510	260
sv	1:6799c07fe510	261	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	262	//
sv	1:6799c07fe510	263	// 6. Data Filter Command
sv	1:6799c07fe510	264	//
sv	1:6799c07fe510	265	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	266
sv	1:6799c07fe510	267	#define RFM_DATA_FILTER 0xC228
sv	1:6799c07fe510	268
sv	1:6799c07fe510	269	#define RFM_DATA_FILTER_AL 0xC2A8 // clock recovery auto-lock
sv	1:6799c07fe510	270	#define RFM_DATA_FILTER_ML 0xC268 // clock recovery fast mode
sv	1:6799c07fe510	271	#define RFM_DATA_FILTER_DIG 0xC228 // data filter type digital
sv	1:6799c07fe510	272	#define RFM_DATA_FILTER_ANALOG 0xC238 // data filter type analog
sv	1:6799c07fe510	273	#define RFM_DATA_FILTER_DQD(level) (RFM_DATA_FILTER \| (level & 0x7))
sv	1:6799c07fe510	274
sv	1:6799c07fe510	275	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	276	//
sv	1:6799c07fe510	277	// 7. FIFO and Reset Mode Command
sv	1:6799c07fe510	278	//
sv	1:6799c07fe510	279	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	280
sv	1:6799c07fe510	281	#define RFM_FIFO 0xCA00
sv	1:6799c07fe510	282
sv	1:6799c07fe510	283	#define RFM_FIFO_AL 0xCA04 // FIFO Start condition sync-word/always
sv	1:6799c07fe510	284	#define RFM_FIFO_FF 0xCA02 // Enable FIFO fill
sv	1:6799c07fe510	285	#define RFM_FIFO_DR 0xCA01 // Disable hi sens reset mode
sv	1:6799c07fe510	286	#define RFM_FIFO_IT(level) (RFM_FIFO \| (( (level) & 0xF)<<4))
sv	1:6799c07fe510	287
sv	1:6799c07fe510	288	#define RFM_FIFO_OFF() RFM_SPI_16(RFM_FIFO_IT(8) \| RFM_FIFO_DR)
sv	1:6799c07fe510	289	#define RFM_FIFO_ON() RFM_SPI_16(RFM_FIFO_IT(8) \| RFM_FIFO_FF \| RFM_FIFO_DR)
sv	1:6799c07fe510	290
sv	1:6799c07fe510	291	/////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	292	//
sv	1:6799c07fe510	293	// 8. Receiver FIFO Read
sv	1:6799c07fe510	294	//
sv	1:6799c07fe510	295	/////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	296
sv	1:6799c07fe510	297	#define RFM_READ_FIFO() (RFM_SPI_16(0xB000) & 0xFF)
sv	1:6799c07fe510	298
sv	1:6799c07fe510	299	/////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	300	//
sv	1:6799c07fe510	301	// 9. AFC Command
sv	1:6799c07fe510	302	//
sv	1:6799c07fe510	303	/////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	304
sv	1:6799c07fe510	305	#define RFM_AFC 0xC400
sv	1:6799c07fe510	306
sv	1:6799c07fe510	307	#define RFM_AFC_EN 0xC401
sv	1:6799c07fe510	308	#define RFM_AFC_OE 0xC402
sv	1:6799c07fe510	309	#define RFM_AFC_FI 0xC404
sv	1:6799c07fe510	310	#define RFM_AFC_ST 0xC408
sv	1:6799c07fe510	311
sv	1:6799c07fe510	312	// Limits the value of the frequency offset register to the next values:
sv	1:6799c07fe510	313
sv	1:6799c07fe510	314	#define RFM_AFC_RANGE_LIMIT_NO 0xC400 // 0: No restriction
sv	1:6799c07fe510	315	#define RFM_AFC_RANGE_LIMIT_15_16 0xC410 // 1: +15 fres to -16 fres
sv	1:6799c07fe510	316	#define RFM_AFC_RANGE_LIMIT_7_8 0xC420 // 2: +7 fres to -8 fres
sv	1:6799c07fe510	317	#define RFM_AFC_RANGE_LIMIT_3_4 0xC430 // 3: +3 fres to -4 fres
sv	1:6799c07fe510	318
sv	1:6799c07fe510	319	// fres=2.5 kHz in 315MHz and 433MHz Bands
sv	1:6799c07fe510	320	// fres=5.0 kHz in 868MHz Band
sv	1:6799c07fe510	321	// fres=7.5 kHz in 915MHz Band
sv	1:6799c07fe510	322
sv	1:6799c07fe510	323	#define RFM_AFC_AUTO_OFF 0xC400 // 0: Auto mode off (Strobe is controlled by microcontroller)
sv	1:6799c07fe510	324	#define RFM_AFC_AUTO_ONCE 0xC440 // 1: Runs only once after each power-up
sv	1:6799c07fe510	325	#define RFM_AFC_AUTO_VDI 0xC480 // 2: Keep the foffset only during receiving(VDI=high)
sv	1:6799c07fe510	326	#define RFM_AFC_AUTO_INDEPENDENT 0xC4C0 // 3: Keep the foffset value independently trom the state of the VDI signal
sv	1:6799c07fe510	327
sv	1:6799c07fe510	328	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	329	//
sv	1:6799c07fe510	330	// 10. TX Configuration Control Command
sv	1:6799c07fe510	331	//
sv	1:6799c07fe510	332	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	333
sv	1:6799c07fe510	334	#define RFM_TX_CONTROL 0x9800
sv	1:6799c07fe510	335
sv	1:6799c07fe510	336	#define RFM_TX_CONTROL_POW_0 0x9800
sv	1:6799c07fe510	337	#define RFM_TX_CONTROL_POW_3 0x9801
sv	1:6799c07fe510	338	#define RFM_TX_CONTROL_POW_6 0x9802
sv	1:6799c07fe510	339	#define RFM_TX_CONTROL_POW_9 0x9803
sv	1:6799c07fe510	340	#define RFM_TX_CONTROL_POW_12 0x9804
sv	1:6799c07fe510	341	#define RFM_TX_CONTROL_POW_15 0x9805
sv	1:6799c07fe510	342	#define RFM_TX_CONTROL_POW_18 0x9806
sv	1:6799c07fe510	343	#define RFM_TX_CONTROL_POW_21 0x9807
sv	1:6799c07fe510	344	#define RFM_TX_CONTROL_MOD_15 0x9800
sv	1:6799c07fe510	345	#define RFM_TX_CONTROL_MOD_30 0x9810
sv	1:6799c07fe510	346	#define RFM_TX_CONTROL_MOD_45 0x9820
sv	1:6799c07fe510	347	#define RFM_TX_CONTROL_MOD_60 0x9830
sv	1:6799c07fe510	348	#define RFM_TX_CONTROL_MOD_75 0x9840
sv	1:6799c07fe510	349	#define RFM_TX_CONTROL_MOD_90 0x9850
sv	1:6799c07fe510	350	#define RFM_TX_CONTROL_MOD_105 0x9860
sv	1:6799c07fe510	351	#define RFM_TX_CONTROL_MOD_120 0x9870
sv	1:6799c07fe510	352	#define RFM_TX_CONTROL_MOD_135 0x9880
sv	1:6799c07fe510	353	#define RFM_TX_CONTROL_MOD_150 0x9890
sv	1:6799c07fe510	354	#define RFM_TX_CONTROL_MOD_165 0x98A0
sv	1:6799c07fe510	355	#define RFM_TX_CONTROL_MOD_180 0x98B0
sv	1:6799c07fe510	356	#define RFM_TX_CONTROL_MOD_195 0x98C0
sv	1:6799c07fe510	357	#define RFM_TX_CONTROL_MOD_210 0x98D0
sv	1:6799c07fe510	358	#define RFM_TX_CONTROL_MOD_225 0x98E0
sv	1:6799c07fe510	359	#define RFM_TX_CONTROL_MOD_240 0x98F0
sv	1:6799c07fe510	360	#define RFM_TX_CONTROL_MP 0x9900
sv	1:6799c07fe510	361
sv	1:6799c07fe510	362	#define RFM_TX_CONTROL_MOD(baud) (((baud)<8000) ? \
sv	1:6799c07fe510	363	RFM_TX_CONTROL_MOD_45 : \
sv	1:6799c07fe510	364	( \
sv	1:6799c07fe510	365	((baud)<20000) ? \
sv	1:6799c07fe510	366	RFM_TX_CONTROL_MOD_60 : \
sv	1:6799c07fe510	367	( \
sv	1:6799c07fe510	368	((baud)<30000) ? \
sv	1:6799c07fe510	369	RFM_TX_CONTROL_MOD_75 : \
sv	1:6799c07fe510	370	( \
sv	1:6799c07fe510	371	((baud)<40000) ? \
sv	1:6799c07fe510	372	RFM_TX_CONTROL_MOD_90 : \
sv	1:6799c07fe510	373	RFM_TX_CONTROL_MOD_120 \
sv	1:6799c07fe510	374	) \
sv	1:6799c07fe510	375	) \
sv	1:6799c07fe510	376	))
sv	1:6799c07fe510	377
sv	1:6799c07fe510	378	/////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	379	//
sv	1:6799c07fe510	380	// 11. Transmitter Register Write Command
sv	1:6799c07fe510	381	//
sv	1:6799c07fe510	382	/////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	383
sv	1:6799c07fe510	384	//#define RFM_WRITE(byte) RFM_SPI_16(0xB800 \| ((byte) & 0xFF))
sv	1:6799c07fe510	385	#define RFM_WRITE(byte) RFM_SPI_16(0xB800 \| (byte) )
sv	1:6799c07fe510	386
sv	1:6799c07fe510	387	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	388	//
sv	1:6799c07fe510	389	// 12. Wake-up Timer Command
sv	1:6799c07fe510	390	//
sv	1:6799c07fe510	391	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	392
sv	1:6799c07fe510	393	#define RFM_WAKEUP_TIMER 0xE000
sv	1:6799c07fe510	394	#define RFM_WAKEUP_SET(time) RFM_SPI_16(RFM_WAKEUP_TIMER \| (time))
sv	1:6799c07fe510	395
sv	1:6799c07fe510	396	#define RFM_WAKEUP_480s (RFM_WAKEUP_TIMER \|(11 << 8)\| 234)
sv	1:6799c07fe510	397	#define RFM_WAKEUP_240s (RFM_WAKEUP_TIMER \|(10 << 8)\| 234)
sv	1:6799c07fe510	398	#define RFM_WAKEUP_120s (RFM_WAKEUP_TIMER \|(9 << 8)\| 234)
sv	1:6799c07fe510	399	#define RFM_WAKEUP_119s (RFM_WAKEUP_TIMER \|(9 << 8)\| 232)
sv	1:6799c07fe510	400
sv	1:6799c07fe510	401	#define RFM_WAKEUP_60s (RFM_WAKEUP_TIMER \|(8 << 8) \| 235)
sv	1:6799c07fe510	402	#define RFM_WAKEUP_59s (RFM_WAKEUP_TIMER \|(8 << 8) \| 230)
sv	1:6799c07fe510	403
sv	1:6799c07fe510	404	#define RFM_WAKEUP_30s (RFM_WAKEUP_TIMER \|(7 << 8) \| 235)
sv	1:6799c07fe510	405	#define RFM_WAKEUP_29s (RFM_WAKEUP_TIMER \|(7 << 8) \| 227)
sv	1:6799c07fe510	406
sv	1:6799c07fe510	407	#define RFM_WAKEUP_8s (RFM_WAKEUP_TIMER \|(5 << 8) \| 250)
sv	1:6799c07fe510	408	#define RFM_WAKEUP_7s (RFM_WAKEUP_TIMER \|(5 << 8) \| 219)
sv	1:6799c07fe510	409	#define RFM_WAKEUP_6s (RFM_WAKEUP_TIMER \|(6 << 8) \| 94)
sv	1:6799c07fe510	410	#define RFM_WAKEUP_5s (RFM_WAKEUP_TIMER \|(5 << 8) \| 156)
sv	1:6799c07fe510	411	#define RFM_WAKEUP_4s (RFM_WAKEUP_TIMER \|(5 << 8) \| 125)
sv	1:6799c07fe510	412	#define RFM_WAKEUP_1s (RFM_WAKEUP_TIMER \|(2 << 8) \| 250)
sv	1:6799c07fe510	413	#define RFM_WAKEUP_900ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 225)
sv	1:6799c07fe510	414	#define RFM_WAKEUP_800ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 200)
sv	1:6799c07fe510	415	#define RFM_WAKEUP_700ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 175)
sv	1:6799c07fe510	416	#define RFM_WAKEUP_600ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 150)
sv	1:6799c07fe510	417	#define RFM_WAKEUP_500ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 125)
sv	1:6799c07fe510	418	#define RFM_WAKEUP_400ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 100)
sv	1:6799c07fe510	419	#define RFM_WAKEUP_300ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 75)
sv	1:6799c07fe510	420	#define RFM_WAKEUP_200ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 50)
sv	1:6799c07fe510	421	#define RFM_WAKEUP_100ms (RFM_WAKEUP_TIMER \|(2 << 8) \| 25)
sv	1:6799c07fe510	422
sv	1:6799c07fe510	423	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	424	//
sv	1:6799c07fe510	425	// 13. Low Duty-Cycle Command
sv	1:6799c07fe510	426	//
sv	1:6799c07fe510	427	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	428
sv	1:6799c07fe510	429	#define RFM_LOW_DUTY_CYCLE 0xC800
sv	1:6799c07fe510	430
sv	1:6799c07fe510	431	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	432	//
sv	1:6799c07fe510	433	// 14. Low Battery Detector Command
sv	1:6799c07fe510	434	//
sv	1:6799c07fe510	435	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	436
sv	1:6799c07fe510	437	#define RFM_LOW_BATT_DETECT 0xC000
sv	1:6799c07fe510	438	#define RFM_LOW_BATT_DETECT_D_1MHZ 0xC000
sv	1:6799c07fe510	439	#define RFM_LOW_BATT_DETECT_D_1_25MHZ 0xC020
sv	1:6799c07fe510	440	#define RFM_LOW_BATT_DETECT_D_1_66MHZ 0xC040
sv	1:6799c07fe510	441	#define RFM_LOW_BATT_DETECT_D_2MHZ 0xC060
sv	1:6799c07fe510	442	#define RFM_LOW_BATT_DETECT_D_2_5MHZ 0xC080
sv	1:6799c07fe510	443	#define RFM_LOW_BATT_DETECT_D_3_33MHZ 0xC0A0
sv	1:6799c07fe510	444	#define RFM_LOW_BATT_DETECT_D_5MHZ 0xC0C0
sv	1:6799c07fe510	445	#define RFM_LOW_BATT_DETECT_D_10MHZ 0xC0E0
sv	1:6799c07fe510	446
sv	1:6799c07fe510	447	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	448	//
sv	1:6799c07fe510	449	// 15. Status Read Command
sv	1:6799c07fe510	450	//
sv	1:6799c07fe510	451	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	452
sv	1:6799c07fe510	453	#define RFM_READ_STATUS() RFM_SPI_16(0x0000)
sv	1:6799c07fe510	454	#define RFM_READ_STATUS_FFIT() SPI_1 (0x00)
sv	1:6799c07fe510	455	#define RFM_READ_STATUS_RGIT RFM_READ_STATUS_FFIT
sv	1:6799c07fe510	456
sv	1:6799c07fe510	457	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	458
sv	1:6799c07fe510	459	// RFM air protocol flags:
sv	1:6799c07fe510	460
sv	1:6799c07fe510	461	#define RFMPROTO_FLAGS_BITASK_PACKETTYPE 0b11000000 //!< the uppermost 2 bits of the flags field encode the packettype
sv	1:6799c07fe510	462	#define RFMPROTO_FLAGS_PACKETTYPE_BROADCAST 0b00000000 //!< broadcast packettype (message from hr20, protocol; step 1)
sv	1:6799c07fe510	463	#define RFMPROTO_FLAGS_PACKETTYPE_COMMAND 0b01000000 //!< command packettype (message to hr20, protocol; step 2)
sv	1:6799c07fe510	464	#define RFMPROTO_FLAGS_PACKETTYPE_REPLY 0b10000000 //!< reply packettype (message from hr20, protocol; step 3)
sv	1:6799c07fe510	465	#define RFMPROTO_FLAGS_PACKETTYPE_SPECIAL 0b11000000 //!< currently unused packettype
sv	1:6799c07fe510	466
sv	1:6799c07fe510	467	#define RFMPROTO_FLAGS_BITASK_DEVICETYPE 0b00011111 //!< the lowermost 5 bytes denote the device type. this way other sensors and actors may coexist
sv	1:6799c07fe510	468	#define RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 0b00010100 //!< topen HR20 device type. 10100 is for decimal 20
sv	1:6799c07fe510	469
sv	1:6799c07fe510	470	#define RFMPROTO_IS_PACKETTYPE_BROADCAST(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_BROADCAST == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
sv	1:6799c07fe510	471	#define RFMPROTO_IS_PACKETTYPE_COMMAND(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_COMMAND == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
sv	1:6799c07fe510	472	#define RFMPROTO_IS_PACKETTYPE_REPLY(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_REPLY == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
sv	1:6799c07fe510	473	#define RFMPROTO_IS_PACKETTYPE_SPECIAL(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_SPECIAL == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
sv	1:6799c07fe510	474	#define RFMPROTO_IS_DEVICETYPE_OPENHR20(FLAGS) ( RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 == ((FLAGS) & RFMPROTO_FLAGS_BITASK_DEVICETYPE) )
sv	1:6799c07fe510	475
sv	1:6799c07fe510	476	///////////////////////////////////////////////////////////////////////////////
sv	1:6799c07fe510	477
sv	1:6799c07fe510	478	#endif