Mark B / Mbed 2 deprecated i2s

Dependencies:   mbed

main.cpp@0:6d43d111bdc1, 2010-01-20 (annotated)

Committer:
macaba
Date:
Wed Jan 20 11:44:57 2010 +0000
Revision:
0:6d43d111bdc1

        

        
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#include "mbed.h"





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#include "i2s.h"





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#include "type.h"





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#include "dma.h"





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extern volatile uint8_t *I2STXBuffer, *I2SRXBuffer;





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extern volatile uint32_t I2SReadLength;





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extern volatile uint32_t I2SWriteLength;





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extern volatile uint32_t I2SRXDone, I2STXDone;





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extern volatile uint32_t I2SDMA0Done, I2SDMA1Done;





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DigitalOut myled(LED1);





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int main() {





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    uint32_t i;





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    /* Configure temp register before reading */





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    for ( i = 0; i < BUFSIZE; i++ ) {	/* clear buffer */





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        I2STXBuffer[i] = i;





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        I2SRXBuffer[i] = 0;





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    }





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    if ( I2SInit() == FALSE ) {	/* initialize I2S */





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        while ( 1 );			/* Fatal error */





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    }





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#if I2S_DMA_ENABLED





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    /* USB RAM is used for test.





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    Please note, Ethernet has its own SRAM, but GPDMA can't access





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    that. GPDMA can access USB SRAM and IRAM. Ethernet DMA controller can





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    access both IRAM and Ethernet SRAM. */





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    LPC_SC->PCONP |= (1 << 29);	/* Enable GPDMA clock */





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    LPC_GPDMA->DMACIntTCClear = 0x03;





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    LPC_GPDMA->DMACIntErrClr = 0x03;





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    LPC_GPDMA->DMACConfig = 0x01;	/* Enable DMA channels, little endian */





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    while ( !(LPC_GPDMA->DMACConfig & 0x01) );





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    /* on DMA channel 0, Source is memory, destination is I2S TX FIFO,





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    on DMA channel 1, source is I2S RX FIFO, Destination is memory */





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    /* Enable channel and IE bit */





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    DMA_Init( 0, M2P );





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    LPC_GPDMACH0->DMACCConfig |= 0x18001 | (0x00 << 1) | (0x05 << 6) | (0x01 << 11);





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    DMA_Init( 1, P2M );





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    LPC_GPDMACH1->DMACCConfig |= 0x08001 | (0x06 << 1) | (0x00 << 6) | (0x02 << 11);





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    NVIC_EnableIRQ(DMA_IRQn);





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    I2SStart();





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    LPC_I2S->I2SDMA2 = (0x01<<0) | (0x08<<8);	/* Channel 2 is for RX, enable RX first. */





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    LPC_I2S->I2SDMA1 = (0x01<<1) | (0x01<<16);/* Channel 1 is for TX. */





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    /* Wait for both DMA0 and DMA1 to finish before verifying. */





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    while ( !I2SDMA0Done || !I2SDMA1Done );





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#else





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    /* Not DMA mode, enable I2S interrupts. */





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    /* RX FIFO depth is 1, TX FIFO depth is 8. */





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    I2SStart();





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    LPC_I2S->I2SIRQ = (8 << 16) | (1 << 8) | (0x01 << 0);





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    while ( I2SWriteLength < BUFSIZE ) {





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        while (((LPC_I2S->I2SSTATE >> 16) & 0xFF) == TXFIFO_FULL);





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        LPC_I2S->I2STXFIFO = I2STXBuffer[I2SWriteLength++];





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    }





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    I2STXDone = 1;





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    /* Wait for RX and TX complete before comparison */





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    while ( !I2SRXDone || !I2STXDone );





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#endif





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    /* Validate TX and RX buffer */





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    for ( i=1; i<BUFSIZE; i++ ) {





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        if ( I2SRXBuffer[i] != I2STXBuffer[i-1] ) {





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            while ( 1 );	/* Validation error */





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        }





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    }





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    return 0;





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}