Mark B
/
i2s
main.cpp@0:6d43d111bdc1, 2010-01-20 (annotated)
- Committer:
- macaba
- Date:
- Wed Jan 20 11:44:57 2010 +0000
- Revision:
- 0:6d43d111bdc1
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
macaba | 0:6d43d111bdc1 | 1 | #include "mbed.h" |
macaba | 0:6d43d111bdc1 | 2 | #include "i2s.h" |
macaba | 0:6d43d111bdc1 | 3 | #include "type.h" |
macaba | 0:6d43d111bdc1 | 4 | #include "dma.h" |
macaba | 0:6d43d111bdc1 | 5 | |
macaba | 0:6d43d111bdc1 | 6 | extern volatile uint8_t *I2STXBuffer, *I2SRXBuffer; |
macaba | 0:6d43d111bdc1 | 7 | extern volatile uint32_t I2SReadLength; |
macaba | 0:6d43d111bdc1 | 8 | extern volatile uint32_t I2SWriteLength; |
macaba | 0:6d43d111bdc1 | 9 | extern volatile uint32_t I2SRXDone, I2STXDone; |
macaba | 0:6d43d111bdc1 | 10 | extern volatile uint32_t I2SDMA0Done, I2SDMA1Done; |
macaba | 0:6d43d111bdc1 | 11 | |
macaba | 0:6d43d111bdc1 | 12 | DigitalOut myled(LED1); |
macaba | 0:6d43d111bdc1 | 13 | |
macaba | 0:6d43d111bdc1 | 14 | |
macaba | 0:6d43d111bdc1 | 15 | int main() { |
macaba | 0:6d43d111bdc1 | 16 | uint32_t i; |
macaba | 0:6d43d111bdc1 | 17 | /* Configure temp register before reading */ |
macaba | 0:6d43d111bdc1 | 18 | for ( i = 0; i < BUFSIZE; i++ ) { /* clear buffer */ |
macaba | 0:6d43d111bdc1 | 19 | I2STXBuffer[i] = i; |
macaba | 0:6d43d111bdc1 | 20 | I2SRXBuffer[i] = 0; |
macaba | 0:6d43d111bdc1 | 21 | } |
macaba | 0:6d43d111bdc1 | 22 | |
macaba | 0:6d43d111bdc1 | 23 | if ( I2SInit() == FALSE ) { /* initialize I2S */ |
macaba | 0:6d43d111bdc1 | 24 | while ( 1 ); /* Fatal error */ |
macaba | 0:6d43d111bdc1 | 25 | } |
macaba | 0:6d43d111bdc1 | 26 | |
macaba | 0:6d43d111bdc1 | 27 | #if I2S_DMA_ENABLED |
macaba | 0:6d43d111bdc1 | 28 | /* USB RAM is used for test. |
macaba | 0:6d43d111bdc1 | 29 | Please note, Ethernet has its own SRAM, but GPDMA can't access |
macaba | 0:6d43d111bdc1 | 30 | that. GPDMA can access USB SRAM and IRAM. Ethernet DMA controller can |
macaba | 0:6d43d111bdc1 | 31 | access both IRAM and Ethernet SRAM. */ |
macaba | 0:6d43d111bdc1 | 32 | LPC_SC->PCONP |= (1 << 29); /* Enable GPDMA clock */ |
macaba | 0:6d43d111bdc1 | 33 | |
macaba | 0:6d43d111bdc1 | 34 | LPC_GPDMA->DMACIntTCClear = 0x03; |
macaba | 0:6d43d111bdc1 | 35 | LPC_GPDMA->DMACIntErrClr = 0x03; |
macaba | 0:6d43d111bdc1 | 36 | |
macaba | 0:6d43d111bdc1 | 37 | LPC_GPDMA->DMACConfig = 0x01; /* Enable DMA channels, little endian */ |
macaba | 0:6d43d111bdc1 | 38 | while ( !(LPC_GPDMA->DMACConfig & 0x01) ); |
macaba | 0:6d43d111bdc1 | 39 | |
macaba | 0:6d43d111bdc1 | 40 | /* on DMA channel 0, Source is memory, destination is I2S TX FIFO, |
macaba | 0:6d43d111bdc1 | 41 | on DMA channel 1, source is I2S RX FIFO, Destination is memory */ |
macaba | 0:6d43d111bdc1 | 42 | /* Enable channel and IE bit */ |
macaba | 0:6d43d111bdc1 | 43 | DMA_Init( 0, M2P ); |
macaba | 0:6d43d111bdc1 | 44 | LPC_GPDMACH0->DMACCConfig |= 0x18001 | (0x00 << 1) | (0x05 << 6) | (0x01 << 11); |
macaba | 0:6d43d111bdc1 | 45 | DMA_Init( 1, P2M ); |
macaba | 0:6d43d111bdc1 | 46 | LPC_GPDMACH1->DMACCConfig |= 0x08001 | (0x06 << 1) | (0x00 << 6) | (0x02 << 11); |
macaba | 0:6d43d111bdc1 | 47 | |
macaba | 0:6d43d111bdc1 | 48 | NVIC_EnableIRQ(DMA_IRQn); |
macaba | 0:6d43d111bdc1 | 49 | |
macaba | 0:6d43d111bdc1 | 50 | I2SStart(); |
macaba | 0:6d43d111bdc1 | 51 | |
macaba | 0:6d43d111bdc1 | 52 | LPC_I2S->I2SDMA2 = (0x01<<0) | (0x08<<8); /* Channel 2 is for RX, enable RX first. */ |
macaba | 0:6d43d111bdc1 | 53 | LPC_I2S->I2SDMA1 = (0x01<<1) | (0x01<<16);/* Channel 1 is for TX. */ |
macaba | 0:6d43d111bdc1 | 54 | |
macaba | 0:6d43d111bdc1 | 55 | /* Wait for both DMA0 and DMA1 to finish before verifying. */ |
macaba | 0:6d43d111bdc1 | 56 | while ( !I2SDMA0Done || !I2SDMA1Done ); |
macaba | 0:6d43d111bdc1 | 57 | #else |
macaba | 0:6d43d111bdc1 | 58 | /* Not DMA mode, enable I2S interrupts. */ |
macaba | 0:6d43d111bdc1 | 59 | /* RX FIFO depth is 1, TX FIFO depth is 8. */ |
macaba | 0:6d43d111bdc1 | 60 | I2SStart(); |
macaba | 0:6d43d111bdc1 | 61 | LPC_I2S->I2SIRQ = (8 << 16) | (1 << 8) | (0x01 << 0); |
macaba | 0:6d43d111bdc1 | 62 | |
macaba | 0:6d43d111bdc1 | 63 | while ( I2SWriteLength < BUFSIZE ) { |
macaba | 0:6d43d111bdc1 | 64 | while (((LPC_I2S->I2SSTATE >> 16) & 0xFF) == TXFIFO_FULL); |
macaba | 0:6d43d111bdc1 | 65 | LPC_I2S->I2STXFIFO = I2STXBuffer[I2SWriteLength++]; |
macaba | 0:6d43d111bdc1 | 66 | } |
macaba | 0:6d43d111bdc1 | 67 | |
macaba | 0:6d43d111bdc1 | 68 | I2STXDone = 1; |
macaba | 0:6d43d111bdc1 | 69 | /* Wait for RX and TX complete before comparison */ |
macaba | 0:6d43d111bdc1 | 70 | while ( !I2SRXDone || !I2STXDone ); |
macaba | 0:6d43d111bdc1 | 71 | #endif |
macaba | 0:6d43d111bdc1 | 72 | |
macaba | 0:6d43d111bdc1 | 73 | /* Validate TX and RX buffer */ |
macaba | 0:6d43d111bdc1 | 74 | for ( i=1; i<BUFSIZE; i++ ) { |
macaba | 0:6d43d111bdc1 | 75 | if ( I2SRXBuffer[i] != I2STXBuffer[i-1] ) { |
macaba | 0:6d43d111bdc1 | 76 | while ( 1 ); /* Validation error */ |
macaba | 0:6d43d111bdc1 | 77 | } |
macaba | 0:6d43d111bdc1 | 78 | } |
macaba | 0:6d43d111bdc1 | 79 | return 0; |
macaba | 0:6d43d111bdc1 | 80 | } |