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i2s/dma.cpp@0:6d43d111bdc1, 2010-01-20 (annotated)

Committer:: macaba
Date:: Wed Jan 20 11:44:57 2010 +0000
Revision:: 0:6d43d111bdc1

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User	Revision	Line number	New contents of line
macaba	0:6d43d111bdc1	1	/*****************************************************************************
macaba	0:6d43d111bdc1	2	* dma.c: DMA module file for NXP LPC17xx Family Microprocessors
macaba	0:6d43d111bdc1	3	*
macaba	0:6d43d111bdc1	4	* Copyright(C) 2009, NXP Semiconductor
macaba	0:6d43d111bdc1	5	* All rights reserved.
macaba	0:6d43d111bdc1	6	*
macaba	0:6d43d111bdc1	7	* History
macaba	0:6d43d111bdc1	8	* 2009.05.26 ver 1.00 Prelimnary version, first Release
macaba	0:6d43d111bdc1	9	*
macaba	0:6d43d111bdc1	10	******************************************************************************/
macaba	0:6d43d111bdc1	11	#include "mbed.h"
macaba	0:6d43d111bdc1	12	#include "type.h"
macaba	0:6d43d111bdc1	13	#include "i2s.h"
macaba	0:6d43d111bdc1	14	#include "dma.h"
macaba	0:6d43d111bdc1	15
macaba	0:6d43d111bdc1	16	#if I2S_DMA_ENABLED
macaba	0:6d43d111bdc1	17	volatile uint32_t DMATCCount = 0;
macaba	0:6d43d111bdc1	18	volatile uint32_t DMAErrCount = 0;
macaba	0:6d43d111bdc1	19	volatile uint32_t I2SDMA0Done = 0;
macaba	0:6d43d111bdc1	20	volatile uint32_t I2SDMA1Done = 0;
macaba	0:6d43d111bdc1	21
macaba	0:6d43d111bdc1	22	/******************************************************************************
macaba	0:6d43d111bdc1	23	** Function name: DMA_IRQHandler
macaba	0:6d43d111bdc1	24	**
macaba	0:6d43d111bdc1	25	** Descriptions: DMA interrupt handler
macaba	0:6d43d111bdc1	26	**
macaba	0:6d43d111bdc1	27	** parameters: None
macaba	0:6d43d111bdc1	28	** Returned value: None
macaba	0:6d43d111bdc1	29	**
macaba	0:6d43d111bdc1	30	******************************************************************************/
macaba	0:6d43d111bdc1	31	void DMA_IRQHandler(void)
macaba	0:6d43d111bdc1	32	{
macaba	0:6d43d111bdc1	33	uint32_t regVal;
macaba	0:6d43d111bdc1	34
macaba	0:6d43d111bdc1	35	regVal = LPC_GPDMA->DMACIntTCStat;
macaba	0:6d43d111bdc1	36	if ( regVal )
macaba	0:6d43d111bdc1	37	{
macaba	0:6d43d111bdc1	38	DMATCCount++;
macaba	0:6d43d111bdc1	39	LPC_GPDMA->DMACIntTCClear \|= regVal;
macaba	0:6d43d111bdc1	40	if ( regVal & 0x01 )
macaba	0:6d43d111bdc1	41	{
macaba	0:6d43d111bdc1	42	I2SDMA0Done = 1;
macaba	0:6d43d111bdc1	43	}
macaba	0:6d43d111bdc1	44	else if ( regVal & 0x02 )
macaba	0:6d43d111bdc1	45	{
macaba	0:6d43d111bdc1	46	I2SDMA1Done = 1;
macaba	0:6d43d111bdc1	47	}
macaba	0:6d43d111bdc1	48	}
macaba	0:6d43d111bdc1	49
macaba	0:6d43d111bdc1	50	regVal = LPC_GPDMA->DMACIntErrStat;
macaba	0:6d43d111bdc1	51	if ( regVal )
macaba	0:6d43d111bdc1	52	{
macaba	0:6d43d111bdc1	53	DMAErrCount++;
macaba	0:6d43d111bdc1	54	LPC_GPDMA->DMACIntErrClr \|= regVal;
macaba	0:6d43d111bdc1	55	}
macaba	0:6d43d111bdc1	56
macaba	0:6d43d111bdc1	57	}
macaba	0:6d43d111bdc1	58
macaba	0:6d43d111bdc1	59	/******************************************************************************
macaba	0:6d43d111bdc1	60	** Function name: DMA_Init
macaba	0:6d43d111bdc1	61	**
macaba	0:6d43d111bdc1	62	** Descriptions:
macaba	0:6d43d111bdc1	63	**
macaba	0:6d43d111bdc1	64	** parameters:
macaba	0:6d43d111bdc1	65	** Returned value:
macaba	0:6d43d111bdc1	66	**
macaba	0:6d43d111bdc1	67	******************************************************************************/
macaba	0:6d43d111bdc1	68	uint32_t DMA_Init( uint32_t ChannelNum, uint32_t DMAMode )
macaba	0:6d43d111bdc1	69	{
macaba	0:6d43d111bdc1	70	if ( ChannelNum == 0 )
macaba	0:6d43d111bdc1	71	{
macaba	0:6d43d111bdc1	72	LPC_GPDMA->DMACIntTCClear = 0x01;
macaba	0:6d43d111bdc1	73	if ( DMAMode == M2P )
macaba	0:6d43d111bdc1	74	{
macaba	0:6d43d111bdc1	75	/* Ch0 set for M2P transfer from mempry to I2S TX FIFO. */
macaba	0:6d43d111bdc1	76	LPC_GPDMACH0->DMACCSrcAddr = DMA_SRC;
macaba	0:6d43d111bdc1	77	LPC_GPDMACH0->DMACCDestAddr = DMA_I2S_TX_FIFO;
macaba	0:6d43d111bdc1	78	/* The burst size is set to 1. Terminal Count Int enable */
macaba	0:6d43d111bdc1	79	LPC_GPDMACH0->DMACCControl = (DMA_SIZE & 0x0FFF) \| (0x00 << 12) \| (0x00 << 15)
macaba	0:6d43d111bdc1	80	\| (1 << 26) \| 0x80000000;
macaba	0:6d43d111bdc1	81	}
macaba	0:6d43d111bdc1	82	else if ( DMAMode == P2M )
macaba	0:6d43d111bdc1	83	{
macaba	0:6d43d111bdc1	84	/* Ch0 set for P2M transfer from I2S RX FIFO to memory. */
macaba	0:6d43d111bdc1	85	LPC_GPDMACH0->DMACCSrcAddr = DMA_I2S_RX_FIFO;
macaba	0:6d43d111bdc1	86	LPC_GPDMACH0->DMACCDestAddr = DMA_DST;
macaba	0:6d43d111bdc1	87	/* The burst size is set to 1. Terminal Count Int enable. */
macaba	0:6d43d111bdc1	88	LPC_GPDMACH0->DMACCControl = (DMA_SIZE & 0x0FFF) \| (0x00 << 12) \| (0x00 << 15)
macaba	0:6d43d111bdc1	89	\| (1 << 27) \| 0x80000000;
macaba	0:6d43d111bdc1	90	}
macaba	0:6d43d111bdc1	91	else if ( DMAMode == P2P )
macaba	0:6d43d111bdc1	92	{
macaba	0:6d43d111bdc1	93	/* Ch0 set for P2P transfer from I2S DAO to I2S DAI. */
macaba	0:6d43d111bdc1	94	LPC_GPDMACH0->DMACCSrcAddr = DMA_I2S_TX_FIFO;
macaba	0:6d43d111bdc1	95	LPC_GPDMACH0->DMACCDestAddr = DMA_I2S_RX_FIFO;
macaba	0:6d43d111bdc1	96	/* The burst size is set to 32. */
macaba	0:6d43d111bdc1	97	LPC_GPDMACH0->DMACCControl = (DMA_SIZE & 0x0FFF) \| (0x04 << 12) \| (0x04 << 15)
macaba	0:6d43d111bdc1	98	\| 0x80000000;
macaba	0:6d43d111bdc1	99	}
macaba	0:6d43d111bdc1	100	else
macaba	0:6d43d111bdc1	101	{
macaba	0:6d43d111bdc1	102	return ( FALSE );
macaba	0:6d43d111bdc1	103	}
macaba	0:6d43d111bdc1	104	}
macaba	0:6d43d111bdc1	105	else if ( ChannelNum == 1 )
macaba	0:6d43d111bdc1	106	{
macaba	0:6d43d111bdc1	107	LPC_GPDMA->DMACIntTCClear = 0x02;
macaba	0:6d43d111bdc1	108	if ( DMAMode == M2P )
macaba	0:6d43d111bdc1	109	{
macaba	0:6d43d111bdc1	110	/* Ch1 set for M2P transfer from mempry to I2S TX FIFO. */
macaba	0:6d43d111bdc1	111	LPC_GPDMACH1->DMACCSrcAddr = DMA_SRC;
macaba	0:6d43d111bdc1	112	LPC_GPDMACH1->DMACCDestAddr = DMA_I2S_TX_FIFO;
macaba	0:6d43d111bdc1	113	/* The burst size is set to 1. Terminal Count Int enable. */
macaba	0:6d43d111bdc1	114	LPC_GPDMACH1->DMACCControl = (DMA_SIZE & 0x0FFF) \| (0x00 << 12) \| (0x00 << 15)
macaba	0:6d43d111bdc1	115	\| (1 << 26) \| 0x80000000;
macaba	0:6d43d111bdc1	116	}
macaba	0:6d43d111bdc1	117	else if ( DMAMode == P2M )
macaba	0:6d43d111bdc1	118	{
macaba	0:6d43d111bdc1	119	/* Ch1 set for P2M transfer from I2S RX FIFO to memory. */
macaba	0:6d43d111bdc1	120	LPC_GPDMACH1->DMACCSrcAddr = DMA_I2S_RX_FIFO;
macaba	0:6d43d111bdc1	121	LPC_GPDMACH1->DMACCDestAddr = DMA_DST;
macaba	0:6d43d111bdc1	122	/* The burst size is set to 1. Terminal Count Int enable. */
macaba	0:6d43d111bdc1	123	LPC_GPDMACH1->DMACCControl = (DMA_SIZE & 0x0FFF) \| (0x00 << 12) \| (0x00 << 15)
macaba	0:6d43d111bdc1	124	\| (1 << 27) \| 0x80000000;
macaba	0:6d43d111bdc1	125	}
macaba	0:6d43d111bdc1	126	else if ( DMAMode == P2P )
macaba	0:6d43d111bdc1	127	{
macaba	0:6d43d111bdc1	128	/* Ch1 set for P2P transfer from I2S DAO to I2S DAI. */
macaba	0:6d43d111bdc1	129	LPC_GPDMACH1->DMACCSrcAddr = DMA_I2S_TX_FIFO;
macaba	0:6d43d111bdc1	130	LPC_GPDMACH1->DMACCDestAddr = DMA_I2S_RX_FIFO;
macaba	0:6d43d111bdc1	131	/* The burst size is set to 32. */
macaba	0:6d43d111bdc1	132	LPC_GPDMACH1->DMACCControl = (DMA_SIZE & 0x0FFF) \| (0x04 << 12) \| (0x04 << 15)
macaba	0:6d43d111bdc1	133	\| 0x80000000;
macaba	0:6d43d111bdc1	134	}
macaba	0:6d43d111bdc1	135	else
macaba	0:6d43d111bdc1	136	{
macaba	0:6d43d111bdc1	137	return ( FALSE );
macaba	0:6d43d111bdc1	138	}
macaba	0:6d43d111bdc1	139	}
macaba	0:6d43d111bdc1	140	else
macaba	0:6d43d111bdc1	141	{
macaba	0:6d43d111bdc1	142	return ( FALSE );
macaba	0:6d43d111bdc1	143	}
macaba	0:6d43d111bdc1	144	return( TRUE );
macaba	0:6d43d111bdc1	145	}
macaba	0:6d43d111bdc1	146
macaba	0:6d43d111bdc1	147	#endif /* end if DMA_ENABLED */
macaba	0:6d43d111bdc1	148
macaba	0:6d43d111bdc1	149	/******************************************************************************
macaba	0:6d43d111bdc1	150	** End Of File
macaba	0:6d43d111bdc1	151	******************************************************************************/

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	20 Jan 2010
Imports:	56
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	2

i2s/dma.cpp@0:6d43d111bdc1, 2010-01-20 (annotated)

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