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core_cm4.h

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00001 /**************************************************************************//**
00002  * @file     core_cm4.h
00003  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
00004  * @version  V3.20
00005  * @date     25. February 2013
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2013 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #if defined ( __ICCARM__ )
00039  #pragma system_include  /* treat file as system include file for MISRA check */
00040 #endif
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 #ifndef __CORE_CM4_H_GENERIC
00047 #define __CORE_CM4_H_GENERIC
00048 
00049 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00050   CMSIS violates the following MISRA-C:2004 rules:
00051 
00052    \li Required Rule 8.5, object/function definition in header file.<br>
00053      Function definitions in header files are used to allow 'inlining'.
00054 
00055    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00056      Unions are used for effective representation of core registers.
00057 
00058    \li Advisory Rule 19.7, Function-like macro defined.<br>
00059      Function-like macros are used to allow more efficient code.
00060  */
00061 
00062 
00063 /*******************************************************************************
00064  *                 CMSIS definitions
00065  ******************************************************************************/
00066 /** \ingroup Cortex_M4
00067   @{
00068  */
00069 
00070 /*  CMSIS CM4 definitions */
00071 #define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
00072 #define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
00073 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
00074                                     __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00075 
00076 #define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
00077 
00078 
00079 #if   defined ( __CC_ARM )
00080   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00081   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00082   #define __STATIC_INLINE  static __inline
00083 
00084 #elif defined ( __ICCARM__ )
00085   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00086   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00087   #define __STATIC_INLINE  static inline
00088 
00089 #elif defined ( __TMS470__ )
00090   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00091   #define __STATIC_INLINE  static inline
00092 
00093 #elif defined ( __GNUC__ )
00094   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00095   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00096   #define __STATIC_INLINE  static inline
00097 
00098 #elif defined ( __TASKING__ )
00099   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00100   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00101   #define __STATIC_INLINE  static inline
00102 
00103 #endif
00104 
00105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
00106 */
00107 #if defined ( __CC_ARM )
00108   #if defined __TARGET_FPU_VFP
00109     #if (__FPU_PRESENT == 1)
00110       #define __FPU_USED       1
00111     #else
00112       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00113       #define __FPU_USED       0
00114     #endif
00115   #else
00116     #define __FPU_USED         0
00117   #endif
00118 
00119 #elif defined ( __ICCARM__ )
00120   #if defined __ARMVFP__
00121     #if (__FPU_PRESENT == 1)
00122       #define __FPU_USED       1
00123     #else
00124       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00125       #define __FPU_USED       0
00126     #endif
00127   #else
00128     #define __FPU_USED         0
00129   #endif
00130 
00131 #elif defined ( __TMS470__ )
00132   #if defined __TI_VFP_SUPPORT__
00133     #if (__FPU_PRESENT == 1)
00134       #define __FPU_USED       1
00135     #else
00136       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00137       #define __FPU_USED       0
00138     #endif
00139   #else
00140     #define __FPU_USED         0
00141   #endif
00142 
00143 #elif defined ( __GNUC__ )
00144   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00145     #if (__FPU_PRESENT == 1)
00146       #define __FPU_USED       1
00147     #else
00148       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00149       #define __FPU_USED       0
00150     #endif
00151   #else
00152     #define __FPU_USED         0
00153   #endif
00154 
00155 #elif defined ( __TASKING__ )
00156   #if defined __FPU_VFP__
00157     #if (__FPU_PRESENT == 1)
00158       #define __FPU_USED       1
00159     #else
00160       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00161       #define __FPU_USED       0
00162     #endif
00163   #else
00164     #define __FPU_USED         0
00165   #endif
00166 #endif
00167 
00168 #include <stdint.h>                      /* standard types definitions                      */
00169 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00170 #include <core_cmFunc.h>                 /* Core Function Access                            */
00171 #include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
00172 
00173 #endif /* __CORE_CM4_H_GENERIC */
00174 
00175 #ifndef __CMSIS_GENERIC
00176 
00177 #ifndef __CORE_CM4_H_DEPENDANT
00178 #define __CORE_CM4_H_DEPENDANT
00179 
00180 /* check device defines and use defaults */
00181 #if defined __CHECK_DEVICE_DEFINES
00182   #ifndef __CM4_REV
00183     #define __CM4_REV               0x0000
00184     #warning "__CM4_REV not defined in device header file; using default!"
00185   #endif
00186 
00187   #ifndef __FPU_PRESENT
00188     #define __FPU_PRESENT             0
00189     #warning "__FPU_PRESENT not defined in device header file; using default!"
00190   #endif
00191 
00192   #ifndef __MPU_PRESENT
00193     #define __MPU_PRESENT             0
00194     #warning "__MPU_PRESENT not defined in device header file; using default!"
00195   #endif
00196 
00197   #ifndef __NVIC_PRIO_BITS
00198     #define __NVIC_PRIO_BITS          4
00199     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00200   #endif
00201 
00202   #ifndef __Vendor_SysTickConfig
00203     #define __Vendor_SysTickConfig    0
00204     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00205   #endif
00206 #endif
00207 
00208 /* IO definitions (access restrictions to peripheral registers) */
00209 /**
00210     \defgroup CMSIS_glob_defs CMSIS Global Defines
00211 
00212     <strong>IO Type Qualifiers</strong> are used
00213     \li to specify the access to peripheral variables.
00214     \li for automatic generation of peripheral register debug information.
00215 */
00216 #ifdef __cplusplus
00217   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00218 #else
00219   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00220 #endif
00221 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00222 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00223 
00224 /*@} end of group Cortex_M4 */
00225 
00226 
00227 
00228 /*******************************************************************************
00229  *                 Register Abstraction
00230   Core Register contain:
00231   - Core Register
00232   - Core NVIC Register
00233   - Core SCB Register
00234   - Core SysTick Register
00235   - Core Debug Register
00236   - Core MPU Register
00237   - Core FPU Register
00238  ******************************************************************************/
00239 /** \defgroup CMSIS_core_register Defines and Type Definitions
00240     \brief Type definitions and defines for Cortex-M processor based devices.
00241 */
00242 
00243 /** \ingroup    CMSIS_core_register
00244     \defgroup   CMSIS_CORE  Status and Control Registers
00245     \brief  Core Register type definitions.
00246   @{
00247  */
00248 
00249 /** \brief  Union type to access the Application Program Status Register (APSR).
00250  */
00251 typedef union
00252 {
00253   struct
00254   {
00255 #if (__CORTEX_M != 0x04)
00256     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00257 #else
00258     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00259     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00260     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
00261 #endif
00262     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00263     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00264     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00265     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00266     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00267   } b;                                   /*!< Structure used for bit  access                  */
00268   uint32_t w;                            /*!< Type      used for word access                  */
00269 } APSR_Type;
00270 
00271 
00272 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00273  */
00274 typedef union
00275 {
00276   struct
00277   {
00278     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00279     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00280   } b;                                   /*!< Structure used for bit  access                  */
00281   uint32_t w;                            /*!< Type      used for word access                  */
00282 } IPSR_Type;
00283 
00284 
00285 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00286  */
00287 typedef union
00288 {
00289   struct
00290   {
00291     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00292 #if (__CORTEX_M != 0x04)
00293     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00294 #else
00295     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
00296     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00297     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
00298 #endif
00299     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00300     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00301     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00302     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00303     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00304     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00305     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00306   } b;                                   /*!< Structure used for bit  access                  */
00307   uint32_t w;                            /*!< Type      used for word access                  */
00308 } xPSR_Type;
00309 
00310 
00311 /** \brief  Union type to access the Control Registers (CONTROL).
00312  */
00313 typedef union
00314 {
00315   struct
00316   {
00317     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00318     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00319     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
00320     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
00321   } b;                                   /*!< Structure used for bit  access                  */
00322   uint32_t w;                            /*!< Type      used for word access                  */
00323 } CONTROL_Type;
00324 
00325 /*@} end of group CMSIS_CORE */
00326 
00327 
00328 /** \ingroup    CMSIS_core_register
00329     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00330     \brief      Type definitions for the NVIC Registers
00331   @{
00332  */
00333 
00334 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00335  */
00336 typedef struct
00337 {
00338   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00339        uint32_t RESERVED0[24];
00340   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
00341        uint32_t RSERVED1[24];
00342   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
00343        uint32_t RESERVED2[24];
00344   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
00345        uint32_t RESERVED3[24];
00346   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
00347        uint32_t RESERVED4[56];
00348   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00349        uint32_t RESERVED5[644];
00350   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
00351 }  NVIC_Type;
00352 
00353 /* Software Triggered Interrupt Register Definitions */
00354 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
00355 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
00356 
00357 /*@} end of group CMSIS_NVIC */
00358 
00359 
00360 /** \ingroup  CMSIS_core_register
00361     \defgroup CMSIS_SCB     System Control Block (SCB)
00362     \brief      Type definitions for the System Control Block Registers
00363   @{
00364  */
00365 
00366 /** \brief  Structure type to access the System Control Block (SCB).
00367  */
00368 typedef struct
00369 {
00370   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00371   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00372   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
00373   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00374   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00375   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00376   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00377   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00378   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
00379   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
00380   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
00381   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
00382   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
00383   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
00384   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
00385   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
00386   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
00387   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
00388   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
00389        uint32_t RESERVED0[5];
00390   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
00391 } SCB_Type;
00392 
00393 /* SCB CPUID Register Definitions */
00394 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00395 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00396 
00397 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00398 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00399 
00400 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00401 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00402 
00403 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00404 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00405 
00406 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00407 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
00408 
00409 /* SCB Interrupt Control State Register Definitions */
00410 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00411 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00412 
00413 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00414 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00415 
00416 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00417 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00418 
00419 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00420 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00421 
00422 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00423 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00424 
00425 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00426 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00427 
00428 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00429 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00430 
00431 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00432 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00433 
00434 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
00435 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00436 
00437 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00438 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
00439 
00440 /* SCB Vector Table Offset Register Definitions */
00441 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00442 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00443 
00444 /* SCB Application Interrupt and Reset Control Register Definitions */
00445 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00446 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00447 
00448 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00449 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00450 
00451 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00452 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00453 
00454 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
00455 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00456 
00457 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00458 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00459 
00460 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00461 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00462 
00463 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
00464 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
00465 
00466 /* SCB System Control Register Definitions */
00467 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00468 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00469 
00470 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00471 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00472 
00473 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00474 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00475 
00476 /* SCB Configuration Control Register Definitions */
00477 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00478 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00479 
00480 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
00481 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00482 
00483 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
00484 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00485 
00486 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00487 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00488 
00489 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
00490 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00491 
00492 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
00493 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
00494 
00495 /* SCB System Handler Control and State Register Definitions */
00496 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
00497 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00498 
00499 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
00500 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00501 
00502 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
00503 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00504 
00505 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00506 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00507 
00508 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
00509 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00510 
00511 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
00512 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00513 
00514 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
00515 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00516 
00517 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
00518 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00519 
00520 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
00521 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00522 
00523 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
00524 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00525 
00526 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
00527 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00528 
00529 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
00530 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00531 
00532 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
00533 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00534 
00535 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
00536 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
00537 
00538 /* SCB Configurable Fault Status Registers Definitions */
00539 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
00540 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00541 
00542 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
00543 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00544 
00545 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00546 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00547 
00548 /* SCB Hard Fault Status Registers Definitions */
00549 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
00550 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00551 
00552 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
00553 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00554 
00555 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
00556 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00557 
00558 /* SCB Debug Fault Status Register Definitions */
00559 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
00560 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00561 
00562 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
00563 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00564 
00565 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
00566 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00567 
00568 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
00569 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00570 
00571 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
00572 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
00573 
00574 /*@} end of group CMSIS_SCB */
00575 
00576 
00577 /** \ingroup  CMSIS_core_register
00578     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00579     \brief      Type definitions for the System Control and ID Register not in the SCB
00580   @{
00581  */
00582 
00583 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
00584  */
00585 typedef struct
00586 {
00587        uint32_t RESERVED0[1];
00588   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
00589   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
00590 } SCnSCB_Type;
00591 
00592 /* Interrupt Controller Type Register Definitions */
00593 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
00594 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
00595 
00596 /* Auxiliary Control Register Definitions */
00597 #define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
00598 #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
00599 
00600 #define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
00601 #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
00602 
00603 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
00604 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00605 
00606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
00607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00608 
00609 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
00610 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
00611 
00612 /*@} end of group CMSIS_SCnotSCB */
00613 
00614 
00615 /** \ingroup  CMSIS_core_register
00616     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00617     \brief      Type definitions for the System Timer Registers.
00618   @{
00619  */
00620 
00621 /** \brief  Structure type to access the System Timer (SysTick).
00622  */
00623 typedef struct
00624 {
00625   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00626   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00627   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00628   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00629 } SysTick_Type;
00630 
00631 /* SysTick Control / Status Register Definitions */
00632 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00633 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00634 
00635 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00636 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00637 
00638 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00639 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00640 
00641 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00642 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
00643 
00644 /* SysTick Reload Register Definitions */
00645 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00646 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
00647 
00648 /* SysTick Current Register Definitions */
00649 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00650 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
00651 
00652 /* SysTick Calibration Register Definitions */
00653 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00654 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00655 
00656 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00657 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00658 
00659 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00660 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
00661 
00662 /*@} end of group CMSIS_SysTick */
00663 
00664 
00665 /** \ingroup  CMSIS_core_register
00666     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00667     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
00668   @{
00669  */
00670 
00671 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00672  */
00673 typedef struct
00674 {
00675   __O  union
00676   {
00677     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
00678     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
00679     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
00680   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
00681        uint32_t RESERVED0[864];
00682   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
00683        uint32_t RESERVED1[15];
00684   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
00685        uint32_t RESERVED2[15];
00686   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
00687        uint32_t RESERVED3[29];
00688   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
00689   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
00690   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
00691        uint32_t RESERVED4[43];
00692   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
00693   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
00694        uint32_t RESERVED5[6];
00695   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00696   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00697   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00698   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00699   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00700   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00701   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00702   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00703   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00704   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00705   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00706   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00707 } ITM_Type;
00708 
00709 /* ITM Trace Privilege Register Definitions */
00710 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
00711 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
00712 
00713 /* ITM Trace Control Register Definitions */
00714 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
00715 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00716 
00717 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
00718 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00719 
00720 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
00721 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00722 
00723 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
00724 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00725 
00726 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
00727 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00728 
00729 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
00730 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00731 
00732 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
00733 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00734 
00735 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
00736 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00737 
00738 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
00739 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
00740 
00741 /* ITM Integration Write Register Definitions */
00742 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
00743 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
00744 
00745 /* ITM Integration Read Register Definitions */
00746 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
00747 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
00748 
00749 /* ITM Integration Mode Control Register Definitions */
00750 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
00751 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
00752 
00753 /* ITM Lock Status Register Definitions */
00754 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
00755 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00756 
00757 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
00758 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00759 
00760 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
00761 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
00762 
00763 /*@}*/ /* end of group CMSIS_ITM */
00764 
00765 
00766 /** \ingroup  CMSIS_core_register
00767     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00768     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
00769   @{
00770  */
00771 
00772 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00773  */
00774 typedef struct
00775 {
00776   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
00777   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
00778   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
00779   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
00780   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
00781   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
00782   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
00783   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
00784   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
00785   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
00786   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
00787        uint32_t RESERVED0[1];
00788   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
00789   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
00790   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
00791        uint32_t RESERVED1[1];
00792   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
00793   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
00794   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
00795        uint32_t RESERVED2[1];
00796   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
00797   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
00798   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
00799 } DWT_Type;
00800 
00801 /* DWT Control Register Definitions */
00802 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
00803 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00804 
00805 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
00806 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00807 
00808 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
00809 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00810 
00811 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
00812 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00813 
00814 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
00815 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00816 
00817 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
00818 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00819 
00820 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
00821 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00822 
00823 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
00824 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00825 
00826 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
00827 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00828 
00829 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
00830 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00831 
00832 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
00833 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00834 
00835 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
00836 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00837 
00838 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
00839 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00840 
00841 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
00842 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00843 
00844 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
00845 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00846 
00847 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
00848 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00849 
00850 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
00851 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00852 
00853 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
00854 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
00855 
00856 /* DWT CPI Count Register Definitions */
00857 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
00858 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
00859 
00860 /* DWT Exception Overhead Count Register Definitions */
00861 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
00862 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
00863 
00864 /* DWT Sleep Count Register Definitions */
00865 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
00866 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00867 
00868 /* DWT LSU Count Register Definitions */
00869 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
00870 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
00871 
00872 /* DWT Folded-instruction Count Register Definitions */
00873 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
00874 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
00875 
00876 /* DWT Comparator Mask Register Definitions */
00877 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
00878 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
00879 
00880 /* DWT Comparator Function Register Definitions */
00881 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
00882 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00883 
00884 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
00885 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00886 
00887 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
00888 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00889 
00890 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
00891 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00892 
00893 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
00894 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00895 
00896 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
00897 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00898 
00899 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
00900 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00901 
00902 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
00903 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00904 
00905 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
00906 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
00907 
00908 /*@}*/ /* end of group CMSIS_DWT */
00909 
00910 
00911 /** \ingroup  CMSIS_core_register
00912     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00913     \brief      Type definitions for the Trace Port Interface (TPI)
00914   @{
00915  */
00916 
00917 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
00918  */
00919 typedef struct
00920 {
00921   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
00922   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00923        uint32_t RESERVED0[2];
00924   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00925        uint32_t RESERVED1[55];
00926   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00927        uint32_t RESERVED2[131];
00928   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00929   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00930   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00931        uint32_t RESERVED3[759];
00932   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00933   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00934   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00935        uint32_t RESERVED4[1];
00936   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00937   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00938   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00939        uint32_t RESERVED5[39];
00940   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00941   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00942        uint32_t RESERVED7[8];
00943   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
00944   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
00945 } TPI_Type;
00946 
00947 /* TPI Asynchronous Clock Prescaler Register Definitions */
00948 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
00949 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
00950 
00951 /* TPI Selected Pin Protocol Register Definitions */
00952 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
00953 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
00954 
00955 /* TPI Formatter and Flush Status Register Definitions */
00956 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
00957 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
00958 
00959 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
00960 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
00961 
00962 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
00963 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
00964 
00965 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
00966 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
00967 
00968 /* TPI Formatter and Flush Control Register Definitions */
00969 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
00970 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
00971 
00972 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
00973 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
00974 
00975 /* TPI TRIGGER Register Definitions */
00976 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
00977 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
00978 
00979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
00980 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
00981 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
00982 
00983 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
00984 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
00985 
00986 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
00987 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
00988 
00989 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
00990 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
00991 
00992 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
00993 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
00994 
00995 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
00996 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
00997 
00998 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
00999 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
01000 
01001 /* TPI ITATBCTR2 Register Definitions */
01002 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
01003 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
01004 
01005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
01006 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
01007 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
01008 
01009 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
01010 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
01011 
01012 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
01013 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
01014 
01015 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
01016 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
01017 
01018 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
01019 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
01020 
01021 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
01022 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01023 
01024 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
01025 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
01026 
01027 /* TPI ITATBCTR0 Register Definitions */
01028 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
01029 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
01030 
01031 /* TPI Integration Mode Control Register Definitions */
01032 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
01033 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
01034 
01035 /* TPI DEVID Register Definitions */
01036 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
01037 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01038 
01039 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
01040 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01041 
01042 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
01043 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01044 
01045 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
01046 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01047 
01048 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
01049 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01050 
01051 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
01052 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
01053 
01054 /* TPI DEVTYPE Register Definitions */
01055 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
01056 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
01057 
01058 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
01059 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01060 
01061 /*@}*/ /* end of group CMSIS_TPI */
01062 
01063 
01064 #if (__MPU_PRESENT == 1)
01065 /** \ingroup  CMSIS_core_register
01066     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01067     \brief      Type definitions for the Memory Protection Unit (MPU)
01068   @{
01069  */
01070 
01071 /** \brief  Structure type to access the Memory Protection Unit (MPU).
01072  */
01073 typedef struct
01074 {
01075   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
01076   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
01077   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
01078   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
01079   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
01080   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
01081   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01082   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
01083   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01084   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
01085   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01086 } MPU_Type;
01087 
01088 /* MPU Type Register */
01089 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
01090 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01091 
01092 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
01093 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01094 
01095 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
01096 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
01097 
01098 /* MPU Control Register */
01099 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
01100 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01101 
01102 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
01103 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01104 
01105 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
01106 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
01107 
01108 /* MPU Region Number Register */
01109 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
01110 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
01111 
01112 /* MPU Region Base Address Register */
01113 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
01114 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01115 
01116 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
01117 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01118 
01119 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
01120 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
01121 
01122 /* MPU Region Attribute and Size Register */
01123 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
01124 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01125 
01126 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
01127 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01128 
01129 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
01130 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01131 
01132 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
01133 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01134 
01135 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
01136 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01137 
01138 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
01139 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01140 
01141 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
01142 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01143 
01144 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
01145 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01146 
01147 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
01148 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01149 
01150 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
01151 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
01152 
01153 /*@} end of group CMSIS_MPU */
01154 #endif
01155 
01156 
01157 #if (__FPU_PRESENT == 1)
01158 /** \ingroup  CMSIS_core_register
01159     \defgroup CMSIS_FPU     Floating Point Unit (FPU)
01160     \brief      Type definitions for the Floating Point Unit (FPU)
01161   @{
01162  */
01163 
01164 /** \brief  Structure type to access the Floating Point Unit (FPU).
01165  */
01166 typedef struct
01167 {
01168        uint32_t RESERVED0[1];
01169   __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
01170   __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
01171   __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
01172   __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
01173   __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
01174 } FPU_Type;
01175 
01176 /* Floating-Point Context Control Register */
01177 #define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
01178 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
01179 
01180 #define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
01181 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
01182 
01183 #define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
01184 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
01185 
01186 #define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
01187 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
01188 
01189 #define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
01190 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
01191 
01192 #define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
01193 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
01194 
01195 #define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
01196 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
01197 
01198 #define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
01199 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
01200 
01201 #define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
01202 #define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
01203 
01204 /* Floating-Point Context Address Register */
01205 #define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
01206 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
01207 
01208 /* Floating-Point Default Status Control Register */
01209 #define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
01210 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
01211 
01212 #define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
01213 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
01214 
01215 #define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
01216 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
01217 
01218 #define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
01219 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
01220 
01221 /* Media and FP Feature Register 0 */
01222 #define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
01223 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
01224 
01225 #define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
01226 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
01227 
01228 #define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
01229 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
01230 
01231 #define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
01232 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
01233 
01234 #define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
01235 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
01236 
01237 #define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
01238 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
01239 
01240 #define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
01241 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
01242 
01243 #define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
01244 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
01245 
01246 /* Media and FP Feature Register 1 */
01247 #define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
01248 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
01249 
01250 #define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
01251 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
01252 
01253 #define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
01254 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
01255 
01256 #define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
01257 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
01258 
01259 /*@} end of group CMSIS_FPU */
01260 #endif
01261 
01262 
01263 /** \ingroup  CMSIS_core_register
01264     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01265     \brief      Type definitions for the Core Debug Registers
01266   @{
01267  */
01268 
01269 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
01270  */
01271 typedef struct
01272 {
01273   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
01274   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
01275   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
01276   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01277 } CoreDebug_Type;
01278 
01279 /* Debug Halting Control and Status Register */
01280 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
01281 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01282 
01283 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
01284 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01285 
01286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01288 
01289 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
01290 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01291 
01292 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
01293 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01294 
01295 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
01296 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01297 
01298 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
01299 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01300 
01301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01303 
01304 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
01305 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01306 
01307 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
01308 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01309 
01310 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
01311 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01312 
01313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01315 
01316 /* Debug Core Register Selector Register */
01317 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
01318 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01319 
01320 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
01321 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
01322 
01323 /* Debug Exception and Monitor Control Register */
01324 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
01325 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01326 
01327 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
01328 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01329 
01330 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
01331 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01332 
01333 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
01334 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01335 
01336 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
01337 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01338 
01339 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
01340 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01341 
01342 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
01343 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01344 
01345 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
01346 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01347 
01348 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
01349 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01350 
01351 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
01352 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01353 
01354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01356 
01357 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
01358 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01359 
01360 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
01361 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01362 
01363 /*@} end of group CMSIS_CoreDebug */
01364 
01365 
01366 /** \ingroup    CMSIS_core_register
01367     \defgroup   CMSIS_core_base     Core Definitions
01368     \brief      Definitions for base addresses, unions, and structures.
01369   @{
01370  */
01371 
01372 /* Memory mapping of Cortex-M4 Hardware */
01373 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
01374 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
01375 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
01376 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
01377 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
01378 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
01379 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
01380 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
01381 
01382 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01383 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
01384 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
01385 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
01386 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
01387 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
01388 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
01389 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
01390 
01391 #if (__MPU_PRESENT == 1)
01392   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
01393   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
01394 #endif
01395 
01396 #if (__FPU_PRESENT == 1)
01397   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
01398   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
01399 #endif
01400 
01401 /*@} */
01402 
01403 
01404 
01405 /*******************************************************************************
01406  *                Hardware Abstraction Layer
01407   Core Function Interface contains:
01408   - Core NVIC Functions
01409   - Core SysTick Functions
01410   - Core Debug Functions
01411   - Core Register Access Functions
01412  ******************************************************************************/
01413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01414 */
01415 
01416 
01417 
01418 /* ##########################   NVIC functions  #################################### */
01419 /** \ingroup  CMSIS_Core_FunctionInterface
01420     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01421     \brief      Functions that manage interrupts and exceptions via the NVIC.
01422     @{
01423  */
01424 
01425 /** \brief  Set Priority Grouping
01426 
01427   The function sets the priority grouping field using the required unlock sequence.
01428   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01429   Only values from 0..7 are used.
01430   In case of a conflict between priority grouping and available
01431   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01432 
01433     \param [in]      PriorityGroup  Priority grouping field.
01434  */
01435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01436 {
01437   uint32_t reg_value;
01438   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
01439 
01440   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01441   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
01442   reg_value  =  (reg_value                                 |
01443                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
01444                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
01445   SCB->AIRCR =  reg_value;
01446 }
01447 
01448 
01449 /** \brief  Get Priority Grouping
01450 
01451   The function reads the priority grouping field from the NVIC Interrupt Controller.
01452 
01453     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01454  */
01455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
01456 {
01457   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
01458 }
01459 
01460 
01461 /** \brief  Enable External Interrupt
01462 
01463     The function enables a device-specific interrupt in the NVIC interrupt controller.
01464 
01465     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01466  */
01467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
01468 {
01469 /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
01470   NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
01471 }
01472 
01473 
01474 /** \brief  Disable External Interrupt
01475 
01476     The function disables a device-specific interrupt in the NVIC interrupt controller.
01477 
01478     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01479  */
01480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
01481 {
01482   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
01483 }
01484 
01485 
01486 /** \brief  Get Pending Interrupt
01487 
01488     The function reads the pending register in the NVIC and returns the pending bit
01489     for the specified interrupt.
01490 
01491     \param [in]      IRQn  Interrupt number.
01492 
01493     \return             0  Interrupt status is not pending.
01494     \return             1  Interrupt status is pending.
01495  */
01496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
01497 {
01498   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
01499 }
01500 
01501 
01502 /** \brief  Set Pending Interrupt
01503 
01504     The function sets the pending bit of an external interrupt.
01505 
01506     \param [in]      IRQn  Interrupt number. Value cannot be negative.
01507  */
01508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
01509 {
01510   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
01511 }
01512 
01513 
01514 /** \brief  Clear Pending Interrupt
01515 
01516     The function clears the pending bit of an external interrupt.
01517 
01518     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01519  */
01520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
01521 {
01522   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
01523 }
01524 
01525 
01526 /** \brief  Get Active Interrupt
01527 
01528     The function reads the active register in NVIC and returns the active bit.
01529 
01530     \param [in]      IRQn  Interrupt number.
01531 
01532     \return             0  Interrupt status is not active.
01533     \return             1  Interrupt status is active.
01534  */
01535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
01536 {
01537   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
01538 }
01539 
01540 
01541 /** \brief  Set Interrupt Priority
01542 
01543     The function sets the priority of an interrupt.
01544 
01545     \note The priority cannot be set for every core interrupt.
01546 
01547     \param [in]      IRQn  Interrupt number.
01548     \param [in]  priority  Priority to set.
01549  */
01550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
01551 {
01552   if(IRQn < 0) {
01553     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
01554   else {
01555     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
01556 }
01557 
01558 
01559 /** \brief  Get Interrupt Priority
01560 
01561     The function reads the priority of an interrupt. The interrupt
01562     number can be positive to specify an external (device specific)
01563     interrupt, or negative to specify an internal (core) interrupt.
01564 
01565 
01566     \param [in]   IRQn  Interrupt number.
01567     \return             Interrupt Priority. Value is aligned automatically to the implemented
01568                         priority bits of the microcontroller.
01569  */
01570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
01571 {
01572 
01573   if(IRQn < 0) {
01574     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
01575   else {
01576     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
01577 }
01578 
01579 
01580 /** \brief  Encode Priority
01581 
01582     The function encodes the priority for an interrupt with the given priority group,
01583     preemptive priority value, and subpriority value.
01584     In case of a conflict between priority grouping and available
01585     priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
01586 
01587     \param [in]     PriorityGroup  Used priority group.
01588     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01589     \param [in]       SubPriority  Subpriority value (starting from 0).
01590     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01591  */
01592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01593 {
01594   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01595   uint32_t PreemptPriorityBits;
01596   uint32_t SubPriorityBits;
01597 
01598   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01599   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01600 
01601   return (
01602            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
01603            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
01604          );
01605 }
01606 
01607 
01608 /** \brief  Decode Priority
01609 
01610     The function decodes an interrupt priority value with a given priority group to
01611     preemptive priority value and subpriority value.
01612     In case of a conflict between priority grouping and available
01613     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
01614 
01615     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01616     \param [in]     PriorityGroup  Used priority group.
01617     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01618     \param [out]     pSubPriority  Subpriority value (starting from 0).
01619  */
01620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
01621 {
01622   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01623   uint32_t PreemptPriorityBits;
01624   uint32_t SubPriorityBits;
01625 
01626   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01627   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01628 
01629   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
01630   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
01631 }
01632 
01633 
01634 /** \brief  System Reset
01635 
01636     The function initiates a system reset request to reset the MCU.
01637  */
01638 __STATIC_INLINE void NVIC_SystemReset(void)
01639 {
01640   __DSB();                                                     /* Ensure all outstanding memory accesses included
01641                                                                   buffered write are completed before reset */
01642   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
01643                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01644                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
01645   __DSB();                                                     /* Ensure completion of memory access */
01646   while(1);                                                    /* wait until reset */
01647 }
01648 
01649 /*@} end of CMSIS_Core_NVICFunctions */
01650 
01651 
01652 
01653 /* ##################################    SysTick function  ############################################ */
01654 /** \ingroup  CMSIS_Core_FunctionInterface
01655     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01656     \brief      Functions that configure the System.
01657   @{
01658  */
01659 
01660 #if (__Vendor_SysTickConfig == 0)
01661 
01662 /** \brief  System Tick Configuration
01663 
01664     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
01665     Counter is in free running mode to generate periodic interrupts.
01666 
01667     \param [in]  ticks  Number of ticks between two interrupts.
01668 
01669     \return          0  Function succeeded.
01670     \return          1  Function failed.
01671 
01672     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01673     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01674     must contain a vendor-specific implementation of this function.
01675 
01676  */
01677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01678 {
01679   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
01680 
01681   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
01682   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
01683   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
01684   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01685                    SysTick_CTRL_TICKINT_Msk   |
01686                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
01687   return (0);                                                  /* Function successful */
01688 }
01689 
01690 #endif
01691 
01692 /*@} end of CMSIS_Core_SysTickFunctions */
01693 
01694 
01695 
01696 /* ##################################### Debug In/Output function ########################################### */
01697 /** \ingroup  CMSIS_Core_FunctionInterface
01698     \defgroup CMSIS_core_DebugFunctions ITM Functions
01699     \brief   Functions that access the ITM debug interface.
01700   @{
01701  */
01702 
01703 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
01704 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01705 
01706 
01707 /** \brief  ITM Send Character
01708 
01709     The function transmits a character via the ITM channel 0, and
01710     \li Just returns when no debugger is connected that has booked the output.
01711     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01712 
01713     \param [in]     ch  Character to transmit.
01714 
01715     \returns            Character to transmit.
01716  */
01717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01718 {
01719   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
01720       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
01721   {
01722     while (ITM->PORT[0].u32 == 0);
01723     ITM->PORT[0].u8 = (uint8_t) ch;
01724   }
01725   return (ch);
01726 }
01727 
01728 
01729 /** \brief  ITM Receive Character
01730 
01731     The function inputs a character via the external variable \ref ITM_RxBuffer.
01732 
01733     \return             Received character.
01734     \return         -1  No character pending.
01735  */
01736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
01737   int32_t ch = -1;                           /* no character available */
01738 
01739   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
01740     ch = ITM_RxBuffer;
01741     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01742   }
01743 
01744   return (ch);
01745 }
01746 
01747 
01748 /** \brief  ITM Check Character
01749 
01750     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01751 
01752     \return          0  No character available.
01753     \return          1  Character available.
01754  */
01755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
01756 
01757   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
01758     return (0);                                 /* no character available */
01759   } else {
01760     return (1);                                 /*    character available */
01761   }
01762 }
01763 
01764 /*@} end of CMSIS_core_DebugFunctions */
01765 
01766 #endif /* __CORE_CM4_H_DEPENDANT */
01767 
01768 #endif /* __CMSIS_GENERIC */
01769 
01770 #ifdef __cplusplus
01771 }
01772 #endif