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I2S_Example/lpc17xx_uart.h@0:63ed631d8c3a, 2011-01-21 (annotated)

Committer:: lynxeyed_atsu
Date:: Fri Jan 21 08:39:48 2011 +0000
Revision:: 0:63ed631d8c3a

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:63ed631d8c3a	1	/*********************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	2	* @file lpc17xx_uart.h
lynxeyed_atsu	0:63ed631d8c3a	3	* @brief Contains all macro definitions and function prototypes
lynxeyed_atsu	0:63ed631d8c3a	4	* support for UART firmware library on LPC17xx
lynxeyed_atsu	0:63ed631d8c3a	5	* @version 3.0
lynxeyed_atsu	0:63ed631d8c3a	6	* @date 18. June. 2010
lynxeyed_atsu	0:63ed631d8c3a	7	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:63ed631d8c3a	8	**************************************************************************
lynxeyed_atsu	0:63ed631d8c3a	9	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:63ed631d8c3a	10	* which provides customers with programming information regarding the
lynxeyed_atsu	0:63ed631d8c3a	11	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:63ed631d8c3a	12	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:63ed631d8c3a	13	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:63ed631d8c3a	14	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:63ed631d8c3a	15	* reserves the right to make changes in the software without
lynxeyed_atsu	0:63ed631d8c3a	16	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:63ed631d8c3a	17	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:63ed631d8c3a	18	* use without further testing or modification.
lynxeyed_atsu	0:63ed631d8c3a	19	**************************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	20
lynxeyed_atsu	0:63ed631d8c3a	21	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	22	/** @defgroup UART UART
lynxeyed_atsu	0:63ed631d8c3a	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu	0:63ed631d8c3a	24	* @{
lynxeyed_atsu	0:63ed631d8c3a	25	*/
lynxeyed_atsu	0:63ed631d8c3a	26
lynxeyed_atsu	0:63ed631d8c3a	27	#ifndef __LPC17XX_UART_H
lynxeyed_atsu	0:63ed631d8c3a	28	#define __LPC17XX_UART_H
lynxeyed_atsu	0:63ed631d8c3a	29
lynxeyed_atsu	0:63ed631d8c3a	30	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	31	#include "LPC17xx.h"
lynxeyed_atsu	0:63ed631d8c3a	32	#include "lpc_types.h"
lynxeyed_atsu	0:63ed631d8c3a	33
lynxeyed_atsu	0:63ed631d8c3a	34
lynxeyed_atsu	0:63ed631d8c3a	35	#ifdef __cplusplus
lynxeyed_atsu	0:63ed631d8c3a	36	extern "C"
lynxeyed_atsu	0:63ed631d8c3a	37	{
lynxeyed_atsu	0:63ed631d8c3a	38	#endif
lynxeyed_atsu	0:63ed631d8c3a	39
lynxeyed_atsu	0:63ed631d8c3a	40	/* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	41	/** @defgroup UART_Public_Macros UART Public Macros
lynxeyed_atsu	0:63ed631d8c3a	42	* @{
lynxeyed_atsu	0:63ed631d8c3a	43	*/
lynxeyed_atsu	0:63ed631d8c3a	44
lynxeyed_atsu	0:63ed631d8c3a	45	/** UART time-out definitions in case of using Read() and Write function
lynxeyed_atsu	0:63ed631d8c3a	46	* with Blocking Flag mode
lynxeyed_atsu	0:63ed631d8c3a	47	*/
lynxeyed_atsu	0:63ed631d8c3a	48	#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
lynxeyed_atsu	0:63ed631d8c3a	49
lynxeyed_atsu	0:63ed631d8c3a	50	/**
lynxeyed_atsu	0:63ed631d8c3a	51	* @}
lynxeyed_atsu	0:63ed631d8c3a	52	*/
lynxeyed_atsu	0:63ed631d8c3a	53
lynxeyed_atsu	0:63ed631d8c3a	54	/* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	55	/** @defgroup UART_Private_Macros UART Private Macros
lynxeyed_atsu	0:63ed631d8c3a	56	* @{
lynxeyed_atsu	0:63ed631d8c3a	57	*/
lynxeyed_atsu	0:63ed631d8c3a	58
lynxeyed_atsu	0:63ed631d8c3a	59	/* Accepted Error baud rate value (in percent unit) */
lynxeyed_atsu	0:63ed631d8c3a	60	#define UART_ACCEPTED_BAUDRATE_ERROR (3) /!< Acceptable UART baudrate error /
lynxeyed_atsu	0:63ed631d8c3a	61
lynxeyed_atsu	0:63ed631d8c3a	62
lynxeyed_atsu	0:63ed631d8c3a	63	/* --------------------- BIT DEFINITIONS -------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	64	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	65	* Macro defines for Macro defines for UARTn Receiver Buffer Register
lynxeyed_atsu	0:63ed631d8c3a	66	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	67	#define UART_RBR_MASKBIT ((uint8_t)0xFF) /!< UART Received Buffer mask bit (8 bits) /
lynxeyed_atsu	0:63ed631d8c3a	68
lynxeyed_atsu	0:63ed631d8c3a	69	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	70	* Macro defines for Macro defines for UARTn Transmit Holding Register
lynxeyed_atsu	0:63ed631d8c3a	71	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	72	#define UART_THR_MASKBIT ((uint8_t)0xFF) /!< UART Transmit Holding mask bit (8 bits) /
lynxeyed_atsu	0:63ed631d8c3a	73
lynxeyed_atsu	0:63ed631d8c3a	74	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	75	* Macro defines for Macro defines for UARTn Divisor Latch LSB register
lynxeyed_atsu	0:63ed631d8c3a	76	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	77	#define UART_LOAD_DLL(div) ((div) & 0xFF) /*< Macro for loading least significant halfs of divisors /
lynxeyed_atsu	0:63ed631d8c3a	78	#define UART_DLL_MASKBIT ((uint8_t)0xFF) /!< Divisor latch LSB bit mask /
lynxeyed_atsu	0:63ed631d8c3a	79
lynxeyed_atsu	0:63ed631d8c3a	80	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	81	* Macro defines for Macro defines for UARTn Divisor Latch MSB register
lynxeyed_atsu	0:63ed631d8c3a	82	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	83	#define UART_DLM_MASKBIT ((uint8_t)0xFF) /!< Divisor latch MSB bit mask /
lynxeyed_atsu	0:63ed631d8c3a	84	#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*< Macro for loading most significant halfs of divisors /
lynxeyed_atsu	0:63ed631d8c3a	85
lynxeyed_atsu	0:63ed631d8c3a	86	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	87	* Macro defines for Macro defines for UART interrupt enable register
lynxeyed_atsu	0:63ed631d8c3a	88	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	89	#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /!< RBR Interrupt enable/
lynxeyed_atsu	0:63ed631d8c3a	90	#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /!< THR Interrupt enable/
lynxeyed_atsu	0:63ed631d8c3a	91	#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /!< RX line status interrupt enable/
lynxeyed_atsu	0:63ed631d8c3a	92	#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /!< Modem status interrupt enable /
lynxeyed_atsu	0:63ed631d8c3a	93	#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /!< CTS1 signal transition interrupt enable /
lynxeyed_atsu	0:63ed631d8c3a	94	#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /!< Enables the end of auto-baud interrupt /
lynxeyed_atsu	0:63ed631d8c3a	95	#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /!< Enables the auto-baud time-out interrupt /
lynxeyed_atsu	0:63ed631d8c3a	96	#define UART_IER_BITMASK ((uint32_t)(0x307)) /!< UART interrupt enable register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	97	#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /!< UART1 interrupt enable register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	98
lynxeyed_atsu	0:63ed631d8c3a	99	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	100	* Macro defines for Macro defines for UART interrupt identification register
lynxeyed_atsu	0:63ed631d8c3a	101	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	102	#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /!<Interrupt Status - Active low /
lynxeyed_atsu	0:63ed631d8c3a	103	#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /!<Interrupt identification: Receive line status/
lynxeyed_atsu	0:63ed631d8c3a	104	#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /!<Interrupt identification: Receive data available/
lynxeyed_atsu	0:63ed631d8c3a	105	#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /!<Interrupt identification: Character time-out indicator/
lynxeyed_atsu	0:63ed631d8c3a	106	#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /!<Interrupt identification: THRE interrupt/
lynxeyed_atsu	0:63ed631d8c3a	107	#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /!<Interrupt identification: Modem interrupt/
lynxeyed_atsu	0:63ed631d8c3a	108	#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /!<Interrupt identification: Interrupt ID mask /
lynxeyed_atsu	0:63ed631d8c3a	109	#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /!<These bits are equivalent to UnFCR[0] /
lynxeyed_atsu	0:63ed631d8c3a	110	#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /!< End of auto-baud interrupt /
lynxeyed_atsu	0:63ed631d8c3a	111	#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /!< Auto-baud time-out interrupt /
lynxeyed_atsu	0:63ed631d8c3a	112	#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /!< UART interrupt identification register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	113
lynxeyed_atsu	0:63ed631d8c3a	114	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	115	* Macro defines for Macro defines for UART FIFO control register
lynxeyed_atsu	0:63ed631d8c3a	116	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	117	#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /!< UART FIFO enable /
lynxeyed_atsu	0:63ed631d8c3a	118	#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /!< UART FIFO RX reset /
lynxeyed_atsu	0:63ed631d8c3a	119	#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /!< UART FIFO TX reset /
lynxeyed_atsu	0:63ed631d8c3a	120	#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /!< UART DMA mode selection /
lynxeyed_atsu	0:63ed631d8c3a	121	#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /!< UART FIFO trigger level 0: 1 character /
lynxeyed_atsu	0:63ed631d8c3a	122	#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /!< UART FIFO trigger level 1: 4 character /
lynxeyed_atsu	0:63ed631d8c3a	123	#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /!< UART FIFO trigger level 2: 8 character /
lynxeyed_atsu	0:63ed631d8c3a	124	#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /!< UART FIFO trigger level 3: 14 character /
lynxeyed_atsu	0:63ed631d8c3a	125	#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /!< UART FIFO control bit mask /
lynxeyed_atsu	0:63ed631d8c3a	126	#define UART_TX_FIFO_SIZE (16)
lynxeyed_atsu	0:63ed631d8c3a	127
lynxeyed_atsu	0:63ed631d8c3a	128	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	129	* Macro defines for Macro defines for UART line control register
lynxeyed_atsu	0:63ed631d8c3a	130	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	131	#define UART_LCR_WLEN5 ((uint8_t)(0)) /!< UART 5 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	132	#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /!< UART 6 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	133	#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /!< UART 7 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	134	#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /!< UART 8 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	135	#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /!< UART Two Stop Bits Select /
lynxeyed_atsu	0:63ed631d8c3a	136	#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /!< UART Parity Enable /
lynxeyed_atsu	0:63ed631d8c3a	137	#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /!< UART Odd Parity Select /
lynxeyed_atsu	0:63ed631d8c3a	138	#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /!< UART Even Parity Select /
lynxeyed_atsu	0:63ed631d8c3a	139	#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /!< UART force 1 stick parity /
lynxeyed_atsu	0:63ed631d8c3a	140	#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /!< UART force 0 stick parity /
lynxeyed_atsu	0:63ed631d8c3a	141	#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /!< UART Transmission Break enable /
lynxeyed_atsu	0:63ed631d8c3a	142	#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /!< UART Divisor Latches Access bit enable /
lynxeyed_atsu	0:63ed631d8c3a	143	#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /!< UART line control bit mask /
lynxeyed_atsu	0:63ed631d8c3a	144
lynxeyed_atsu	0:63ed631d8c3a	145	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	146	* Macro defines for Macro defines for UART1 Modem Control Register
lynxeyed_atsu	0:63ed631d8c3a	147	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	148	#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /!< Source for modem output pin DTR /
lynxeyed_atsu	0:63ed631d8c3a	149	#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /!< Source for modem output pin RTS /
lynxeyed_atsu	0:63ed631d8c3a	150	#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /!< Loop back mode select /
lynxeyed_atsu	0:63ed631d8c3a	151	#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /!< Enable Auto RTS flow-control /
lynxeyed_atsu	0:63ed631d8c3a	152	#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /!< Enable Auto CTS flow-control /
lynxeyed_atsu	0:63ed631d8c3a	153	#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /!< UART1 bit mask value /
lynxeyed_atsu	0:63ed631d8c3a	154
lynxeyed_atsu	0:63ed631d8c3a	155	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	156	* Macro defines for Macro defines for UART line status register
lynxeyed_atsu	0:63ed631d8c3a	157	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	158	#define UART_LSR_RDR ((uint8_t)(1<<0)) /!<Line status register: Receive data ready/
lynxeyed_atsu	0:63ed631d8c3a	159	#define UART_LSR_OE ((uint8_t)(1<<1)) /!<Line status register: Overrun error/
lynxeyed_atsu	0:63ed631d8c3a	160	#define UART_LSR_PE ((uint8_t)(1<<2)) /!<Line status register: Parity error/
lynxeyed_atsu	0:63ed631d8c3a	161	#define UART_LSR_FE ((uint8_t)(1<<3)) /!<Line status register: Framing error/
lynxeyed_atsu	0:63ed631d8c3a	162	#define UART_LSR_BI ((uint8_t)(1<<4)) /!<Line status register: Break interrupt/
lynxeyed_atsu	0:63ed631d8c3a	163	#define UART_LSR_THRE ((uint8_t)(1<<5)) /!<Line status register: Transmit holding register empty/
lynxeyed_atsu	0:63ed631d8c3a	164	#define UART_LSR_TEMT ((uint8_t)(1<<6)) /!<Line status register: Transmitter empty/
lynxeyed_atsu	0:63ed631d8c3a	165	#define UART_LSR_RXFE ((uint8_t)(1<<7)) /!<Error in RX FIFO/
lynxeyed_atsu	0:63ed631d8c3a	166	#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /!<UART Line status bit mask /
lynxeyed_atsu	0:63ed631d8c3a	167
lynxeyed_atsu	0:63ed631d8c3a	168	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	169	* Macro defines for Macro defines for UART Modem (UART1 only) status register
lynxeyed_atsu	0:63ed631d8c3a	170	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	171	#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /!< Set upon state change of input CTS /
lynxeyed_atsu	0:63ed631d8c3a	172	#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /!< Set upon state change of input DSR /
lynxeyed_atsu	0:63ed631d8c3a	173	#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /!< Set upon low to high transition of input RI /
lynxeyed_atsu	0:63ed631d8c3a	174	#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /!< Set upon state change of input DCD /
lynxeyed_atsu	0:63ed631d8c3a	175	#define UART1_MSR_CTS ((uint8_t)(1<<4)) /!< Clear To Send State /
lynxeyed_atsu	0:63ed631d8c3a	176	#define UART1_MSR_DSR ((uint8_t)(1<<5)) /!< Data Set Ready State /
lynxeyed_atsu	0:63ed631d8c3a	177	#define UART1_MSR_RI ((uint8_t)(1<<6)) /!< Ring Indicator State /
lynxeyed_atsu	0:63ed631d8c3a	178	#define UART1_MSR_DCD ((uint8_t)(1<<7)) /!< Data Carrier Detect State /
lynxeyed_atsu	0:63ed631d8c3a	179	#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /!< MSR register bit-mask value /
lynxeyed_atsu	0:63ed631d8c3a	180
lynxeyed_atsu	0:63ed631d8c3a	181	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	182	* Macro defines for Macro defines for UART Scratch Pad Register
lynxeyed_atsu	0:63ed631d8c3a	183	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	184	#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /!< UART Scratch Pad bit mask /
lynxeyed_atsu	0:63ed631d8c3a	185
lynxeyed_atsu	0:63ed631d8c3a	186	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	187	* Macro defines for Macro defines for UART Auto baudrate control register
lynxeyed_atsu	0:63ed631d8c3a	188	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	189	#define UART_ACR_START ((uint32_t)(1<<0)) /*< UART Auto-baud start /
lynxeyed_atsu	0:63ed631d8c3a	190	#define UART_ACR_MODE ((uint32_t)(1<<1)) /*< UART Auto baudrate Mode 1 /
lynxeyed_atsu	0:63ed631d8c3a	191	#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /*< UART Auto baudrate restart /
lynxeyed_atsu	0:63ed631d8c3a	192	#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /*< UART End of auto-baud interrupt clear /
lynxeyed_atsu	0:63ed631d8c3a	193	#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /*< UART Auto-baud time-out interrupt clear /
lynxeyed_atsu	0:63ed631d8c3a	194	#define UART_ACR_BITMASK ((uint32_t)(0x307)) /*< UART Auto Baudrate register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	195
lynxeyed_atsu	0:63ed631d8c3a	196	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	197	* Macro defines for Macro defines for UART IrDA control register
lynxeyed_atsu	0:63ed631d8c3a	198	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	199	#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /*< IrDA mode enable /
lynxeyed_atsu	0:63ed631d8c3a	200	#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /*< IrDA serial input inverted /
lynxeyed_atsu	0:63ed631d8c3a	201	#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /*< IrDA fixed pulse width mode /
lynxeyed_atsu	0:63ed631d8c3a	202	#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /*< PulseDiv - Configures the pulse when FixPulseEn = 1 /
lynxeyed_atsu	0:63ed631d8c3a	203	#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /!< UART IRDA bit mask /
lynxeyed_atsu	0:63ed631d8c3a	204
lynxeyed_atsu	0:63ed631d8c3a	205	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	206	* Macro defines for Macro defines for UART Fractional divider register
lynxeyed_atsu	0:63ed631d8c3a	207	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	208	#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /*< Baud-rate generation pre-scaler divisor /
lynxeyed_atsu	0:63ed631d8c3a	209	#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /*< Baud-rate pre-scaler multiplier value /
lynxeyed_atsu	0:63ed631d8c3a	210	#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /*< UART Fractional Divider register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	211
lynxeyed_atsu	0:63ed631d8c3a	212	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	213	* Macro defines for Macro defines for UART Tx Enable register
lynxeyed_atsu	0:63ed631d8c3a	214	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	215	#define UART_TER_TXEN ((uint8_t)(1<<7)) /!< Transmit enable bit /
lynxeyed_atsu	0:63ed631d8c3a	216	#define UART_TER_BITMASK ((uint8_t)(0x80)) /*< UART Transmit Enable Register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	217
lynxeyed_atsu	0:63ed631d8c3a	218	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	219	* Macro defines for Macro defines for UART1 RS485 Control register
lynxeyed_atsu	0:63ed631d8c3a	220	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	221	#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
lynxeyed_atsu	0:63ed631d8c3a	222	is disabled */
lynxeyed_atsu	0:63ed631d8c3a	223	#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /!< The receiver is disabled /
lynxeyed_atsu	0:63ed631d8c3a	224	#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /!< Auto Address Detect (AAD) is enabled /
lynxeyed_atsu	0:63ed631d8c3a	225	#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
lynxeyed_atsu	0:63ed631d8c3a	226	(bit DCTRL = 1), pin DTR is used for direction control */
lynxeyed_atsu	0:63ed631d8c3a	227	#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /!< Enable Auto Direction Control /
lynxeyed_atsu	0:63ed631d8c3a	228	#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
lynxeyed_atsu	0:63ed631d8c3a	229	control signal on the RTS (or DTR) pin. The direction control pin
lynxeyed_atsu	0:63ed631d8c3a	230	will be driven to logic "1" when the transmitter has data to be sent */
lynxeyed_atsu	0:63ed631d8c3a	231	#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /*< RS485 control bit-mask value /
lynxeyed_atsu	0:63ed631d8c3a	232
lynxeyed_atsu	0:63ed631d8c3a	233	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	234	* Macro defines for Macro defines for UART1 RS-485 Address Match register
lynxeyed_atsu	0:63ed631d8c3a	235	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	236	#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /*< Bit mask value /
lynxeyed_atsu	0:63ed631d8c3a	237
lynxeyed_atsu	0:63ed631d8c3a	238	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	239	* Macro defines for Macro defines for UART1 RS-485 Delay value register
lynxeyed_atsu	0:63ed631d8c3a	240	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	241	/* Macro defines for UART1 RS-485 Delay value register */
lynxeyed_atsu	0:63ed631d8c3a	242	#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
lynxeyed_atsu	0:63ed631d8c3a	243
lynxeyed_atsu	0:63ed631d8c3a	244	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	245	* Macro defines for Macro defines for UART FIFO Level register
lynxeyed_atsu	0:63ed631d8c3a	246	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	247	#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /*< Reflects the current level of the UART receiver FIFO /
lynxeyed_atsu	0:63ed631d8c3a	248	#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /*< Reflects the current level of the UART transmitter FIFO /
lynxeyed_atsu	0:63ed631d8c3a	249	#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /*< UART FIFO Level Register bit mask /
lynxeyed_atsu	0:63ed631d8c3a	250
lynxeyed_atsu	0:63ed631d8c3a	251
lynxeyed_atsu	0:63ed631d8c3a	252	/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	253
lynxeyed_atsu	0:63ed631d8c3a	254	/** Macro to check the input UART_DATABIT parameters */
lynxeyed_atsu	0:63ed631d8c3a	255	#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) \|\| (databit==UART_DATABIT_6)\
lynxeyed_atsu	0:63ed631d8c3a	256	\|\| (databit==UART_DATABIT_7) \|\| (databit==UART_DATABIT_8))
lynxeyed_atsu	0:63ed631d8c3a	257
lynxeyed_atsu	0:63ed631d8c3a	258	/** Macro to check the input UART_STOPBIT parameters */
lynxeyed_atsu	0:63ed631d8c3a	259	#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) \|\| (stopbit==UART_STOPBIT_2))
lynxeyed_atsu	0:63ed631d8c3a	260
lynxeyed_atsu	0:63ed631d8c3a	261	/** Macro to check the input UART_PARITY parameters */
lynxeyed_atsu	0:63ed631d8c3a	262	#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) \|\| (parity==UART_PARITY_ODD) \
lynxeyed_atsu	0:63ed631d8c3a	263	\|\| (parity==UART_PARITY_EVEN) \|\| (parity==UART_PARITY_SP_1) \
lynxeyed_atsu	0:63ed631d8c3a	264	\|\| (parity==UART_PARITY_SP_0))
lynxeyed_atsu	0:63ed631d8c3a	265
lynxeyed_atsu	0:63ed631d8c3a	266	/** Macro to check the input UART_FIFO parameters */
lynxeyed_atsu	0:63ed631d8c3a	267	#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
lynxeyed_atsu	0:63ed631d8c3a	268	\|\| (fifo==UART_FIFO_TRGLEV1) \|\| (fifo==UART_FIFO_TRGLEV2) \
lynxeyed_atsu	0:63ed631d8c3a	269	\|\| (fifo==UART_FIFO_TRGLEV3))
lynxeyed_atsu	0:63ed631d8c3a	270
lynxeyed_atsu	0:63ed631d8c3a	271	/** Macro to check the input UART_INTCFG parameters */
lynxeyed_atsu	0:63ed631d8c3a	272	#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) \|\| (IntCfg==UART_INTCFG_THRE) \
lynxeyed_atsu	0:63ed631d8c3a	273	\|\| (IntCfg==UART_INTCFG_RLS) \|\| (IntCfg==UART_INTCFG_ABEO) \
lynxeyed_atsu	0:63ed631d8c3a	274	\|\| (IntCfg==UART_INTCFG_ABTO))
lynxeyed_atsu	0:63ed631d8c3a	275
lynxeyed_atsu	0:63ed631d8c3a	276	/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
lynxeyed_atsu	0:63ed631d8c3a	277	#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) \|\| (IntCfg==UART1_INTCFG_CTS))
lynxeyed_atsu	0:63ed631d8c3a	278
lynxeyed_atsu	0:63ed631d8c3a	279	/** Macro to check the input UART_AUTOBAUD_MODE parameters */
lynxeyed_atsu	0:63ed631d8c3a	280	#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) \|\| (ABmode==UART_AUTOBAUD_MODE1))
lynxeyed_atsu	0:63ed631d8c3a	281
lynxeyed_atsu	0:63ed631d8c3a	282	/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
lynxeyed_atsu	0:63ed631d8c3a	283	#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) \|\| \
lynxeyed_atsu	0:63ed631d8c3a	284	(ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
lynxeyed_atsu	0:63ed631d8c3a	285
lynxeyed_atsu	0:63ed631d8c3a	286	/** Macro to check the input UART_IrDA_PULSEDIV parameters */
lynxeyed_atsu	0:63ed631d8c3a	287	#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) \|\| (PulseDiv==UART_IrDA_PULSEDIV4) \
lynxeyed_atsu	0:63ed631d8c3a	288	\|\| (PulseDiv==UART_IrDA_PULSEDIV8) \|\| (PulseDiv==UART_IrDA_PULSEDIV16) \
lynxeyed_atsu	0:63ed631d8c3a	289	\|\| (PulseDiv==UART_IrDA_PULSEDIV32) \|\| (PulseDiv==UART_IrDA_PULSEDIV64) \
lynxeyed_atsu	0:63ed631d8c3a	290	\|\| (PulseDiv==UART_IrDA_PULSEDIV128) \|\| (PulseDiv==UART_IrDA_PULSEDIV256))
lynxeyed_atsu	0:63ed631d8c3a	291
lynxeyed_atsu	0:63ed631d8c3a	292	/* Macro to check the input UART1_SignalState parameters */
lynxeyed_atsu	0:63ed631d8c3a	293	#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) \|\| (x==ACTIVE))
lynxeyed_atsu	0:63ed631d8c3a	294
lynxeyed_atsu	0:63ed631d8c3a	295	/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
lynxeyed_atsu	0:63ed631d8c3a	296	#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) \|\| (x==UART1_MODEM_PIN_RTS))
lynxeyed_atsu	0:63ed631d8c3a	297
lynxeyed_atsu	0:63ed631d8c3a	298	/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
lynxeyed_atsu	0:63ed631d8c3a	299	#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) \|\| (x==UART1_MODEM_MODE_AUTO_RTS) \
lynxeyed_atsu	0:63ed631d8c3a	300	\|\| (x==UART1_MODEM_MODE_AUTO_CTS))
lynxeyed_atsu	0:63ed631d8c3a	301
lynxeyed_atsu	0:63ed631d8c3a	302	/** Macro to check the direction control pin type */
lynxeyed_atsu	0:63ed631d8c3a	303	#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) \|\| (x==UART1_RS485_DIRCTRL_DTR))
lynxeyed_atsu	0:63ed631d8c3a	304
lynxeyed_atsu	0:63ed631d8c3a	305	/* Macro to determine if it is valid UART port number */
lynxeyed_atsu	0:63ed631d8c3a	306	#define PARAM_UARTx(x) ((((uint32_t )x)==((uint32_t )LPC_UART0)) \
lynxeyed_atsu	0:63ed631d8c3a	307	\|\| (((uint32_t )x)==((uint32_t )LPC_UART1)) \
lynxeyed_atsu	0:63ed631d8c3a	308	\|\| (((uint32_t )x)==((uint32_t )LPC_UART2)) \
lynxeyed_atsu	0:63ed631d8c3a	309	\|\| (((uint32_t )x)==((uint32_t )LPC_UART3)))
lynxeyed_atsu	0:63ed631d8c3a	310	#define PARAM_UART_IrDA(x) (((uint32_t )x)==((uint32_t )LPC_UART3))
lynxeyed_atsu	0:63ed631d8c3a	311	#define PARAM_UART1_MODEM(x) (((uint32_t )x)==((uint32_t )LPC_UART1))
lynxeyed_atsu	0:63ed631d8c3a	312
lynxeyed_atsu	0:63ed631d8c3a	313	/** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */
lynxeyed_atsu	0:63ed631d8c3a	314	#define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
lynxeyed_atsu	0:63ed631d8c3a	315
lynxeyed_atsu	0:63ed631d8c3a	316	/** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */
lynxeyed_atsu	0:63ed631d8c3a	317	#define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
lynxeyed_atsu	0:63ed631d8c3a	318
lynxeyed_atsu	0:63ed631d8c3a	319	/**
lynxeyed_atsu	0:63ed631d8c3a	320	* @}
lynxeyed_atsu	0:63ed631d8c3a	321	*/
lynxeyed_atsu	0:63ed631d8c3a	322
lynxeyed_atsu	0:63ed631d8c3a	323
lynxeyed_atsu	0:63ed631d8c3a	324	/* Public Types --------------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	325	/** @defgroup UART_Public_Types UART Public Types
lynxeyed_atsu	0:63ed631d8c3a	326	* @{
lynxeyed_atsu	0:63ed631d8c3a	327	*/
lynxeyed_atsu	0:63ed631d8c3a	328
lynxeyed_atsu	0:63ed631d8c3a	329	/**
lynxeyed_atsu	0:63ed631d8c3a	330	* @brief UART Databit type definitions
lynxeyed_atsu	0:63ed631d8c3a	331	*/
lynxeyed_atsu	0:63ed631d8c3a	332	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	333	UART_DATABIT_5 = 0, /!< UART 5 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	334	UART_DATABIT_6, /!< UART 6 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	335	UART_DATABIT_7, /!< UART 7 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	336	UART_DATABIT_8 /!< UART 8 bit data mode /
lynxeyed_atsu	0:63ed631d8c3a	337	} UART_DATABIT_Type;
lynxeyed_atsu	0:63ed631d8c3a	338
lynxeyed_atsu	0:63ed631d8c3a	339	/**
lynxeyed_atsu	0:63ed631d8c3a	340	* @brief UART Stop bit type definitions
lynxeyed_atsu	0:63ed631d8c3a	341	*/
lynxeyed_atsu	0:63ed631d8c3a	342	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	343	UART_STOPBIT_1 = (0), /!< UART 1 Stop Bits Select /
lynxeyed_atsu	0:63ed631d8c3a	344	UART_STOPBIT_2, /!< UART Two Stop Bits Select /
lynxeyed_atsu	0:63ed631d8c3a	345	} UART_STOPBIT_Type;
lynxeyed_atsu	0:63ed631d8c3a	346
lynxeyed_atsu	0:63ed631d8c3a	347	/**
lynxeyed_atsu	0:63ed631d8c3a	348	* @brief UART Parity type definitions
lynxeyed_atsu	0:63ed631d8c3a	349	*/
lynxeyed_atsu	0:63ed631d8c3a	350	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	351	UART_PARITY_NONE = 0, /!< No parity /
lynxeyed_atsu	0:63ed631d8c3a	352	UART_PARITY_ODD, /!< Odd parity /
lynxeyed_atsu	0:63ed631d8c3a	353	UART_PARITY_EVEN, /!< Even parity /
lynxeyed_atsu	0:63ed631d8c3a	354	UART_PARITY_SP_1, /!< Forced "1" stick parity /
lynxeyed_atsu	0:63ed631d8c3a	355	UART_PARITY_SP_0 /!< Forced "0" stick parity /
lynxeyed_atsu	0:63ed631d8c3a	356	} UART_PARITY_Type;
lynxeyed_atsu	0:63ed631d8c3a	357
lynxeyed_atsu	0:63ed631d8c3a	358	/**
lynxeyed_atsu	0:63ed631d8c3a	359	* @brief FIFO Level type definitions
lynxeyed_atsu	0:63ed631d8c3a	360	*/
lynxeyed_atsu	0:63ed631d8c3a	361	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	362	UART_FIFO_TRGLEV0 = 0, /!< UART FIFO trigger level 0: 1 character /
lynxeyed_atsu	0:63ed631d8c3a	363	UART_FIFO_TRGLEV1, /!< UART FIFO trigger level 1: 4 character /
lynxeyed_atsu	0:63ed631d8c3a	364	UART_FIFO_TRGLEV2, /!< UART FIFO trigger level 2: 8 character /
lynxeyed_atsu	0:63ed631d8c3a	365	UART_FIFO_TRGLEV3 /!< UART FIFO trigger level 3: 14 character /
lynxeyed_atsu	0:63ed631d8c3a	366	} UART_FITO_LEVEL_Type;
lynxeyed_atsu	0:63ed631d8c3a	367
lynxeyed_atsu	0:63ed631d8c3a	368	/******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	369	* @brief UART Interrupt Type definitions
lynxeyed_atsu	0:63ed631d8c3a	370	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	371	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	372	UART_INTCFG_RBR = 0, /!< RBR Interrupt enable/
lynxeyed_atsu	0:63ed631d8c3a	373	UART_INTCFG_THRE, /!< THR Interrupt enable/
lynxeyed_atsu	0:63ed631d8c3a	374	UART_INTCFG_RLS, /!< RX line status interrupt enable/
lynxeyed_atsu	0:63ed631d8c3a	375	UART1_INTCFG_MS, /!< Modem status interrupt enable (UART1 only) /
lynxeyed_atsu	0:63ed631d8c3a	376	UART1_INTCFG_CTS, /!< CTS1 signal transition interrupt enable (UART1 only) /
lynxeyed_atsu	0:63ed631d8c3a	377	UART_INTCFG_ABEO, /!< Enables the end of auto-baud interrupt /
lynxeyed_atsu	0:63ed631d8c3a	378	UART_INTCFG_ABTO /!< Enables the auto-baud time-out interrupt /
lynxeyed_atsu	0:63ed631d8c3a	379	} UART_INT_Type;
lynxeyed_atsu	0:63ed631d8c3a	380
lynxeyed_atsu	0:63ed631d8c3a	381	/**
lynxeyed_atsu	0:63ed631d8c3a	382	* @brief UART Line Status Type definition
lynxeyed_atsu	0:63ed631d8c3a	383	*/
lynxeyed_atsu	0:63ed631d8c3a	384	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	385	UART_LINESTAT_RDR = UART_LSR_RDR, /!<Line status register: Receive data ready/
lynxeyed_atsu	0:63ed631d8c3a	386	UART_LINESTAT_OE = UART_LSR_OE, /!<Line status register: Overrun error/
lynxeyed_atsu	0:63ed631d8c3a	387	UART_LINESTAT_PE = UART_LSR_PE, /!<Line status register: Parity error/
lynxeyed_atsu	0:63ed631d8c3a	388	UART_LINESTAT_FE = UART_LSR_FE, /!<Line status register: Framing error/
lynxeyed_atsu	0:63ed631d8c3a	389	UART_LINESTAT_BI = UART_LSR_BI, /!<Line status register: Break interrupt/
lynxeyed_atsu	0:63ed631d8c3a	390	UART_LINESTAT_THRE = UART_LSR_THRE, /!<Line status register: Transmit holding register empty/
lynxeyed_atsu	0:63ed631d8c3a	391	UART_LINESTAT_TEMT = UART_LSR_TEMT, /!<Line status register: Transmitter empty/
lynxeyed_atsu	0:63ed631d8c3a	392	UART_LINESTAT_RXFE = UART_LSR_RXFE /!<Error in RX FIFO/
lynxeyed_atsu	0:63ed631d8c3a	393	} UART_LS_Type;
lynxeyed_atsu	0:63ed631d8c3a	394
lynxeyed_atsu	0:63ed631d8c3a	395	/**
lynxeyed_atsu	0:63ed631d8c3a	396	* @brief UART Auto-baudrate mode type definition
lynxeyed_atsu	0:63ed631d8c3a	397	*/
lynxeyed_atsu	0:63ed631d8c3a	398	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	399	UART_AUTOBAUD_MODE0 = 0, /*< UART Auto baudrate Mode 0 /
lynxeyed_atsu	0:63ed631d8c3a	400	UART_AUTOBAUD_MODE1, /*< UART Auto baudrate Mode 1 /
lynxeyed_atsu	0:63ed631d8c3a	401	} UART_AB_MODE_Type;
lynxeyed_atsu	0:63ed631d8c3a	402
lynxeyed_atsu	0:63ed631d8c3a	403	/**
lynxeyed_atsu	0:63ed631d8c3a	404	* @brief Auto Baudrate mode configuration type definition
lynxeyed_atsu	0:63ed631d8c3a	405	*/
lynxeyed_atsu	0:63ed631d8c3a	406	typedef struct {
lynxeyed_atsu	0:63ed631d8c3a	407	UART_AB_MODE_Type ABMode; /*< Autobaudrate mode /
lynxeyed_atsu	0:63ed631d8c3a	408	FunctionalState AutoRestart; /*< Auto Restart state /
lynxeyed_atsu	0:63ed631d8c3a	409	} UART_AB_CFG_Type;
lynxeyed_atsu	0:63ed631d8c3a	410
lynxeyed_atsu	0:63ed631d8c3a	411	/**
lynxeyed_atsu	0:63ed631d8c3a	412	* @brief UART End of Auto-baudrate type definition
lynxeyed_atsu	0:63ed631d8c3a	413	*/
lynxeyed_atsu	0:63ed631d8c3a	414	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	415	UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /*< UART End of auto-baud interrupt /
lynxeyed_atsu	0:63ed631d8c3a	416	UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /*< UART Auto-baud time-out interrupt /
lynxeyed_atsu	0:63ed631d8c3a	417	}UART_ABEO_Type;
lynxeyed_atsu	0:63ed631d8c3a	418
lynxeyed_atsu	0:63ed631d8c3a	419	/**
lynxeyed_atsu	0:63ed631d8c3a	420	* UART IrDA Control type Definition
lynxeyed_atsu	0:63ed631d8c3a	421	*/
lynxeyed_atsu	0:63ed631d8c3a	422	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	423	UART_IrDA_PULSEDIV2 = 0, /*< Pulse width = 2 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	424	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	425	UART_IrDA_PULSEDIV4, /*< Pulse width = 4 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	426	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	427	UART_IrDA_PULSEDIV8, /*< Pulse width = 8 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	428	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	429	UART_IrDA_PULSEDIV16, /*< Pulse width = 16 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	430	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	431	UART_IrDA_PULSEDIV32, /*< Pulse width = 32 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	432	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	433	UART_IrDA_PULSEDIV64, /*< Pulse width = 64 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	434	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	435	UART_IrDA_PULSEDIV128, /*< Pulse width = 128 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	436	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	437	UART_IrDA_PULSEDIV256 /*< Pulse width = 256 Tpclk
lynxeyed_atsu	0:63ed631d8c3a	438	- Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu	0:63ed631d8c3a	439	} UART_IrDA_PULSE_Type;
lynxeyed_atsu	0:63ed631d8c3a	440
lynxeyed_atsu	0:63ed631d8c3a	441	/******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	442	* @brief UART1 Full modem - Signal states definition
lynxeyed_atsu	0:63ed631d8c3a	443	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	444	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	445	INACTIVE = 0, /* In-active state */
lynxeyed_atsu	0:63ed631d8c3a	446	ACTIVE = !INACTIVE /* Active state */
lynxeyed_atsu	0:63ed631d8c3a	447	}UART1_SignalState;
lynxeyed_atsu	0:63ed631d8c3a	448
lynxeyed_atsu	0:63ed631d8c3a	449	/**
lynxeyed_atsu	0:63ed631d8c3a	450	* @brief UART modem status type definition
lynxeyed_atsu	0:63ed631d8c3a	451	*/
lynxeyed_atsu	0:63ed631d8c3a	452	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	453	UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /!< Set upon state change of input CTS /
lynxeyed_atsu	0:63ed631d8c3a	454	UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /!< Set upon state change of input DSR /
lynxeyed_atsu	0:63ed631d8c3a	455	UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /!< Set upon low to high transition of input RI /
lynxeyed_atsu	0:63ed631d8c3a	456	UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /!< Set upon state change of input DCD /
lynxeyed_atsu	0:63ed631d8c3a	457	UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /!< Clear To Send State /
lynxeyed_atsu	0:63ed631d8c3a	458	UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /!< Data Set Ready State /
lynxeyed_atsu	0:63ed631d8c3a	459	UART1_MODEM_STAT_RI = UART1_MSR_RI, /!< Ring Indicator State /
lynxeyed_atsu	0:63ed631d8c3a	460	UART1_MODEM_STAT_DCD = UART1_MSR_DCD /!< Data Carrier Detect State /
lynxeyed_atsu	0:63ed631d8c3a	461	} UART_MODEM_STAT_type;
lynxeyed_atsu	0:63ed631d8c3a	462
lynxeyed_atsu	0:63ed631d8c3a	463	/**
lynxeyed_atsu	0:63ed631d8c3a	464	* @brief Modem output pin type definition
lynxeyed_atsu	0:63ed631d8c3a	465	*/
lynxeyed_atsu	0:63ed631d8c3a	466	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	467	UART1_MODEM_PIN_DTR = 0, /!< Source for modem output pin DTR /
lynxeyed_atsu	0:63ed631d8c3a	468	UART1_MODEM_PIN_RTS /!< Source for modem output pin RTS /
lynxeyed_atsu	0:63ed631d8c3a	469	} UART_MODEM_PIN_Type;
lynxeyed_atsu	0:63ed631d8c3a	470
lynxeyed_atsu	0:63ed631d8c3a	471	/**
lynxeyed_atsu	0:63ed631d8c3a	472	* @brief UART Modem mode type definition
lynxeyed_atsu	0:63ed631d8c3a	473	*/
lynxeyed_atsu	0:63ed631d8c3a	474	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	475	UART1_MODEM_MODE_LOOPBACK = 0, /!< Loop back mode select /
lynxeyed_atsu	0:63ed631d8c3a	476	UART1_MODEM_MODE_AUTO_RTS, /!< Enable Auto RTS flow-control /
lynxeyed_atsu	0:63ed631d8c3a	477	UART1_MODEM_MODE_AUTO_CTS /!< Enable Auto CTS flow-control /
lynxeyed_atsu	0:63ed631d8c3a	478	} UART_MODEM_MODE_Type;
lynxeyed_atsu	0:63ed631d8c3a	479
lynxeyed_atsu	0:63ed631d8c3a	480	/**
lynxeyed_atsu	0:63ed631d8c3a	481	* @brief UART Direction Control Pin type definition
lynxeyed_atsu	0:63ed631d8c3a	482	*/
lynxeyed_atsu	0:63ed631d8c3a	483	typedef enum {
lynxeyed_atsu	0:63ed631d8c3a	484	UART1_RS485_DIRCTRL_RTS = 0, /*< Pin RTS is used for direction control /
lynxeyed_atsu	0:63ed631d8c3a	485	UART1_RS485_DIRCTRL_DTR /*< Pin DTR is used for direction control /
lynxeyed_atsu	0:63ed631d8c3a	486	} UART_RS485_DIRCTRL_PIN_Type;
lynxeyed_atsu	0:63ed631d8c3a	487
lynxeyed_atsu	0:63ed631d8c3a	488	/******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	489	* @brief UART Configuration Structure definition
lynxeyed_atsu	0:63ed631d8c3a	490	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	491	typedef struct {
lynxeyed_atsu	0:63ed631d8c3a	492	uint32_t Baud_rate; /*< UART baud rate /
lynxeyed_atsu	0:63ed631d8c3a	493	UART_PARITY_Type Parity; /**< Parity selection, should be:
lynxeyed_atsu	0:63ed631d8c3a	494	- UART_PARITY_NONE: No parity
lynxeyed_atsu	0:63ed631d8c3a	495	- UART_PARITY_ODD: Odd parity
lynxeyed_atsu	0:63ed631d8c3a	496	- UART_PARITY_EVEN: Even parity
lynxeyed_atsu	0:63ed631d8c3a	497	- UART_PARITY_SP_1: Forced "1" stick parity
lynxeyed_atsu	0:63ed631d8c3a	498	- UART_PARITY_SP_0: Forced "0" stick parity
lynxeyed_atsu	0:63ed631d8c3a	499	*/
lynxeyed_atsu	0:63ed631d8c3a	500	UART_DATABIT_Type Databits; /**< Number of data bits, should be:
lynxeyed_atsu	0:63ed631d8c3a	501	- UART_DATABIT_5: UART 5 bit data mode
lynxeyed_atsu	0:63ed631d8c3a	502	- UART_DATABIT_6: UART 6 bit data mode
lynxeyed_atsu	0:63ed631d8c3a	503	- UART_DATABIT_7: UART 7 bit data mode
lynxeyed_atsu	0:63ed631d8c3a	504	- UART_DATABIT_8: UART 8 bit data mode
lynxeyed_atsu	0:63ed631d8c3a	505	*/
lynxeyed_atsu	0:63ed631d8c3a	506	UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
lynxeyed_atsu	0:63ed631d8c3a	507	- UART_STOPBIT_1: UART 1 Stop Bits Select
lynxeyed_atsu	0:63ed631d8c3a	508	- UART_STOPBIT_2: UART 2 Stop Bits Select
lynxeyed_atsu	0:63ed631d8c3a	509	*/
lynxeyed_atsu	0:63ed631d8c3a	510	} UART_CFG_Type;
lynxeyed_atsu	0:63ed631d8c3a	511
lynxeyed_atsu	0:63ed631d8c3a	512	/******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	513	* @brief UART FIFO Configuration Structure definition
lynxeyed_atsu	0:63ed631d8c3a	514	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	515
lynxeyed_atsu	0:63ed631d8c3a	516	typedef struct {
lynxeyed_atsu	0:63ed631d8c3a	517	FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
lynxeyed_atsu	0:63ed631d8c3a	518	- ENABLE: Reset Rx FIFO in UART
lynxeyed_atsu	0:63ed631d8c3a	519	- DISABLE: Do not reset Rx FIFO in UART
lynxeyed_atsu	0:63ed631d8c3a	520	*/
lynxeyed_atsu	0:63ed631d8c3a	521	FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
lynxeyed_atsu	0:63ed631d8c3a	522	- ENABLE: Reset Tx FIFO in UART
lynxeyed_atsu	0:63ed631d8c3a	523	- DISABLE: Do not reset Tx FIFO in UART
lynxeyed_atsu	0:63ed631d8c3a	524	*/
lynxeyed_atsu	0:63ed631d8c3a	525	FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
lynxeyed_atsu	0:63ed631d8c3a	526	- ENABLE: Enable DMA mode in UART
lynxeyed_atsu	0:63ed631d8c3a	527	- DISABLE: Disable DMA mode in UART
lynxeyed_atsu	0:63ed631d8c3a	528	*/
lynxeyed_atsu	0:63ed631d8c3a	529	UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
lynxeyed_atsu	0:63ed631d8c3a	530	- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
lynxeyed_atsu	0:63ed631d8c3a	531	- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
lynxeyed_atsu	0:63ed631d8c3a	532	- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
lynxeyed_atsu	0:63ed631d8c3a	533	- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
lynxeyed_atsu	0:63ed631d8c3a	534	*/
lynxeyed_atsu	0:63ed631d8c3a	535	} UART_FIFO_CFG_Type;
lynxeyed_atsu	0:63ed631d8c3a	536
lynxeyed_atsu	0:63ed631d8c3a	537	/******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	538	* @brief UART1 Full modem - RS485 Control configuration type
lynxeyed_atsu	0:63ed631d8c3a	539	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	540	typedef struct {
lynxeyed_atsu	0:63ed631d8c3a	541	FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
lynxeyed_atsu	0:63ed631d8c3a	542	- ENABLE: Enable this function.
lynxeyed_atsu	0:63ed631d8c3a	543	- DISABLE: Disable this function. */
lynxeyed_atsu	0:63ed631d8c3a	544	FunctionalState Rx_State; /*!< Receiver State:
lynxeyed_atsu	0:63ed631d8c3a	545	- ENABLE: Enable Receiver.
lynxeyed_atsu	0:63ed631d8c3a	546	- DISABLE: Disable Receiver. */
lynxeyed_atsu	0:63ed631d8c3a	547	FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
lynxeyed_atsu	0:63ed631d8c3a	548	- ENABLE: ENABLE this function.
lynxeyed_atsu	0:63ed631d8c3a	549	- DISABLE: Disable this function. */
lynxeyed_atsu	0:63ed631d8c3a	550	FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
lynxeyed_atsu	0:63ed631d8c3a	551	- ENABLE: Enable this function.
lynxeyed_atsu	0:63ed631d8c3a	552	- DISABLE: Disable this function. */
lynxeyed_atsu	0:63ed631d8c3a	553	UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
lynxeyed_atsu	0:63ed631d8c3a	554	- UART1_RS485_DIRCTRL_RTS:
lynxeyed_atsu	0:63ed631d8c3a	555	pin RTS is used for direction control.
lynxeyed_atsu	0:63ed631d8c3a	556	- UART1_RS485_DIRCTRL_DTR:
lynxeyed_atsu	0:63ed631d8c3a	557	pin DTR is used for direction control. */
lynxeyed_atsu	0:63ed631d8c3a	558	SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
lynxeyed_atsu	0:63ed631d8c3a	559	the RTS (or DTR) pin:
lynxeyed_atsu	0:63ed631d8c3a	560	- RESET: The direction control pin will be driven
lynxeyed_atsu	0:63ed631d8c3a	561	to logic "0" when the transmitter has data to be sent.
lynxeyed_atsu	0:63ed631d8c3a	562	- SET: The direction control pin will be driven
lynxeyed_atsu	0:63ed631d8c3a	563	to logic "1" when the transmitter has data to be sent. */
lynxeyed_atsu	0:63ed631d8c3a	564	uint8_t MatchAddrValue; /!< address match value for RS-485/EIA-485 mode, 8-bit long /
lynxeyed_atsu	0:63ed631d8c3a	565	uint8_t DelayValue; /!< delay time is in periods of the baud clock, 8-bit long /
lynxeyed_atsu	0:63ed631d8c3a	566	} UART1_RS485_CTRLCFG_Type;
lynxeyed_atsu	0:63ed631d8c3a	567
lynxeyed_atsu	0:63ed631d8c3a	568	/**
lynxeyed_atsu	0:63ed631d8c3a	569	* @}
lynxeyed_atsu	0:63ed631d8c3a	570	*/
lynxeyed_atsu	0:63ed631d8c3a	571
lynxeyed_atsu	0:63ed631d8c3a	572
lynxeyed_atsu	0:63ed631d8c3a	573	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	574	/** @defgroup UART_Public_Functions UART Public Functions
lynxeyed_atsu	0:63ed631d8c3a	575	* @{
lynxeyed_atsu	0:63ed631d8c3a	576	*/
lynxeyed_atsu	0:63ed631d8c3a	577	/* UART Init/DeInit functions --------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	578	void UART_Init(LPC_UART_TypeDef UARTx, UART_CFG_Type UART_ConfigStruct);
lynxeyed_atsu	0:63ed631d8c3a	579	void UART_DeInit(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu	0:63ed631d8c3a	580	void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
lynxeyed_atsu	0:63ed631d8c3a	581
lynxeyed_atsu	0:63ed631d8c3a	582	/* UART Send/Receive functions -------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	583	void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
lynxeyed_atsu	0:63ed631d8c3a	584	uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu	0:63ed631d8c3a	585	uint32_t UART_Send(LPC_UART_TypeDef UARTx, uint8_t txbuf,
lynxeyed_atsu	0:63ed631d8c3a	586	uint32_t buflen, TRANSFER_BLOCK_Type flag);
lynxeyed_atsu	0:63ed631d8c3a	587	uint32_t UART_Receive(LPC_UART_TypeDef UARTx, uint8_t rxbuf, \
lynxeyed_atsu	0:63ed631d8c3a	588	uint32_t buflen, TRANSFER_BLOCK_Type flag);
lynxeyed_atsu	0:63ed631d8c3a	589
lynxeyed_atsu	0:63ed631d8c3a	590	/* UART FIFO functions ----------------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	591	void UART_FIFOConfig(LPC_UART_TypeDef UARTx, UART_FIFO_CFG_Type FIFOCfg);
lynxeyed_atsu	0:63ed631d8c3a	592	void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
lynxeyed_atsu	0:63ed631d8c3a	593
lynxeyed_atsu	0:63ed631d8c3a	594	/* UART get information functions -----------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	595	uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu	0:63ed631d8c3a	596	uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu	0:63ed631d8c3a	597
lynxeyed_atsu	0:63ed631d8c3a	598	/* UART operate functions -------------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	599	void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
lynxeyed_atsu	0:63ed631d8c3a	600	FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	601	void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	602	FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
lynxeyed_atsu	0:63ed631d8c3a	603	void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu	0:63ed631d8c3a	604
lynxeyed_atsu	0:63ed631d8c3a	605	/* UART Auto-baud functions -----------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	606	void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
lynxeyed_atsu	0:63ed631d8c3a	607	void UART_ABCmd(LPC_UART_TypeDef UARTx, UART_AB_CFG_Type ABConfigStruct, \
lynxeyed_atsu	0:63ed631d8c3a	608	FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	609
lynxeyed_atsu	0:63ed631d8c3a	610	/* UART1 FullModem functions ----------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	611	void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
lynxeyed_atsu	0:63ed631d8c3a	612	UART1_SignalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	613	void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
lynxeyed_atsu	0:63ed631d8c3a	614	FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	615	uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
lynxeyed_atsu	0:63ed631d8c3a	616
lynxeyed_atsu	0:63ed631d8c3a	617	/* UART RS485 functions ----------------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	618	void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \
lynxeyed_atsu	0:63ed631d8c3a	619	UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
lynxeyed_atsu	0:63ed631d8c3a	620	void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	621	void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr);
lynxeyed_atsu	0:63ed631d8c3a	622	uint32_t UART_RS485SendData(LPC_UART1_TypeDef UARTx, uint8_t pData, uint32_t size);
lynxeyed_atsu	0:63ed631d8c3a	623
lynxeyed_atsu	0:63ed631d8c3a	624	/* UART IrDA functions-------------------------------------------------------------*/
lynxeyed_atsu	0:63ed631d8c3a	625	void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	626	void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
lynxeyed_atsu	0:63ed631d8c3a	627	void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
lynxeyed_atsu	0:63ed631d8c3a	628	/**
lynxeyed_atsu	0:63ed631d8c3a	629	* @}
lynxeyed_atsu	0:63ed631d8c3a	630	*/
lynxeyed_atsu	0:63ed631d8c3a	631
lynxeyed_atsu	0:63ed631d8c3a	632
lynxeyed_atsu	0:63ed631d8c3a	633	#ifdef __cplusplus
lynxeyed_atsu	0:63ed631d8c3a	634	}
lynxeyed_atsu	0:63ed631d8c3a	635	#endif
lynxeyed_atsu	0:63ed631d8c3a	636
lynxeyed_atsu	0:63ed631d8c3a	637
lynxeyed_atsu	0:63ed631d8c3a	638	#endif /* __LPC17XX_UART_H */
lynxeyed_atsu	0:63ed631d8c3a	639
lynxeyed_atsu	0:63ed631d8c3a	640	/**
lynxeyed_atsu	0:63ed631d8c3a	641	* @}
lynxeyed_atsu	0:63ed631d8c3a	642	*/
lynxeyed_atsu	0:63ed631d8c3a	643
lynxeyed_atsu	0:63ed631d8c3a	644	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	21 Jan 2011
Imports:	2
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	2

I2S_Example/lpc17xx_uart.h@0:63ed631d8c3a, 2011-01-21 (annotated)

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