Li Weiyi
/
BalanceCar
虽然移植完毕,但是不work。需要细调……
MPU6050.cpp@3:c6caae712d5d, 2016-06-07 (annotated)
- Committer:
- lixianyu
- Date:
- Tue Jun 07 08:14:15 2016 +0000
- Revision:
- 3:c6caae712d5d
- Parent:
- 2:99785a1007a4
??????????work? ?????
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
lixianyu | 0:a4d8f5b3c546 | 1 | // I2Cdev library collection - MPU6050 I2C device class |
lixianyu | 0:a4d8f5b3c546 | 2 | // Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00) |
lixianyu | 0:a4d8f5b3c546 | 3 | // 8/24/2011 by Jeff Rowberg <jeff@rowberg.net> |
lixianyu | 0:a4d8f5b3c546 | 4 | // Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib |
lixianyu | 0:a4d8f5b3c546 | 5 | // |
lixianyu | 0:a4d8f5b3c546 | 6 | // Changelog: |
lixianyu | 0:a4d8f5b3c546 | 7 | // ... - ongoing debug release |
lixianyu | 0:a4d8f5b3c546 | 8 | |
lixianyu | 0:a4d8f5b3c546 | 9 | // NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE |
lixianyu | 0:a4d8f5b3c546 | 10 | // DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF |
lixianyu | 0:a4d8f5b3c546 | 11 | // YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING. |
lixianyu | 0:a4d8f5b3c546 | 12 | |
lixianyu | 0:a4d8f5b3c546 | 13 | /* ============================================ |
lixianyu | 0:a4d8f5b3c546 | 14 | I2Cdev device library code is placed under the MIT license |
lixianyu | 0:a4d8f5b3c546 | 15 | Copyright (c) 2012 Jeff Rowberg |
lixianyu | 0:a4d8f5b3c546 | 16 | |
lixianyu | 0:a4d8f5b3c546 | 17 | Permission is hereby granted, free of charge, to any person obtaining a copy |
lixianyu | 0:a4d8f5b3c546 | 18 | of this software and associated documentation files (the "Software"), to deal |
lixianyu | 0:a4d8f5b3c546 | 19 | in the Software without restriction, including without limitation the rights |
lixianyu | 0:a4d8f5b3c546 | 20 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
lixianyu | 0:a4d8f5b3c546 | 21 | copies of the Software, and to permit persons to whom the Software is |
lixianyu | 0:a4d8f5b3c546 | 22 | furnished to do so, subject to the following conditions: |
lixianyu | 0:a4d8f5b3c546 | 23 | |
lixianyu | 0:a4d8f5b3c546 | 24 | The above copyright notice and this permission notice shall be included in |
lixianyu | 0:a4d8f5b3c546 | 25 | all copies or substantial portions of the Software. |
lixianyu | 0:a4d8f5b3c546 | 26 | |
lixianyu | 0:a4d8f5b3c546 | 27 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
lixianyu | 0:a4d8f5b3c546 | 28 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
lixianyu | 0:a4d8f5b3c546 | 29 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
lixianyu | 0:a4d8f5b3c546 | 30 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
lixianyu | 0:a4d8f5b3c546 | 31 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
lixianyu | 0:a4d8f5b3c546 | 32 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
lixianyu | 0:a4d8f5b3c546 | 33 | THE SOFTWARE. |
lixianyu | 0:a4d8f5b3c546 | 34 | =============================================== |
lixianyu | 0:a4d8f5b3c546 | 35 | */ |
lixianyu | 0:a4d8f5b3c546 | 36 | |
lixianyu | 0:a4d8f5b3c546 | 37 | #include "MPU6050.h" |
lixianyu | 2:99785a1007a4 | 38 | extern DigitalOut myled; |
lixianyu | 0:a4d8f5b3c546 | 39 | #define pgm_read_byte(addr) (*(const unsigned char *)(addr)) |
lixianyu | 0:a4d8f5b3c546 | 40 | /** Default constructor, uses default I2C address. |
lixianyu | 0:a4d8f5b3c546 | 41 | * @see MPU6050_DEFAULT_ADDRESS |
lixianyu | 0:a4d8f5b3c546 | 42 | */ |
lixianyu | 0:a4d8f5b3c546 | 43 | MPU6050::MPU6050() { |
lixianyu | 0:a4d8f5b3c546 | 44 | devAddr = MPU6050_DEFAULT_ADDRESS; |
lixianyu | 2:99785a1007a4 | 45 | //myled = 1; |
lixianyu | 0:a4d8f5b3c546 | 46 | } |
lixianyu | 0:a4d8f5b3c546 | 47 | |
lixianyu | 0:a4d8f5b3c546 | 48 | /** Specific address constructor. |
lixianyu | 0:a4d8f5b3c546 | 49 | * @param address I2C address |
lixianyu | 0:a4d8f5b3c546 | 50 | * @see MPU6050_DEFAULT_ADDRESS |
lixianyu | 0:a4d8f5b3c546 | 51 | * @see MPU6050_ADDRESS_AD0_LOW |
lixianyu | 0:a4d8f5b3c546 | 52 | * @see MPU6050_ADDRESS_AD0_HIGH |
lixianyu | 0:a4d8f5b3c546 | 53 | */ |
lixianyu | 0:a4d8f5b3c546 | 54 | MPU6050::MPU6050(uint8_t address) { |
lixianyu | 0:a4d8f5b3c546 | 55 | devAddr = address; |
lixianyu | 0:a4d8f5b3c546 | 56 | } |
lixianyu | 0:a4d8f5b3c546 | 57 | |
lixianyu | 0:a4d8f5b3c546 | 58 | /** Power on and prepare for general usage. |
lixianyu | 0:a4d8f5b3c546 | 59 | * This will activate the device and take it out of sleep mode (which must be done |
lixianyu | 0:a4d8f5b3c546 | 60 | * after start-up). This function also sets both the accelerometer and the gyroscope |
lixianyu | 0:a4d8f5b3c546 | 61 | * to their most sensitive settings, namely +/- 2g and +/- 250 degrees/sec, and sets |
lixianyu | 0:a4d8f5b3c546 | 62 | * the clock source to use the X Gyro for reference, which is slightly better than |
lixianyu | 0:a4d8f5b3c546 | 63 | * the default internal clock source. |
lixianyu | 0:a4d8f5b3c546 | 64 | */ |
lixianyu | 0:a4d8f5b3c546 | 65 | void MPU6050::initialize() { |
lixianyu | 2:99785a1007a4 | 66 | //I2Cdev i2cdev; |
lixianyu | 2:99785a1007a4 | 67 | I2Cdev::init(); |
lixianyu | 0:a4d8f5b3c546 | 68 | setClockSource(MPU6050_CLOCK_PLL_XGYRO); |
lixianyu | 0:a4d8f5b3c546 | 69 | setFullScaleGyroRange(MPU6050_GYRO_FS_250); |
lixianyu | 0:a4d8f5b3c546 | 70 | setFullScaleAccelRange(MPU6050_ACCEL_FS_2); |
lixianyu | 0:a4d8f5b3c546 | 71 | setSleepEnabled(false); // thanks to Jack Elston for pointing this one out! |
lixianyu | 0:a4d8f5b3c546 | 72 | } |
lixianyu | 0:a4d8f5b3c546 | 73 | |
lixianyu | 0:a4d8f5b3c546 | 74 | /** Verify the I2C connection. |
lixianyu | 0:a4d8f5b3c546 | 75 | * Make sure the device is connected and responds as expected. |
lixianyu | 0:a4d8f5b3c546 | 76 | * @return True if connection is valid, false otherwise |
lixianyu | 0:a4d8f5b3c546 | 77 | */ |
lixianyu | 0:a4d8f5b3c546 | 78 | bool MPU6050::testConnection() { |
lixianyu | 0:a4d8f5b3c546 | 79 | return getDeviceID() == 0x34; |
lixianyu | 0:a4d8f5b3c546 | 80 | } |
lixianyu | 0:a4d8f5b3c546 | 81 | |
lixianyu | 0:a4d8f5b3c546 | 82 | // AUX_VDDIO register (InvenSense demo code calls this RA_*G_OFFS_TC) |
lixianyu | 0:a4d8f5b3c546 | 83 | |
lixianyu | 0:a4d8f5b3c546 | 84 | /** Get the auxiliary I2C supply voltage level. |
lixianyu | 0:a4d8f5b3c546 | 85 | * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to |
lixianyu | 0:a4d8f5b3c546 | 86 | * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to |
lixianyu | 0:a4d8f5b3c546 | 87 | * the MPU-6000, which does not have a VLOGIC pin. |
lixianyu | 0:a4d8f5b3c546 | 88 | * @return I2C supply voltage level (0=VLOGIC, 1=VDD) |
lixianyu | 0:a4d8f5b3c546 | 89 | */ |
lixianyu | 0:a4d8f5b3c546 | 90 | uint8_t MPU6050::getAuxVDDIOLevel() { |
lixianyu | 0:a4d8f5b3c546 | 91 | I2Cdev::readBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 92 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 93 | } |
lixianyu | 0:a4d8f5b3c546 | 94 | /** Set the auxiliary I2C supply voltage level. |
lixianyu | 0:a4d8f5b3c546 | 95 | * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to |
lixianyu | 0:a4d8f5b3c546 | 96 | * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to |
lixianyu | 0:a4d8f5b3c546 | 97 | * the MPU-6000, which does not have a VLOGIC pin. |
lixianyu | 0:a4d8f5b3c546 | 98 | * @param level I2C supply voltage level (0=VLOGIC, 1=VDD) |
lixianyu | 0:a4d8f5b3c546 | 99 | */ |
lixianyu | 0:a4d8f5b3c546 | 100 | void MPU6050::setAuxVDDIOLevel(uint8_t level) { |
lixianyu | 0:a4d8f5b3c546 | 101 | I2Cdev::writeBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, level); |
lixianyu | 0:a4d8f5b3c546 | 102 | } |
lixianyu | 0:a4d8f5b3c546 | 103 | |
lixianyu | 0:a4d8f5b3c546 | 104 | // SMPLRT_DIV register |
lixianyu | 0:a4d8f5b3c546 | 105 | |
lixianyu | 0:a4d8f5b3c546 | 106 | /** Get gyroscope output rate divider. |
lixianyu | 0:a4d8f5b3c546 | 107 | * The sensor register output, FIFO output, DMP sampling, Motion detection, Zero |
lixianyu | 0:a4d8f5b3c546 | 108 | * Motion detection, and Free Fall detection are all based on the Sample Rate. |
lixianyu | 0:a4d8f5b3c546 | 109 | * The Sample Rate is generated by dividing the gyroscope output rate by |
lixianyu | 0:a4d8f5b3c546 | 110 | * SMPLRT_DIV: |
lixianyu | 0:a4d8f5b3c546 | 111 | * |
lixianyu | 0:a4d8f5b3c546 | 112 | * Sample Rate = Gyroscope Output Rate / (1 + SMPLRT_DIV) |
lixianyu | 0:a4d8f5b3c546 | 113 | * |
lixianyu | 0:a4d8f5b3c546 | 114 | * where Gyroscope Output Rate = 8kHz when the DLPF is disabled (DLPF_CFG = 0 or |
lixianyu | 0:a4d8f5b3c546 | 115 | * 7), and 1kHz when the DLPF is enabled (see Register 26). |
lixianyu | 0:a4d8f5b3c546 | 116 | * |
lixianyu | 0:a4d8f5b3c546 | 117 | * Note: The accelerometer output rate is 1kHz. This means that for a Sample |
lixianyu | 0:a4d8f5b3c546 | 118 | * Rate greater than 1kHz, the same accelerometer sample may be output to the |
lixianyu | 0:a4d8f5b3c546 | 119 | * FIFO, DMP, and sensor registers more than once. |
lixianyu | 0:a4d8f5b3c546 | 120 | * |
lixianyu | 0:a4d8f5b3c546 | 121 | * For a diagram of the gyroscope and accelerometer signal paths, see Section 8 |
lixianyu | 0:a4d8f5b3c546 | 122 | * of the MPU-6000/MPU-6050 Product Specification document. |
lixianyu | 0:a4d8f5b3c546 | 123 | * |
lixianyu | 0:a4d8f5b3c546 | 124 | * @return Current sample rate |
lixianyu | 0:a4d8f5b3c546 | 125 | * @see MPU6050_RA_SMPLRT_DIV |
lixianyu | 0:a4d8f5b3c546 | 126 | */ |
lixianyu | 0:a4d8f5b3c546 | 127 | uint8_t MPU6050::getRate() { |
lixianyu | 0:a4d8f5b3c546 | 128 | I2Cdev::readByte(devAddr, MPU6050_RA_SMPLRT_DIV, buffer); |
lixianyu | 0:a4d8f5b3c546 | 129 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 130 | } |
lixianyu | 0:a4d8f5b3c546 | 131 | /** Set gyroscope sample rate divider. |
lixianyu | 0:a4d8f5b3c546 | 132 | * @param rate New sample rate divider |
lixianyu | 0:a4d8f5b3c546 | 133 | * @see getRate() |
lixianyu | 0:a4d8f5b3c546 | 134 | * @see MPU6050_RA_SMPLRT_DIV |
lixianyu | 0:a4d8f5b3c546 | 135 | */ |
lixianyu | 0:a4d8f5b3c546 | 136 | void MPU6050::setRate(uint8_t rate) { |
lixianyu | 0:a4d8f5b3c546 | 137 | I2Cdev::writeByte(devAddr, MPU6050_RA_SMPLRT_DIV, rate); |
lixianyu | 0:a4d8f5b3c546 | 138 | } |
lixianyu | 0:a4d8f5b3c546 | 139 | |
lixianyu | 0:a4d8f5b3c546 | 140 | // CONFIG register |
lixianyu | 0:a4d8f5b3c546 | 141 | |
lixianyu | 0:a4d8f5b3c546 | 142 | /** Get external FSYNC configuration. |
lixianyu | 0:a4d8f5b3c546 | 143 | * Configures the external Frame Synchronization (FSYNC) pin sampling. An |
lixianyu | 0:a4d8f5b3c546 | 144 | * external signal connected to the FSYNC pin can be sampled by configuring |
lixianyu | 0:a4d8f5b3c546 | 145 | * EXT_SYNC_SET. Signal changes to the FSYNC pin are latched so that short |
lixianyu | 0:a4d8f5b3c546 | 146 | * strobes may be captured. The latched FSYNC signal will be sampled at the |
lixianyu | 0:a4d8f5b3c546 | 147 | * Sampling Rate, as defined in register 25. After sampling, the latch will |
lixianyu | 0:a4d8f5b3c546 | 148 | * reset to the current FSYNC signal state. |
lixianyu | 0:a4d8f5b3c546 | 149 | * |
lixianyu | 0:a4d8f5b3c546 | 150 | * The sampled value will be reported in place of the least significant bit in |
lixianyu | 0:a4d8f5b3c546 | 151 | * a sensor data register determined by the value of EXT_SYNC_SET according to |
lixianyu | 0:a4d8f5b3c546 | 152 | * the following table. |
lixianyu | 0:a4d8f5b3c546 | 153 | * |
lixianyu | 0:a4d8f5b3c546 | 154 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 155 | * EXT_SYNC_SET | FSYNC Bit Location |
lixianyu | 0:a4d8f5b3c546 | 156 | * -------------+------------------- |
lixianyu | 0:a4d8f5b3c546 | 157 | * 0 | Input disabled |
lixianyu | 0:a4d8f5b3c546 | 158 | * 1 | TEMP_OUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 159 | * 2 | GYRO_XOUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 160 | * 3 | GYRO_YOUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 161 | * 4 | GYRO_ZOUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 162 | * 5 | ACCEL_XOUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 163 | * 6 | ACCEL_YOUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 164 | * 7 | ACCEL_ZOUT_L[0] |
lixianyu | 0:a4d8f5b3c546 | 165 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 166 | * |
lixianyu | 0:a4d8f5b3c546 | 167 | * @return FSYNC configuration value |
lixianyu | 0:a4d8f5b3c546 | 168 | */ |
lixianyu | 0:a4d8f5b3c546 | 169 | uint8_t MPU6050::getExternalFrameSync() { |
lixianyu | 0:a4d8f5b3c546 | 170 | I2Cdev::readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 171 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 172 | } |
lixianyu | 0:a4d8f5b3c546 | 173 | /** Set external FSYNC configuration. |
lixianyu | 0:a4d8f5b3c546 | 174 | * @see getExternalFrameSync() |
lixianyu | 0:a4d8f5b3c546 | 175 | * @see MPU6050_RA_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 176 | * @param sync New FSYNC configuration value |
lixianyu | 0:a4d8f5b3c546 | 177 | */ |
lixianyu | 0:a4d8f5b3c546 | 178 | void MPU6050::setExternalFrameSync(uint8_t sync) { |
lixianyu | 0:a4d8f5b3c546 | 179 | I2Cdev::writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, sync); |
lixianyu | 0:a4d8f5b3c546 | 180 | } |
lixianyu | 0:a4d8f5b3c546 | 181 | /** Get digital low-pass filter configuration. |
lixianyu | 0:a4d8f5b3c546 | 182 | * The DLPF_CFG parameter sets the digital low pass filter configuration. It |
lixianyu | 0:a4d8f5b3c546 | 183 | * also determines the internal sampling rate used by the device as shown in |
lixianyu | 0:a4d8f5b3c546 | 184 | * the table below. |
lixianyu | 0:a4d8f5b3c546 | 185 | * |
lixianyu | 0:a4d8f5b3c546 | 186 | * Note: The accelerometer output rate is 1kHz. This means that for a Sample |
lixianyu | 0:a4d8f5b3c546 | 187 | * Rate greater than 1kHz, the same accelerometer sample may be output to the |
lixianyu | 0:a4d8f5b3c546 | 188 | * FIFO, DMP, and sensor registers more than once. |
lixianyu | 0:a4d8f5b3c546 | 189 | * |
lixianyu | 0:a4d8f5b3c546 | 190 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 191 | * | ACCELEROMETER | GYROSCOPE |
lixianyu | 0:a4d8f5b3c546 | 192 | * DLPF_CFG | Bandwidth | Delay | Bandwidth | Delay | Sample Rate |
lixianyu | 0:a4d8f5b3c546 | 193 | * ---------+-----------+--------+-----------+--------+------------- |
lixianyu | 0:a4d8f5b3c546 | 194 | * 0 | 260Hz | 0ms | 256Hz | 0.98ms | 8kHz |
lixianyu | 0:a4d8f5b3c546 | 195 | * 1 | 184Hz | 2.0ms | 188Hz | 1.9ms | 1kHz |
lixianyu | 0:a4d8f5b3c546 | 196 | * 2 | 94Hz | 3.0ms | 98Hz | 2.8ms | 1kHz |
lixianyu | 0:a4d8f5b3c546 | 197 | * 3 | 44Hz | 4.9ms | 42Hz | 4.8ms | 1kHz |
lixianyu | 0:a4d8f5b3c546 | 198 | * 4 | 21Hz | 8.5ms | 20Hz | 8.3ms | 1kHz |
lixianyu | 0:a4d8f5b3c546 | 199 | * 5 | 10Hz | 13.8ms | 10Hz | 13.4ms | 1kHz |
lixianyu | 0:a4d8f5b3c546 | 200 | * 6 | 5Hz | 19.0ms | 5Hz | 18.6ms | 1kHz |
lixianyu | 0:a4d8f5b3c546 | 201 | * 7 | -- Reserved -- | -- Reserved -- | Reserved |
lixianyu | 0:a4d8f5b3c546 | 202 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 203 | * |
lixianyu | 0:a4d8f5b3c546 | 204 | * @return DLFP configuration |
lixianyu | 0:a4d8f5b3c546 | 205 | * @see MPU6050_RA_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 206 | * @see MPU6050_CFG_DLPF_CFG_BIT |
lixianyu | 0:a4d8f5b3c546 | 207 | * @see MPU6050_CFG_DLPF_CFG_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 208 | */ |
lixianyu | 0:a4d8f5b3c546 | 209 | uint8_t MPU6050::getDLPFMode() { |
lixianyu | 0:a4d8f5b3c546 | 210 | I2Cdev::readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 211 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 212 | } |
lixianyu | 0:a4d8f5b3c546 | 213 | /** Set digital low-pass filter configuration. |
lixianyu | 0:a4d8f5b3c546 | 214 | * @param mode New DLFP configuration setting |
lixianyu | 0:a4d8f5b3c546 | 215 | * @see getDLPFBandwidth() |
lixianyu | 0:a4d8f5b3c546 | 216 | * @see MPU6050_DLPF_BW_256 |
lixianyu | 0:a4d8f5b3c546 | 217 | * @see MPU6050_RA_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 218 | * @see MPU6050_CFG_DLPF_CFG_BIT |
lixianyu | 0:a4d8f5b3c546 | 219 | * @see MPU6050_CFG_DLPF_CFG_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 220 | */ |
lixianyu | 0:a4d8f5b3c546 | 221 | void MPU6050::setDLPFMode(uint8_t mode) { |
lixianyu | 0:a4d8f5b3c546 | 222 | I2Cdev::writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, mode); |
lixianyu | 0:a4d8f5b3c546 | 223 | } |
lixianyu | 0:a4d8f5b3c546 | 224 | |
lixianyu | 0:a4d8f5b3c546 | 225 | // GYRO_CONFIG register |
lixianyu | 0:a4d8f5b3c546 | 226 | |
lixianyu | 0:a4d8f5b3c546 | 227 | /** Get full-scale gyroscope range. |
lixianyu | 0:a4d8f5b3c546 | 228 | * The FS_SEL parameter allows setting the full-scale range of the gyro sensors, |
lixianyu | 0:a4d8f5b3c546 | 229 | * as described in the table below. |
lixianyu | 0:a4d8f5b3c546 | 230 | * |
lixianyu | 0:a4d8f5b3c546 | 231 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 232 | * 0 = +/- 250 degrees/sec |
lixianyu | 0:a4d8f5b3c546 | 233 | * 1 = +/- 500 degrees/sec |
lixianyu | 0:a4d8f5b3c546 | 234 | * 2 = +/- 1000 degrees/sec |
lixianyu | 0:a4d8f5b3c546 | 235 | * 3 = +/- 2000 degrees/sec |
lixianyu | 0:a4d8f5b3c546 | 236 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 237 | * |
lixianyu | 0:a4d8f5b3c546 | 238 | * @return Current full-scale gyroscope range setting |
lixianyu | 0:a4d8f5b3c546 | 239 | * @see MPU6050_GYRO_FS_250 |
lixianyu | 0:a4d8f5b3c546 | 240 | * @see MPU6050_RA_GYRO_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 241 | * @see MPU6050_GCONFIG_FS_SEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 242 | * @see MPU6050_GCONFIG_FS_SEL_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 243 | */ |
lixianyu | 0:a4d8f5b3c546 | 244 | uint8_t MPU6050::getFullScaleGyroRange() { |
lixianyu | 0:a4d8f5b3c546 | 245 | I2Cdev::readBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 246 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 247 | } |
lixianyu | 0:a4d8f5b3c546 | 248 | /** Set full-scale gyroscope range. |
lixianyu | 0:a4d8f5b3c546 | 249 | * @param range New full-scale gyroscope range value |
lixianyu | 0:a4d8f5b3c546 | 250 | * @see getFullScaleRange() |
lixianyu | 0:a4d8f5b3c546 | 251 | * @see MPU6050_GYRO_FS_250 |
lixianyu | 0:a4d8f5b3c546 | 252 | * @see MPU6050_RA_GYRO_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 253 | * @see MPU6050_GCONFIG_FS_SEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 254 | * @see MPU6050_GCONFIG_FS_SEL_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 255 | */ |
lixianyu | 0:a4d8f5b3c546 | 256 | void MPU6050::setFullScaleGyroRange(uint8_t range) { |
lixianyu | 0:a4d8f5b3c546 | 257 | I2Cdev::writeBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, range); |
lixianyu | 0:a4d8f5b3c546 | 258 | } |
lixianyu | 0:a4d8f5b3c546 | 259 | |
lixianyu | 0:a4d8f5b3c546 | 260 | // ACCEL_CONFIG register |
lixianyu | 0:a4d8f5b3c546 | 261 | |
lixianyu | 0:a4d8f5b3c546 | 262 | /** Get self-test enabled setting for accelerometer X axis. |
lixianyu | 0:a4d8f5b3c546 | 263 | * @return Self-test enabled value |
lixianyu | 0:a4d8f5b3c546 | 264 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 265 | */ |
lixianyu | 0:a4d8f5b3c546 | 266 | bool MPU6050::getAccelXSelfTest() { |
lixianyu | 0:a4d8f5b3c546 | 267 | I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 268 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 269 | } |
lixianyu | 0:a4d8f5b3c546 | 270 | /** Get self-test enabled setting for accelerometer X axis. |
lixianyu | 0:a4d8f5b3c546 | 271 | * @param enabled Self-test enabled value |
lixianyu | 0:a4d8f5b3c546 | 272 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 273 | */ |
lixianyu | 0:a4d8f5b3c546 | 274 | void MPU6050::setAccelXSelfTest(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 275 | I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 276 | } |
lixianyu | 0:a4d8f5b3c546 | 277 | /** Get self-test enabled value for accelerometer Y axis. |
lixianyu | 0:a4d8f5b3c546 | 278 | * @return Self-test enabled value |
lixianyu | 0:a4d8f5b3c546 | 279 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 280 | */ |
lixianyu | 0:a4d8f5b3c546 | 281 | bool MPU6050::getAccelYSelfTest() { |
lixianyu | 0:a4d8f5b3c546 | 282 | I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 283 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 284 | } |
lixianyu | 0:a4d8f5b3c546 | 285 | /** Get self-test enabled value for accelerometer Y axis. |
lixianyu | 0:a4d8f5b3c546 | 286 | * @param enabled Self-test enabled value |
lixianyu | 0:a4d8f5b3c546 | 287 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 288 | */ |
lixianyu | 0:a4d8f5b3c546 | 289 | void MPU6050::setAccelYSelfTest(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 290 | I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 291 | } |
lixianyu | 0:a4d8f5b3c546 | 292 | /** Get self-test enabled value for accelerometer Z axis. |
lixianyu | 0:a4d8f5b3c546 | 293 | * @return Self-test enabled value |
lixianyu | 0:a4d8f5b3c546 | 294 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 295 | */ |
lixianyu | 0:a4d8f5b3c546 | 296 | bool MPU6050::getAccelZSelfTest() { |
lixianyu | 0:a4d8f5b3c546 | 297 | I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 298 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 299 | } |
lixianyu | 0:a4d8f5b3c546 | 300 | /** Set self-test enabled value for accelerometer Z axis. |
lixianyu | 0:a4d8f5b3c546 | 301 | * @param enabled Self-test enabled value |
lixianyu | 0:a4d8f5b3c546 | 302 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 303 | */ |
lixianyu | 0:a4d8f5b3c546 | 304 | void MPU6050::setAccelZSelfTest(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 305 | I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 306 | } |
lixianyu | 0:a4d8f5b3c546 | 307 | /** Get full-scale accelerometer range. |
lixianyu | 0:a4d8f5b3c546 | 308 | * The FS_SEL parameter allows setting the full-scale range of the accelerometer |
lixianyu | 0:a4d8f5b3c546 | 309 | * sensors, as described in the table below. |
lixianyu | 0:a4d8f5b3c546 | 310 | * |
lixianyu | 0:a4d8f5b3c546 | 311 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 312 | * 0 = +/- 2g |
lixianyu | 0:a4d8f5b3c546 | 313 | * 1 = +/- 4g |
lixianyu | 0:a4d8f5b3c546 | 314 | * 2 = +/- 8g |
lixianyu | 0:a4d8f5b3c546 | 315 | * 3 = +/- 16g |
lixianyu | 0:a4d8f5b3c546 | 316 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 317 | * |
lixianyu | 0:a4d8f5b3c546 | 318 | * @return Current full-scale accelerometer range setting |
lixianyu | 0:a4d8f5b3c546 | 319 | * @see MPU6050_ACCEL_FS_2 |
lixianyu | 0:a4d8f5b3c546 | 320 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 321 | * @see MPU6050_ACONFIG_AFS_SEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 322 | * @see MPU6050_ACONFIG_AFS_SEL_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 323 | */ |
lixianyu | 0:a4d8f5b3c546 | 324 | uint8_t MPU6050::getFullScaleAccelRange() { |
lixianyu | 0:a4d8f5b3c546 | 325 | I2Cdev::readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 326 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 327 | } |
lixianyu | 0:a4d8f5b3c546 | 328 | /** Set full-scale accelerometer range. |
lixianyu | 0:a4d8f5b3c546 | 329 | * @param range New full-scale accelerometer range setting |
lixianyu | 0:a4d8f5b3c546 | 330 | * @see getFullScaleAccelRange() |
lixianyu | 0:a4d8f5b3c546 | 331 | */ |
lixianyu | 0:a4d8f5b3c546 | 332 | void MPU6050::setFullScaleAccelRange(uint8_t range) { |
lixianyu | 0:a4d8f5b3c546 | 333 | I2Cdev::writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, range); |
lixianyu | 0:a4d8f5b3c546 | 334 | } |
lixianyu | 0:a4d8f5b3c546 | 335 | /** Get the high-pass filter configuration. |
lixianyu | 0:a4d8f5b3c546 | 336 | * The DHPF is a filter module in the path leading to motion detectors (Free |
lixianyu | 0:a4d8f5b3c546 | 337 | * Fall, Motion threshold, and Zero Motion). The high pass filter output is not |
lixianyu | 0:a4d8f5b3c546 | 338 | * available to the data registers (see Figure in Section 8 of the MPU-6000/ |
lixianyu | 0:a4d8f5b3c546 | 339 | * MPU-6050 Product Specification document). |
lixianyu | 0:a4d8f5b3c546 | 340 | * |
lixianyu | 0:a4d8f5b3c546 | 341 | * The high pass filter has three modes: |
lixianyu | 0:a4d8f5b3c546 | 342 | * |
lixianyu | 0:a4d8f5b3c546 | 343 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 344 | * Reset: The filter output settles to zero within one sample. This |
lixianyu | 0:a4d8f5b3c546 | 345 | * effectively disables the high pass filter. This mode may be toggled |
lixianyu | 0:a4d8f5b3c546 | 346 | * to quickly settle the filter. |
lixianyu | 0:a4d8f5b3c546 | 347 | * |
lixianyu | 0:a4d8f5b3c546 | 348 | * On: The high pass filter will pass signals above the cut off frequency. |
lixianyu | 0:a4d8f5b3c546 | 349 | * |
lixianyu | 0:a4d8f5b3c546 | 350 | * Hold: When triggered, the filter holds the present sample. The filter |
lixianyu | 0:a4d8f5b3c546 | 351 | * output will be the difference between the input sample and the held |
lixianyu | 0:a4d8f5b3c546 | 352 | * sample. |
lixianyu | 0:a4d8f5b3c546 | 353 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 354 | * |
lixianyu | 0:a4d8f5b3c546 | 355 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 356 | * ACCEL_HPF | Filter Mode | Cut-off Frequency |
lixianyu | 0:a4d8f5b3c546 | 357 | * ----------+-------------+------------------ |
lixianyu | 0:a4d8f5b3c546 | 358 | * 0 | Reset | None |
lixianyu | 0:a4d8f5b3c546 | 359 | * 1 | On | 5Hz |
lixianyu | 0:a4d8f5b3c546 | 360 | * 2 | On | 2.5Hz |
lixianyu | 0:a4d8f5b3c546 | 361 | * 3 | On | 1.25Hz |
lixianyu | 0:a4d8f5b3c546 | 362 | * 4 | On | 0.63Hz |
lixianyu | 0:a4d8f5b3c546 | 363 | * 7 | Hold | None |
lixianyu | 0:a4d8f5b3c546 | 364 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 365 | * |
lixianyu | 0:a4d8f5b3c546 | 366 | * @return Current high-pass filter configuration |
lixianyu | 0:a4d8f5b3c546 | 367 | * @see MPU6050_DHPF_RESET |
lixianyu | 0:a4d8f5b3c546 | 368 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 369 | */ |
lixianyu | 0:a4d8f5b3c546 | 370 | uint8_t MPU6050::getDHPFMode() { |
lixianyu | 0:a4d8f5b3c546 | 371 | I2Cdev::readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 372 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 373 | } |
lixianyu | 0:a4d8f5b3c546 | 374 | /** Set the high-pass filter configuration. |
lixianyu | 0:a4d8f5b3c546 | 375 | * @param bandwidth New high-pass filter configuration |
lixianyu | 0:a4d8f5b3c546 | 376 | * @see setDHPFMode() |
lixianyu | 0:a4d8f5b3c546 | 377 | * @see MPU6050_DHPF_RESET |
lixianyu | 0:a4d8f5b3c546 | 378 | * @see MPU6050_RA_ACCEL_CONFIG |
lixianyu | 0:a4d8f5b3c546 | 379 | */ |
lixianyu | 0:a4d8f5b3c546 | 380 | void MPU6050::setDHPFMode(uint8_t bandwidth) { |
lixianyu | 0:a4d8f5b3c546 | 381 | I2Cdev::writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH, bandwidth); |
lixianyu | 0:a4d8f5b3c546 | 382 | } |
lixianyu | 0:a4d8f5b3c546 | 383 | |
lixianyu | 0:a4d8f5b3c546 | 384 | // FF_THR register |
lixianyu | 0:a4d8f5b3c546 | 385 | |
lixianyu | 0:a4d8f5b3c546 | 386 | /** Get free-fall event acceleration threshold. |
lixianyu | 0:a4d8f5b3c546 | 387 | * This register configures the detection threshold for Free Fall event |
lixianyu | 0:a4d8f5b3c546 | 388 | * detection. The unit of FF_THR is 1LSB = 2mg. Free Fall is detected when the |
lixianyu | 0:a4d8f5b3c546 | 389 | * absolute value of the accelerometer measurements for the three axes are each |
lixianyu | 0:a4d8f5b3c546 | 390 | * less than the detection threshold. This condition increments the Free Fall |
lixianyu | 0:a4d8f5b3c546 | 391 | * duration counter (Register 30). The Free Fall interrupt is triggered when the |
lixianyu | 0:a4d8f5b3c546 | 392 | * Free Fall duration counter reaches the time specified in FF_DUR. |
lixianyu | 0:a4d8f5b3c546 | 393 | * |
lixianyu | 0:a4d8f5b3c546 | 394 | * For more details on the Free Fall detection interrupt, see Section 8.2 of the |
lixianyu | 0:a4d8f5b3c546 | 395 | * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and |
lixianyu | 0:a4d8f5b3c546 | 396 | * 58 of this document. |
lixianyu | 0:a4d8f5b3c546 | 397 | * |
lixianyu | 0:a4d8f5b3c546 | 398 | * @return Current free-fall acceleration threshold value (LSB = 2mg) |
lixianyu | 0:a4d8f5b3c546 | 399 | * @see MPU6050_RA_FF_THR |
lixianyu | 0:a4d8f5b3c546 | 400 | */ |
lixianyu | 0:a4d8f5b3c546 | 401 | uint8_t MPU6050::getFreefallDetectionThreshold() { |
lixianyu | 0:a4d8f5b3c546 | 402 | I2Cdev::readByte(devAddr, MPU6050_RA_FF_THR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 403 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 404 | } |
lixianyu | 0:a4d8f5b3c546 | 405 | /** Get free-fall event acceleration threshold. |
lixianyu | 0:a4d8f5b3c546 | 406 | * @param threshold New free-fall acceleration threshold value (LSB = 2mg) |
lixianyu | 0:a4d8f5b3c546 | 407 | * @see getFreefallDetectionThreshold() |
lixianyu | 0:a4d8f5b3c546 | 408 | * @see MPU6050_RA_FF_THR |
lixianyu | 0:a4d8f5b3c546 | 409 | */ |
lixianyu | 0:a4d8f5b3c546 | 410 | void MPU6050::setFreefallDetectionThreshold(uint8_t threshold) { |
lixianyu | 0:a4d8f5b3c546 | 411 | I2Cdev::writeByte(devAddr, MPU6050_RA_FF_THR, threshold); |
lixianyu | 0:a4d8f5b3c546 | 412 | } |
lixianyu | 0:a4d8f5b3c546 | 413 | |
lixianyu | 0:a4d8f5b3c546 | 414 | // FF_DUR register |
lixianyu | 0:a4d8f5b3c546 | 415 | |
lixianyu | 0:a4d8f5b3c546 | 416 | /** Get free-fall event duration threshold. |
lixianyu | 0:a4d8f5b3c546 | 417 | * This register configures the duration counter threshold for Free Fall event |
lixianyu | 0:a4d8f5b3c546 | 418 | * detection. The duration counter ticks at 1kHz, therefore FF_DUR has a unit |
lixianyu | 0:a4d8f5b3c546 | 419 | * of 1 LSB = 1 ms. |
lixianyu | 0:a4d8f5b3c546 | 420 | * |
lixianyu | 0:a4d8f5b3c546 | 421 | * The Free Fall duration counter increments while the absolute value of the |
lixianyu | 0:a4d8f5b3c546 | 422 | * accelerometer measurements are each less than the detection threshold |
lixianyu | 0:a4d8f5b3c546 | 423 | * (Register 29). The Free Fall interrupt is triggered when the Free Fall |
lixianyu | 0:a4d8f5b3c546 | 424 | * duration counter reaches the time specified in this register. |
lixianyu | 0:a4d8f5b3c546 | 425 | * |
lixianyu | 0:a4d8f5b3c546 | 426 | * For more details on the Free Fall detection interrupt, see Section 8.2 of |
lixianyu | 0:a4d8f5b3c546 | 427 | * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 |
lixianyu | 0:a4d8f5b3c546 | 428 | * and 58 of this document. |
lixianyu | 0:a4d8f5b3c546 | 429 | * |
lixianyu | 0:a4d8f5b3c546 | 430 | * @return Current free-fall duration threshold value (LSB = 1ms) |
lixianyu | 0:a4d8f5b3c546 | 431 | * @see MPU6050_RA_FF_DUR |
lixianyu | 0:a4d8f5b3c546 | 432 | */ |
lixianyu | 0:a4d8f5b3c546 | 433 | uint8_t MPU6050::getFreefallDetectionDuration() { |
lixianyu | 0:a4d8f5b3c546 | 434 | I2Cdev::readByte(devAddr, MPU6050_RA_FF_DUR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 435 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 436 | } |
lixianyu | 0:a4d8f5b3c546 | 437 | /** Get free-fall event duration threshold. |
lixianyu | 0:a4d8f5b3c546 | 438 | * @param duration New free-fall duration threshold value (LSB = 1ms) |
lixianyu | 0:a4d8f5b3c546 | 439 | * @see getFreefallDetectionDuration() |
lixianyu | 0:a4d8f5b3c546 | 440 | * @see MPU6050_RA_FF_DUR |
lixianyu | 0:a4d8f5b3c546 | 441 | */ |
lixianyu | 0:a4d8f5b3c546 | 442 | void MPU6050::setFreefallDetectionDuration(uint8_t duration) { |
lixianyu | 0:a4d8f5b3c546 | 443 | I2Cdev::writeByte(devAddr, MPU6050_RA_FF_DUR, duration); |
lixianyu | 0:a4d8f5b3c546 | 444 | } |
lixianyu | 0:a4d8f5b3c546 | 445 | |
lixianyu | 0:a4d8f5b3c546 | 446 | // MOT_THR register |
lixianyu | 0:a4d8f5b3c546 | 447 | |
lixianyu | 0:a4d8f5b3c546 | 448 | /** Get motion detection event acceleration threshold. |
lixianyu | 0:a4d8f5b3c546 | 449 | * This register configures the detection threshold for Motion interrupt |
lixianyu | 0:a4d8f5b3c546 | 450 | * generation. The unit of MOT_THR is 1LSB = 2mg. Motion is detected when the |
lixianyu | 0:a4d8f5b3c546 | 451 | * absolute value of any of the accelerometer measurements exceeds this Motion |
lixianyu | 0:a4d8f5b3c546 | 452 | * detection threshold. This condition increments the Motion detection duration |
lixianyu | 0:a4d8f5b3c546 | 453 | * counter (Register 32). The Motion detection interrupt is triggered when the |
lixianyu | 0:a4d8f5b3c546 | 454 | * Motion Detection counter reaches the time count specified in MOT_DUR |
lixianyu | 0:a4d8f5b3c546 | 455 | * (Register 32). |
lixianyu | 0:a4d8f5b3c546 | 456 | * |
lixianyu | 0:a4d8f5b3c546 | 457 | * The Motion interrupt will indicate the axis and polarity of detected motion |
lixianyu | 0:a4d8f5b3c546 | 458 | * in MOT_DETECT_STATUS (Register 97). |
lixianyu | 0:a4d8f5b3c546 | 459 | * |
lixianyu | 0:a4d8f5b3c546 | 460 | * For more details on the Motion detection interrupt, see Section 8.3 of the |
lixianyu | 0:a4d8f5b3c546 | 461 | * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and |
lixianyu | 0:a4d8f5b3c546 | 462 | * 58 of this document. |
lixianyu | 0:a4d8f5b3c546 | 463 | * |
lixianyu | 0:a4d8f5b3c546 | 464 | * @return Current motion detection acceleration threshold value (LSB = 2mg) |
lixianyu | 0:a4d8f5b3c546 | 465 | * @see MPU6050_RA_MOT_THR |
lixianyu | 0:a4d8f5b3c546 | 466 | */ |
lixianyu | 0:a4d8f5b3c546 | 467 | uint8_t MPU6050::getMotionDetectionThreshold() { |
lixianyu | 0:a4d8f5b3c546 | 468 | I2Cdev::readByte(devAddr, MPU6050_RA_MOT_THR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 469 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 470 | } |
lixianyu | 0:a4d8f5b3c546 | 471 | /** Set free-fall event acceleration threshold. |
lixianyu | 0:a4d8f5b3c546 | 472 | * @param threshold New motion detection acceleration threshold value (LSB = 2mg) |
lixianyu | 0:a4d8f5b3c546 | 473 | * @see getMotionDetectionThreshold() |
lixianyu | 0:a4d8f5b3c546 | 474 | * @see MPU6050_RA_MOT_THR |
lixianyu | 0:a4d8f5b3c546 | 475 | */ |
lixianyu | 0:a4d8f5b3c546 | 476 | void MPU6050::setMotionDetectionThreshold(uint8_t threshold) { |
lixianyu | 0:a4d8f5b3c546 | 477 | I2Cdev::writeByte(devAddr, MPU6050_RA_MOT_THR, threshold); |
lixianyu | 0:a4d8f5b3c546 | 478 | } |
lixianyu | 0:a4d8f5b3c546 | 479 | |
lixianyu | 0:a4d8f5b3c546 | 480 | // MOT_DUR register |
lixianyu | 0:a4d8f5b3c546 | 481 | |
lixianyu | 0:a4d8f5b3c546 | 482 | /** Get motion detection event duration threshold. |
lixianyu | 0:a4d8f5b3c546 | 483 | * This register configures the duration counter threshold for Motion interrupt |
lixianyu | 0:a4d8f5b3c546 | 484 | * generation. The duration counter ticks at 1 kHz, therefore MOT_DUR has a unit |
lixianyu | 0:a4d8f5b3c546 | 485 | * of 1LSB = 1ms. The Motion detection duration counter increments when the |
lixianyu | 0:a4d8f5b3c546 | 486 | * absolute value of any of the accelerometer measurements exceeds the Motion |
lixianyu | 0:a4d8f5b3c546 | 487 | * detection threshold (Register 31). The Motion detection interrupt is |
lixianyu | 0:a4d8f5b3c546 | 488 | * triggered when the Motion detection counter reaches the time count specified |
lixianyu | 0:a4d8f5b3c546 | 489 | * in this register. |
lixianyu | 0:a4d8f5b3c546 | 490 | * |
lixianyu | 0:a4d8f5b3c546 | 491 | * For more details on the Motion detection interrupt, see Section 8.3 of the |
lixianyu | 0:a4d8f5b3c546 | 492 | * MPU-6000/MPU-6050 Product Specification document. |
lixianyu | 0:a4d8f5b3c546 | 493 | * |
lixianyu | 0:a4d8f5b3c546 | 494 | * @return Current motion detection duration threshold value (LSB = 1ms) |
lixianyu | 0:a4d8f5b3c546 | 495 | * @see MPU6050_RA_MOT_DUR |
lixianyu | 0:a4d8f5b3c546 | 496 | */ |
lixianyu | 0:a4d8f5b3c546 | 497 | uint8_t MPU6050::getMotionDetectionDuration() { |
lixianyu | 0:a4d8f5b3c546 | 498 | I2Cdev::readByte(devAddr, MPU6050_RA_MOT_DUR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 499 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 500 | } |
lixianyu | 0:a4d8f5b3c546 | 501 | /** Set motion detection event duration threshold. |
lixianyu | 0:a4d8f5b3c546 | 502 | * @param duration New motion detection duration threshold value (LSB = 1ms) |
lixianyu | 0:a4d8f5b3c546 | 503 | * @see getMotionDetectionDuration() |
lixianyu | 0:a4d8f5b3c546 | 504 | * @see MPU6050_RA_MOT_DUR |
lixianyu | 0:a4d8f5b3c546 | 505 | */ |
lixianyu | 0:a4d8f5b3c546 | 506 | void MPU6050::setMotionDetectionDuration(uint8_t duration) { |
lixianyu | 0:a4d8f5b3c546 | 507 | I2Cdev::writeByte(devAddr, MPU6050_RA_MOT_DUR, duration); |
lixianyu | 0:a4d8f5b3c546 | 508 | } |
lixianyu | 0:a4d8f5b3c546 | 509 | |
lixianyu | 0:a4d8f5b3c546 | 510 | // ZRMOT_THR register |
lixianyu | 0:a4d8f5b3c546 | 511 | |
lixianyu | 0:a4d8f5b3c546 | 512 | /** Get zero motion detection event acceleration threshold. |
lixianyu | 0:a4d8f5b3c546 | 513 | * This register configures the detection threshold for Zero Motion interrupt |
lixianyu | 0:a4d8f5b3c546 | 514 | * generation. The unit of ZRMOT_THR is 1LSB = 2mg. Zero Motion is detected when |
lixianyu | 0:a4d8f5b3c546 | 515 | * the absolute value of the accelerometer measurements for the 3 axes are each |
lixianyu | 0:a4d8f5b3c546 | 516 | * less than the detection threshold. This condition increments the Zero Motion |
lixianyu | 0:a4d8f5b3c546 | 517 | * duration counter (Register 34). The Zero Motion interrupt is triggered when |
lixianyu | 0:a4d8f5b3c546 | 518 | * the Zero Motion duration counter reaches the time count specified in |
lixianyu | 0:a4d8f5b3c546 | 519 | * ZRMOT_DUR (Register 34). |
lixianyu | 0:a4d8f5b3c546 | 520 | * |
lixianyu | 0:a4d8f5b3c546 | 521 | * Unlike Free Fall or Motion detection, Zero Motion detection triggers an |
lixianyu | 0:a4d8f5b3c546 | 522 | * interrupt both when Zero Motion is first detected and when Zero Motion is no |
lixianyu | 0:a4d8f5b3c546 | 523 | * longer detected. |
lixianyu | 0:a4d8f5b3c546 | 524 | * |
lixianyu | 0:a4d8f5b3c546 | 525 | * When a zero motion event is detected, a Zero Motion Status will be indicated |
lixianyu | 0:a4d8f5b3c546 | 526 | * in the MOT_DETECT_STATUS register (Register 97). When a motion-to-zero-motion |
lixianyu | 0:a4d8f5b3c546 | 527 | * condition is detected, the status bit is set to 1. When a zero-motion-to- |
lixianyu | 0:a4d8f5b3c546 | 528 | * motion condition is detected, the status bit is set to 0. |
lixianyu | 0:a4d8f5b3c546 | 529 | * |
lixianyu | 0:a4d8f5b3c546 | 530 | * For more details on the Zero Motion detection interrupt, see Section 8.4 of |
lixianyu | 0:a4d8f5b3c546 | 531 | * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 |
lixianyu | 0:a4d8f5b3c546 | 532 | * and 58 of this document. |
lixianyu | 0:a4d8f5b3c546 | 533 | * |
lixianyu | 0:a4d8f5b3c546 | 534 | * @return Current zero motion detection acceleration threshold value (LSB = 2mg) |
lixianyu | 0:a4d8f5b3c546 | 535 | * @see MPU6050_RA_ZRMOT_THR |
lixianyu | 0:a4d8f5b3c546 | 536 | */ |
lixianyu | 0:a4d8f5b3c546 | 537 | uint8_t MPU6050::getZeroMotionDetectionThreshold() { |
lixianyu | 0:a4d8f5b3c546 | 538 | I2Cdev::readByte(devAddr, MPU6050_RA_ZRMOT_THR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 539 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 540 | } |
lixianyu | 0:a4d8f5b3c546 | 541 | /** Set zero motion detection event acceleration threshold. |
lixianyu | 0:a4d8f5b3c546 | 542 | * @param threshold New zero motion detection acceleration threshold value (LSB = 2mg) |
lixianyu | 0:a4d8f5b3c546 | 543 | * @see getZeroMotionDetectionThreshold() |
lixianyu | 0:a4d8f5b3c546 | 544 | * @see MPU6050_RA_ZRMOT_THR |
lixianyu | 0:a4d8f5b3c546 | 545 | */ |
lixianyu | 0:a4d8f5b3c546 | 546 | void MPU6050::setZeroMotionDetectionThreshold(uint8_t threshold) { |
lixianyu | 0:a4d8f5b3c546 | 547 | I2Cdev::writeByte(devAddr, MPU6050_RA_ZRMOT_THR, threshold); |
lixianyu | 0:a4d8f5b3c546 | 548 | } |
lixianyu | 0:a4d8f5b3c546 | 549 | |
lixianyu | 0:a4d8f5b3c546 | 550 | // ZRMOT_DUR register |
lixianyu | 0:a4d8f5b3c546 | 551 | |
lixianyu | 0:a4d8f5b3c546 | 552 | /** Get zero motion detection event duration threshold. |
lixianyu | 0:a4d8f5b3c546 | 553 | * This register configures the duration counter threshold for Zero Motion |
lixianyu | 0:a4d8f5b3c546 | 554 | * interrupt generation. The duration counter ticks at 16 Hz, therefore |
lixianyu | 0:a4d8f5b3c546 | 555 | * ZRMOT_DUR has a unit of 1 LSB = 64 ms. The Zero Motion duration counter |
lixianyu | 0:a4d8f5b3c546 | 556 | * increments while the absolute value of the accelerometer measurements are |
lixianyu | 0:a4d8f5b3c546 | 557 | * each less than the detection threshold (Register 33). The Zero Motion |
lixianyu | 0:a4d8f5b3c546 | 558 | * interrupt is triggered when the Zero Motion duration counter reaches the time |
lixianyu | 0:a4d8f5b3c546 | 559 | * count specified in this register. |
lixianyu | 0:a4d8f5b3c546 | 560 | * |
lixianyu | 0:a4d8f5b3c546 | 561 | * For more details on the Zero Motion detection interrupt, see Section 8.4 of |
lixianyu | 0:a4d8f5b3c546 | 562 | * the MPU-6000/MPU-6050 Product Specification document, as well as Registers 56 |
lixianyu | 0:a4d8f5b3c546 | 563 | * and 58 of this document. |
lixianyu | 0:a4d8f5b3c546 | 564 | * |
lixianyu | 0:a4d8f5b3c546 | 565 | * @return Current zero motion detection duration threshold value (LSB = 64ms) |
lixianyu | 0:a4d8f5b3c546 | 566 | * @see MPU6050_RA_ZRMOT_DUR |
lixianyu | 0:a4d8f5b3c546 | 567 | */ |
lixianyu | 0:a4d8f5b3c546 | 568 | uint8_t MPU6050::getZeroMotionDetectionDuration() { |
lixianyu | 0:a4d8f5b3c546 | 569 | I2Cdev::readByte(devAddr, MPU6050_RA_ZRMOT_DUR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 570 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 571 | } |
lixianyu | 0:a4d8f5b3c546 | 572 | /** Set zero motion detection event duration threshold. |
lixianyu | 0:a4d8f5b3c546 | 573 | * @param duration New zero motion detection duration threshold value (LSB = 1ms) |
lixianyu | 0:a4d8f5b3c546 | 574 | * @see getZeroMotionDetectionDuration() |
lixianyu | 0:a4d8f5b3c546 | 575 | * @see MPU6050_RA_ZRMOT_DUR |
lixianyu | 0:a4d8f5b3c546 | 576 | */ |
lixianyu | 0:a4d8f5b3c546 | 577 | void MPU6050::setZeroMotionDetectionDuration(uint8_t duration) { |
lixianyu | 0:a4d8f5b3c546 | 578 | I2Cdev::writeByte(devAddr, MPU6050_RA_ZRMOT_DUR, duration); |
lixianyu | 0:a4d8f5b3c546 | 579 | } |
lixianyu | 0:a4d8f5b3c546 | 580 | |
lixianyu | 0:a4d8f5b3c546 | 581 | // FIFO_EN register |
lixianyu | 0:a4d8f5b3c546 | 582 | |
lixianyu | 0:a4d8f5b3c546 | 583 | /** Get temperature FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 584 | * When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers 65 and |
lixianyu | 0:a4d8f5b3c546 | 585 | * 66) to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 586 | * @return Current temperature FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 587 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 588 | */ |
lixianyu | 0:a4d8f5b3c546 | 589 | bool MPU6050::getTempFIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 590 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 591 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 592 | } |
lixianyu | 0:a4d8f5b3c546 | 593 | /** Set temperature FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 594 | * @param enabled New temperature FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 595 | * @see getTempFIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 596 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 597 | */ |
lixianyu | 0:a4d8f5b3c546 | 598 | void MPU6050::setTempFIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 599 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 600 | } |
lixianyu | 0:a4d8f5b3c546 | 601 | /** Get gyroscope X-axis FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 602 | * When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L (Registers 67 and |
lixianyu | 0:a4d8f5b3c546 | 603 | * 68) to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 604 | * @return Current gyroscope X-axis FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 605 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 606 | */ |
lixianyu | 0:a4d8f5b3c546 | 607 | bool MPU6050::getXGyroFIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 608 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 609 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 610 | } |
lixianyu | 0:a4d8f5b3c546 | 611 | /** Set gyroscope X-axis FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 612 | * @param enabled New gyroscope X-axis FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 613 | * @see getXGyroFIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 614 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 615 | */ |
lixianyu | 0:a4d8f5b3c546 | 616 | void MPU6050::setXGyroFIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 617 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 618 | } |
lixianyu | 0:a4d8f5b3c546 | 619 | /** Get gyroscope Y-axis FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 620 | * When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L (Registers 69 and |
lixianyu | 0:a4d8f5b3c546 | 621 | * 70) to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 622 | * @return Current gyroscope Y-axis FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 623 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 624 | */ |
lixianyu | 0:a4d8f5b3c546 | 625 | bool MPU6050::getYGyroFIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 626 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 627 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 628 | } |
lixianyu | 0:a4d8f5b3c546 | 629 | /** Set gyroscope Y-axis FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 630 | * @param enabled New gyroscope Y-axis FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 631 | * @see getYGyroFIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 632 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 633 | */ |
lixianyu | 0:a4d8f5b3c546 | 634 | void MPU6050::setYGyroFIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 635 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 636 | } |
lixianyu | 0:a4d8f5b3c546 | 637 | /** Get gyroscope Z-axis FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 638 | * When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L (Registers 71 and |
lixianyu | 0:a4d8f5b3c546 | 639 | * 72) to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 640 | * @return Current gyroscope Z-axis FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 641 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 642 | */ |
lixianyu | 0:a4d8f5b3c546 | 643 | bool MPU6050::getZGyroFIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 644 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 645 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 646 | } |
lixianyu | 0:a4d8f5b3c546 | 647 | /** Set gyroscope Z-axis FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 648 | * @param enabled New gyroscope Z-axis FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 649 | * @see getZGyroFIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 650 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 651 | */ |
lixianyu | 0:a4d8f5b3c546 | 652 | void MPU6050::setZGyroFIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 653 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 654 | } |
lixianyu | 0:a4d8f5b3c546 | 655 | /** Get accelerometer FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 656 | * When set to 1, this bit enables ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, |
lixianyu | 0:a4d8f5b3c546 | 657 | * ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L (Registers 59 to 64) to be |
lixianyu | 0:a4d8f5b3c546 | 658 | * written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 659 | * @return Current accelerometer FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 660 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 661 | */ |
lixianyu | 0:a4d8f5b3c546 | 662 | bool MPU6050::getAccelFIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 663 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 664 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 665 | } |
lixianyu | 0:a4d8f5b3c546 | 666 | /** Set accelerometer FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 667 | * @param enabled New accelerometer FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 668 | * @see getAccelFIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 669 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 670 | */ |
lixianyu | 0:a4d8f5b3c546 | 671 | void MPU6050::setAccelFIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 672 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 673 | } |
lixianyu | 0:a4d8f5b3c546 | 674 | /** Get Slave 2 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 675 | * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) |
lixianyu | 0:a4d8f5b3c546 | 676 | * associated with Slave 2 to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 677 | * @return Current Slave 2 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 678 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 679 | */ |
lixianyu | 0:a4d8f5b3c546 | 680 | bool MPU6050::getSlave2FIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 681 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 682 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 683 | } |
lixianyu | 0:a4d8f5b3c546 | 684 | /** Set Slave 2 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 685 | * @param enabled New Slave 2 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 686 | * @see getSlave2FIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 687 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 688 | */ |
lixianyu | 0:a4d8f5b3c546 | 689 | void MPU6050::setSlave2FIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 690 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 691 | } |
lixianyu | 0:a4d8f5b3c546 | 692 | /** Get Slave 1 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 693 | * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) |
lixianyu | 0:a4d8f5b3c546 | 694 | * associated with Slave 1 to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 695 | * @return Current Slave 1 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 696 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 697 | */ |
lixianyu | 0:a4d8f5b3c546 | 698 | bool MPU6050::getSlave1FIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 699 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 700 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 701 | } |
lixianyu | 0:a4d8f5b3c546 | 702 | /** Set Slave 1 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 703 | * @param enabled New Slave 1 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 704 | * @see getSlave1FIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 705 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 706 | */ |
lixianyu | 0:a4d8f5b3c546 | 707 | void MPU6050::setSlave1FIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 708 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 709 | } |
lixianyu | 0:a4d8f5b3c546 | 710 | /** Get Slave 0 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 711 | * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) |
lixianyu | 0:a4d8f5b3c546 | 712 | * associated with Slave 0 to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 713 | * @return Current Slave 0 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 714 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 715 | */ |
lixianyu | 0:a4d8f5b3c546 | 716 | bool MPU6050::getSlave0FIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 717 | I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 718 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 719 | } |
lixianyu | 0:a4d8f5b3c546 | 720 | /** Set Slave 0 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 721 | * @param enabled New Slave 0 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 722 | * @see getSlave0FIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 723 | * @see MPU6050_RA_FIFO_EN |
lixianyu | 0:a4d8f5b3c546 | 724 | */ |
lixianyu | 0:a4d8f5b3c546 | 725 | void MPU6050::setSlave0FIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 726 | I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 727 | } |
lixianyu | 0:a4d8f5b3c546 | 728 | |
lixianyu | 0:a4d8f5b3c546 | 729 | // I2C_MST_CTRL register |
lixianyu | 0:a4d8f5b3c546 | 730 | |
lixianyu | 0:a4d8f5b3c546 | 731 | /** Get multi-master enabled value. |
lixianyu | 0:a4d8f5b3c546 | 732 | * Multi-master capability allows multiple I2C masters to operate on the same |
lixianyu | 0:a4d8f5b3c546 | 733 | * bus. In circuits where multi-master capability is required, set MULT_MST_EN |
lixianyu | 0:a4d8f5b3c546 | 734 | * to 1. This will increase current drawn by approximately 30uA. |
lixianyu | 0:a4d8f5b3c546 | 735 | * |
lixianyu | 0:a4d8f5b3c546 | 736 | * In circuits where multi-master capability is required, the state of the I2C |
lixianyu | 0:a4d8f5b3c546 | 737 | * bus must always be monitored by each separate I2C Master. Before an I2C |
lixianyu | 0:a4d8f5b3c546 | 738 | * Master can assume arbitration of the bus, it must first confirm that no other |
lixianyu | 0:a4d8f5b3c546 | 739 | * I2C Master has arbitration of the bus. When MULT_MST_EN is set to 1, the |
lixianyu | 0:a4d8f5b3c546 | 740 | * MPU-60X0's bus arbitration detection logic is turned on, enabling it to |
lixianyu | 0:a4d8f5b3c546 | 741 | * detect when the bus is available. |
lixianyu | 0:a4d8f5b3c546 | 742 | * |
lixianyu | 0:a4d8f5b3c546 | 743 | * @return Current multi-master enabled value |
lixianyu | 0:a4d8f5b3c546 | 744 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 745 | */ |
lixianyu | 0:a4d8f5b3c546 | 746 | bool MPU6050::getMultiMasterEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 747 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 748 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 749 | } |
lixianyu | 0:a4d8f5b3c546 | 750 | /** Set multi-master enabled value. |
lixianyu | 0:a4d8f5b3c546 | 751 | * @param enabled New multi-master enabled value |
lixianyu | 0:a4d8f5b3c546 | 752 | * @see getMultiMasterEnabled() |
lixianyu | 0:a4d8f5b3c546 | 753 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 754 | */ |
lixianyu | 0:a4d8f5b3c546 | 755 | void MPU6050::setMultiMasterEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 756 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 757 | } |
lixianyu | 0:a4d8f5b3c546 | 758 | /** Get wait-for-external-sensor-data enabled value. |
lixianyu | 0:a4d8f5b3c546 | 759 | * When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be |
lixianyu | 0:a4d8f5b3c546 | 760 | * delayed until External Sensor data from the Slave Devices are loaded into the |
lixianyu | 0:a4d8f5b3c546 | 761 | * EXT_SENS_DATA registers. This is used to ensure that both the internal sensor |
lixianyu | 0:a4d8f5b3c546 | 762 | * data (i.e. from gyro and accel) and external sensor data have been loaded to |
lixianyu | 0:a4d8f5b3c546 | 763 | * their respective data registers (i.e. the data is synced) when the Data Ready |
lixianyu | 0:a4d8f5b3c546 | 764 | * interrupt is triggered. |
lixianyu | 0:a4d8f5b3c546 | 765 | * |
lixianyu | 0:a4d8f5b3c546 | 766 | * @return Current wait-for-external-sensor-data enabled value |
lixianyu | 0:a4d8f5b3c546 | 767 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 768 | */ |
lixianyu | 0:a4d8f5b3c546 | 769 | bool MPU6050::getWaitForExternalSensorEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 770 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 771 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 772 | } |
lixianyu | 0:a4d8f5b3c546 | 773 | /** Set wait-for-external-sensor-data enabled value. |
lixianyu | 0:a4d8f5b3c546 | 774 | * @param enabled New wait-for-external-sensor-data enabled value |
lixianyu | 0:a4d8f5b3c546 | 775 | * @see getWaitForExternalSensorEnabled() |
lixianyu | 0:a4d8f5b3c546 | 776 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 777 | */ |
lixianyu | 0:a4d8f5b3c546 | 778 | void MPU6050::setWaitForExternalSensorEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 779 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 780 | } |
lixianyu | 0:a4d8f5b3c546 | 781 | /** Get Slave 3 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 782 | * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) |
lixianyu | 0:a4d8f5b3c546 | 783 | * associated with Slave 3 to be written into the FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 784 | * @return Current Slave 3 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 785 | * @see MPU6050_RA_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 786 | */ |
lixianyu | 0:a4d8f5b3c546 | 787 | bool MPU6050::getSlave3FIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 788 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 789 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 790 | } |
lixianyu | 0:a4d8f5b3c546 | 791 | /** Set Slave 3 FIFO enabled value. |
lixianyu | 0:a4d8f5b3c546 | 792 | * @param enabled New Slave 3 FIFO enabled value |
lixianyu | 0:a4d8f5b3c546 | 793 | * @see getSlave3FIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 794 | * @see MPU6050_RA_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 795 | */ |
lixianyu | 0:a4d8f5b3c546 | 796 | void MPU6050::setSlave3FIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 797 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 798 | } |
lixianyu | 0:a4d8f5b3c546 | 799 | /** Get slave read/write transition enabled value. |
lixianyu | 0:a4d8f5b3c546 | 800 | * The I2C_MST_P_NSR bit configures the I2C Master's transition from one slave |
lixianyu | 0:a4d8f5b3c546 | 801 | * read to the next slave read. If the bit equals 0, there will be a restart |
lixianyu | 0:a4d8f5b3c546 | 802 | * between reads. If the bit equals 1, there will be a stop followed by a start |
lixianyu | 0:a4d8f5b3c546 | 803 | * of the following read. When a write transaction follows a read transaction, |
lixianyu | 0:a4d8f5b3c546 | 804 | * the stop followed by a start of the successive write will be always used. |
lixianyu | 0:a4d8f5b3c546 | 805 | * |
lixianyu | 0:a4d8f5b3c546 | 806 | * @return Current slave read/write transition enabled value |
lixianyu | 0:a4d8f5b3c546 | 807 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 808 | */ |
lixianyu | 0:a4d8f5b3c546 | 809 | bool MPU6050::getSlaveReadWriteTransitionEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 810 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 811 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 812 | } |
lixianyu | 0:a4d8f5b3c546 | 813 | /** Set slave read/write transition enabled value. |
lixianyu | 0:a4d8f5b3c546 | 814 | * @param enabled New slave read/write transition enabled value |
lixianyu | 0:a4d8f5b3c546 | 815 | * @see getSlaveReadWriteTransitionEnabled() |
lixianyu | 0:a4d8f5b3c546 | 816 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 817 | */ |
lixianyu | 0:a4d8f5b3c546 | 818 | void MPU6050::setSlaveReadWriteTransitionEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 819 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 820 | } |
lixianyu | 0:a4d8f5b3c546 | 821 | /** Get I2C master clock speed. |
lixianyu | 0:a4d8f5b3c546 | 822 | * I2C_MST_CLK is a 4 bit unsigned value which configures a divider on the |
lixianyu | 0:a4d8f5b3c546 | 823 | * MPU-60X0 internal 8MHz clock. It sets the I2C master clock speed according to |
lixianyu | 0:a4d8f5b3c546 | 824 | * the following table: |
lixianyu | 0:a4d8f5b3c546 | 825 | * |
lixianyu | 0:a4d8f5b3c546 | 826 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 827 | * I2C_MST_CLK | I2C Master Clock Speed | 8MHz Clock Divider |
lixianyu | 0:a4d8f5b3c546 | 828 | * ------------+------------------------+------------------- |
lixianyu | 0:a4d8f5b3c546 | 829 | * 0 | 348kHz | 23 |
lixianyu | 0:a4d8f5b3c546 | 830 | * 1 | 333kHz | 24 |
lixianyu | 0:a4d8f5b3c546 | 831 | * 2 | 320kHz | 25 |
lixianyu | 0:a4d8f5b3c546 | 832 | * 3 | 308kHz | 26 |
lixianyu | 0:a4d8f5b3c546 | 833 | * 4 | 296kHz | 27 |
lixianyu | 0:a4d8f5b3c546 | 834 | * 5 | 286kHz | 28 |
lixianyu | 0:a4d8f5b3c546 | 835 | * 6 | 276kHz | 29 |
lixianyu | 0:a4d8f5b3c546 | 836 | * 7 | 267kHz | 30 |
lixianyu | 0:a4d8f5b3c546 | 837 | * 8 | 258kHz | 31 |
lixianyu | 0:a4d8f5b3c546 | 838 | * 9 | 500kHz | 16 |
lixianyu | 0:a4d8f5b3c546 | 839 | * 10 | 471kHz | 17 |
lixianyu | 0:a4d8f5b3c546 | 840 | * 11 | 444kHz | 18 |
lixianyu | 0:a4d8f5b3c546 | 841 | * 12 | 421kHz | 19 |
lixianyu | 0:a4d8f5b3c546 | 842 | * 13 | 400kHz | 20 |
lixianyu | 0:a4d8f5b3c546 | 843 | * 14 | 381kHz | 21 |
lixianyu | 0:a4d8f5b3c546 | 844 | * 15 | 364kHz | 22 |
lixianyu | 0:a4d8f5b3c546 | 845 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 846 | * |
lixianyu | 0:a4d8f5b3c546 | 847 | * @return Current I2C master clock speed |
lixianyu | 0:a4d8f5b3c546 | 848 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 849 | */ |
lixianyu | 0:a4d8f5b3c546 | 850 | uint8_t MPU6050::getMasterClockSpeed() { |
lixianyu | 0:a4d8f5b3c546 | 851 | I2Cdev::readBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 852 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 853 | } |
lixianyu | 0:a4d8f5b3c546 | 854 | /** Set I2C master clock speed. |
lixianyu | 0:a4d8f5b3c546 | 855 | * @reparam speed Current I2C master clock speed |
lixianyu | 0:a4d8f5b3c546 | 856 | * @see MPU6050_RA_I2C_MST_CTRL |
lixianyu | 0:a4d8f5b3c546 | 857 | */ |
lixianyu | 0:a4d8f5b3c546 | 858 | void MPU6050::setMasterClockSpeed(uint8_t speed) { |
lixianyu | 0:a4d8f5b3c546 | 859 | I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, speed); |
lixianyu | 0:a4d8f5b3c546 | 860 | } |
lixianyu | 0:a4d8f5b3c546 | 861 | |
lixianyu | 0:a4d8f5b3c546 | 862 | // I2C_SLV* registers (Slave 0-3) |
lixianyu | 0:a4d8f5b3c546 | 863 | |
lixianyu | 0:a4d8f5b3c546 | 864 | /** Get the I2C address of the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 865 | * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read |
lixianyu | 0:a4d8f5b3c546 | 866 | * operation, and if it is cleared, then it's a write operation. The remaining |
lixianyu | 0:a4d8f5b3c546 | 867 | * bits (6-0) are the 7-bit device address of the slave device. |
lixianyu | 0:a4d8f5b3c546 | 868 | * |
lixianyu | 0:a4d8f5b3c546 | 869 | * In read mode, the result of the read is placed in the lowest available |
lixianyu | 0:a4d8f5b3c546 | 870 | * EXT_SENS_DATA register. For further information regarding the allocation of |
lixianyu | 0:a4d8f5b3c546 | 871 | * read results, please refer to the EXT_SENS_DATA register description |
lixianyu | 0:a4d8f5b3c546 | 872 | * (Registers 73 - 96). |
lixianyu | 0:a4d8f5b3c546 | 873 | * |
lixianyu | 0:a4d8f5b3c546 | 874 | * The MPU-6050 supports a total of five slaves, but Slave 4 has unique |
lixianyu | 0:a4d8f5b3c546 | 875 | * characteristics, and so it has its own functions (getSlave4* and setSlave4*). |
lixianyu | 0:a4d8f5b3c546 | 876 | * |
lixianyu | 0:a4d8f5b3c546 | 877 | * I2C data transactions are performed at the Sample Rate, as defined in |
lixianyu | 0:a4d8f5b3c546 | 878 | * Register 25. The user is responsible for ensuring that I2C data transactions |
lixianyu | 0:a4d8f5b3c546 | 879 | * to and from each enabled Slave can be completed within a single period of the |
lixianyu | 0:a4d8f5b3c546 | 880 | * Sample Rate. |
lixianyu | 0:a4d8f5b3c546 | 881 | * |
lixianyu | 0:a4d8f5b3c546 | 882 | * The I2C slave access rate can be reduced relative to the Sample Rate. This |
lixianyu | 0:a4d8f5b3c546 | 883 | * reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a |
lixianyu | 0:a4d8f5b3c546 | 884 | * slave's access rate is reduced relative to the Sample Rate is determined by |
lixianyu | 0:a4d8f5b3c546 | 885 | * I2C_MST_DELAY_CTRL (Register 103). |
lixianyu | 0:a4d8f5b3c546 | 886 | * |
lixianyu | 0:a4d8f5b3c546 | 887 | * The processing order for the slaves is fixed. The sequence followed for |
lixianyu | 0:a4d8f5b3c546 | 888 | * processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a |
lixianyu | 0:a4d8f5b3c546 | 889 | * particular Slave is disabled it will be skipped. |
lixianyu | 0:a4d8f5b3c546 | 890 | * |
lixianyu | 0:a4d8f5b3c546 | 891 | * Each slave can either be accessed at the sample rate or at a reduced sample |
lixianyu | 0:a4d8f5b3c546 | 892 | * rate. In a case where some slaves are accessed at the Sample Rate and some |
lixianyu | 0:a4d8f5b3c546 | 893 | * slaves are accessed at the reduced rate, the sequence of accessing the slaves |
lixianyu | 0:a4d8f5b3c546 | 894 | * (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will |
lixianyu | 0:a4d8f5b3c546 | 895 | * be skipped if their access rate dictates that they should not be accessed |
lixianyu | 0:a4d8f5b3c546 | 896 | * during that particular cycle. For further information regarding the reduced |
lixianyu | 0:a4d8f5b3c546 | 897 | * access rate, please refer to Register 52. Whether a slave is accessed at the |
lixianyu | 0:a4d8f5b3c546 | 898 | * Sample Rate or at the reduced rate is determined by the Delay Enable bits in |
lixianyu | 0:a4d8f5b3c546 | 899 | * Register 103. |
lixianyu | 0:a4d8f5b3c546 | 900 | * |
lixianyu | 0:a4d8f5b3c546 | 901 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 902 | * @return Current address for specified slave |
lixianyu | 0:a4d8f5b3c546 | 903 | * @see MPU6050_RA_I2C_SLV0_ADDR |
lixianyu | 0:a4d8f5b3c546 | 904 | */ |
lixianyu | 0:a4d8f5b3c546 | 905 | uint8_t MPU6050::getSlaveAddress(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 906 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 907 | I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num*3, buffer); |
lixianyu | 0:a4d8f5b3c546 | 908 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 909 | } |
lixianyu | 0:a4d8f5b3c546 | 910 | /** Set the I2C address of the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 911 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 912 | * @param address New address for specified slave |
lixianyu | 0:a4d8f5b3c546 | 913 | * @see getSlaveAddress() |
lixianyu | 0:a4d8f5b3c546 | 914 | * @see MPU6050_RA_I2C_SLV0_ADDR |
lixianyu | 0:a4d8f5b3c546 | 915 | */ |
lixianyu | 0:a4d8f5b3c546 | 916 | void MPU6050::setSlaveAddress(uint8_t num, uint8_t address) { |
lixianyu | 0:a4d8f5b3c546 | 917 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 918 | I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num*3, address); |
lixianyu | 0:a4d8f5b3c546 | 919 | } |
lixianyu | 0:a4d8f5b3c546 | 920 | /** Get the active internal register for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 921 | * Read/write operations for this slave will be done to whatever internal |
lixianyu | 0:a4d8f5b3c546 | 922 | * register address is stored in this MPU register. |
lixianyu | 0:a4d8f5b3c546 | 923 | * |
lixianyu | 0:a4d8f5b3c546 | 924 | * The MPU-6050 supports a total of five slaves, but Slave 4 has unique |
lixianyu | 0:a4d8f5b3c546 | 925 | * characteristics, and so it has its own functions. |
lixianyu | 0:a4d8f5b3c546 | 926 | * |
lixianyu | 0:a4d8f5b3c546 | 927 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 928 | * @return Current active register for specified slave |
lixianyu | 0:a4d8f5b3c546 | 929 | * @see MPU6050_RA_I2C_SLV0_REG |
lixianyu | 0:a4d8f5b3c546 | 930 | */ |
lixianyu | 0:a4d8f5b3c546 | 931 | uint8_t MPU6050::getSlaveRegister(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 932 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 933 | I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num*3, buffer); |
lixianyu | 0:a4d8f5b3c546 | 934 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 935 | } |
lixianyu | 0:a4d8f5b3c546 | 936 | /** Set the active internal register for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 937 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 938 | * @param reg New active register for specified slave |
lixianyu | 0:a4d8f5b3c546 | 939 | * @see getSlaveRegister() |
lixianyu | 0:a4d8f5b3c546 | 940 | * @see MPU6050_RA_I2C_SLV0_REG |
lixianyu | 0:a4d8f5b3c546 | 941 | */ |
lixianyu | 0:a4d8f5b3c546 | 942 | void MPU6050::setSlaveRegister(uint8_t num, uint8_t reg) { |
lixianyu | 0:a4d8f5b3c546 | 943 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 944 | I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num*3, reg); |
lixianyu | 0:a4d8f5b3c546 | 945 | } |
lixianyu | 0:a4d8f5b3c546 | 946 | /** Get the enabled value for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 947 | * When set to 1, this bit enables Slave 0 for data transfer operations. When |
lixianyu | 0:a4d8f5b3c546 | 948 | * cleared to 0, this bit disables Slave 0 from data transfer operations. |
lixianyu | 0:a4d8f5b3c546 | 949 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 950 | * @return Current enabled value for specified slave |
lixianyu | 0:a4d8f5b3c546 | 951 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 952 | */ |
lixianyu | 0:a4d8f5b3c546 | 953 | bool MPU6050::getSlaveEnabled(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 954 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 955 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 956 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 957 | } |
lixianyu | 0:a4d8f5b3c546 | 958 | /** Set the enabled value for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 959 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 960 | * @param enabled New enabled value for specified slave |
lixianyu | 0:a4d8f5b3c546 | 961 | * @see getSlaveEnabled() |
lixianyu | 0:a4d8f5b3c546 | 962 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 963 | */ |
lixianyu | 0:a4d8f5b3c546 | 964 | void MPU6050::setSlaveEnabled(uint8_t num, bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 965 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 966 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 967 | } |
lixianyu | 0:a4d8f5b3c546 | 968 | /** Get word pair byte-swapping enabled for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 969 | * When set to 1, this bit enables byte swapping. When byte swapping is enabled, |
lixianyu | 0:a4d8f5b3c546 | 970 | * the high and low bytes of a word pair are swapped. Please refer to |
lixianyu | 0:a4d8f5b3c546 | 971 | * I2C_SLV0_GRP for the pairing convention of the word pairs. When cleared to 0, |
lixianyu | 0:a4d8f5b3c546 | 972 | * bytes transferred to and from Slave 0 will be written to EXT_SENS_DATA |
lixianyu | 0:a4d8f5b3c546 | 973 | * registers in the order they were transferred. |
lixianyu | 0:a4d8f5b3c546 | 974 | * |
lixianyu | 0:a4d8f5b3c546 | 975 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 976 | * @return Current word pair byte-swapping enabled value for specified slave |
lixianyu | 0:a4d8f5b3c546 | 977 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 978 | */ |
lixianyu | 0:a4d8f5b3c546 | 979 | bool MPU6050::getSlaveWordByteSwap(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 980 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 981 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_BYTE_SW_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 982 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 983 | } |
lixianyu | 0:a4d8f5b3c546 | 984 | /** Set word pair byte-swapping enabled for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 985 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 986 | * @param enabled New word pair byte-swapping enabled value for specified slave |
lixianyu | 0:a4d8f5b3c546 | 987 | * @see getSlaveWordByteSwap() |
lixianyu | 0:a4d8f5b3c546 | 988 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 989 | */ |
lixianyu | 0:a4d8f5b3c546 | 990 | void MPU6050::setSlaveWordByteSwap(uint8_t num, bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 991 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 992 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_BYTE_SW_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 993 | } |
lixianyu | 0:a4d8f5b3c546 | 994 | /** Get write mode for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 995 | * When set to 1, the transaction will read or write data only. When cleared to |
lixianyu | 0:a4d8f5b3c546 | 996 | * 0, the transaction will write a register address prior to reading or writing |
lixianyu | 0:a4d8f5b3c546 | 997 | * data. This should equal 0 when specifying the register address within the |
lixianyu | 0:a4d8f5b3c546 | 998 | * Slave device to/from which the ensuing data transaction will take place. |
lixianyu | 0:a4d8f5b3c546 | 999 | * |
lixianyu | 0:a4d8f5b3c546 | 1000 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 1001 | * @return Current write mode for specified slave (0 = register address + data, 1 = data only) |
lixianyu | 0:a4d8f5b3c546 | 1002 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1003 | */ |
lixianyu | 0:a4d8f5b3c546 | 1004 | bool MPU6050::getSlaveWriteMode(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 1005 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 1006 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_REG_DIS_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1007 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1008 | } |
lixianyu | 0:a4d8f5b3c546 | 1009 | /** Set write mode for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 1010 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 1011 | * @param mode New write mode for specified slave (0 = register address + data, 1 = data only) |
lixianyu | 0:a4d8f5b3c546 | 1012 | * @see getSlaveWriteMode() |
lixianyu | 0:a4d8f5b3c546 | 1013 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1014 | */ |
lixianyu | 0:a4d8f5b3c546 | 1015 | void MPU6050::setSlaveWriteMode(uint8_t num, bool mode) { |
lixianyu | 0:a4d8f5b3c546 | 1016 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 1017 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_REG_DIS_BIT, mode); |
lixianyu | 0:a4d8f5b3c546 | 1018 | } |
lixianyu | 0:a4d8f5b3c546 | 1019 | /** Get word pair grouping order offset for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 1020 | * This sets specifies the grouping order of word pairs received from registers. |
lixianyu | 0:a4d8f5b3c546 | 1021 | * When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even, |
lixianyu | 0:a4d8f5b3c546 | 1022 | * then odd register addresses) are paired to form a word. When set to 1, bytes |
lixianyu | 0:a4d8f5b3c546 | 1023 | * from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even |
lixianyu | 0:a4d8f5b3c546 | 1024 | * register addresses) are paired to form a word. |
lixianyu | 0:a4d8f5b3c546 | 1025 | * |
lixianyu | 0:a4d8f5b3c546 | 1026 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 1027 | * @return Current word pair grouping order offset for specified slave |
lixianyu | 0:a4d8f5b3c546 | 1028 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1029 | */ |
lixianyu | 0:a4d8f5b3c546 | 1030 | bool MPU6050::getSlaveWordGroupOffset(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 1031 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 1032 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_GRP_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1033 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1034 | } |
lixianyu | 0:a4d8f5b3c546 | 1035 | /** Set word pair grouping order offset for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 1036 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 1037 | * @param enabled New word pair grouping order offset for specified slave |
lixianyu | 0:a4d8f5b3c546 | 1038 | * @see getSlaveWordGroupOffset() |
lixianyu | 0:a4d8f5b3c546 | 1039 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1040 | */ |
lixianyu | 0:a4d8f5b3c546 | 1041 | void MPU6050::setSlaveWordGroupOffset(uint8_t num, bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1042 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 1043 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_GRP_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1044 | } |
lixianyu | 0:a4d8f5b3c546 | 1045 | /** Get number of bytes to read for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 1046 | * Specifies the number of bytes transferred to and from Slave 0. Clearing this |
lixianyu | 0:a4d8f5b3c546 | 1047 | * bit to 0 is equivalent to disabling the register by writing 0 to I2C_SLV0_EN. |
lixianyu | 0:a4d8f5b3c546 | 1048 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 1049 | * @return Number of bytes to read for specified slave |
lixianyu | 0:a4d8f5b3c546 | 1050 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1051 | */ |
lixianyu | 0:a4d8f5b3c546 | 1052 | uint8_t MPU6050::getSlaveDataLength(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 1053 | if (num > 3) return 0; |
lixianyu | 0:a4d8f5b3c546 | 1054 | I2Cdev::readBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1055 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1056 | } |
lixianyu | 0:a4d8f5b3c546 | 1057 | /** Set number of bytes to read for the specified slave (0-3). |
lixianyu | 0:a4d8f5b3c546 | 1058 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 1059 | * @param length Number of bytes to read for specified slave |
lixianyu | 0:a4d8f5b3c546 | 1060 | * @see getSlaveDataLength() |
lixianyu | 0:a4d8f5b3c546 | 1061 | * @see MPU6050_RA_I2C_SLV0_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1062 | */ |
lixianyu | 0:a4d8f5b3c546 | 1063 | void MPU6050::setSlaveDataLength(uint8_t num, uint8_t length) { |
lixianyu | 0:a4d8f5b3c546 | 1064 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 1065 | I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH, length); |
lixianyu | 0:a4d8f5b3c546 | 1066 | } |
lixianyu | 0:a4d8f5b3c546 | 1067 | |
lixianyu | 0:a4d8f5b3c546 | 1068 | // I2C_SLV* registers (Slave 4) |
lixianyu | 0:a4d8f5b3c546 | 1069 | |
lixianyu | 0:a4d8f5b3c546 | 1070 | /** Get the I2C address of Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1071 | * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read |
lixianyu | 0:a4d8f5b3c546 | 1072 | * operation, and if it is cleared, then it's a write operation. The remaining |
lixianyu | 0:a4d8f5b3c546 | 1073 | * bits (6-0) are the 7-bit device address of the slave device. |
lixianyu | 0:a4d8f5b3c546 | 1074 | * |
lixianyu | 0:a4d8f5b3c546 | 1075 | * @return Current address for Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1076 | * @see getSlaveAddress() |
lixianyu | 0:a4d8f5b3c546 | 1077 | * @see MPU6050_RA_I2C_SLV4_ADDR |
lixianyu | 0:a4d8f5b3c546 | 1078 | */ |
lixianyu | 0:a4d8f5b3c546 | 1079 | uint8_t MPU6050::getSlave4Address() { |
lixianyu | 0:a4d8f5b3c546 | 1080 | I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1081 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1082 | } |
lixianyu | 0:a4d8f5b3c546 | 1083 | /** Set the I2C address of Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1084 | * @param address New address for Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1085 | * @see getSlave4Address() |
lixianyu | 0:a4d8f5b3c546 | 1086 | * @see MPU6050_RA_I2C_SLV4_ADDR |
lixianyu | 0:a4d8f5b3c546 | 1087 | */ |
lixianyu | 0:a4d8f5b3c546 | 1088 | void MPU6050::setSlave4Address(uint8_t address) { |
lixianyu | 0:a4d8f5b3c546 | 1089 | I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, address); |
lixianyu | 0:a4d8f5b3c546 | 1090 | } |
lixianyu | 0:a4d8f5b3c546 | 1091 | /** Get the active internal register for the Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1092 | * Read/write operations for this slave will be done to whatever internal |
lixianyu | 0:a4d8f5b3c546 | 1093 | * register address is stored in this MPU register. |
lixianyu | 0:a4d8f5b3c546 | 1094 | * |
lixianyu | 0:a4d8f5b3c546 | 1095 | * @return Current active register for Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1096 | * @see MPU6050_RA_I2C_SLV4_REG |
lixianyu | 0:a4d8f5b3c546 | 1097 | */ |
lixianyu | 0:a4d8f5b3c546 | 1098 | uint8_t MPU6050::getSlave4Register() { |
lixianyu | 0:a4d8f5b3c546 | 1099 | I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_REG, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1100 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1101 | } |
lixianyu | 0:a4d8f5b3c546 | 1102 | /** Set the active internal register for Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1103 | * @param reg New active register for Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1104 | * @see getSlave4Register() |
lixianyu | 0:a4d8f5b3c546 | 1105 | * @see MPU6050_RA_I2C_SLV4_REG |
lixianyu | 0:a4d8f5b3c546 | 1106 | */ |
lixianyu | 0:a4d8f5b3c546 | 1107 | void MPU6050::setSlave4Register(uint8_t reg) { |
lixianyu | 0:a4d8f5b3c546 | 1108 | I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_REG, reg); |
lixianyu | 0:a4d8f5b3c546 | 1109 | } |
lixianyu | 0:a4d8f5b3c546 | 1110 | /** Set new byte to write to Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1111 | * This register stores the data to be written into the Slave 4. If I2C_SLV4_RW |
lixianyu | 0:a4d8f5b3c546 | 1112 | * is set 1 (set to read), this register has no effect. |
lixianyu | 0:a4d8f5b3c546 | 1113 | * @param data New byte to write to Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1114 | * @see MPU6050_RA_I2C_SLV4_DO |
lixianyu | 0:a4d8f5b3c546 | 1115 | */ |
lixianyu | 0:a4d8f5b3c546 | 1116 | void MPU6050::setSlave4OutputByte(uint8_t data) { |
lixianyu | 0:a4d8f5b3c546 | 1117 | I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_DO, data); |
lixianyu | 0:a4d8f5b3c546 | 1118 | } |
lixianyu | 0:a4d8f5b3c546 | 1119 | /** Get the enabled value for the Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1120 | * When set to 1, this bit enables Slave 4 for data transfer operations. When |
lixianyu | 0:a4d8f5b3c546 | 1121 | * cleared to 0, this bit disables Slave 4 from data transfer operations. |
lixianyu | 0:a4d8f5b3c546 | 1122 | * @return Current enabled value for Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1123 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1124 | */ |
lixianyu | 0:a4d8f5b3c546 | 1125 | bool MPU6050::getSlave4Enabled() { |
lixianyu | 0:a4d8f5b3c546 | 1126 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1127 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1128 | } |
lixianyu | 0:a4d8f5b3c546 | 1129 | /** Set the enabled value for Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1130 | * @param enabled New enabled value for Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1131 | * @see getSlave4Enabled() |
lixianyu | 0:a4d8f5b3c546 | 1132 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1133 | */ |
lixianyu | 0:a4d8f5b3c546 | 1134 | void MPU6050::setSlave4Enabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1135 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1136 | } |
lixianyu | 0:a4d8f5b3c546 | 1137 | /** Get the enabled value for Slave 4 transaction interrupts. |
lixianyu | 0:a4d8f5b3c546 | 1138 | * When set to 1, this bit enables the generation of an interrupt signal upon |
lixianyu | 0:a4d8f5b3c546 | 1139 | * completion of a Slave 4 transaction. When cleared to 0, this bit disables the |
lixianyu | 0:a4d8f5b3c546 | 1140 | * generation of an interrupt signal upon completion of a Slave 4 transaction. |
lixianyu | 0:a4d8f5b3c546 | 1141 | * The interrupt status can be observed in Register 54. |
lixianyu | 0:a4d8f5b3c546 | 1142 | * |
lixianyu | 0:a4d8f5b3c546 | 1143 | * @return Current enabled value for Slave 4 transaction interrupts. |
lixianyu | 0:a4d8f5b3c546 | 1144 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1145 | */ |
lixianyu | 0:a4d8f5b3c546 | 1146 | bool MPU6050::getSlave4InterruptEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1147 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1148 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1149 | } |
lixianyu | 0:a4d8f5b3c546 | 1150 | /** Set the enabled value for Slave 4 transaction interrupts. |
lixianyu | 0:a4d8f5b3c546 | 1151 | * @param enabled New enabled value for Slave 4 transaction interrupts. |
lixianyu | 0:a4d8f5b3c546 | 1152 | * @see getSlave4InterruptEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1153 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1154 | */ |
lixianyu | 0:a4d8f5b3c546 | 1155 | void MPU6050::setSlave4InterruptEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1156 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1157 | } |
lixianyu | 0:a4d8f5b3c546 | 1158 | /** Get write mode for Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1159 | * When set to 1, the transaction will read or write data only. When cleared to |
lixianyu | 0:a4d8f5b3c546 | 1160 | * 0, the transaction will write a register address prior to reading or writing |
lixianyu | 0:a4d8f5b3c546 | 1161 | * data. This should equal 0 when specifying the register address within the |
lixianyu | 0:a4d8f5b3c546 | 1162 | * Slave device to/from which the ensuing data transaction will take place. |
lixianyu | 0:a4d8f5b3c546 | 1163 | * |
lixianyu | 0:a4d8f5b3c546 | 1164 | * @return Current write mode for Slave 4 (0 = register address + data, 1 = data only) |
lixianyu | 0:a4d8f5b3c546 | 1165 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1166 | */ |
lixianyu | 0:a4d8f5b3c546 | 1167 | bool MPU6050::getSlave4WriteMode() { |
lixianyu | 0:a4d8f5b3c546 | 1168 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1169 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1170 | } |
lixianyu | 0:a4d8f5b3c546 | 1171 | /** Set write mode for the Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1172 | * @param mode New write mode for Slave 4 (0 = register address + data, 1 = data only) |
lixianyu | 0:a4d8f5b3c546 | 1173 | * @see getSlave4WriteMode() |
lixianyu | 0:a4d8f5b3c546 | 1174 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1175 | */ |
lixianyu | 0:a4d8f5b3c546 | 1176 | void MPU6050::setSlave4WriteMode(bool mode) { |
lixianyu | 0:a4d8f5b3c546 | 1177 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, mode); |
lixianyu | 0:a4d8f5b3c546 | 1178 | } |
lixianyu | 0:a4d8f5b3c546 | 1179 | /** Get Slave 4 master delay value. |
lixianyu | 0:a4d8f5b3c546 | 1180 | * This configures the reduced access rate of I2C slaves relative to the Sample |
lixianyu | 0:a4d8f5b3c546 | 1181 | * Rate. When a slave's access rate is decreased relative to the Sample Rate, |
lixianyu | 0:a4d8f5b3c546 | 1182 | * the slave is accessed every: |
lixianyu | 0:a4d8f5b3c546 | 1183 | * |
lixianyu | 0:a4d8f5b3c546 | 1184 | * 1 / (1 + I2C_MST_DLY) samples |
lixianyu | 0:a4d8f5b3c546 | 1185 | * |
lixianyu | 0:a4d8f5b3c546 | 1186 | * This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and |
lixianyu | 0:a4d8f5b3c546 | 1187 | * DLPF_CFG (register 26). Whether a slave's access rate is reduced relative to |
lixianyu | 0:a4d8f5b3c546 | 1188 | * the Sample Rate is determined by I2C_MST_DELAY_CTRL (register 103). For |
lixianyu | 0:a4d8f5b3c546 | 1189 | * further information regarding the Sample Rate, please refer to register 25. |
lixianyu | 0:a4d8f5b3c546 | 1190 | * |
lixianyu | 0:a4d8f5b3c546 | 1191 | * @return Current Slave 4 master delay value |
lixianyu | 0:a4d8f5b3c546 | 1192 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1193 | */ |
lixianyu | 0:a4d8f5b3c546 | 1194 | uint8_t MPU6050::getSlave4MasterDelay() { |
lixianyu | 0:a4d8f5b3c546 | 1195 | I2Cdev::readBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1196 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1197 | } |
lixianyu | 0:a4d8f5b3c546 | 1198 | /** Set Slave 4 master delay value. |
lixianyu | 0:a4d8f5b3c546 | 1199 | * @param delay New Slave 4 master delay value |
lixianyu | 0:a4d8f5b3c546 | 1200 | * @see getSlave4MasterDelay() |
lixianyu | 0:a4d8f5b3c546 | 1201 | * @see MPU6050_RA_I2C_SLV4_CTRL |
lixianyu | 0:a4d8f5b3c546 | 1202 | */ |
lixianyu | 0:a4d8f5b3c546 | 1203 | void MPU6050::setSlave4MasterDelay(uint8_t delay) { |
lixianyu | 0:a4d8f5b3c546 | 1204 | I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH, delay); |
lixianyu | 0:a4d8f5b3c546 | 1205 | } |
lixianyu | 0:a4d8f5b3c546 | 1206 | /** Get last available byte read from Slave 4. |
lixianyu | 0:a4d8f5b3c546 | 1207 | * This register stores the data read from Slave 4. This field is populated |
lixianyu | 0:a4d8f5b3c546 | 1208 | * after a read transaction. |
lixianyu | 0:a4d8f5b3c546 | 1209 | * @return Last available byte read from to Slave 4 |
lixianyu | 0:a4d8f5b3c546 | 1210 | * @see MPU6050_RA_I2C_SLV4_DI |
lixianyu | 0:a4d8f5b3c546 | 1211 | */ |
lixianyu | 0:a4d8f5b3c546 | 1212 | uint8_t MPU6050::getSlate4InputByte() { |
lixianyu | 0:a4d8f5b3c546 | 1213 | I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_DI, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1214 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1215 | } |
lixianyu | 0:a4d8f5b3c546 | 1216 | |
lixianyu | 0:a4d8f5b3c546 | 1217 | // I2C_MST_STATUS register |
lixianyu | 0:a4d8f5b3c546 | 1218 | |
lixianyu | 0:a4d8f5b3c546 | 1219 | /** Get FSYNC interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1220 | * This bit reflects the status of the FSYNC interrupt from an external device |
lixianyu | 0:a4d8f5b3c546 | 1221 | * into the MPU-60X0. This is used as a way to pass an external interrupt |
lixianyu | 0:a4d8f5b3c546 | 1222 | * through the MPU-60X0 to the host application processor. When set to 1, this |
lixianyu | 0:a4d8f5b3c546 | 1223 | * bit will cause an interrupt if FSYNC_INT_EN is asserted in INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1224 | * (Register 55). |
lixianyu | 0:a4d8f5b3c546 | 1225 | * @return FSYNC interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1226 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1227 | */ |
lixianyu | 0:a4d8f5b3c546 | 1228 | bool MPU6050::getPassthroughStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1229 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_PASS_THROUGH_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1230 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1231 | } |
lixianyu | 0:a4d8f5b3c546 | 1232 | /** Get Slave 4 transaction done status. |
lixianyu | 0:a4d8f5b3c546 | 1233 | * Automatically sets to 1 when a Slave 4 transaction has completed. This |
lixianyu | 0:a4d8f5b3c546 | 1234 | * triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register |
lixianyu | 0:a4d8f5b3c546 | 1235 | * (Register 56) is asserted and if the SLV_4_DONE_INT bit is asserted in the |
lixianyu | 0:a4d8f5b3c546 | 1236 | * I2C_SLV4_CTRL register (Register 52). |
lixianyu | 0:a4d8f5b3c546 | 1237 | * @return Slave 4 transaction done status |
lixianyu | 0:a4d8f5b3c546 | 1238 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1239 | */ |
lixianyu | 0:a4d8f5b3c546 | 1240 | bool MPU6050::getSlave4IsDone() { |
lixianyu | 0:a4d8f5b3c546 | 1241 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_DONE_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1242 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1243 | } |
lixianyu | 0:a4d8f5b3c546 | 1244 | /** Get master arbitration lost status. |
lixianyu | 0:a4d8f5b3c546 | 1245 | * This bit automatically sets to 1 when the I2C Master has lost arbitration of |
lixianyu | 0:a4d8f5b3c546 | 1246 | * the auxiliary I2C bus (an error condition). This triggers an interrupt if the |
lixianyu | 0:a4d8f5b3c546 | 1247 | * I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted. |
lixianyu | 0:a4d8f5b3c546 | 1248 | * @return Master arbitration lost status |
lixianyu | 0:a4d8f5b3c546 | 1249 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1250 | */ |
lixianyu | 0:a4d8f5b3c546 | 1251 | bool MPU6050::getLostArbitration() { |
lixianyu | 0:a4d8f5b3c546 | 1252 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_LOST_ARB_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1253 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1254 | } |
lixianyu | 0:a4d8f5b3c546 | 1255 | /** Get Slave 4 NACK status. |
lixianyu | 0:a4d8f5b3c546 | 1256 | * This bit automatically sets to 1 when the I2C Master receives a NACK in a |
lixianyu | 0:a4d8f5b3c546 | 1257 | * transaction with Slave 4. This triggers an interrupt if the I2C_MST_INT_EN |
lixianyu | 0:a4d8f5b3c546 | 1258 | * bit in the INT_ENABLE register (Register 56) is asserted. |
lixianyu | 0:a4d8f5b3c546 | 1259 | * @return Slave 4 NACK interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1260 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1261 | */ |
lixianyu | 0:a4d8f5b3c546 | 1262 | bool MPU6050::getSlave4Nack() { |
lixianyu | 0:a4d8f5b3c546 | 1263 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_NACK_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1264 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1265 | } |
lixianyu | 0:a4d8f5b3c546 | 1266 | /** Get Slave 3 NACK status. |
lixianyu | 0:a4d8f5b3c546 | 1267 | * This bit automatically sets to 1 when the I2C Master receives a NACK in a |
lixianyu | 0:a4d8f5b3c546 | 1268 | * transaction with Slave 3. This triggers an interrupt if the I2C_MST_INT_EN |
lixianyu | 0:a4d8f5b3c546 | 1269 | * bit in the INT_ENABLE register (Register 56) is asserted. |
lixianyu | 0:a4d8f5b3c546 | 1270 | * @return Slave 3 NACK interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1271 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1272 | */ |
lixianyu | 0:a4d8f5b3c546 | 1273 | bool MPU6050::getSlave3Nack() { |
lixianyu | 0:a4d8f5b3c546 | 1274 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV3_NACK_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1275 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1276 | } |
lixianyu | 0:a4d8f5b3c546 | 1277 | /** Get Slave 2 NACK status. |
lixianyu | 0:a4d8f5b3c546 | 1278 | * This bit automatically sets to 1 when the I2C Master receives a NACK in a |
lixianyu | 0:a4d8f5b3c546 | 1279 | * transaction with Slave 2. This triggers an interrupt if the I2C_MST_INT_EN |
lixianyu | 0:a4d8f5b3c546 | 1280 | * bit in the INT_ENABLE register (Register 56) is asserted. |
lixianyu | 0:a4d8f5b3c546 | 1281 | * @return Slave 2 NACK interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1282 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1283 | */ |
lixianyu | 0:a4d8f5b3c546 | 1284 | bool MPU6050::getSlave2Nack() { |
lixianyu | 0:a4d8f5b3c546 | 1285 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV2_NACK_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1286 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1287 | } |
lixianyu | 0:a4d8f5b3c546 | 1288 | /** Get Slave 1 NACK status. |
lixianyu | 0:a4d8f5b3c546 | 1289 | * This bit automatically sets to 1 when the I2C Master receives a NACK in a |
lixianyu | 0:a4d8f5b3c546 | 1290 | * transaction with Slave 1. This triggers an interrupt if the I2C_MST_INT_EN |
lixianyu | 0:a4d8f5b3c546 | 1291 | * bit in the INT_ENABLE register (Register 56) is asserted. |
lixianyu | 0:a4d8f5b3c546 | 1292 | * @return Slave 1 NACK interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1293 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1294 | */ |
lixianyu | 0:a4d8f5b3c546 | 1295 | bool MPU6050::getSlave1Nack() { |
lixianyu | 0:a4d8f5b3c546 | 1296 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV1_NACK_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1297 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1298 | } |
lixianyu | 0:a4d8f5b3c546 | 1299 | /** Get Slave 0 NACK status. |
lixianyu | 0:a4d8f5b3c546 | 1300 | * This bit automatically sets to 1 when the I2C Master receives a NACK in a |
lixianyu | 0:a4d8f5b3c546 | 1301 | * transaction with Slave 0. This triggers an interrupt if the I2C_MST_INT_EN |
lixianyu | 0:a4d8f5b3c546 | 1302 | * bit in the INT_ENABLE register (Register 56) is asserted. |
lixianyu | 0:a4d8f5b3c546 | 1303 | * @return Slave 0 NACK interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1304 | * @see MPU6050_RA_I2C_MST_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1305 | */ |
lixianyu | 0:a4d8f5b3c546 | 1306 | bool MPU6050::getSlave0Nack() { |
lixianyu | 0:a4d8f5b3c546 | 1307 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV0_NACK_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1308 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1309 | } |
lixianyu | 0:a4d8f5b3c546 | 1310 | |
lixianyu | 0:a4d8f5b3c546 | 1311 | // INT_PIN_CFG register |
lixianyu | 0:a4d8f5b3c546 | 1312 | |
lixianyu | 0:a4d8f5b3c546 | 1313 | /** Get interrupt logic level mode. |
lixianyu | 0:a4d8f5b3c546 | 1314 | * Will be set 0 for active-high, 1 for active-low. |
lixianyu | 0:a4d8f5b3c546 | 1315 | * @return Current interrupt mode (0=active-high, 1=active-low) |
lixianyu | 0:a4d8f5b3c546 | 1316 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1317 | * @see MPU6050_INTCFG_INT_LEVEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 1318 | */ |
lixianyu | 0:a4d8f5b3c546 | 1319 | bool MPU6050::getInterruptMode() { |
lixianyu | 0:a4d8f5b3c546 | 1320 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1321 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1322 | } |
lixianyu | 0:a4d8f5b3c546 | 1323 | /** Set interrupt logic level mode. |
lixianyu | 0:a4d8f5b3c546 | 1324 | * @param mode New interrupt mode (0=active-high, 1=active-low) |
lixianyu | 0:a4d8f5b3c546 | 1325 | * @see getInterruptMode() |
lixianyu | 0:a4d8f5b3c546 | 1326 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1327 | * @see MPU6050_INTCFG_INT_LEVEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 1328 | */ |
lixianyu | 0:a4d8f5b3c546 | 1329 | void MPU6050::setInterruptMode(bool mode) { |
lixianyu | 0:a4d8f5b3c546 | 1330 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, mode); |
lixianyu | 0:a4d8f5b3c546 | 1331 | } |
lixianyu | 0:a4d8f5b3c546 | 1332 | /** Get interrupt drive mode. |
lixianyu | 0:a4d8f5b3c546 | 1333 | * Will be set 0 for push-pull, 1 for open-drain. |
lixianyu | 0:a4d8f5b3c546 | 1334 | * @return Current interrupt drive mode (0=push-pull, 1=open-drain) |
lixianyu | 0:a4d8f5b3c546 | 1335 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1336 | * @see MPU6050_INTCFG_INT_OPEN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1337 | */ |
lixianyu | 0:a4d8f5b3c546 | 1338 | bool MPU6050::getInterruptDrive() { |
lixianyu | 0:a4d8f5b3c546 | 1339 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1340 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1341 | } |
lixianyu | 0:a4d8f5b3c546 | 1342 | /** Set interrupt drive mode. |
lixianyu | 0:a4d8f5b3c546 | 1343 | * @param drive New interrupt drive mode (0=push-pull, 1=open-drain) |
lixianyu | 0:a4d8f5b3c546 | 1344 | * @see getInterruptDrive() |
lixianyu | 0:a4d8f5b3c546 | 1345 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1346 | * @see MPU6050_INTCFG_INT_OPEN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1347 | */ |
lixianyu | 0:a4d8f5b3c546 | 1348 | void MPU6050::setInterruptDrive(bool drive) { |
lixianyu | 0:a4d8f5b3c546 | 1349 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, drive); |
lixianyu | 0:a4d8f5b3c546 | 1350 | } |
lixianyu | 0:a4d8f5b3c546 | 1351 | /** Get interrupt latch mode. |
lixianyu | 0:a4d8f5b3c546 | 1352 | * Will be set 0 for 50us-pulse, 1 for latch-until-int-cleared. |
lixianyu | 0:a4d8f5b3c546 | 1353 | * @return Current latch mode (0=50us-pulse, 1=latch-until-int-cleared) |
lixianyu | 0:a4d8f5b3c546 | 1354 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1355 | * @see MPU6050_INTCFG_LATCH_INT_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1356 | */ |
lixianyu | 0:a4d8f5b3c546 | 1357 | bool MPU6050::getInterruptLatch() { |
lixianyu | 0:a4d8f5b3c546 | 1358 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1359 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1360 | } |
lixianyu | 0:a4d8f5b3c546 | 1361 | /** Set interrupt latch mode. |
lixianyu | 0:a4d8f5b3c546 | 1362 | * @param latch New latch mode (0=50us-pulse, 1=latch-until-int-cleared) |
lixianyu | 0:a4d8f5b3c546 | 1363 | * @see getInterruptLatch() |
lixianyu | 0:a4d8f5b3c546 | 1364 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1365 | * @see MPU6050_INTCFG_LATCH_INT_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1366 | */ |
lixianyu | 0:a4d8f5b3c546 | 1367 | void MPU6050::setInterruptLatch(bool latch) { |
lixianyu | 0:a4d8f5b3c546 | 1368 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, latch); |
lixianyu | 0:a4d8f5b3c546 | 1369 | } |
lixianyu | 0:a4d8f5b3c546 | 1370 | /** Get interrupt latch clear mode. |
lixianyu | 0:a4d8f5b3c546 | 1371 | * Will be set 0 for status-read-only, 1 for any-register-read. |
lixianyu | 0:a4d8f5b3c546 | 1372 | * @return Current latch clear mode (0=status-read-only, 1=any-register-read) |
lixianyu | 0:a4d8f5b3c546 | 1373 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1374 | * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT |
lixianyu | 0:a4d8f5b3c546 | 1375 | */ |
lixianyu | 0:a4d8f5b3c546 | 1376 | bool MPU6050::getInterruptLatchClear() { |
lixianyu | 0:a4d8f5b3c546 | 1377 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1378 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1379 | } |
lixianyu | 0:a4d8f5b3c546 | 1380 | /** Set interrupt latch clear mode. |
lixianyu | 0:a4d8f5b3c546 | 1381 | * @param clear New latch clear mode (0=status-read-only, 1=any-register-read) |
lixianyu | 0:a4d8f5b3c546 | 1382 | * @see getInterruptLatchClear() |
lixianyu | 0:a4d8f5b3c546 | 1383 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1384 | * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT |
lixianyu | 0:a4d8f5b3c546 | 1385 | */ |
lixianyu | 0:a4d8f5b3c546 | 1386 | void MPU6050::setInterruptLatchClear(bool clear) { |
lixianyu | 0:a4d8f5b3c546 | 1387 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, clear); |
lixianyu | 0:a4d8f5b3c546 | 1388 | } |
lixianyu | 0:a4d8f5b3c546 | 1389 | /** Get FSYNC interrupt logic level mode. |
lixianyu | 0:a4d8f5b3c546 | 1390 | * @return Current FSYNC interrupt mode (0=active-high, 1=active-low) |
lixianyu | 0:a4d8f5b3c546 | 1391 | * @see getFSyncInterruptMode() |
lixianyu | 0:a4d8f5b3c546 | 1392 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1393 | * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 1394 | */ |
lixianyu | 0:a4d8f5b3c546 | 1395 | bool MPU6050::getFSyncInterruptLevel() { |
lixianyu | 0:a4d8f5b3c546 | 1396 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1397 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1398 | } |
lixianyu | 0:a4d8f5b3c546 | 1399 | /** Set FSYNC interrupt logic level mode. |
lixianyu | 0:a4d8f5b3c546 | 1400 | * @param mode New FSYNC interrupt mode (0=active-high, 1=active-low) |
lixianyu | 0:a4d8f5b3c546 | 1401 | * @see getFSyncInterruptMode() |
lixianyu | 0:a4d8f5b3c546 | 1402 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1403 | * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 1404 | */ |
lixianyu | 0:a4d8f5b3c546 | 1405 | void MPU6050::setFSyncInterruptLevel(bool level) { |
lixianyu | 0:a4d8f5b3c546 | 1406 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, level); |
lixianyu | 0:a4d8f5b3c546 | 1407 | } |
lixianyu | 0:a4d8f5b3c546 | 1408 | /** Get FSYNC pin interrupt enabled setting. |
lixianyu | 0:a4d8f5b3c546 | 1409 | * Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1410 | * @return Current interrupt enabled setting |
lixianyu | 0:a4d8f5b3c546 | 1411 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1412 | * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1413 | */ |
lixianyu | 0:a4d8f5b3c546 | 1414 | bool MPU6050::getFSyncInterruptEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1415 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1416 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1417 | } |
lixianyu | 0:a4d8f5b3c546 | 1418 | /** Set FSYNC pin interrupt enabled setting. |
lixianyu | 0:a4d8f5b3c546 | 1419 | * @param enabled New FSYNC pin interrupt enabled setting |
lixianyu | 0:a4d8f5b3c546 | 1420 | * @see getFSyncInterruptEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1421 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1422 | * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1423 | */ |
lixianyu | 0:a4d8f5b3c546 | 1424 | void MPU6050::setFSyncInterruptEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1425 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1426 | } |
lixianyu | 0:a4d8f5b3c546 | 1427 | /** Get I2C bypass enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1428 | * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to |
lixianyu | 0:a4d8f5b3c546 | 1429 | * 0, the host application processor will be able to directly access the |
lixianyu | 0:a4d8f5b3c546 | 1430 | * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host |
lixianyu | 0:a4d8f5b3c546 | 1431 | * application processor will not be able to directly access the auxiliary I2C |
lixianyu | 0:a4d8f5b3c546 | 1432 | * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106 |
lixianyu | 0:a4d8f5b3c546 | 1433 | * bit[5]). |
lixianyu | 0:a4d8f5b3c546 | 1434 | * @return Current I2C bypass enabled status |
lixianyu | 0:a4d8f5b3c546 | 1435 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1436 | * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1437 | */ |
lixianyu | 0:a4d8f5b3c546 | 1438 | bool MPU6050::getI2CBypassEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1439 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1440 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1441 | } |
lixianyu | 0:a4d8f5b3c546 | 1442 | /** Set I2C bypass enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1443 | * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to |
lixianyu | 0:a4d8f5b3c546 | 1444 | * 0, the host application processor will be able to directly access the |
lixianyu | 0:a4d8f5b3c546 | 1445 | * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host |
lixianyu | 0:a4d8f5b3c546 | 1446 | * application processor will not be able to directly access the auxiliary I2C |
lixianyu | 0:a4d8f5b3c546 | 1447 | * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106 |
lixianyu | 0:a4d8f5b3c546 | 1448 | * bit[5]). |
lixianyu | 0:a4d8f5b3c546 | 1449 | * @param enabled New I2C bypass enabled status |
lixianyu | 0:a4d8f5b3c546 | 1450 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1451 | * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1452 | */ |
lixianyu | 0:a4d8f5b3c546 | 1453 | void MPU6050::setI2CBypassEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1454 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1455 | } |
lixianyu | 0:a4d8f5b3c546 | 1456 | /** Get reference clock output enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1457 | * When this bit is equal to 1, a reference clock output is provided at the |
lixianyu | 0:a4d8f5b3c546 | 1458 | * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For |
lixianyu | 0:a4d8f5b3c546 | 1459 | * further information regarding CLKOUT, please refer to the MPU-60X0 Product |
lixianyu | 0:a4d8f5b3c546 | 1460 | * Specification document. |
lixianyu | 0:a4d8f5b3c546 | 1461 | * @return Current reference clock output enabled status |
lixianyu | 0:a4d8f5b3c546 | 1462 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1463 | * @see MPU6050_INTCFG_CLKOUT_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1464 | */ |
lixianyu | 0:a4d8f5b3c546 | 1465 | bool MPU6050::getClockOutputEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1466 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1467 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1468 | } |
lixianyu | 0:a4d8f5b3c546 | 1469 | /** Set reference clock output enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1470 | * When this bit is equal to 1, a reference clock output is provided at the |
lixianyu | 0:a4d8f5b3c546 | 1471 | * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For |
lixianyu | 0:a4d8f5b3c546 | 1472 | * further information regarding CLKOUT, please refer to the MPU-60X0 Product |
lixianyu | 0:a4d8f5b3c546 | 1473 | * Specification document. |
lixianyu | 0:a4d8f5b3c546 | 1474 | * @param enabled New reference clock output enabled status |
lixianyu | 0:a4d8f5b3c546 | 1475 | * @see MPU6050_RA_INT_PIN_CFG |
lixianyu | 0:a4d8f5b3c546 | 1476 | * @see MPU6050_INTCFG_CLKOUT_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 1477 | */ |
lixianyu | 0:a4d8f5b3c546 | 1478 | void MPU6050::setClockOutputEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1479 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1480 | } |
lixianyu | 0:a4d8f5b3c546 | 1481 | |
lixianyu | 0:a4d8f5b3c546 | 1482 | // INT_ENABLE register |
lixianyu | 0:a4d8f5b3c546 | 1483 | |
lixianyu | 0:a4d8f5b3c546 | 1484 | /** Get full interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1485 | * Full register byte for all interrupts, for quick reading. Each bit will be |
lixianyu | 0:a4d8f5b3c546 | 1486 | * set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1487 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1488 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1489 | * @see MPU6050_INTERRUPT_FF_BIT |
lixianyu | 0:a4d8f5b3c546 | 1490 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1491 | uint8_t MPU6050::getIntEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1492 | I2Cdev::readByte(devAddr, MPU6050_RA_INT_ENABLE, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1493 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1494 | } |
lixianyu | 0:a4d8f5b3c546 | 1495 | /** Set full interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1496 | * Full register byte for all interrupts, for quick reading. Each bit should be |
lixianyu | 0:a4d8f5b3c546 | 1497 | * set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1498 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1499 | * @see getIntFreefallEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1500 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1501 | * @see MPU6050_INTERRUPT_FF_BIT |
lixianyu | 0:a4d8f5b3c546 | 1502 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1503 | void MPU6050::setIntEnabled(uint8_t enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1504 | I2Cdev::writeByte(devAddr, MPU6050_RA_INT_ENABLE, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1505 | } |
lixianyu | 0:a4d8f5b3c546 | 1506 | /** Get Free Fall interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1507 | * Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1508 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1509 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1510 | * @see MPU6050_INTERRUPT_FF_BIT |
lixianyu | 0:a4d8f5b3c546 | 1511 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1512 | bool MPU6050::getIntFreefallEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1513 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1514 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1515 | } |
lixianyu | 0:a4d8f5b3c546 | 1516 | /** Set Free Fall interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1517 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1518 | * @see getIntFreefallEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1519 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1520 | * @see MPU6050_INTERRUPT_FF_BIT |
lixianyu | 0:a4d8f5b3c546 | 1521 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1522 | void MPU6050::setIntFreefallEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1523 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1524 | } |
lixianyu | 0:a4d8f5b3c546 | 1525 | /** Get Motion Detection interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1526 | * Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1527 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1528 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1529 | * @see MPU6050_INTERRUPT_MOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1530 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1531 | bool MPU6050::getIntMotionEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1532 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1533 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1534 | } |
lixianyu | 0:a4d8f5b3c546 | 1535 | /** Set Motion Detection interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1536 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1537 | * @see getIntMotionEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1538 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1539 | * @see MPU6050_INTERRUPT_MOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1540 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1541 | void MPU6050::setIntMotionEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1542 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1543 | } |
lixianyu | 0:a4d8f5b3c546 | 1544 | /** Get Zero Motion Detection interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1545 | * Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1546 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1547 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1548 | * @see MPU6050_INTERRUPT_ZMOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1549 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1550 | bool MPU6050::getIntZeroMotionEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1551 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1552 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1553 | } |
lixianyu | 0:a4d8f5b3c546 | 1554 | /** Set Zero Motion Detection interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1555 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1556 | * @see getIntZeroMotionEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1557 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1558 | * @see MPU6050_INTERRUPT_ZMOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1559 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1560 | void MPU6050::setIntZeroMotionEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1561 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1562 | } |
lixianyu | 0:a4d8f5b3c546 | 1563 | /** Get FIFO Buffer Overflow interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1564 | * Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1565 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1566 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1567 | * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT |
lixianyu | 0:a4d8f5b3c546 | 1568 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1569 | bool MPU6050::getIntFIFOBufferOverflowEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1570 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1571 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1572 | } |
lixianyu | 0:a4d8f5b3c546 | 1573 | /** Set FIFO Buffer Overflow interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1574 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1575 | * @see getIntFIFOBufferOverflowEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1576 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1577 | * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT |
lixianyu | 0:a4d8f5b3c546 | 1578 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1579 | void MPU6050::setIntFIFOBufferOverflowEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1580 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1581 | } |
lixianyu | 0:a4d8f5b3c546 | 1582 | /** Get I2C Master interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1583 | * This enables any of the I2C Master interrupt sources to generate an |
lixianyu | 0:a4d8f5b3c546 | 1584 | * interrupt. Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1585 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1586 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1587 | * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1588 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1589 | bool MPU6050::getIntI2CMasterEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1590 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1591 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1592 | } |
lixianyu | 0:a4d8f5b3c546 | 1593 | /** Set I2C Master interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1594 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1595 | * @see getIntI2CMasterEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1596 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1597 | * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1598 | **/ |
lixianyu | 0:a4d8f5b3c546 | 1599 | void MPU6050::setIntI2CMasterEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1600 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1601 | } |
lixianyu | 0:a4d8f5b3c546 | 1602 | /** Get Data Ready interrupt enabled setting. |
lixianyu | 0:a4d8f5b3c546 | 1603 | * This event occurs each time a write operation to all of the sensor registers |
lixianyu | 0:a4d8f5b3c546 | 1604 | * has been completed. Will be set 0 for disabled, 1 for enabled. |
lixianyu | 0:a4d8f5b3c546 | 1605 | * @return Current interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1606 | * @see MPU6050_RA_INT_ENABLE |
lixianyu | 0:a4d8f5b3c546 | 1607 | * @see MPU6050_INTERRUPT_DATA_RDY_BIT |
lixianyu | 0:a4d8f5b3c546 | 1608 | */ |
lixianyu | 0:a4d8f5b3c546 | 1609 | bool MPU6050::getIntDataReadyEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 1610 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1611 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1612 | } |
lixianyu | 0:a4d8f5b3c546 | 1613 | /** Set Data Ready interrupt enabled status. |
lixianyu | 0:a4d8f5b3c546 | 1614 | * @param enabled New interrupt enabled status |
lixianyu | 0:a4d8f5b3c546 | 1615 | * @see getIntDataReadyEnabled() |
lixianyu | 0:a4d8f5b3c546 | 1616 | * @see MPU6050_RA_INT_CFG |
lixianyu | 0:a4d8f5b3c546 | 1617 | * @see MPU6050_INTERRUPT_DATA_RDY_BIT |
lixianyu | 0:a4d8f5b3c546 | 1618 | */ |
lixianyu | 0:a4d8f5b3c546 | 1619 | void MPU6050::setIntDataReadyEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 1620 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 1621 | } |
lixianyu | 0:a4d8f5b3c546 | 1622 | |
lixianyu | 0:a4d8f5b3c546 | 1623 | // INT_STATUS register |
lixianyu | 0:a4d8f5b3c546 | 1624 | |
lixianyu | 0:a4d8f5b3c546 | 1625 | /** Get full set of interrupt status bits. |
lixianyu | 0:a4d8f5b3c546 | 1626 | * These bits clear to 0 after the register has been read. Very useful |
lixianyu | 0:a4d8f5b3c546 | 1627 | * for getting multiple INT statuses, since each single bit read clears |
lixianyu | 0:a4d8f5b3c546 | 1628 | * all of them because it has to read the whole byte. |
lixianyu | 0:a4d8f5b3c546 | 1629 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1630 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1631 | */ |
lixianyu | 0:a4d8f5b3c546 | 1632 | uint8_t MPU6050::getIntStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1633 | I2Cdev::readByte(devAddr, MPU6050_RA_INT_STATUS, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1634 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1635 | } |
lixianyu | 0:a4d8f5b3c546 | 1636 | /** Get Free Fall interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1637 | * This bit automatically sets to 1 when a Free Fall interrupt has been |
lixianyu | 0:a4d8f5b3c546 | 1638 | * generated. The bit clears to 0 after the register has been read. |
lixianyu | 0:a4d8f5b3c546 | 1639 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1640 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1641 | * @see MPU6050_INTERRUPT_FF_BIT |
lixianyu | 0:a4d8f5b3c546 | 1642 | */ |
lixianyu | 0:a4d8f5b3c546 | 1643 | bool MPU6050::getIntFreefallStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1644 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FF_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1645 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1646 | } |
lixianyu | 0:a4d8f5b3c546 | 1647 | /** Get Motion Detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1648 | * This bit automatically sets to 1 when a Motion Detection interrupt has been |
lixianyu | 0:a4d8f5b3c546 | 1649 | * generated. The bit clears to 0 after the register has been read. |
lixianyu | 0:a4d8f5b3c546 | 1650 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1651 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1652 | * @see MPU6050_INTERRUPT_MOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1653 | */ |
lixianyu | 0:a4d8f5b3c546 | 1654 | bool MPU6050::getIntMotionStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1655 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_MOT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1656 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1657 | } |
lixianyu | 0:a4d8f5b3c546 | 1658 | /** Get Zero Motion Detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1659 | * This bit automatically sets to 1 when a Zero Motion Detection interrupt has |
lixianyu | 0:a4d8f5b3c546 | 1660 | * been generated. The bit clears to 0 after the register has been read. |
lixianyu | 0:a4d8f5b3c546 | 1661 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1662 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1663 | * @see MPU6050_INTERRUPT_ZMOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1664 | */ |
lixianyu | 0:a4d8f5b3c546 | 1665 | bool MPU6050::getIntZeroMotionStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1666 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_ZMOT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1667 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1668 | } |
lixianyu | 0:a4d8f5b3c546 | 1669 | /** Get FIFO Buffer Overflow interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1670 | * This bit automatically sets to 1 when a Free Fall interrupt has been |
lixianyu | 0:a4d8f5b3c546 | 1671 | * generated. The bit clears to 0 after the register has been read. |
lixianyu | 0:a4d8f5b3c546 | 1672 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1673 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1674 | * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT |
lixianyu | 0:a4d8f5b3c546 | 1675 | */ |
lixianyu | 0:a4d8f5b3c546 | 1676 | bool MPU6050::getIntFIFOBufferOverflowStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1677 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1678 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1679 | } |
lixianyu | 0:a4d8f5b3c546 | 1680 | /** Get I2C Master interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1681 | * This bit automatically sets to 1 when an I2C Master interrupt has been |
lixianyu | 0:a4d8f5b3c546 | 1682 | * generated. For a list of I2C Master interrupts, please refer to Register 54. |
lixianyu | 0:a4d8f5b3c546 | 1683 | * The bit clears to 0 after the register has been read. |
lixianyu | 0:a4d8f5b3c546 | 1684 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1685 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1686 | * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT |
lixianyu | 0:a4d8f5b3c546 | 1687 | */ |
lixianyu | 0:a4d8f5b3c546 | 1688 | bool MPU6050::getIntI2CMasterStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1689 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1690 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1691 | } |
lixianyu | 0:a4d8f5b3c546 | 1692 | /** Get Data Ready interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1693 | * This bit automatically sets to 1 when a Data Ready interrupt has been |
lixianyu | 0:a4d8f5b3c546 | 1694 | * generated. The bit clears to 0 after the register has been read. |
lixianyu | 0:a4d8f5b3c546 | 1695 | * @return Current interrupt status |
lixianyu | 0:a4d8f5b3c546 | 1696 | * @see MPU6050_RA_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 1697 | * @see MPU6050_INTERRUPT_DATA_RDY_BIT |
lixianyu | 0:a4d8f5b3c546 | 1698 | */ |
lixianyu | 0:a4d8f5b3c546 | 1699 | bool MPU6050::getIntDataReadyStatus() { |
lixianyu | 0:a4d8f5b3c546 | 1700 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1701 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1702 | } |
lixianyu | 0:a4d8f5b3c546 | 1703 | |
lixianyu | 0:a4d8f5b3c546 | 1704 | // ACCEL_*OUT_* registers |
lixianyu | 0:a4d8f5b3c546 | 1705 | |
lixianyu | 0:a4d8f5b3c546 | 1706 | /** Get raw 9-axis motion sensor readings (accel/gyro/compass). |
lixianyu | 0:a4d8f5b3c546 | 1707 | * FUNCTION NOT FULLY IMPLEMENTED YET. |
lixianyu | 0:a4d8f5b3c546 | 1708 | * @param ax 16-bit signed integer container for accelerometer X-axis value |
lixianyu | 0:a4d8f5b3c546 | 1709 | * @param ay 16-bit signed integer container for accelerometer Y-axis value |
lixianyu | 0:a4d8f5b3c546 | 1710 | * @param az 16-bit signed integer container for accelerometer Z-axis value |
lixianyu | 0:a4d8f5b3c546 | 1711 | * @param gx 16-bit signed integer container for gyroscope X-axis value |
lixianyu | 0:a4d8f5b3c546 | 1712 | * @param gy 16-bit signed integer container for gyroscope Y-axis value |
lixianyu | 0:a4d8f5b3c546 | 1713 | * @param gz 16-bit signed integer container for gyroscope Z-axis value |
lixianyu | 0:a4d8f5b3c546 | 1714 | * @param mx 16-bit signed integer container for magnetometer X-axis value |
lixianyu | 0:a4d8f5b3c546 | 1715 | * @param my 16-bit signed integer container for magnetometer Y-axis value |
lixianyu | 0:a4d8f5b3c546 | 1716 | * @param mz 16-bit signed integer container for magnetometer Z-axis value |
lixianyu | 0:a4d8f5b3c546 | 1717 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1718 | * @see getAcceleration() |
lixianyu | 0:a4d8f5b3c546 | 1719 | * @see getRotation() |
lixianyu | 0:a4d8f5b3c546 | 1720 | * @see MPU6050_RA_ACCEL_XOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1721 | */ |
lixianyu | 0:a4d8f5b3c546 | 1722 | void MPU6050::getMotion9(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz, int16_t* mx, int16_t* my, int16_t* mz) { |
lixianyu | 0:a4d8f5b3c546 | 1723 | getMotion6(ax, ay, az, gx, gy, gz); |
lixianyu | 0:a4d8f5b3c546 | 1724 | // TODO: magnetometer integration |
lixianyu | 0:a4d8f5b3c546 | 1725 | } |
lixianyu | 0:a4d8f5b3c546 | 1726 | /** Get raw 6-axis motion sensor readings (accel/gyro). |
lixianyu | 0:a4d8f5b3c546 | 1727 | * Retrieves all currently available motion sensor values. |
lixianyu | 0:a4d8f5b3c546 | 1728 | * @param ax 16-bit signed integer container for accelerometer X-axis value |
lixianyu | 0:a4d8f5b3c546 | 1729 | * @param ay 16-bit signed integer container for accelerometer Y-axis value |
lixianyu | 0:a4d8f5b3c546 | 1730 | * @param az 16-bit signed integer container for accelerometer Z-axis value |
lixianyu | 0:a4d8f5b3c546 | 1731 | * @param gx 16-bit signed integer container for gyroscope X-axis value |
lixianyu | 0:a4d8f5b3c546 | 1732 | * @param gy 16-bit signed integer container for gyroscope Y-axis value |
lixianyu | 0:a4d8f5b3c546 | 1733 | * @param gz 16-bit signed integer container for gyroscope Z-axis value |
lixianyu | 0:a4d8f5b3c546 | 1734 | * @see getAcceleration() |
lixianyu | 0:a4d8f5b3c546 | 1735 | * @see getRotation() |
lixianyu | 0:a4d8f5b3c546 | 1736 | * @see MPU6050_RA_ACCEL_XOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1737 | */ |
lixianyu | 0:a4d8f5b3c546 | 1738 | void MPU6050::getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz) { |
lixianyu | 0:a4d8f5b3c546 | 1739 | I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 14, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1740 | *ax = (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1741 | *ay = (((int16_t)buffer[2]) << 8) | buffer[3]; |
lixianyu | 0:a4d8f5b3c546 | 1742 | *az = (((int16_t)buffer[4]) << 8) | buffer[5]; |
lixianyu | 0:a4d8f5b3c546 | 1743 | *gx = (((int16_t)buffer[8]) << 8) | buffer[9]; |
lixianyu | 0:a4d8f5b3c546 | 1744 | *gy = (((int16_t)buffer[10]) << 8) | buffer[11]; |
lixianyu | 0:a4d8f5b3c546 | 1745 | *gz = (((int16_t)buffer[12]) << 8) | buffer[13]; |
lixianyu | 0:a4d8f5b3c546 | 1746 | } |
lixianyu | 0:a4d8f5b3c546 | 1747 | /** Get 3-axis accelerometer readings. |
lixianyu | 0:a4d8f5b3c546 | 1748 | * These registers store the most recent accelerometer measurements. |
lixianyu | 0:a4d8f5b3c546 | 1749 | * Accelerometer measurements are written to these registers at the Sample Rate |
lixianyu | 0:a4d8f5b3c546 | 1750 | * as defined in Register 25. |
lixianyu | 0:a4d8f5b3c546 | 1751 | * |
lixianyu | 0:a4d8f5b3c546 | 1752 | * The accelerometer measurement registers, along with the temperature |
lixianyu | 0:a4d8f5b3c546 | 1753 | * measurement registers, gyroscope measurement registers, and external sensor |
lixianyu | 0:a4d8f5b3c546 | 1754 | * data registers, are composed of two sets of registers: an internal register |
lixianyu | 0:a4d8f5b3c546 | 1755 | * set and a user-facing read register set. |
lixianyu | 0:a4d8f5b3c546 | 1756 | * |
lixianyu | 0:a4d8f5b3c546 | 1757 | * The data within the accelerometer sensors' internal register set is always |
lixianyu | 0:a4d8f5b3c546 | 1758 | * updated at the Sample Rate. Meanwhile, the user-facing read register set |
lixianyu | 0:a4d8f5b3c546 | 1759 | * duplicates the internal register set's data values whenever the serial |
lixianyu | 0:a4d8f5b3c546 | 1760 | * interface is idle. This guarantees that a burst read of sensor registers will |
lixianyu | 0:a4d8f5b3c546 | 1761 | * read measurements from the same sampling instant. Note that if burst reads |
lixianyu | 0:a4d8f5b3c546 | 1762 | * are not used, the user is responsible for ensuring a set of single byte reads |
lixianyu | 0:a4d8f5b3c546 | 1763 | * correspond to a single sampling instant by checking the Data Ready interrupt. |
lixianyu | 0:a4d8f5b3c546 | 1764 | * |
lixianyu | 0:a4d8f5b3c546 | 1765 | * Each 16-bit accelerometer measurement has a full scale defined in ACCEL_FS |
lixianyu | 0:a4d8f5b3c546 | 1766 | * (Register 28). For each full scale setting, the accelerometers' sensitivity |
lixianyu | 0:a4d8f5b3c546 | 1767 | * per LSB in ACCEL_xOUT is shown in the table below: |
lixianyu | 0:a4d8f5b3c546 | 1768 | * |
lixianyu | 0:a4d8f5b3c546 | 1769 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 1770 | * AFS_SEL | Full Scale Range | LSB Sensitivity |
lixianyu | 0:a4d8f5b3c546 | 1771 | * --------+------------------+---------------- |
lixianyu | 0:a4d8f5b3c546 | 1772 | * 0 | +/- 2g | 8192 LSB/mg |
lixianyu | 0:a4d8f5b3c546 | 1773 | * 1 | +/- 4g | 4096 LSB/mg |
lixianyu | 0:a4d8f5b3c546 | 1774 | * 2 | +/- 8g | 2048 LSB/mg |
lixianyu | 0:a4d8f5b3c546 | 1775 | * 3 | +/- 16g | 1024 LSB/mg |
lixianyu | 0:a4d8f5b3c546 | 1776 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 1777 | * |
lixianyu | 0:a4d8f5b3c546 | 1778 | * @param x 16-bit signed integer container for X-axis acceleration |
lixianyu | 0:a4d8f5b3c546 | 1779 | * @param y 16-bit signed integer container for Y-axis acceleration |
lixianyu | 0:a4d8f5b3c546 | 1780 | * @param z 16-bit signed integer container for Z-axis acceleration |
lixianyu | 0:a4d8f5b3c546 | 1781 | * @see MPU6050_RA_GYRO_XOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1782 | */ |
lixianyu | 0:a4d8f5b3c546 | 1783 | void MPU6050::getAcceleration(int16_t* x, int16_t* y, int16_t* z) { |
lixianyu | 0:a4d8f5b3c546 | 1784 | I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 6, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1785 | *x = (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1786 | *y = (((int16_t)buffer[2]) << 8) | buffer[3]; |
lixianyu | 0:a4d8f5b3c546 | 1787 | *z = (((int16_t)buffer[4]) << 8) | buffer[5]; |
lixianyu | 0:a4d8f5b3c546 | 1788 | } |
lixianyu | 0:a4d8f5b3c546 | 1789 | /** Get X-axis accelerometer reading. |
lixianyu | 0:a4d8f5b3c546 | 1790 | * @return X-axis acceleration measurement in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1791 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1792 | * @see MPU6050_RA_ACCEL_XOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1793 | */ |
lixianyu | 0:a4d8f5b3c546 | 1794 | int16_t MPU6050::getAccelerationX() { |
lixianyu | 0:a4d8f5b3c546 | 1795 | I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1796 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1797 | } |
lixianyu | 0:a4d8f5b3c546 | 1798 | /** Get Y-axis accelerometer reading. |
lixianyu | 0:a4d8f5b3c546 | 1799 | * @return Y-axis acceleration measurement in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1800 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1801 | * @see MPU6050_RA_ACCEL_YOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1802 | */ |
lixianyu | 0:a4d8f5b3c546 | 1803 | int16_t MPU6050::getAccelerationY() { |
lixianyu | 0:a4d8f5b3c546 | 1804 | I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_YOUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1805 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1806 | } |
lixianyu | 0:a4d8f5b3c546 | 1807 | /** Get Z-axis accelerometer reading. |
lixianyu | 0:a4d8f5b3c546 | 1808 | * @return Z-axis acceleration measurement in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1809 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1810 | * @see MPU6050_RA_ACCEL_ZOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1811 | */ |
lixianyu | 0:a4d8f5b3c546 | 1812 | int16_t MPU6050::getAccelerationZ() { |
lixianyu | 0:a4d8f5b3c546 | 1813 | I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_ZOUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1814 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1815 | } |
lixianyu | 0:a4d8f5b3c546 | 1816 | |
lixianyu | 0:a4d8f5b3c546 | 1817 | // TEMP_OUT_* registers |
lixianyu | 0:a4d8f5b3c546 | 1818 | |
lixianyu | 0:a4d8f5b3c546 | 1819 | /** Get current internal temperature. |
lixianyu | 0:a4d8f5b3c546 | 1820 | * @return Temperature reading in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1821 | * @see MPU6050_RA_TEMP_OUT_H |
lixianyu | 0:a4d8f5b3c546 | 1822 | */ |
lixianyu | 0:a4d8f5b3c546 | 1823 | int16_t MPU6050::getTemperature() { |
lixianyu | 0:a4d8f5b3c546 | 1824 | I2Cdev::readBytes(devAddr, MPU6050_RA_TEMP_OUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1825 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1826 | } |
lixianyu | 0:a4d8f5b3c546 | 1827 | |
lixianyu | 0:a4d8f5b3c546 | 1828 | // GYRO_*OUT_* registers |
lixianyu | 0:a4d8f5b3c546 | 1829 | |
lixianyu | 0:a4d8f5b3c546 | 1830 | /** Get 3-axis gyroscope readings. |
lixianyu | 0:a4d8f5b3c546 | 1831 | * These gyroscope measurement registers, along with the accelerometer |
lixianyu | 0:a4d8f5b3c546 | 1832 | * measurement registers, temperature measurement registers, and external sensor |
lixianyu | 0:a4d8f5b3c546 | 1833 | * data registers, are composed of two sets of registers: an internal register |
lixianyu | 0:a4d8f5b3c546 | 1834 | * set and a user-facing read register set. |
lixianyu | 0:a4d8f5b3c546 | 1835 | * The data within the gyroscope sensors' internal register set is always |
lixianyu | 0:a4d8f5b3c546 | 1836 | * updated at the Sample Rate. Meanwhile, the user-facing read register set |
lixianyu | 0:a4d8f5b3c546 | 1837 | * duplicates the internal register set's data values whenever the serial |
lixianyu | 0:a4d8f5b3c546 | 1838 | * interface is idle. This guarantees that a burst read of sensor registers will |
lixianyu | 0:a4d8f5b3c546 | 1839 | * read measurements from the same sampling instant. Note that if burst reads |
lixianyu | 0:a4d8f5b3c546 | 1840 | * are not used, the user is responsible for ensuring a set of single byte reads |
lixianyu | 0:a4d8f5b3c546 | 1841 | * correspond to a single sampling instant by checking the Data Ready interrupt. |
lixianyu | 0:a4d8f5b3c546 | 1842 | * |
lixianyu | 0:a4d8f5b3c546 | 1843 | * Each 16-bit gyroscope measurement has a full scale defined in FS_SEL |
lixianyu | 0:a4d8f5b3c546 | 1844 | * (Register 27). For each full scale setting, the gyroscopes' sensitivity per |
lixianyu | 0:a4d8f5b3c546 | 1845 | * LSB in GYRO_xOUT is shown in the table below: |
lixianyu | 0:a4d8f5b3c546 | 1846 | * |
lixianyu | 0:a4d8f5b3c546 | 1847 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 1848 | * FS_SEL | Full Scale Range | LSB Sensitivity |
lixianyu | 0:a4d8f5b3c546 | 1849 | * -------+--------------------+---------------- |
lixianyu | 0:a4d8f5b3c546 | 1850 | * 0 | +/- 250 degrees/s | 131 LSB/deg/s |
lixianyu | 0:a4d8f5b3c546 | 1851 | * 1 | +/- 500 degrees/s | 65.5 LSB/deg/s |
lixianyu | 0:a4d8f5b3c546 | 1852 | * 2 | +/- 1000 degrees/s | 32.8 LSB/deg/s |
lixianyu | 0:a4d8f5b3c546 | 1853 | * 3 | +/- 2000 degrees/s | 16.4 LSB/deg/s |
lixianyu | 0:a4d8f5b3c546 | 1854 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 1855 | * |
lixianyu | 0:a4d8f5b3c546 | 1856 | * @param x 16-bit signed integer container for X-axis rotation |
lixianyu | 0:a4d8f5b3c546 | 1857 | * @param y 16-bit signed integer container for Y-axis rotation |
lixianyu | 0:a4d8f5b3c546 | 1858 | * @param z 16-bit signed integer container for Z-axis rotation |
lixianyu | 0:a4d8f5b3c546 | 1859 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1860 | * @see MPU6050_RA_GYRO_XOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1861 | */ |
lixianyu | 0:a4d8f5b3c546 | 1862 | void MPU6050::getRotation(int16_t* x, int16_t* y, int16_t* z) { |
lixianyu | 0:a4d8f5b3c546 | 1863 | I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 6, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1864 | *x = (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1865 | *y = (((int16_t)buffer[2]) << 8) | buffer[3]; |
lixianyu | 0:a4d8f5b3c546 | 1866 | *z = (((int16_t)buffer[4]) << 8) | buffer[5]; |
lixianyu | 0:a4d8f5b3c546 | 1867 | } |
lixianyu | 0:a4d8f5b3c546 | 1868 | /** Get X-axis gyroscope reading. |
lixianyu | 0:a4d8f5b3c546 | 1869 | * @return X-axis rotation measurement in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1870 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1871 | * @see MPU6050_RA_GYRO_XOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1872 | */ |
lixianyu | 0:a4d8f5b3c546 | 1873 | int16_t MPU6050::getRotationX() { |
lixianyu | 0:a4d8f5b3c546 | 1874 | I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1875 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1876 | } |
lixianyu | 0:a4d8f5b3c546 | 1877 | /** Get Y-axis gyroscope reading. |
lixianyu | 0:a4d8f5b3c546 | 1878 | * @return Y-axis rotation measurement in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1879 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1880 | * @see MPU6050_RA_GYRO_YOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1881 | */ |
lixianyu | 0:a4d8f5b3c546 | 1882 | int16_t MPU6050::getRotationY() { |
lixianyu | 0:a4d8f5b3c546 | 1883 | I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_YOUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1884 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1885 | } |
lixianyu | 0:a4d8f5b3c546 | 1886 | /** Get Z-axis gyroscope reading. |
lixianyu | 0:a4d8f5b3c546 | 1887 | * @return Z-axis rotation measurement in 16-bit 2's complement format |
lixianyu | 0:a4d8f5b3c546 | 1888 | * @see getMotion6() |
lixianyu | 0:a4d8f5b3c546 | 1889 | * @see MPU6050_RA_GYRO_ZOUT_H |
lixianyu | 0:a4d8f5b3c546 | 1890 | */ |
lixianyu | 0:a4d8f5b3c546 | 1891 | int16_t MPU6050::getRotationZ() { |
lixianyu | 0:a4d8f5b3c546 | 1892 | I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_ZOUT_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1893 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1894 | } |
lixianyu | 0:a4d8f5b3c546 | 1895 | |
lixianyu | 0:a4d8f5b3c546 | 1896 | // EXT_SENS_DATA_* registers |
lixianyu | 0:a4d8f5b3c546 | 1897 | |
lixianyu | 0:a4d8f5b3c546 | 1898 | /** Read single byte from external sensor data register. |
lixianyu | 0:a4d8f5b3c546 | 1899 | * These registers store data read from external sensors by the Slave 0, 1, 2, |
lixianyu | 0:a4d8f5b3c546 | 1900 | * and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in |
lixianyu | 0:a4d8f5b3c546 | 1901 | * I2C_SLV4_DI (Register 53). |
lixianyu | 0:a4d8f5b3c546 | 1902 | * |
lixianyu | 0:a4d8f5b3c546 | 1903 | * External sensor data is written to these registers at the Sample Rate as |
lixianyu | 0:a4d8f5b3c546 | 1904 | * defined in Register 25. This access rate can be reduced by using the Slave |
lixianyu | 0:a4d8f5b3c546 | 1905 | * Delay Enable registers (Register 103). |
lixianyu | 0:a4d8f5b3c546 | 1906 | * |
lixianyu | 0:a4d8f5b3c546 | 1907 | * External sensor data registers, along with the gyroscope measurement |
lixianyu | 0:a4d8f5b3c546 | 1908 | * registers, accelerometer measurement registers, and temperature measurement |
lixianyu | 0:a4d8f5b3c546 | 1909 | * registers, are composed of two sets of registers: an internal register set |
lixianyu | 0:a4d8f5b3c546 | 1910 | * and a user-facing read register set. |
lixianyu | 0:a4d8f5b3c546 | 1911 | * |
lixianyu | 0:a4d8f5b3c546 | 1912 | * The data within the external sensors' internal register set is always updated |
lixianyu | 0:a4d8f5b3c546 | 1913 | * at the Sample Rate (or the reduced access rate) whenever the serial interface |
lixianyu | 0:a4d8f5b3c546 | 1914 | * is idle. This guarantees that a burst read of sensor registers will read |
lixianyu | 0:a4d8f5b3c546 | 1915 | * measurements from the same sampling instant. Note that if burst reads are not |
lixianyu | 0:a4d8f5b3c546 | 1916 | * used, the user is responsible for ensuring a set of single byte reads |
lixianyu | 0:a4d8f5b3c546 | 1917 | * correspond to a single sampling instant by checking the Data Ready interrupt. |
lixianyu | 0:a4d8f5b3c546 | 1918 | * |
lixianyu | 0:a4d8f5b3c546 | 1919 | * Data is placed in these external sensor data registers according to |
lixianyu | 0:a4d8f5b3c546 | 1920 | * I2C_SLV0_CTRL, I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39, |
lixianyu | 0:a4d8f5b3c546 | 1921 | * 42, 45, and 48). When more than zero bytes are read (I2C_SLVx_LEN > 0) from |
lixianyu | 0:a4d8f5b3c546 | 1922 | * an enabled slave (I2C_SLVx_EN = 1), the slave is read at the Sample Rate (as |
lixianyu | 0:a4d8f5b3c546 | 1923 | * defined in Register 25) or delayed rate (if specified in Register 52 and |
lixianyu | 0:a4d8f5b3c546 | 1924 | * 103). During each Sample cycle, slave reads are performed in order of Slave |
lixianyu | 0:a4d8f5b3c546 | 1925 | * number. If all slaves are enabled with more than zero bytes to be read, the |
lixianyu | 0:a4d8f5b3c546 | 1926 | * order will be Slave 0, followed by Slave 1, Slave 2, and Slave 3. |
lixianyu | 0:a4d8f5b3c546 | 1927 | * |
lixianyu | 0:a4d8f5b3c546 | 1928 | * Each enabled slave will have EXT_SENS_DATA registers associated with it by |
lixianyu | 0:a4d8f5b3c546 | 1929 | * number of bytes read (I2C_SLVx_LEN) in order of slave number, starting from |
lixianyu | 0:a4d8f5b3c546 | 1930 | * EXT_SENS_DATA_00. Note that this means enabling or disabling a slave may |
lixianyu | 0:a4d8f5b3c546 | 1931 | * change the higher numbered slaves' associated registers. Furthermore, if |
lixianyu | 0:a4d8f5b3c546 | 1932 | * fewer total bytes are being read from the external sensors as a result of |
lixianyu | 0:a4d8f5b3c546 | 1933 | * such a change, then the data remaining in the registers which no longer have |
lixianyu | 0:a4d8f5b3c546 | 1934 | * an associated slave device (i.e. high numbered registers) will remain in |
lixianyu | 0:a4d8f5b3c546 | 1935 | * these previously allocated registers unless reset. |
lixianyu | 0:a4d8f5b3c546 | 1936 | * |
lixianyu | 0:a4d8f5b3c546 | 1937 | * If the sum of the read lengths of all SLVx transactions exceed the number of |
lixianyu | 0:a4d8f5b3c546 | 1938 | * available EXT_SENS_DATA registers, the excess bytes will be dropped. There |
lixianyu | 0:a4d8f5b3c546 | 1939 | * are 24 EXT_SENS_DATA registers and hence the total read lengths between all |
lixianyu | 0:a4d8f5b3c546 | 1940 | * the slaves cannot be greater than 24 or some bytes will be lost. |
lixianyu | 0:a4d8f5b3c546 | 1941 | * |
lixianyu | 0:a4d8f5b3c546 | 1942 | * Note: Slave 4's behavior is distinct from that of Slaves 0-3. For further |
lixianyu | 0:a4d8f5b3c546 | 1943 | * information regarding the characteristics of Slave 4, please refer to |
lixianyu | 0:a4d8f5b3c546 | 1944 | * Registers 49 to 53. |
lixianyu | 0:a4d8f5b3c546 | 1945 | * |
lixianyu | 0:a4d8f5b3c546 | 1946 | * EXAMPLE: |
lixianyu | 0:a4d8f5b3c546 | 1947 | * Suppose that Slave 0 is enabled with 4 bytes to be read (I2C_SLV0_EN = 1 and |
lixianyu | 0:a4d8f5b3c546 | 1948 | * I2C_SLV0_LEN = 4) while Slave 1 is enabled with 2 bytes to be read so that |
lixianyu | 0:a4d8f5b3c546 | 1949 | * I2C_SLV1_EN = 1 and I2C_SLV1_LEN = 2. In such a situation, EXT_SENS_DATA _00 |
lixianyu | 0:a4d8f5b3c546 | 1950 | * through _03 will be associated with Slave 0, while EXT_SENS_DATA _04 and 05 |
lixianyu | 0:a4d8f5b3c546 | 1951 | * will be associated with Slave 1. If Slave 2 is enabled as well, registers |
lixianyu | 0:a4d8f5b3c546 | 1952 | * starting from EXT_SENS_DATA_06 will be allocated to Slave 2. |
lixianyu | 0:a4d8f5b3c546 | 1953 | * |
lixianyu | 0:a4d8f5b3c546 | 1954 | * If Slave 2 is disabled while Slave 3 is enabled in this same situation, then |
lixianyu | 0:a4d8f5b3c546 | 1955 | * registers starting from EXT_SENS_DATA_06 will be allocated to Slave 3 |
lixianyu | 0:a4d8f5b3c546 | 1956 | * instead. |
lixianyu | 0:a4d8f5b3c546 | 1957 | * |
lixianyu | 0:a4d8f5b3c546 | 1958 | * REGISTER ALLOCATION FOR DYNAMIC DISABLE VS. NORMAL DISABLE: |
lixianyu | 0:a4d8f5b3c546 | 1959 | * If a slave is disabled at any time, the space initially allocated to the |
lixianyu | 0:a4d8f5b3c546 | 1960 | * slave in the EXT_SENS_DATA register, will remain associated with that slave. |
lixianyu | 0:a4d8f5b3c546 | 1961 | * This is to avoid dynamic adjustment of the register allocation. |
lixianyu | 0:a4d8f5b3c546 | 1962 | * |
lixianyu | 0:a4d8f5b3c546 | 1963 | * The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all |
lixianyu | 0:a4d8f5b3c546 | 1964 | * slaves are disabled, or (2) the I2C_MST_RST bit is set (Register 106). |
lixianyu | 0:a4d8f5b3c546 | 1965 | * |
lixianyu | 0:a4d8f5b3c546 | 1966 | * This above is also true if one of the slaves gets NACKed and stops |
lixianyu | 0:a4d8f5b3c546 | 1967 | * functioning. |
lixianyu | 0:a4d8f5b3c546 | 1968 | * |
lixianyu | 0:a4d8f5b3c546 | 1969 | * @param position Starting position (0-23) |
lixianyu | 0:a4d8f5b3c546 | 1970 | * @return Byte read from register |
lixianyu | 0:a4d8f5b3c546 | 1971 | */ |
lixianyu | 0:a4d8f5b3c546 | 1972 | uint8_t MPU6050::getExternalSensorByte(int position) { |
lixianyu | 0:a4d8f5b3c546 | 1973 | I2Cdev::readByte(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1974 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 1975 | } |
lixianyu | 0:a4d8f5b3c546 | 1976 | /** Read word (2 bytes) from external sensor data registers. |
lixianyu | 0:a4d8f5b3c546 | 1977 | * @param position Starting position (0-21) |
lixianyu | 0:a4d8f5b3c546 | 1978 | * @return Word read from register |
lixianyu | 0:a4d8f5b3c546 | 1979 | * @see getExternalSensorByte() |
lixianyu | 0:a4d8f5b3c546 | 1980 | */ |
lixianyu | 0:a4d8f5b3c546 | 1981 | uint16_t MPU6050::getExternalSensorWord(int position) { |
lixianyu | 0:a4d8f5b3c546 | 1982 | I2Cdev::readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1983 | return (((uint16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 1984 | } |
lixianyu | 0:a4d8f5b3c546 | 1985 | /** Read double word (4 bytes) from external sensor data registers. |
lixianyu | 0:a4d8f5b3c546 | 1986 | * @param position Starting position (0-20) |
lixianyu | 0:a4d8f5b3c546 | 1987 | * @return Double word read from registers |
lixianyu | 0:a4d8f5b3c546 | 1988 | * @see getExternalSensorByte() |
lixianyu | 0:a4d8f5b3c546 | 1989 | */ |
lixianyu | 0:a4d8f5b3c546 | 1990 | uint32_t MPU6050::getExternalSensorDWord(int position) { |
lixianyu | 0:a4d8f5b3c546 | 1991 | I2Cdev::readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 4, buffer); |
lixianyu | 0:a4d8f5b3c546 | 1992 | return (((uint32_t)buffer[0]) << 24) | (((uint32_t)buffer[1]) << 16) | (((uint16_t)buffer[2]) << 8) | buffer[3]; |
lixianyu | 0:a4d8f5b3c546 | 1993 | } |
lixianyu | 0:a4d8f5b3c546 | 1994 | |
lixianyu | 0:a4d8f5b3c546 | 1995 | // MOT_DETECT_STATUS register |
lixianyu | 0:a4d8f5b3c546 | 1996 | |
lixianyu | 0:a4d8f5b3c546 | 1997 | /** Get X-axis negative motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 1998 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 1999 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2000 | * @see MPU6050_MOTION_MOT_XNEG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2001 | */ |
lixianyu | 0:a4d8f5b3c546 | 2002 | bool MPU6050::getXNegMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2003 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XNEG_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2004 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2005 | } |
lixianyu | 0:a4d8f5b3c546 | 2006 | /** Get X-axis positive motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 2007 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 2008 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2009 | * @see MPU6050_MOTION_MOT_XPOS_BIT |
lixianyu | 0:a4d8f5b3c546 | 2010 | */ |
lixianyu | 0:a4d8f5b3c546 | 2011 | bool MPU6050::getXPosMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2012 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XPOS_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2013 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2014 | } |
lixianyu | 0:a4d8f5b3c546 | 2015 | /** Get Y-axis negative motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 2016 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 2017 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2018 | * @see MPU6050_MOTION_MOT_YNEG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2019 | */ |
lixianyu | 0:a4d8f5b3c546 | 2020 | bool MPU6050::getYNegMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2021 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YNEG_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2022 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2023 | } |
lixianyu | 0:a4d8f5b3c546 | 2024 | /** Get Y-axis positive motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 2025 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 2026 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2027 | * @see MPU6050_MOTION_MOT_YPOS_BIT |
lixianyu | 0:a4d8f5b3c546 | 2028 | */ |
lixianyu | 0:a4d8f5b3c546 | 2029 | bool MPU6050::getYPosMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2030 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YPOS_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2031 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2032 | } |
lixianyu | 0:a4d8f5b3c546 | 2033 | /** Get Z-axis negative motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 2034 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 2035 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2036 | * @see MPU6050_MOTION_MOT_ZNEG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2037 | */ |
lixianyu | 0:a4d8f5b3c546 | 2038 | bool MPU6050::getZNegMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2039 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZNEG_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2040 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2041 | } |
lixianyu | 0:a4d8f5b3c546 | 2042 | /** Get Z-axis positive motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 2043 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 2044 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2045 | * @see MPU6050_MOTION_MOT_ZPOS_BIT |
lixianyu | 0:a4d8f5b3c546 | 2046 | */ |
lixianyu | 0:a4d8f5b3c546 | 2047 | bool MPU6050::getZPosMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2048 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZPOS_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2049 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2050 | } |
lixianyu | 0:a4d8f5b3c546 | 2051 | /** Get zero motion detection interrupt status. |
lixianyu | 0:a4d8f5b3c546 | 2052 | * @return Motion detection status |
lixianyu | 0:a4d8f5b3c546 | 2053 | * @see MPU6050_RA_MOT_DETECT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2054 | * @see MPU6050_MOTION_MOT_ZRMOT_BIT |
lixianyu | 0:a4d8f5b3c546 | 2055 | */ |
lixianyu | 0:a4d8f5b3c546 | 2056 | bool MPU6050::getZeroMotionDetected() { |
lixianyu | 0:a4d8f5b3c546 | 2057 | I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZRMOT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2058 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2059 | } |
lixianyu | 0:a4d8f5b3c546 | 2060 | |
lixianyu | 0:a4d8f5b3c546 | 2061 | // I2C_SLV*_DO register |
lixianyu | 0:a4d8f5b3c546 | 2062 | |
lixianyu | 0:a4d8f5b3c546 | 2063 | /** Write byte to Data Output container for specified slave. |
lixianyu | 0:a4d8f5b3c546 | 2064 | * This register holds the output data written into Slave when Slave is set to |
lixianyu | 0:a4d8f5b3c546 | 2065 | * write mode. For further information regarding Slave control, please |
lixianyu | 0:a4d8f5b3c546 | 2066 | * refer to Registers 37 to 39 and immediately following. |
lixianyu | 0:a4d8f5b3c546 | 2067 | * @param num Slave number (0-3) |
lixianyu | 0:a4d8f5b3c546 | 2068 | * @param data Byte to write |
lixianyu | 0:a4d8f5b3c546 | 2069 | * @see MPU6050_RA_I2C_SLV0_DO |
lixianyu | 0:a4d8f5b3c546 | 2070 | */ |
lixianyu | 0:a4d8f5b3c546 | 2071 | void MPU6050::setSlaveOutputByte(uint8_t num, uint8_t data) { |
lixianyu | 0:a4d8f5b3c546 | 2072 | if (num > 3) return; |
lixianyu | 0:a4d8f5b3c546 | 2073 | I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_DO + num, data); |
lixianyu | 0:a4d8f5b3c546 | 2074 | } |
lixianyu | 0:a4d8f5b3c546 | 2075 | |
lixianyu | 0:a4d8f5b3c546 | 2076 | // I2C_MST_DELAY_CTRL register |
lixianyu | 0:a4d8f5b3c546 | 2077 | |
lixianyu | 0:a4d8f5b3c546 | 2078 | /** Get external data shadow delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2079 | * This register is used to specify the timing of external sensor data |
lixianyu | 0:a4d8f5b3c546 | 2080 | * shadowing. When DELAY_ES_SHADOW is set to 1, shadowing of external |
lixianyu | 0:a4d8f5b3c546 | 2081 | * sensor data is delayed until all data has been received. |
lixianyu | 0:a4d8f5b3c546 | 2082 | * @return Current external data shadow delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2083 | * @see MPU6050_RA_I2C_MST_DELAY_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2084 | * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT |
lixianyu | 0:a4d8f5b3c546 | 2085 | */ |
lixianyu | 0:a4d8f5b3c546 | 2086 | bool MPU6050::getExternalShadowDelayEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2087 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2088 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2089 | } |
lixianyu | 0:a4d8f5b3c546 | 2090 | /** Set external data shadow delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2091 | * @param enabled New external data shadow delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2092 | * @see getExternalShadowDelayEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2093 | * @see MPU6050_RA_I2C_MST_DELAY_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2094 | * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT |
lixianyu | 0:a4d8f5b3c546 | 2095 | */ |
lixianyu | 0:a4d8f5b3c546 | 2096 | void MPU6050::setExternalShadowDelayEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2097 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2098 | } |
lixianyu | 0:a4d8f5b3c546 | 2099 | /** Get slave delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2100 | * When a particular slave delay is enabled, the rate of access for the that |
lixianyu | 0:a4d8f5b3c546 | 2101 | * slave device is reduced. When a slave's access rate is decreased relative to |
lixianyu | 0:a4d8f5b3c546 | 2102 | * the Sample Rate, the slave is accessed every: |
lixianyu | 0:a4d8f5b3c546 | 2103 | * |
lixianyu | 0:a4d8f5b3c546 | 2104 | * 1 / (1 + I2C_MST_DLY) Samples |
lixianyu | 0:a4d8f5b3c546 | 2105 | * |
lixianyu | 0:a4d8f5b3c546 | 2106 | * This base Sample Rate in turn is determined by SMPLRT_DIV (register * 25) |
lixianyu | 0:a4d8f5b3c546 | 2107 | * and DLPF_CFG (register 26). |
lixianyu | 0:a4d8f5b3c546 | 2108 | * |
lixianyu | 0:a4d8f5b3c546 | 2109 | * For further information regarding I2C_MST_DLY, please refer to register 52. |
lixianyu | 0:a4d8f5b3c546 | 2110 | * For further information regarding the Sample Rate, please refer to register 25. |
lixianyu | 0:a4d8f5b3c546 | 2111 | * |
lixianyu | 0:a4d8f5b3c546 | 2112 | * @param num Slave number (0-4) |
lixianyu | 0:a4d8f5b3c546 | 2113 | * @return Current slave delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2114 | * @see MPU6050_RA_I2C_MST_DELAY_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2115 | * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 2116 | */ |
lixianyu | 0:a4d8f5b3c546 | 2117 | bool MPU6050::getSlaveDelayEnabled(uint8_t num) { |
lixianyu | 0:a4d8f5b3c546 | 2118 | // MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT is 4, SLV3 is 3, etc. |
lixianyu | 0:a4d8f5b3c546 | 2119 | if (num > 4) return 0; |
lixianyu | 0:a4d8f5b3c546 | 2120 | I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2121 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2122 | } |
lixianyu | 0:a4d8f5b3c546 | 2123 | /** Set slave delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2124 | * @param num Slave number (0-4) |
lixianyu | 0:a4d8f5b3c546 | 2125 | * @param enabled New slave delay enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2126 | * @see MPU6050_RA_I2C_MST_DELAY_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2127 | * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 2128 | */ |
lixianyu | 0:a4d8f5b3c546 | 2129 | void MPU6050::setSlaveDelayEnabled(uint8_t num, bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2130 | I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2131 | } |
lixianyu | 0:a4d8f5b3c546 | 2132 | |
lixianyu | 0:a4d8f5b3c546 | 2133 | // SIGNAL_PATH_RESET register |
lixianyu | 0:a4d8f5b3c546 | 2134 | |
lixianyu | 0:a4d8f5b3c546 | 2135 | /** Reset gyroscope signal path. |
lixianyu | 0:a4d8f5b3c546 | 2136 | * The reset will revert the signal path analog to digital converters and |
lixianyu | 0:a4d8f5b3c546 | 2137 | * filters to their power up configurations. |
lixianyu | 0:a4d8f5b3c546 | 2138 | * @see MPU6050_RA_SIGNAL_PATH_RESET |
lixianyu | 0:a4d8f5b3c546 | 2139 | * @see MPU6050_PATHRESET_GYRO_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2140 | */ |
lixianyu | 0:a4d8f5b3c546 | 2141 | void MPU6050::resetGyroscopePath() { |
lixianyu | 0:a4d8f5b3c546 | 2142 | I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_GYRO_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2143 | } |
lixianyu | 0:a4d8f5b3c546 | 2144 | /** Reset accelerometer signal path. |
lixianyu | 0:a4d8f5b3c546 | 2145 | * The reset will revert the signal path analog to digital converters and |
lixianyu | 0:a4d8f5b3c546 | 2146 | * filters to their power up configurations. |
lixianyu | 0:a4d8f5b3c546 | 2147 | * @see MPU6050_RA_SIGNAL_PATH_RESET |
lixianyu | 0:a4d8f5b3c546 | 2148 | * @see MPU6050_PATHRESET_ACCEL_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2149 | */ |
lixianyu | 0:a4d8f5b3c546 | 2150 | void MPU6050::resetAccelerometerPath() { |
lixianyu | 0:a4d8f5b3c546 | 2151 | I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_ACCEL_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2152 | } |
lixianyu | 0:a4d8f5b3c546 | 2153 | /** Reset temperature sensor signal path. |
lixianyu | 0:a4d8f5b3c546 | 2154 | * The reset will revert the signal path analog to digital converters and |
lixianyu | 0:a4d8f5b3c546 | 2155 | * filters to their power up configurations. |
lixianyu | 0:a4d8f5b3c546 | 2156 | * @see MPU6050_RA_SIGNAL_PATH_RESET |
lixianyu | 0:a4d8f5b3c546 | 2157 | * @see MPU6050_PATHRESET_TEMP_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2158 | */ |
lixianyu | 0:a4d8f5b3c546 | 2159 | void MPU6050::resetTemperaturePath() { |
lixianyu | 0:a4d8f5b3c546 | 2160 | I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_TEMP_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2161 | } |
lixianyu | 0:a4d8f5b3c546 | 2162 | |
lixianyu | 0:a4d8f5b3c546 | 2163 | // MOT_DETECT_CTRL register |
lixianyu | 0:a4d8f5b3c546 | 2164 | |
lixianyu | 0:a4d8f5b3c546 | 2165 | /** Get accelerometer power-on delay. |
lixianyu | 0:a4d8f5b3c546 | 2166 | * The accelerometer data path provides samples to the sensor registers, Motion |
lixianyu | 0:a4d8f5b3c546 | 2167 | * detection, Zero Motion detection, and Free Fall detection modules. The |
lixianyu | 0:a4d8f5b3c546 | 2168 | * signal path contains filters which must be flushed on wake-up with new |
lixianyu | 0:a4d8f5b3c546 | 2169 | * samples before the detection modules begin operations. The default wake-up |
lixianyu | 0:a4d8f5b3c546 | 2170 | * delay, of 4ms can be lengthened by up to 3ms. This additional delay is |
lixianyu | 0:a4d8f5b3c546 | 2171 | * specified in ACCEL_ON_DELAY in units of 1 LSB = 1 ms. The user may select |
lixianyu | 0:a4d8f5b3c546 | 2172 | * any value above zero unless instructed otherwise by InvenSense. Please refer |
lixianyu | 0:a4d8f5b3c546 | 2173 | * to Section 8 of the MPU-6000/MPU-6050 Product Specification document for |
lixianyu | 0:a4d8f5b3c546 | 2174 | * further information regarding the detection modules. |
lixianyu | 0:a4d8f5b3c546 | 2175 | * @return Current accelerometer power-on delay |
lixianyu | 0:a4d8f5b3c546 | 2176 | * @see MPU6050_RA_MOT_DETECT_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2177 | * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT |
lixianyu | 0:a4d8f5b3c546 | 2178 | */ |
lixianyu | 0:a4d8f5b3c546 | 2179 | uint8_t MPU6050::getAccelerometerPowerOnDelay() { |
lixianyu | 0:a4d8f5b3c546 | 2180 | I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT, MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2181 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2182 | } |
lixianyu | 0:a4d8f5b3c546 | 2183 | /** Set accelerometer power-on delay. |
lixianyu | 0:a4d8f5b3c546 | 2184 | * @param delay New accelerometer power-on delay (0-3) |
lixianyu | 0:a4d8f5b3c546 | 2185 | * @see getAccelerometerPowerOnDelay() |
lixianyu | 0:a4d8f5b3c546 | 2186 | * @see MPU6050_RA_MOT_DETECT_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2187 | * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT |
lixianyu | 0:a4d8f5b3c546 | 2188 | */ |
lixianyu | 0:a4d8f5b3c546 | 2189 | void MPU6050::setAccelerometerPowerOnDelay(uint8_t delay) { |
lixianyu | 0:a4d8f5b3c546 | 2190 | I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT, MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, delay); |
lixianyu | 0:a4d8f5b3c546 | 2191 | } |
lixianyu | 0:a4d8f5b3c546 | 2192 | /** Get Free Fall detection counter decrement configuration. |
lixianyu | 0:a4d8f5b3c546 | 2193 | * Detection is registered by the Free Fall detection module after accelerometer |
lixianyu | 0:a4d8f5b3c546 | 2194 | * measurements meet their respective threshold conditions over a specified |
lixianyu | 0:a4d8f5b3c546 | 2195 | * number of samples. When the threshold conditions are met, the corresponding |
lixianyu | 0:a4d8f5b3c546 | 2196 | * detection counter increments by 1. The user may control the rate at which the |
lixianyu | 0:a4d8f5b3c546 | 2197 | * detection counter decrements when the threshold condition is not met by |
lixianyu | 0:a4d8f5b3c546 | 2198 | * configuring FF_COUNT. The decrement rate can be set according to the |
lixianyu | 0:a4d8f5b3c546 | 2199 | * following table: |
lixianyu | 0:a4d8f5b3c546 | 2200 | * |
lixianyu | 0:a4d8f5b3c546 | 2201 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 2202 | * FF_COUNT | Counter Decrement |
lixianyu | 0:a4d8f5b3c546 | 2203 | * ---------+------------------ |
lixianyu | 0:a4d8f5b3c546 | 2204 | * 0 | Reset |
lixianyu | 0:a4d8f5b3c546 | 2205 | * 1 | 1 |
lixianyu | 0:a4d8f5b3c546 | 2206 | * 2 | 2 |
lixianyu | 0:a4d8f5b3c546 | 2207 | * 3 | 4 |
lixianyu | 0:a4d8f5b3c546 | 2208 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 2209 | * |
lixianyu | 0:a4d8f5b3c546 | 2210 | * When FF_COUNT is configured to 0 (reset), any non-qualifying sample will |
lixianyu | 0:a4d8f5b3c546 | 2211 | * reset the counter to 0. For further information on Free Fall detection, |
lixianyu | 0:a4d8f5b3c546 | 2212 | * please refer to Registers 29 to 32. |
lixianyu | 0:a4d8f5b3c546 | 2213 | * |
lixianyu | 0:a4d8f5b3c546 | 2214 | * @return Current decrement configuration |
lixianyu | 0:a4d8f5b3c546 | 2215 | * @see MPU6050_RA_MOT_DETECT_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2216 | * @see MPU6050_DETECT_FF_COUNT_BIT |
lixianyu | 0:a4d8f5b3c546 | 2217 | */ |
lixianyu | 0:a4d8f5b3c546 | 2218 | uint8_t MPU6050::getFreefallDetectionCounterDecrement() { |
lixianyu | 0:a4d8f5b3c546 | 2219 | I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2220 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2221 | } |
lixianyu | 0:a4d8f5b3c546 | 2222 | /** Set Free Fall detection counter decrement configuration. |
lixianyu | 0:a4d8f5b3c546 | 2223 | * @param decrement New decrement configuration value |
lixianyu | 0:a4d8f5b3c546 | 2224 | * @see getFreefallDetectionCounterDecrement() |
lixianyu | 0:a4d8f5b3c546 | 2225 | * @see MPU6050_RA_MOT_DETECT_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2226 | * @see MPU6050_DETECT_FF_COUNT_BIT |
lixianyu | 0:a4d8f5b3c546 | 2227 | */ |
lixianyu | 0:a4d8f5b3c546 | 2228 | void MPU6050::setFreefallDetectionCounterDecrement(uint8_t decrement) { |
lixianyu | 0:a4d8f5b3c546 | 2229 | I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH, decrement); |
lixianyu | 0:a4d8f5b3c546 | 2230 | } |
lixianyu | 0:a4d8f5b3c546 | 2231 | /** Get Motion detection counter decrement configuration. |
lixianyu | 0:a4d8f5b3c546 | 2232 | * Detection is registered by the Motion detection module after accelerometer |
lixianyu | 0:a4d8f5b3c546 | 2233 | * measurements meet their respective threshold conditions over a specified |
lixianyu | 0:a4d8f5b3c546 | 2234 | * number of samples. When the threshold conditions are met, the corresponding |
lixianyu | 0:a4d8f5b3c546 | 2235 | * detection counter increments by 1. The user may control the rate at which the |
lixianyu | 0:a4d8f5b3c546 | 2236 | * detection counter decrements when the threshold condition is not met by |
lixianyu | 0:a4d8f5b3c546 | 2237 | * configuring MOT_COUNT. The decrement rate can be set according to the |
lixianyu | 0:a4d8f5b3c546 | 2238 | * following table: |
lixianyu | 0:a4d8f5b3c546 | 2239 | * |
lixianyu | 0:a4d8f5b3c546 | 2240 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 2241 | * MOT_COUNT | Counter Decrement |
lixianyu | 0:a4d8f5b3c546 | 2242 | * ----------+------------------ |
lixianyu | 0:a4d8f5b3c546 | 2243 | * 0 | Reset |
lixianyu | 0:a4d8f5b3c546 | 2244 | * 1 | 1 |
lixianyu | 0:a4d8f5b3c546 | 2245 | * 2 | 2 |
lixianyu | 0:a4d8f5b3c546 | 2246 | * 3 | 4 |
lixianyu | 0:a4d8f5b3c546 | 2247 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 2248 | * |
lixianyu | 0:a4d8f5b3c546 | 2249 | * When MOT_COUNT is configured to 0 (reset), any non-qualifying sample will |
lixianyu | 0:a4d8f5b3c546 | 2250 | * reset the counter to 0. For further information on Motion detection, |
lixianyu | 0:a4d8f5b3c546 | 2251 | * please refer to Registers 29 to 32. |
lixianyu | 0:a4d8f5b3c546 | 2252 | * |
lixianyu | 0:a4d8f5b3c546 | 2253 | */ |
lixianyu | 0:a4d8f5b3c546 | 2254 | uint8_t MPU6050::getMotionDetectionCounterDecrement() { |
lixianyu | 0:a4d8f5b3c546 | 2255 | I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2256 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2257 | } |
lixianyu | 0:a4d8f5b3c546 | 2258 | /** Set Motion detection counter decrement configuration. |
lixianyu | 0:a4d8f5b3c546 | 2259 | * @param decrement New decrement configuration value |
lixianyu | 0:a4d8f5b3c546 | 2260 | * @see getMotionDetectionCounterDecrement() |
lixianyu | 0:a4d8f5b3c546 | 2261 | * @see MPU6050_RA_MOT_DETECT_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2262 | * @see MPU6050_DETECT_MOT_COUNT_BIT |
lixianyu | 0:a4d8f5b3c546 | 2263 | */ |
lixianyu | 0:a4d8f5b3c546 | 2264 | void MPU6050::setMotionDetectionCounterDecrement(uint8_t decrement) { |
lixianyu | 0:a4d8f5b3c546 | 2265 | I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH, decrement); |
lixianyu | 0:a4d8f5b3c546 | 2266 | } |
lixianyu | 0:a4d8f5b3c546 | 2267 | |
lixianyu | 0:a4d8f5b3c546 | 2268 | // USER_CTRL register |
lixianyu | 0:a4d8f5b3c546 | 2269 | |
lixianyu | 0:a4d8f5b3c546 | 2270 | /** Get FIFO enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2271 | * When this bit is set to 0, the FIFO buffer is disabled. The FIFO buffer |
lixianyu | 0:a4d8f5b3c546 | 2272 | * cannot be written to or read from while disabled. The FIFO buffer's state |
lixianyu | 0:a4d8f5b3c546 | 2273 | * does not change unless the MPU-60X0 is power cycled. |
lixianyu | 0:a4d8f5b3c546 | 2274 | * @return Current FIFO enabled status |
lixianyu | 0:a4d8f5b3c546 | 2275 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2276 | * @see MPU6050_USERCTRL_FIFO_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 2277 | */ |
lixianyu | 0:a4d8f5b3c546 | 2278 | bool MPU6050::getFIFOEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2279 | I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2280 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2281 | } |
lixianyu | 0:a4d8f5b3c546 | 2282 | /** Set FIFO enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2283 | * @param enabled New FIFO enabled status |
lixianyu | 0:a4d8f5b3c546 | 2284 | * @see getFIFOEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2285 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2286 | * @see MPU6050_USERCTRL_FIFO_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 2287 | */ |
lixianyu | 0:a4d8f5b3c546 | 2288 | void MPU6050::setFIFOEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2289 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2290 | } |
lixianyu | 0:a4d8f5b3c546 | 2291 | /** Get I2C Master Mode enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2292 | * When this mode is enabled, the MPU-60X0 acts as the I2C Master to the |
lixianyu | 0:a4d8f5b3c546 | 2293 | * external sensor slave devices on the auxiliary I2C bus. When this bit is |
lixianyu | 0:a4d8f5b3c546 | 2294 | * cleared to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically |
lixianyu | 0:a4d8f5b3c546 | 2295 | * driven by the primary I2C bus (SDA and SCL). This is a precondition to |
lixianyu | 0:a4d8f5b3c546 | 2296 | * enabling Bypass Mode. For further information regarding Bypass Mode, please |
lixianyu | 0:a4d8f5b3c546 | 2297 | * refer to Register 55. |
lixianyu | 0:a4d8f5b3c546 | 2298 | * @return Current I2C Master Mode enabled status |
lixianyu | 0:a4d8f5b3c546 | 2299 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2300 | * @see MPU6050_USERCTRL_I2C_MST_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 2301 | */ |
lixianyu | 0:a4d8f5b3c546 | 2302 | bool MPU6050::getI2CMasterModeEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2303 | I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2304 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2305 | } |
lixianyu | 0:a4d8f5b3c546 | 2306 | /** Set I2C Master Mode enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2307 | * @param enabled New I2C Master Mode enabled status |
lixianyu | 0:a4d8f5b3c546 | 2308 | * @see getI2CMasterModeEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2309 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2310 | * @see MPU6050_USERCTRL_I2C_MST_EN_BIT |
lixianyu | 0:a4d8f5b3c546 | 2311 | */ |
lixianyu | 0:a4d8f5b3c546 | 2312 | void MPU6050::setI2CMasterModeEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2313 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2314 | } |
lixianyu | 0:a4d8f5b3c546 | 2315 | /** Switch from I2C to SPI mode (MPU-6000 only) |
lixianyu | 0:a4d8f5b3c546 | 2316 | * If this is set, the primary SPI interface will be enabled in place of the |
lixianyu | 0:a4d8f5b3c546 | 2317 | * disabled primary I2C interface. |
lixianyu | 0:a4d8f5b3c546 | 2318 | */ |
lixianyu | 0:a4d8f5b3c546 | 2319 | void MPU6050::switchSPIEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2320 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_IF_DIS_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2321 | } |
lixianyu | 0:a4d8f5b3c546 | 2322 | /** Reset the FIFO. |
lixianyu | 0:a4d8f5b3c546 | 2323 | * This bit resets the FIFO buffer when set to 1 while FIFO_EN equals 0. This |
lixianyu | 0:a4d8f5b3c546 | 2324 | * bit automatically clears to 0 after the reset has been triggered. |
lixianyu | 0:a4d8f5b3c546 | 2325 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2326 | * @see MPU6050_USERCTRL_FIFO_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2327 | */ |
lixianyu | 0:a4d8f5b3c546 | 2328 | void MPU6050::resetFIFO() { |
lixianyu | 0:a4d8f5b3c546 | 2329 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2330 | } |
lixianyu | 0:a4d8f5b3c546 | 2331 | /** Reset the I2C Master. |
lixianyu | 0:a4d8f5b3c546 | 2332 | * This bit resets the I2C Master when set to 1 while I2C_MST_EN equals 0. |
lixianyu | 0:a4d8f5b3c546 | 2333 | * This bit automatically clears to 0 after the reset has been triggered. |
lixianyu | 0:a4d8f5b3c546 | 2334 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2335 | * @see MPU6050_USERCTRL_I2C_MST_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2336 | */ |
lixianyu | 0:a4d8f5b3c546 | 2337 | void MPU6050::resetI2CMaster() { |
lixianyu | 0:a4d8f5b3c546 | 2338 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2339 | } |
lixianyu | 0:a4d8f5b3c546 | 2340 | /** Reset all sensor registers and signal paths. |
lixianyu | 0:a4d8f5b3c546 | 2341 | * When set to 1, this bit resets the signal paths for all sensors (gyroscopes, |
lixianyu | 0:a4d8f5b3c546 | 2342 | * accelerometers, and temperature sensor). This operation will also clear the |
lixianyu | 0:a4d8f5b3c546 | 2343 | * sensor registers. This bit automatically clears to 0 after the reset has been |
lixianyu | 0:a4d8f5b3c546 | 2344 | * triggered. |
lixianyu | 0:a4d8f5b3c546 | 2345 | * |
lixianyu | 0:a4d8f5b3c546 | 2346 | * When resetting only the signal path (and not the sensor registers), please |
lixianyu | 0:a4d8f5b3c546 | 2347 | * use Register 104, SIGNAL_PATH_RESET. |
lixianyu | 0:a4d8f5b3c546 | 2348 | * |
lixianyu | 0:a4d8f5b3c546 | 2349 | * @see MPU6050_RA_USER_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2350 | * @see MPU6050_USERCTRL_SIG_COND_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2351 | */ |
lixianyu | 0:a4d8f5b3c546 | 2352 | void MPU6050::resetSensors() { |
lixianyu | 0:a4d8f5b3c546 | 2353 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_SIG_COND_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2354 | } |
lixianyu | 0:a4d8f5b3c546 | 2355 | |
lixianyu | 0:a4d8f5b3c546 | 2356 | // PWR_MGMT_1 register |
lixianyu | 0:a4d8f5b3c546 | 2357 | |
lixianyu | 0:a4d8f5b3c546 | 2358 | /** Trigger a full device reset. |
lixianyu | 0:a4d8f5b3c546 | 2359 | * A small delay of ~50ms may be desirable after triggering a reset. |
lixianyu | 0:a4d8f5b3c546 | 2360 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2361 | * @see MPU6050_PWR1_DEVICE_RESET_BIT |
lixianyu | 0:a4d8f5b3c546 | 2362 | */ |
lixianyu | 0:a4d8f5b3c546 | 2363 | void MPU6050::reset() { |
lixianyu | 0:a4d8f5b3c546 | 2364 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_DEVICE_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2365 | } |
lixianyu | 0:a4d8f5b3c546 | 2366 | /** Get sleep mode status. |
lixianyu | 0:a4d8f5b3c546 | 2367 | * Setting the SLEEP bit in the register puts the device into very low power |
lixianyu | 0:a4d8f5b3c546 | 2368 | * sleep mode. In this mode, only the serial interface and internal registers |
lixianyu | 0:a4d8f5b3c546 | 2369 | * remain active, allowing for a very low standby current. Clearing this bit |
lixianyu | 0:a4d8f5b3c546 | 2370 | * puts the device back into normal mode. To save power, the individual standby |
lixianyu | 0:a4d8f5b3c546 | 2371 | * selections for each of the gyros should be used if any gyro axis is not used |
lixianyu | 0:a4d8f5b3c546 | 2372 | * by the application. |
lixianyu | 0:a4d8f5b3c546 | 2373 | * @return Current sleep mode enabled status |
lixianyu | 0:a4d8f5b3c546 | 2374 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2375 | * @see MPU6050_PWR1_SLEEP_BIT |
lixianyu | 0:a4d8f5b3c546 | 2376 | */ |
lixianyu | 0:a4d8f5b3c546 | 2377 | bool MPU6050::getSleepEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2378 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2379 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2380 | } |
lixianyu | 0:a4d8f5b3c546 | 2381 | /** Set sleep mode status. |
lixianyu | 0:a4d8f5b3c546 | 2382 | * @param enabled New sleep mode enabled status |
lixianyu | 0:a4d8f5b3c546 | 2383 | * @see getSleepEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2384 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2385 | * @see MPU6050_PWR1_SLEEP_BIT |
lixianyu | 0:a4d8f5b3c546 | 2386 | */ |
lixianyu | 0:a4d8f5b3c546 | 2387 | void MPU6050::setSleepEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2388 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2389 | } |
lixianyu | 0:a4d8f5b3c546 | 2390 | /** Get wake cycle enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2391 | * When this bit is set to 1 and SLEEP is disabled, the MPU-60X0 will cycle |
lixianyu | 0:a4d8f5b3c546 | 2392 | * between sleep mode and waking up to take a single sample of data from active |
lixianyu | 0:a4d8f5b3c546 | 2393 | * sensors at a rate determined by LP_WAKE_CTRL (register 108). |
lixianyu | 0:a4d8f5b3c546 | 2394 | * @return Current sleep mode enabled status |
lixianyu | 0:a4d8f5b3c546 | 2395 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2396 | * @see MPU6050_PWR1_CYCLE_BIT |
lixianyu | 0:a4d8f5b3c546 | 2397 | */ |
lixianyu | 0:a4d8f5b3c546 | 2398 | bool MPU6050::getWakeCycleEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2399 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2400 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2401 | } |
lixianyu | 0:a4d8f5b3c546 | 2402 | /** Set wake cycle enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2403 | * @param enabled New sleep mode enabled status |
lixianyu | 0:a4d8f5b3c546 | 2404 | * @see getWakeCycleEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2405 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2406 | * @see MPU6050_PWR1_CYCLE_BIT |
lixianyu | 0:a4d8f5b3c546 | 2407 | */ |
lixianyu | 0:a4d8f5b3c546 | 2408 | void MPU6050::setWakeCycleEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2409 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2410 | } |
lixianyu | 0:a4d8f5b3c546 | 2411 | /** Get temperature sensor enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2412 | * Control the usage of the internal temperature sensor. |
lixianyu | 0:a4d8f5b3c546 | 2413 | * |
lixianyu | 0:a4d8f5b3c546 | 2414 | * Note: this register stores the *disabled* value, but for consistency with the |
lixianyu | 0:a4d8f5b3c546 | 2415 | * rest of the code, the function is named and used with standard true/false |
lixianyu | 0:a4d8f5b3c546 | 2416 | * values to indicate whether the sensor is enabled or disabled, respectively. |
lixianyu | 0:a4d8f5b3c546 | 2417 | * |
lixianyu | 0:a4d8f5b3c546 | 2418 | * @return Current temperature sensor enabled status |
lixianyu | 0:a4d8f5b3c546 | 2419 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2420 | * @see MPU6050_PWR1_TEMP_DIS_BIT |
lixianyu | 0:a4d8f5b3c546 | 2421 | */ |
lixianyu | 0:a4d8f5b3c546 | 2422 | bool MPU6050::getTempSensorEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2423 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2424 | return buffer[0] == 0; // 1 is actually disabled here |
lixianyu | 0:a4d8f5b3c546 | 2425 | } |
lixianyu | 0:a4d8f5b3c546 | 2426 | /** Set temperature sensor enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2427 | * Note: this register stores the *disabled* value, but for consistency with the |
lixianyu | 0:a4d8f5b3c546 | 2428 | * rest of the code, the function is named and used with standard true/false |
lixianyu | 0:a4d8f5b3c546 | 2429 | * values to indicate whether the sensor is enabled or disabled, respectively. |
lixianyu | 0:a4d8f5b3c546 | 2430 | * |
lixianyu | 0:a4d8f5b3c546 | 2431 | * @param enabled New temperature sensor enabled status |
lixianyu | 0:a4d8f5b3c546 | 2432 | * @see getTempSensorEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2433 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2434 | * @see MPU6050_PWR1_TEMP_DIS_BIT |
lixianyu | 0:a4d8f5b3c546 | 2435 | */ |
lixianyu | 0:a4d8f5b3c546 | 2436 | void MPU6050::setTempSensorEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2437 | // 1 is actually disabled here |
lixianyu | 0:a4d8f5b3c546 | 2438 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, !enabled); |
lixianyu | 0:a4d8f5b3c546 | 2439 | } |
lixianyu | 0:a4d8f5b3c546 | 2440 | /** Get clock source setting. |
lixianyu | 0:a4d8f5b3c546 | 2441 | * @return Current clock source setting |
lixianyu | 0:a4d8f5b3c546 | 2442 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2443 | * @see MPU6050_PWR1_CLKSEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 2444 | * @see MPU6050_PWR1_CLKSEL_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 2445 | */ |
lixianyu | 0:a4d8f5b3c546 | 2446 | uint8_t MPU6050::getClockSource() { |
lixianyu | 0:a4d8f5b3c546 | 2447 | I2Cdev::readBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2448 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2449 | } |
lixianyu | 0:a4d8f5b3c546 | 2450 | /** Set clock source setting. |
lixianyu | 0:a4d8f5b3c546 | 2451 | * An internal 8MHz oscillator, gyroscope based clock, or external sources can |
lixianyu | 0:a4d8f5b3c546 | 2452 | * be selected as the MPU-60X0 clock source. When the internal 8 MHz oscillator |
lixianyu | 0:a4d8f5b3c546 | 2453 | * or an external source is chosen as the clock source, the MPU-60X0 can operate |
lixianyu | 0:a4d8f5b3c546 | 2454 | * in low power modes with the gyroscopes disabled. |
lixianyu | 0:a4d8f5b3c546 | 2455 | * |
lixianyu | 0:a4d8f5b3c546 | 2456 | * Upon power up, the MPU-60X0 clock source defaults to the internal oscillator. |
lixianyu | 0:a4d8f5b3c546 | 2457 | * However, it is highly recommended that the device be configured to use one of |
lixianyu | 0:a4d8f5b3c546 | 2458 | * the gyroscopes (or an external clock source) as the clock reference for |
lixianyu | 0:a4d8f5b3c546 | 2459 | * improved stability. The clock source can be selected according to the following table: |
lixianyu | 0:a4d8f5b3c546 | 2460 | * |
lixianyu | 0:a4d8f5b3c546 | 2461 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 2462 | * CLK_SEL | Clock Source |
lixianyu | 0:a4d8f5b3c546 | 2463 | * --------+-------------------------------------- |
lixianyu | 0:a4d8f5b3c546 | 2464 | * 0 | Internal oscillator |
lixianyu | 0:a4d8f5b3c546 | 2465 | * 1 | PLL with X Gyro reference |
lixianyu | 0:a4d8f5b3c546 | 2466 | * 2 | PLL with Y Gyro reference |
lixianyu | 0:a4d8f5b3c546 | 2467 | * 3 | PLL with Z Gyro reference |
lixianyu | 0:a4d8f5b3c546 | 2468 | * 4 | PLL with external 32.768kHz reference |
lixianyu | 0:a4d8f5b3c546 | 2469 | * 5 | PLL with external 19.2MHz reference |
lixianyu | 0:a4d8f5b3c546 | 2470 | * 6 | Reserved |
lixianyu | 0:a4d8f5b3c546 | 2471 | * 7 | Stops the clock and keeps the timing generator in reset |
lixianyu | 0:a4d8f5b3c546 | 2472 | * </pre> |
lixianyu | 0:a4d8f5b3c546 | 2473 | * |
lixianyu | 0:a4d8f5b3c546 | 2474 | * @param source New clock source setting |
lixianyu | 0:a4d8f5b3c546 | 2475 | * @see getClockSource() |
lixianyu | 0:a4d8f5b3c546 | 2476 | * @see MPU6050_RA_PWR_MGMT_1 |
lixianyu | 0:a4d8f5b3c546 | 2477 | * @see MPU6050_PWR1_CLKSEL_BIT |
lixianyu | 0:a4d8f5b3c546 | 2478 | * @see MPU6050_PWR1_CLKSEL_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 2479 | */ |
lixianyu | 0:a4d8f5b3c546 | 2480 | void MPU6050::setClockSource(uint8_t source) { |
lixianyu | 0:a4d8f5b3c546 | 2481 | I2Cdev::writeBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source); |
lixianyu | 0:a4d8f5b3c546 | 2482 | } |
lixianyu | 0:a4d8f5b3c546 | 2483 | |
lixianyu | 0:a4d8f5b3c546 | 2484 | // PWR_MGMT_2 register |
lixianyu | 0:a4d8f5b3c546 | 2485 | |
lixianyu | 0:a4d8f5b3c546 | 2486 | /** Get wake frequency in Accel-Only Low Power Mode. |
lixianyu | 0:a4d8f5b3c546 | 2487 | * The MPU-60X0 can be put into Accerlerometer Only Low Power Mode by setting |
lixianyu | 0:a4d8f5b3c546 | 2488 | * PWRSEL to 1 in the Power Management 1 register (Register 107). In this mode, |
lixianyu | 0:a4d8f5b3c546 | 2489 | * the device will power off all devices except for the primary I2C interface, |
lixianyu | 0:a4d8f5b3c546 | 2490 | * waking only the accelerometer at fixed intervals to take a single |
lixianyu | 0:a4d8f5b3c546 | 2491 | * measurement. The frequency of wake-ups can be configured with LP_WAKE_CTRL |
lixianyu | 0:a4d8f5b3c546 | 2492 | * as shown below: |
lixianyu | 0:a4d8f5b3c546 | 2493 | * |
lixianyu | 0:a4d8f5b3c546 | 2494 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 2495 | * LP_WAKE_CTRL | Wake-up Frequency |
lixianyu | 0:a4d8f5b3c546 | 2496 | * -------------+------------------ |
lixianyu | 0:a4d8f5b3c546 | 2497 | * 0 | 1.25 Hz |
lixianyu | 0:a4d8f5b3c546 | 2498 | * 1 | 2.5 Hz |
lixianyu | 0:a4d8f5b3c546 | 2499 | * 2 | 5 Hz |
lixianyu | 0:a4d8f5b3c546 | 2500 | * 3 | 10 Hz |
lixianyu | 0:a4d8f5b3c546 | 2501 | * <pre> |
lixianyu | 0:a4d8f5b3c546 | 2502 | * |
lixianyu | 0:a4d8f5b3c546 | 2503 | * For further information regarding the MPU-60X0's power modes, please refer to |
lixianyu | 0:a4d8f5b3c546 | 2504 | * Register 107. |
lixianyu | 0:a4d8f5b3c546 | 2505 | * |
lixianyu | 0:a4d8f5b3c546 | 2506 | * @return Current wake frequency |
lixianyu | 0:a4d8f5b3c546 | 2507 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2508 | */ |
lixianyu | 0:a4d8f5b3c546 | 2509 | uint8_t MPU6050::getWakeFrequency() { |
lixianyu | 0:a4d8f5b3c546 | 2510 | I2Cdev::readBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2511 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2512 | } |
lixianyu | 0:a4d8f5b3c546 | 2513 | /** Set wake frequency in Accel-Only Low Power Mode. |
lixianyu | 0:a4d8f5b3c546 | 2514 | * @param frequency New wake frequency |
lixianyu | 0:a4d8f5b3c546 | 2515 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2516 | */ |
lixianyu | 0:a4d8f5b3c546 | 2517 | void MPU6050::setWakeFrequency(uint8_t frequency) { |
lixianyu | 0:a4d8f5b3c546 | 2518 | I2Cdev::writeBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH, frequency); |
lixianyu | 0:a4d8f5b3c546 | 2519 | } |
lixianyu | 0:a4d8f5b3c546 | 2520 | |
lixianyu | 0:a4d8f5b3c546 | 2521 | /** Get X-axis accelerometer standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2522 | * If enabled, the X-axis will not gather or report data (or use power). |
lixianyu | 0:a4d8f5b3c546 | 2523 | * @return Current X-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2524 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2525 | * @see MPU6050_PWR2_STBY_XA_BIT |
lixianyu | 0:a4d8f5b3c546 | 2526 | */ |
lixianyu | 0:a4d8f5b3c546 | 2527 | bool MPU6050::getStandbyXAccelEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2528 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2529 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2530 | } |
lixianyu | 0:a4d8f5b3c546 | 2531 | /** Set X-axis accelerometer standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2532 | * @param New X-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2533 | * @see getStandbyXAccelEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2534 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2535 | * @see MPU6050_PWR2_STBY_XA_BIT |
lixianyu | 0:a4d8f5b3c546 | 2536 | */ |
lixianyu | 0:a4d8f5b3c546 | 2537 | void MPU6050::setStandbyXAccelEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2538 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2539 | } |
lixianyu | 0:a4d8f5b3c546 | 2540 | /** Get Y-axis accelerometer standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2541 | * If enabled, the Y-axis will not gather or report data (or use power). |
lixianyu | 0:a4d8f5b3c546 | 2542 | * @return Current Y-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2543 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2544 | * @see MPU6050_PWR2_STBY_YA_BIT |
lixianyu | 0:a4d8f5b3c546 | 2545 | */ |
lixianyu | 0:a4d8f5b3c546 | 2546 | bool MPU6050::getStandbyYAccelEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2547 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2548 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2549 | } |
lixianyu | 0:a4d8f5b3c546 | 2550 | /** Set Y-axis accelerometer standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2551 | * @param New Y-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2552 | * @see getStandbyYAccelEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2553 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2554 | * @see MPU6050_PWR2_STBY_YA_BIT |
lixianyu | 0:a4d8f5b3c546 | 2555 | */ |
lixianyu | 0:a4d8f5b3c546 | 2556 | void MPU6050::setStandbyYAccelEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2557 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2558 | } |
lixianyu | 0:a4d8f5b3c546 | 2559 | /** Get Z-axis accelerometer standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2560 | * If enabled, the Z-axis will not gather or report data (or use power). |
lixianyu | 0:a4d8f5b3c546 | 2561 | * @return Current Z-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2562 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2563 | * @see MPU6050_PWR2_STBY_ZA_BIT |
lixianyu | 0:a4d8f5b3c546 | 2564 | */ |
lixianyu | 0:a4d8f5b3c546 | 2565 | bool MPU6050::getStandbyZAccelEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2566 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2567 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2568 | } |
lixianyu | 0:a4d8f5b3c546 | 2569 | /** Set Z-axis accelerometer standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2570 | * @param New Z-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2571 | * @see getStandbyZAccelEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2572 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2573 | * @see MPU6050_PWR2_STBY_ZA_BIT |
lixianyu | 0:a4d8f5b3c546 | 2574 | */ |
lixianyu | 0:a4d8f5b3c546 | 2575 | void MPU6050::setStandbyZAccelEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2576 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2577 | } |
lixianyu | 0:a4d8f5b3c546 | 2578 | /** Get X-axis gyroscope standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2579 | * If enabled, the X-axis will not gather or report data (or use power). |
lixianyu | 0:a4d8f5b3c546 | 2580 | * @return Current X-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2581 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2582 | * @see MPU6050_PWR2_STBY_XG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2583 | */ |
lixianyu | 0:a4d8f5b3c546 | 2584 | bool MPU6050::getStandbyXGyroEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2585 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2586 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2587 | } |
lixianyu | 0:a4d8f5b3c546 | 2588 | /** Set X-axis gyroscope standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2589 | * @param New X-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2590 | * @see getStandbyXGyroEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2591 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2592 | * @see MPU6050_PWR2_STBY_XG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2593 | */ |
lixianyu | 0:a4d8f5b3c546 | 2594 | void MPU6050::setStandbyXGyroEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2595 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2596 | } |
lixianyu | 0:a4d8f5b3c546 | 2597 | /** Get Y-axis gyroscope standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2598 | * If enabled, the Y-axis will not gather or report data (or use power). |
lixianyu | 0:a4d8f5b3c546 | 2599 | * @return Current Y-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2600 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2601 | * @see MPU6050_PWR2_STBY_YG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2602 | */ |
lixianyu | 0:a4d8f5b3c546 | 2603 | bool MPU6050::getStandbyYGyroEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2604 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2605 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2606 | } |
lixianyu | 0:a4d8f5b3c546 | 2607 | /** Set Y-axis gyroscope standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2608 | * @param New Y-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2609 | * @see getStandbyYGyroEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2610 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2611 | * @see MPU6050_PWR2_STBY_YG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2612 | */ |
lixianyu | 0:a4d8f5b3c546 | 2613 | void MPU6050::setStandbyYGyroEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2614 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2615 | } |
lixianyu | 0:a4d8f5b3c546 | 2616 | /** Get Z-axis gyroscope standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2617 | * If enabled, the Z-axis will not gather or report data (or use power). |
lixianyu | 0:a4d8f5b3c546 | 2618 | * @return Current Z-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2619 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2620 | * @see MPU6050_PWR2_STBY_ZG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2621 | */ |
lixianyu | 0:a4d8f5b3c546 | 2622 | bool MPU6050::getStandbyZGyroEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2623 | I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2624 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2625 | } |
lixianyu | 0:a4d8f5b3c546 | 2626 | /** Set Z-axis gyroscope standby enabled status. |
lixianyu | 0:a4d8f5b3c546 | 2627 | * @param New Z-axis standby enabled status |
lixianyu | 0:a4d8f5b3c546 | 2628 | * @see getStandbyZGyroEnabled() |
lixianyu | 0:a4d8f5b3c546 | 2629 | * @see MPU6050_RA_PWR_MGMT_2 |
lixianyu | 0:a4d8f5b3c546 | 2630 | * @see MPU6050_PWR2_STBY_ZG_BIT |
lixianyu | 0:a4d8f5b3c546 | 2631 | */ |
lixianyu | 0:a4d8f5b3c546 | 2632 | void MPU6050::setStandbyZGyroEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2633 | I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2634 | } |
lixianyu | 0:a4d8f5b3c546 | 2635 | |
lixianyu | 0:a4d8f5b3c546 | 2636 | // FIFO_COUNT* registers |
lixianyu | 0:a4d8f5b3c546 | 2637 | |
lixianyu | 0:a4d8f5b3c546 | 2638 | /** Get current FIFO buffer size. |
lixianyu | 0:a4d8f5b3c546 | 2639 | * This value indicates the number of bytes stored in the FIFO buffer. This |
lixianyu | 0:a4d8f5b3c546 | 2640 | * number is in turn the number of bytes that can be read from the FIFO buffer |
lixianyu | 0:a4d8f5b3c546 | 2641 | * and it is directly proportional to the number of samples available given the |
lixianyu | 0:a4d8f5b3c546 | 2642 | * set of sensor data bound to be stored in the FIFO (register 35 and 36). |
lixianyu | 0:a4d8f5b3c546 | 2643 | * @return Current FIFO buffer size |
lixianyu | 0:a4d8f5b3c546 | 2644 | */ |
lixianyu | 0:a4d8f5b3c546 | 2645 | uint16_t MPU6050::getFIFOCount() { |
lixianyu | 0:a4d8f5b3c546 | 2646 | I2Cdev::readBytes(devAddr, MPU6050_RA_FIFO_COUNTH, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2647 | return (((uint16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2648 | } |
lixianyu | 0:a4d8f5b3c546 | 2649 | |
lixianyu | 0:a4d8f5b3c546 | 2650 | // FIFO_R_W register |
lixianyu | 0:a4d8f5b3c546 | 2651 | |
lixianyu | 0:a4d8f5b3c546 | 2652 | /** Get byte from FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 2653 | * This register is used to read and write data from the FIFO buffer. Data is |
lixianyu | 0:a4d8f5b3c546 | 2654 | * written to the FIFO in order of register number (from lowest to highest). If |
lixianyu | 0:a4d8f5b3c546 | 2655 | * all the FIFO enable flags (see below) are enabled and all External Sensor |
lixianyu | 0:a4d8f5b3c546 | 2656 | * Data registers (Registers 73 to 96) are associated with a Slave device, the |
lixianyu | 0:a4d8f5b3c546 | 2657 | * contents of registers 59 through 96 will be written in order at the Sample |
lixianyu | 0:a4d8f5b3c546 | 2658 | * Rate. |
lixianyu | 0:a4d8f5b3c546 | 2659 | * |
lixianyu | 0:a4d8f5b3c546 | 2660 | * The contents of the sensor data registers (Registers 59 to 96) are written |
lixianyu | 0:a4d8f5b3c546 | 2661 | * into the FIFO buffer when their corresponding FIFO enable flags are set to 1 |
lixianyu | 0:a4d8f5b3c546 | 2662 | * in FIFO_EN (Register 35). An additional flag for the sensor data registers |
lixianyu | 0:a4d8f5b3c546 | 2663 | * associated with I2C Slave 3 can be found in I2C_MST_CTRL (Register 36). |
lixianyu | 0:a4d8f5b3c546 | 2664 | * |
lixianyu | 0:a4d8f5b3c546 | 2665 | * If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is |
lixianyu | 0:a4d8f5b3c546 | 2666 | * automatically set to 1. This bit is located in INT_STATUS (Register 58). |
lixianyu | 0:a4d8f5b3c546 | 2667 | * When the FIFO buffer has overflowed, the oldest data will be lost and new |
lixianyu | 0:a4d8f5b3c546 | 2668 | * data will be written to the FIFO. |
lixianyu | 0:a4d8f5b3c546 | 2669 | * |
lixianyu | 0:a4d8f5b3c546 | 2670 | * If the FIFO buffer is empty, reading this register will return the last byte |
lixianyu | 0:a4d8f5b3c546 | 2671 | * that was previously read from the FIFO until new data is available. The user |
lixianyu | 0:a4d8f5b3c546 | 2672 | * should check FIFO_COUNT to ensure that the FIFO buffer is not read when |
lixianyu | 0:a4d8f5b3c546 | 2673 | * empty. |
lixianyu | 0:a4d8f5b3c546 | 2674 | * |
lixianyu | 0:a4d8f5b3c546 | 2675 | * @return Byte from FIFO buffer |
lixianyu | 0:a4d8f5b3c546 | 2676 | */ |
lixianyu | 0:a4d8f5b3c546 | 2677 | uint8_t MPU6050::getFIFOByte() { |
lixianyu | 0:a4d8f5b3c546 | 2678 | I2Cdev::readByte(devAddr, MPU6050_RA_FIFO_R_W, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2679 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2680 | } |
lixianyu | 0:a4d8f5b3c546 | 2681 | void MPU6050::getFIFOBytes(uint8_t *data, uint8_t length) { |
lixianyu | 0:a4d8f5b3c546 | 2682 | I2Cdev::readBytes(devAddr, MPU6050_RA_FIFO_R_W, length, data); |
lixianyu | 0:a4d8f5b3c546 | 2683 | } |
lixianyu | 0:a4d8f5b3c546 | 2684 | /** Write byte to FIFO buffer. |
lixianyu | 0:a4d8f5b3c546 | 2685 | * @see getFIFOByte() |
lixianyu | 0:a4d8f5b3c546 | 2686 | * @see MPU6050_RA_FIFO_R_W |
lixianyu | 0:a4d8f5b3c546 | 2687 | */ |
lixianyu | 0:a4d8f5b3c546 | 2688 | void MPU6050::setFIFOByte(uint8_t data) { |
lixianyu | 0:a4d8f5b3c546 | 2689 | I2Cdev::writeByte(devAddr, MPU6050_RA_FIFO_R_W, data); |
lixianyu | 0:a4d8f5b3c546 | 2690 | } |
lixianyu | 0:a4d8f5b3c546 | 2691 | |
lixianyu | 0:a4d8f5b3c546 | 2692 | // WHO_AM_I register |
lixianyu | 0:a4d8f5b3c546 | 2693 | |
lixianyu | 0:a4d8f5b3c546 | 2694 | /** Get Device ID. |
lixianyu | 0:a4d8f5b3c546 | 2695 | * This register is used to verify the identity of the device (0b110100, 0x34). |
lixianyu | 0:a4d8f5b3c546 | 2696 | * @return Device ID (6 bits only! should be 0x34) |
lixianyu | 0:a4d8f5b3c546 | 2697 | * @see MPU6050_RA_WHO_AM_I |
lixianyu | 0:a4d8f5b3c546 | 2698 | * @see MPU6050_WHO_AM_I_BIT |
lixianyu | 0:a4d8f5b3c546 | 2699 | * @see MPU6050_WHO_AM_I_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 2700 | */ |
lixianyu | 0:a4d8f5b3c546 | 2701 | uint8_t MPU6050::getDeviceID() { |
lixianyu | 0:a4d8f5b3c546 | 2702 | I2Cdev::readBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2703 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2704 | } |
lixianyu | 0:a4d8f5b3c546 | 2705 | /** Set Device ID. |
lixianyu | 0:a4d8f5b3c546 | 2706 | * Write a new ID into the WHO_AM_I register (no idea why this should ever be |
lixianyu | 0:a4d8f5b3c546 | 2707 | * necessary though). |
lixianyu | 0:a4d8f5b3c546 | 2708 | * @param id New device ID to set. |
lixianyu | 0:a4d8f5b3c546 | 2709 | * @see getDeviceID() |
lixianyu | 0:a4d8f5b3c546 | 2710 | * @see MPU6050_RA_WHO_AM_I |
lixianyu | 0:a4d8f5b3c546 | 2711 | * @see MPU6050_WHO_AM_I_BIT |
lixianyu | 0:a4d8f5b3c546 | 2712 | * @see MPU6050_WHO_AM_I_LENGTH |
lixianyu | 0:a4d8f5b3c546 | 2713 | */ |
lixianyu | 0:a4d8f5b3c546 | 2714 | void MPU6050::setDeviceID(uint8_t id) { |
lixianyu | 0:a4d8f5b3c546 | 2715 | I2Cdev::writeBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, id); |
lixianyu | 0:a4d8f5b3c546 | 2716 | } |
lixianyu | 0:a4d8f5b3c546 | 2717 | |
lixianyu | 0:a4d8f5b3c546 | 2718 | // ======== UNDOCUMENTED/DMP REGISTERS/METHODS ======== |
lixianyu | 0:a4d8f5b3c546 | 2719 | |
lixianyu | 0:a4d8f5b3c546 | 2720 | // XG_OFFS_TC register |
lixianyu | 0:a4d8f5b3c546 | 2721 | |
lixianyu | 0:a4d8f5b3c546 | 2722 | uint8_t MPU6050::getOTPBankValid() { |
lixianyu | 0:a4d8f5b3c546 | 2723 | I2Cdev::readBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2724 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2725 | } |
lixianyu | 0:a4d8f5b3c546 | 2726 | void MPU6050::setOTPBankValid(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2727 | I2Cdev::writeBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2728 | } |
lixianyu | 0:a4d8f5b3c546 | 2729 | int8_t MPU6050::getXGyroOffsetTC() { |
lixianyu | 0:a4d8f5b3c546 | 2730 | I2Cdev::readBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2731 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2732 | } |
lixianyu | 0:a4d8f5b3c546 | 2733 | void MPU6050::setXGyroOffsetTC(int8_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2734 | I2Cdev::writeBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset); |
lixianyu | 0:a4d8f5b3c546 | 2735 | } |
lixianyu | 0:a4d8f5b3c546 | 2736 | |
lixianyu | 0:a4d8f5b3c546 | 2737 | // YG_OFFS_TC register |
lixianyu | 0:a4d8f5b3c546 | 2738 | |
lixianyu | 0:a4d8f5b3c546 | 2739 | int8_t MPU6050::getYGyroOffsetTC() { |
lixianyu | 0:a4d8f5b3c546 | 2740 | I2Cdev::readBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2741 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2742 | } |
lixianyu | 0:a4d8f5b3c546 | 2743 | void MPU6050::setYGyroOffsetTC(int8_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2744 | I2Cdev::writeBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset); |
lixianyu | 0:a4d8f5b3c546 | 2745 | } |
lixianyu | 0:a4d8f5b3c546 | 2746 | |
lixianyu | 0:a4d8f5b3c546 | 2747 | // ZG_OFFS_TC register |
lixianyu | 0:a4d8f5b3c546 | 2748 | |
lixianyu | 0:a4d8f5b3c546 | 2749 | int8_t MPU6050::getZGyroOffsetTC() { |
lixianyu | 0:a4d8f5b3c546 | 2750 | I2Cdev::readBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2751 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2752 | } |
lixianyu | 0:a4d8f5b3c546 | 2753 | void MPU6050::setZGyroOffsetTC(int8_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2754 | I2Cdev::writeBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset); |
lixianyu | 0:a4d8f5b3c546 | 2755 | } |
lixianyu | 0:a4d8f5b3c546 | 2756 | |
lixianyu | 0:a4d8f5b3c546 | 2757 | // X_FINE_GAIN register |
lixianyu | 0:a4d8f5b3c546 | 2758 | |
lixianyu | 0:a4d8f5b3c546 | 2759 | int8_t MPU6050::getXFineGain() { |
lixianyu | 0:a4d8f5b3c546 | 2760 | I2Cdev::readByte(devAddr, MPU6050_RA_X_FINE_GAIN, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2761 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2762 | } |
lixianyu | 0:a4d8f5b3c546 | 2763 | void MPU6050::setXFineGain(int8_t gain) { |
lixianyu | 0:a4d8f5b3c546 | 2764 | I2Cdev::writeByte(devAddr, MPU6050_RA_X_FINE_GAIN, gain); |
lixianyu | 0:a4d8f5b3c546 | 2765 | } |
lixianyu | 0:a4d8f5b3c546 | 2766 | |
lixianyu | 0:a4d8f5b3c546 | 2767 | // Y_FINE_GAIN register |
lixianyu | 0:a4d8f5b3c546 | 2768 | |
lixianyu | 0:a4d8f5b3c546 | 2769 | int8_t MPU6050::getYFineGain() { |
lixianyu | 0:a4d8f5b3c546 | 2770 | I2Cdev::readByte(devAddr, MPU6050_RA_Y_FINE_GAIN, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2771 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2772 | } |
lixianyu | 0:a4d8f5b3c546 | 2773 | void MPU6050::setYFineGain(int8_t gain) { |
lixianyu | 0:a4d8f5b3c546 | 2774 | I2Cdev::writeByte(devAddr, MPU6050_RA_Y_FINE_GAIN, gain); |
lixianyu | 0:a4d8f5b3c546 | 2775 | } |
lixianyu | 0:a4d8f5b3c546 | 2776 | |
lixianyu | 0:a4d8f5b3c546 | 2777 | // Z_FINE_GAIN register |
lixianyu | 0:a4d8f5b3c546 | 2778 | |
lixianyu | 0:a4d8f5b3c546 | 2779 | int8_t MPU6050::getZFineGain() { |
lixianyu | 0:a4d8f5b3c546 | 2780 | I2Cdev::readByte(devAddr, MPU6050_RA_Z_FINE_GAIN, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2781 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2782 | } |
lixianyu | 0:a4d8f5b3c546 | 2783 | void MPU6050::setZFineGain(int8_t gain) { |
lixianyu | 0:a4d8f5b3c546 | 2784 | I2Cdev::writeByte(devAddr, MPU6050_RA_Z_FINE_GAIN, gain); |
lixianyu | 0:a4d8f5b3c546 | 2785 | } |
lixianyu | 0:a4d8f5b3c546 | 2786 | |
lixianyu | 0:a4d8f5b3c546 | 2787 | // XA_OFFS_* registers |
lixianyu | 0:a4d8f5b3c546 | 2788 | |
lixianyu | 0:a4d8f5b3c546 | 2789 | int16_t MPU6050::getXAccelOffset() { |
lixianyu | 0:a4d8f5b3c546 | 2790 | I2Cdev::readBytes(devAddr, MPU6050_RA_XA_OFFS_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2791 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2792 | } |
lixianyu | 0:a4d8f5b3c546 | 2793 | void MPU6050::setXAccelOffset(int16_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2794 | I2Cdev::writeWord(devAddr, MPU6050_RA_XA_OFFS_H, offset); |
lixianyu | 0:a4d8f5b3c546 | 2795 | } |
lixianyu | 0:a4d8f5b3c546 | 2796 | |
lixianyu | 0:a4d8f5b3c546 | 2797 | // YA_OFFS_* register |
lixianyu | 0:a4d8f5b3c546 | 2798 | |
lixianyu | 0:a4d8f5b3c546 | 2799 | int16_t MPU6050::getYAccelOffset() { |
lixianyu | 0:a4d8f5b3c546 | 2800 | I2Cdev::readBytes(devAddr, MPU6050_RA_YA_OFFS_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2801 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2802 | } |
lixianyu | 0:a4d8f5b3c546 | 2803 | void MPU6050::setYAccelOffset(int16_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2804 | I2Cdev::writeWord(devAddr, MPU6050_RA_YA_OFFS_H, offset); |
lixianyu | 0:a4d8f5b3c546 | 2805 | } |
lixianyu | 0:a4d8f5b3c546 | 2806 | |
lixianyu | 0:a4d8f5b3c546 | 2807 | // ZA_OFFS_* register |
lixianyu | 0:a4d8f5b3c546 | 2808 | |
lixianyu | 0:a4d8f5b3c546 | 2809 | int16_t MPU6050::getZAccelOffset() { |
lixianyu | 0:a4d8f5b3c546 | 2810 | I2Cdev::readBytes(devAddr, MPU6050_RA_ZA_OFFS_H, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2811 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2812 | } |
lixianyu | 0:a4d8f5b3c546 | 2813 | void MPU6050::setZAccelOffset(int16_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2814 | I2Cdev::writeWord(devAddr, MPU6050_RA_ZA_OFFS_H, offset); |
lixianyu | 0:a4d8f5b3c546 | 2815 | } |
lixianyu | 0:a4d8f5b3c546 | 2816 | |
lixianyu | 0:a4d8f5b3c546 | 2817 | // XG_OFFS_USR* registers |
lixianyu | 0:a4d8f5b3c546 | 2818 | |
lixianyu | 0:a4d8f5b3c546 | 2819 | int16_t MPU6050::getXGyroOffset() { |
lixianyu | 0:a4d8f5b3c546 | 2820 | I2Cdev::readBytes(devAddr, MPU6050_RA_XG_OFFS_USRH, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2821 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2822 | } |
lixianyu | 0:a4d8f5b3c546 | 2823 | void MPU6050::setXGyroOffset(int16_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2824 | I2Cdev::writeWord(devAddr, MPU6050_RA_XG_OFFS_USRH, offset); |
lixianyu | 0:a4d8f5b3c546 | 2825 | } |
lixianyu | 0:a4d8f5b3c546 | 2826 | |
lixianyu | 0:a4d8f5b3c546 | 2827 | // YG_OFFS_USR* register |
lixianyu | 0:a4d8f5b3c546 | 2828 | |
lixianyu | 0:a4d8f5b3c546 | 2829 | int16_t MPU6050::getYGyroOffset() { |
lixianyu | 0:a4d8f5b3c546 | 2830 | I2Cdev::readBytes(devAddr, MPU6050_RA_YG_OFFS_USRH, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2831 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2832 | } |
lixianyu | 0:a4d8f5b3c546 | 2833 | void MPU6050::setYGyroOffset(int16_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2834 | I2Cdev::writeWord(devAddr, MPU6050_RA_YG_OFFS_USRH, offset); |
lixianyu | 0:a4d8f5b3c546 | 2835 | } |
lixianyu | 0:a4d8f5b3c546 | 2836 | |
lixianyu | 0:a4d8f5b3c546 | 2837 | // ZG_OFFS_USR* register |
lixianyu | 0:a4d8f5b3c546 | 2838 | |
lixianyu | 0:a4d8f5b3c546 | 2839 | int16_t MPU6050::getZGyroOffset() { |
lixianyu | 0:a4d8f5b3c546 | 2840 | I2Cdev::readBytes(devAddr, MPU6050_RA_ZG_OFFS_USRH, 2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2841 | return (((int16_t)buffer[0]) << 8) | buffer[1]; |
lixianyu | 0:a4d8f5b3c546 | 2842 | } |
lixianyu | 0:a4d8f5b3c546 | 2843 | void MPU6050::setZGyroOffset(int16_t offset) { |
lixianyu | 0:a4d8f5b3c546 | 2844 | I2Cdev::writeWord(devAddr, MPU6050_RA_ZG_OFFS_USRH, offset); |
lixianyu | 0:a4d8f5b3c546 | 2845 | } |
lixianyu | 0:a4d8f5b3c546 | 2846 | |
lixianyu | 0:a4d8f5b3c546 | 2847 | // INT_ENABLE register (DMP functions) |
lixianyu | 0:a4d8f5b3c546 | 2848 | |
lixianyu | 0:a4d8f5b3c546 | 2849 | bool MPU6050::getIntPLLReadyEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2850 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2851 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2852 | } |
lixianyu | 0:a4d8f5b3c546 | 2853 | void MPU6050::setIntPLLReadyEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2854 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2855 | } |
lixianyu | 0:a4d8f5b3c546 | 2856 | bool MPU6050::getIntDMPEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2857 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2858 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2859 | } |
lixianyu | 0:a4d8f5b3c546 | 2860 | void MPU6050::setIntDMPEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2861 | I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2862 | } |
lixianyu | 0:a4d8f5b3c546 | 2863 | |
lixianyu | 0:a4d8f5b3c546 | 2864 | // DMP_INT_STATUS |
lixianyu | 0:a4d8f5b3c546 | 2865 | |
lixianyu | 0:a4d8f5b3c546 | 2866 | bool MPU6050::getDMPInt5Status() { |
lixianyu | 0:a4d8f5b3c546 | 2867 | I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_5_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2868 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2869 | } |
lixianyu | 0:a4d8f5b3c546 | 2870 | bool MPU6050::getDMPInt4Status() { |
lixianyu | 0:a4d8f5b3c546 | 2871 | I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_4_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2872 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2873 | } |
lixianyu | 0:a4d8f5b3c546 | 2874 | bool MPU6050::getDMPInt3Status() { |
lixianyu | 0:a4d8f5b3c546 | 2875 | I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_3_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2876 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2877 | } |
lixianyu | 0:a4d8f5b3c546 | 2878 | bool MPU6050::getDMPInt2Status() { |
lixianyu | 0:a4d8f5b3c546 | 2879 | I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_2_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2880 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2881 | } |
lixianyu | 0:a4d8f5b3c546 | 2882 | bool MPU6050::getDMPInt1Status() { |
lixianyu | 0:a4d8f5b3c546 | 2883 | I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_1_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2884 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2885 | } |
lixianyu | 0:a4d8f5b3c546 | 2886 | bool MPU6050::getDMPInt0Status() { |
lixianyu | 0:a4d8f5b3c546 | 2887 | I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_0_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2888 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2889 | } |
lixianyu | 0:a4d8f5b3c546 | 2890 | |
lixianyu | 0:a4d8f5b3c546 | 2891 | // INT_STATUS register (DMP functions) |
lixianyu | 0:a4d8f5b3c546 | 2892 | |
lixianyu | 0:a4d8f5b3c546 | 2893 | bool MPU6050::getIntPLLReadyStatus() { |
lixianyu | 0:a4d8f5b3c546 | 2894 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2895 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2896 | } |
lixianyu | 0:a4d8f5b3c546 | 2897 | bool MPU6050::getIntDMPStatus() { |
lixianyu | 0:a4d8f5b3c546 | 2898 | I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DMP_INT_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2899 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2900 | } |
lixianyu | 0:a4d8f5b3c546 | 2901 | |
lixianyu | 0:a4d8f5b3c546 | 2902 | // USER_CTRL register (DMP functions) |
lixianyu | 0:a4d8f5b3c546 | 2903 | |
lixianyu | 0:a4d8f5b3c546 | 2904 | bool MPU6050::getDMPEnabled() { |
lixianyu | 0:a4d8f5b3c546 | 2905 | I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2906 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2907 | } |
lixianyu | 0:a4d8f5b3c546 | 2908 | void MPU6050::setDMPEnabled(bool enabled) { |
lixianyu | 0:a4d8f5b3c546 | 2909 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, enabled); |
lixianyu | 0:a4d8f5b3c546 | 2910 | } |
lixianyu | 0:a4d8f5b3c546 | 2911 | void MPU6050::resetDMP() { |
lixianyu | 0:a4d8f5b3c546 | 2912 | I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_RESET_BIT, true); |
lixianyu | 0:a4d8f5b3c546 | 2913 | } |
lixianyu | 0:a4d8f5b3c546 | 2914 | |
lixianyu | 0:a4d8f5b3c546 | 2915 | // BANK_SEL register |
lixianyu | 0:a4d8f5b3c546 | 2916 | |
lixianyu | 0:a4d8f5b3c546 | 2917 | void MPU6050::setMemoryBank(uint8_t bank, bool prefetchEnabled, bool userBank) { |
lixianyu | 0:a4d8f5b3c546 | 2918 | bank &= 0x1F; |
lixianyu | 0:a4d8f5b3c546 | 2919 | if (userBank) bank |= 0x20; |
lixianyu | 0:a4d8f5b3c546 | 2920 | if (prefetchEnabled) bank |= 0x40; |
lixianyu | 0:a4d8f5b3c546 | 2921 | I2Cdev::writeByte(devAddr, MPU6050_RA_BANK_SEL, bank); |
lixianyu | 0:a4d8f5b3c546 | 2922 | } |
lixianyu | 0:a4d8f5b3c546 | 2923 | |
lixianyu | 0:a4d8f5b3c546 | 2924 | // MEM_START_ADDR register |
lixianyu | 0:a4d8f5b3c546 | 2925 | |
lixianyu | 0:a4d8f5b3c546 | 2926 | void MPU6050::setMemoryStartAddress(uint8_t address) { |
lixianyu | 0:a4d8f5b3c546 | 2927 | I2Cdev::writeByte(devAddr, MPU6050_RA_MEM_START_ADDR, address); |
lixianyu | 0:a4d8f5b3c546 | 2928 | } |
lixianyu | 0:a4d8f5b3c546 | 2929 | |
lixianyu | 0:a4d8f5b3c546 | 2930 | // MEM_R_W register |
lixianyu | 0:a4d8f5b3c546 | 2931 | |
lixianyu | 0:a4d8f5b3c546 | 2932 | uint8_t MPU6050::readMemoryByte() { |
lixianyu | 0:a4d8f5b3c546 | 2933 | I2Cdev::readByte(devAddr, MPU6050_RA_MEM_R_W, buffer); |
lixianyu | 0:a4d8f5b3c546 | 2934 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 2935 | } |
lixianyu | 0:a4d8f5b3c546 | 2936 | void MPU6050::writeMemoryByte(uint8_t data) { |
lixianyu | 0:a4d8f5b3c546 | 2937 | I2Cdev::writeByte(devAddr, MPU6050_RA_MEM_R_W, data); |
lixianyu | 0:a4d8f5b3c546 | 2938 | } |
lixianyu | 0:a4d8f5b3c546 | 2939 | void MPU6050::readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address) { |
lixianyu | 0:a4d8f5b3c546 | 2940 | setMemoryBank(bank); |
lixianyu | 0:a4d8f5b3c546 | 2941 | setMemoryStartAddress(address); |
lixianyu | 0:a4d8f5b3c546 | 2942 | uint8_t chunkSize; |
lixianyu | 0:a4d8f5b3c546 | 2943 | for (uint16_t i = 0; i < dataSize;) { |
lixianyu | 0:a4d8f5b3c546 | 2944 | // determine correct chunk size according to bank position and data size |
lixianyu | 0:a4d8f5b3c546 | 2945 | chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE; |
lixianyu | 0:a4d8f5b3c546 | 2946 | |
lixianyu | 0:a4d8f5b3c546 | 2947 | // make sure we don't go past the data size |
lixianyu | 0:a4d8f5b3c546 | 2948 | if (i + chunkSize > dataSize) chunkSize = dataSize - i; |
lixianyu | 0:a4d8f5b3c546 | 2949 | |
lixianyu | 0:a4d8f5b3c546 | 2950 | // make sure this chunk doesn't go past the bank boundary (256 bytes) |
lixianyu | 0:a4d8f5b3c546 | 2951 | if (chunkSize > 256 - address) chunkSize = 256 - address; |
lixianyu | 0:a4d8f5b3c546 | 2952 | |
lixianyu | 0:a4d8f5b3c546 | 2953 | // read the chunk of data as specified |
lixianyu | 0:a4d8f5b3c546 | 2954 | I2Cdev::readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, data + i); |
lixianyu | 0:a4d8f5b3c546 | 2955 | |
lixianyu | 0:a4d8f5b3c546 | 2956 | // increase byte index by [chunkSize] |
lixianyu | 0:a4d8f5b3c546 | 2957 | i += chunkSize; |
lixianyu | 0:a4d8f5b3c546 | 2958 | |
lixianyu | 0:a4d8f5b3c546 | 2959 | // uint8_t automatically wraps to 0 at 256 |
lixianyu | 0:a4d8f5b3c546 | 2960 | address += chunkSize; |
lixianyu | 0:a4d8f5b3c546 | 2961 | |
lixianyu | 0:a4d8f5b3c546 | 2962 | // if we aren't done, update bank (if necessary) and address |
lixianyu | 0:a4d8f5b3c546 | 2963 | if (i < dataSize) { |
lixianyu | 0:a4d8f5b3c546 | 2964 | if (address == 0) bank++; |
lixianyu | 0:a4d8f5b3c546 | 2965 | setMemoryBank(bank); |
lixianyu | 0:a4d8f5b3c546 | 2966 | setMemoryStartAddress(address); |
lixianyu | 0:a4d8f5b3c546 | 2967 | } |
lixianyu | 0:a4d8f5b3c546 | 2968 | } |
lixianyu | 0:a4d8f5b3c546 | 2969 | } |
lixianyu | 0:a4d8f5b3c546 | 2970 | bool MPU6050::writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify, bool useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 2971 | setMemoryBank(bank); |
lixianyu | 0:a4d8f5b3c546 | 2972 | setMemoryStartAddress(address); |
lixianyu | 0:a4d8f5b3c546 | 2973 | uint8_t chunkSize; |
lixianyu | 0:a4d8f5b3c546 | 2974 | uint8_t *verifyBuffer; |
lixianyu | 0:a4d8f5b3c546 | 2975 | uint8_t *progBuffer; |
lixianyu | 0:a4d8f5b3c546 | 2976 | uint16_t i; |
lixianyu | 0:a4d8f5b3c546 | 2977 | uint8_t j; |
lixianyu | 0:a4d8f5b3c546 | 2978 | if (verify) verifyBuffer = (uint8_t *)malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE); |
lixianyu | 0:a4d8f5b3c546 | 2979 | if (useProgMem) progBuffer = (uint8_t *)malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE); |
lixianyu | 0:a4d8f5b3c546 | 2980 | for (i = 0; i < dataSize;) { |
lixianyu | 0:a4d8f5b3c546 | 2981 | // determine correct chunk size according to bank position and data size |
lixianyu | 0:a4d8f5b3c546 | 2982 | chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE; |
lixianyu | 0:a4d8f5b3c546 | 2983 | |
lixianyu | 0:a4d8f5b3c546 | 2984 | // make sure we don't go past the data size |
lixianyu | 0:a4d8f5b3c546 | 2985 | if (i + chunkSize > dataSize) chunkSize = dataSize - i; |
lixianyu | 0:a4d8f5b3c546 | 2986 | |
lixianyu | 0:a4d8f5b3c546 | 2987 | // make sure this chunk doesn't go past the bank boundary (256 bytes) |
lixianyu | 0:a4d8f5b3c546 | 2988 | if (chunkSize > 256 - address) chunkSize = 256 - address; |
lixianyu | 0:a4d8f5b3c546 | 2989 | |
lixianyu | 0:a4d8f5b3c546 | 2990 | if (useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 2991 | // write the chunk of data as specified |
lixianyu | 0:a4d8f5b3c546 | 2992 | for (j = 0; j < chunkSize; j++) progBuffer[j] = pgm_read_byte(data + i + j); |
lixianyu | 0:a4d8f5b3c546 | 2993 | } else { |
lixianyu | 0:a4d8f5b3c546 | 2994 | // write the chunk of data as specified |
lixianyu | 0:a4d8f5b3c546 | 2995 | progBuffer = (uint8_t *)data + i; |
lixianyu | 0:a4d8f5b3c546 | 2996 | } |
lixianyu | 0:a4d8f5b3c546 | 2997 | |
lixianyu | 0:a4d8f5b3c546 | 2998 | I2Cdev::writeBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, progBuffer); |
lixianyu | 0:a4d8f5b3c546 | 2999 | |
lixianyu | 0:a4d8f5b3c546 | 3000 | // verify data if needed |
lixianyu | 0:a4d8f5b3c546 | 3001 | if (verify && verifyBuffer) { |
lixianyu | 0:a4d8f5b3c546 | 3002 | setMemoryBank(bank); |
lixianyu | 0:a4d8f5b3c546 | 3003 | setMemoryStartAddress(address); |
lixianyu | 0:a4d8f5b3c546 | 3004 | I2Cdev::readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, verifyBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3005 | if (memcmp(progBuffer, verifyBuffer, chunkSize) != 0) { |
lixianyu | 0:a4d8f5b3c546 | 3006 | /*Serial.print("Block write verification error, bank "); |
lixianyu | 0:a4d8f5b3c546 | 3007 | Serial.print(bank, DEC); |
lixianyu | 0:a4d8f5b3c546 | 3008 | Serial.print(", address "); |
lixianyu | 0:a4d8f5b3c546 | 3009 | Serial.print(address, DEC); |
lixianyu | 0:a4d8f5b3c546 | 3010 | Serial.print("!\nExpected:"); |
lixianyu | 0:a4d8f5b3c546 | 3011 | for (j = 0; j < chunkSize; j++) { |
lixianyu | 0:a4d8f5b3c546 | 3012 | Serial.print(" 0x"); |
lixianyu | 0:a4d8f5b3c546 | 3013 | if (progBuffer[j] < 16) Serial.print("0"); |
lixianyu | 0:a4d8f5b3c546 | 3014 | Serial.print(progBuffer[j], HEX); |
lixianyu | 0:a4d8f5b3c546 | 3015 | } |
lixianyu | 0:a4d8f5b3c546 | 3016 | Serial.print("\nReceived:"); |
lixianyu | 0:a4d8f5b3c546 | 3017 | for (uint8_t j = 0; j < chunkSize; j++) { |
lixianyu | 0:a4d8f5b3c546 | 3018 | Serial.print(" 0x"); |
lixianyu | 0:a4d8f5b3c546 | 3019 | if (verifyBuffer[i + j] < 16) Serial.print("0"); |
lixianyu | 0:a4d8f5b3c546 | 3020 | Serial.print(verifyBuffer[i + j], HEX); |
lixianyu | 0:a4d8f5b3c546 | 3021 | } |
lixianyu | 0:a4d8f5b3c546 | 3022 | Serial.print("\n");*/ |
lixianyu | 0:a4d8f5b3c546 | 3023 | free(verifyBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3024 | if (useProgMem) free(progBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3025 | return false; // uh oh. |
lixianyu | 0:a4d8f5b3c546 | 3026 | } |
lixianyu | 0:a4d8f5b3c546 | 3027 | } |
lixianyu | 0:a4d8f5b3c546 | 3028 | |
lixianyu | 0:a4d8f5b3c546 | 3029 | // increase byte index by [chunkSize] |
lixianyu | 0:a4d8f5b3c546 | 3030 | i += chunkSize; |
lixianyu | 0:a4d8f5b3c546 | 3031 | |
lixianyu | 0:a4d8f5b3c546 | 3032 | // uint8_t automatically wraps to 0 at 256 |
lixianyu | 0:a4d8f5b3c546 | 3033 | address += chunkSize; |
lixianyu | 0:a4d8f5b3c546 | 3034 | |
lixianyu | 0:a4d8f5b3c546 | 3035 | // if we aren't done, update bank (if necessary) and address |
lixianyu | 0:a4d8f5b3c546 | 3036 | if (i < dataSize) { |
lixianyu | 0:a4d8f5b3c546 | 3037 | if (address == 0) bank++; |
lixianyu | 0:a4d8f5b3c546 | 3038 | setMemoryBank(bank); |
lixianyu | 0:a4d8f5b3c546 | 3039 | setMemoryStartAddress(address); |
lixianyu | 0:a4d8f5b3c546 | 3040 | } |
lixianyu | 0:a4d8f5b3c546 | 3041 | } |
lixianyu | 0:a4d8f5b3c546 | 3042 | if (verify) free(verifyBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3043 | if (useProgMem) free(progBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3044 | return true; |
lixianyu | 0:a4d8f5b3c546 | 3045 | } |
lixianyu | 0:a4d8f5b3c546 | 3046 | bool MPU6050::writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify) { |
lixianyu | 0:a4d8f5b3c546 | 3047 | return writeMemoryBlock(data, dataSize, bank, address, verify, true); |
lixianyu | 0:a4d8f5b3c546 | 3048 | } |
lixianyu | 0:a4d8f5b3c546 | 3049 | bool MPU6050::writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 3050 | uint8_t *progBuffer, success, special; |
lixianyu | 0:a4d8f5b3c546 | 3051 | uint16_t i, j; |
lixianyu | 0:a4d8f5b3c546 | 3052 | if (useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 3053 | progBuffer = (uint8_t *)malloc(8); // assume 8-byte blocks, realloc later if necessary |
lixianyu | 0:a4d8f5b3c546 | 3054 | } |
lixianyu | 0:a4d8f5b3c546 | 3055 | |
lixianyu | 0:a4d8f5b3c546 | 3056 | // config set data is a long string of blocks with the following structure: |
lixianyu | 0:a4d8f5b3c546 | 3057 | // [bank] [offset] [length] [byte[0], byte[1], ..., byte[length]] |
lixianyu | 0:a4d8f5b3c546 | 3058 | uint8_t bank, offset, length; |
lixianyu | 0:a4d8f5b3c546 | 3059 | for (i = 0; i < dataSize;) { |
lixianyu | 0:a4d8f5b3c546 | 3060 | if (useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 3061 | bank = pgm_read_byte(data + i++); |
lixianyu | 0:a4d8f5b3c546 | 3062 | offset = pgm_read_byte(data + i++); |
lixianyu | 0:a4d8f5b3c546 | 3063 | length = pgm_read_byte(data + i++); |
lixianyu | 0:a4d8f5b3c546 | 3064 | } else { |
lixianyu | 0:a4d8f5b3c546 | 3065 | bank = data[i++]; |
lixianyu | 0:a4d8f5b3c546 | 3066 | offset = data[i++]; |
lixianyu | 0:a4d8f5b3c546 | 3067 | length = data[i++]; |
lixianyu | 0:a4d8f5b3c546 | 3068 | } |
lixianyu | 0:a4d8f5b3c546 | 3069 | |
lixianyu | 0:a4d8f5b3c546 | 3070 | // write data or perform special action |
lixianyu | 0:a4d8f5b3c546 | 3071 | if (length > 0) { |
lixianyu | 0:a4d8f5b3c546 | 3072 | // regular block of data to write |
lixianyu | 0:a4d8f5b3c546 | 3073 | /*Serial.print("Writing config block to bank "); |
lixianyu | 0:a4d8f5b3c546 | 3074 | Serial.print(bank); |
lixianyu | 0:a4d8f5b3c546 | 3075 | Serial.print(", offset "); |
lixianyu | 0:a4d8f5b3c546 | 3076 | Serial.print(offset); |
lixianyu | 0:a4d8f5b3c546 | 3077 | Serial.print(", length="); |
lixianyu | 0:a4d8f5b3c546 | 3078 | Serial.println(length);*/ |
lixianyu | 0:a4d8f5b3c546 | 3079 | if (useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 3080 | if (sizeof(progBuffer) < length) progBuffer = (uint8_t *)realloc(progBuffer, length); |
lixianyu | 0:a4d8f5b3c546 | 3081 | for (j = 0; j < length; j++) progBuffer[j] = pgm_read_byte(data + i + j); |
lixianyu | 0:a4d8f5b3c546 | 3082 | } else { |
lixianyu | 0:a4d8f5b3c546 | 3083 | progBuffer = (uint8_t *)data + i; |
lixianyu | 0:a4d8f5b3c546 | 3084 | } |
lixianyu | 0:a4d8f5b3c546 | 3085 | success = writeMemoryBlock(progBuffer, length, bank, offset, true); |
lixianyu | 0:a4d8f5b3c546 | 3086 | i += length; |
lixianyu | 0:a4d8f5b3c546 | 3087 | } else { |
lixianyu | 0:a4d8f5b3c546 | 3088 | // special instruction |
lixianyu | 0:a4d8f5b3c546 | 3089 | // NOTE: this kind of behavior (what and when to do certain things) |
lixianyu | 0:a4d8f5b3c546 | 3090 | // is totally undocumented. This code is in here based on observed |
lixianyu | 0:a4d8f5b3c546 | 3091 | // behavior only, and exactly why (or even whether) it has to be here |
lixianyu | 0:a4d8f5b3c546 | 3092 | // is anybody's guess for now. |
lixianyu | 0:a4d8f5b3c546 | 3093 | if (useProgMem) { |
lixianyu | 0:a4d8f5b3c546 | 3094 | special = pgm_read_byte(data + i++); |
lixianyu | 0:a4d8f5b3c546 | 3095 | } else { |
lixianyu | 0:a4d8f5b3c546 | 3096 | special = data[i++]; |
lixianyu | 0:a4d8f5b3c546 | 3097 | } |
lixianyu | 0:a4d8f5b3c546 | 3098 | /*Serial.print("Special command code "); |
lixianyu | 0:a4d8f5b3c546 | 3099 | Serial.print(special, HEX); |
lixianyu | 0:a4d8f5b3c546 | 3100 | Serial.println(" found...");*/ |
lixianyu | 0:a4d8f5b3c546 | 3101 | if (special == 0x01) { |
lixianyu | 0:a4d8f5b3c546 | 3102 | // enable DMP-related interrupts |
lixianyu | 0:a4d8f5b3c546 | 3103 | |
lixianyu | 0:a4d8f5b3c546 | 3104 | //setIntZeroMotionEnabled(true); |
lixianyu | 0:a4d8f5b3c546 | 3105 | //setIntFIFOBufferOverflowEnabled(true); |
lixianyu | 0:a4d8f5b3c546 | 3106 | //setIntDMPEnabled(true); |
lixianyu | 0:a4d8f5b3c546 | 3107 | I2Cdev::writeByte(devAddr, MPU6050_RA_INT_ENABLE, 0x32); // single operation |
lixianyu | 0:a4d8f5b3c546 | 3108 | |
lixianyu | 0:a4d8f5b3c546 | 3109 | success = true; |
lixianyu | 0:a4d8f5b3c546 | 3110 | } else { |
lixianyu | 0:a4d8f5b3c546 | 3111 | // unknown special command |
lixianyu | 0:a4d8f5b3c546 | 3112 | success = false; |
lixianyu | 0:a4d8f5b3c546 | 3113 | } |
lixianyu | 0:a4d8f5b3c546 | 3114 | } |
lixianyu | 0:a4d8f5b3c546 | 3115 | |
lixianyu | 0:a4d8f5b3c546 | 3116 | if (!success) { |
lixianyu | 0:a4d8f5b3c546 | 3117 | if (useProgMem) free(progBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3118 | return false; // uh oh |
lixianyu | 0:a4d8f5b3c546 | 3119 | } |
lixianyu | 0:a4d8f5b3c546 | 3120 | } |
lixianyu | 0:a4d8f5b3c546 | 3121 | if (useProgMem) free(progBuffer); |
lixianyu | 0:a4d8f5b3c546 | 3122 | return true; |
lixianyu | 0:a4d8f5b3c546 | 3123 | } |
lixianyu | 0:a4d8f5b3c546 | 3124 | bool MPU6050::writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize) { |
lixianyu | 0:a4d8f5b3c546 | 3125 | return writeDMPConfigurationSet(data, dataSize, true); |
lixianyu | 0:a4d8f5b3c546 | 3126 | } |
lixianyu | 0:a4d8f5b3c546 | 3127 | |
lixianyu | 0:a4d8f5b3c546 | 3128 | // DMP_CFG_1 register |
lixianyu | 0:a4d8f5b3c546 | 3129 | |
lixianyu | 0:a4d8f5b3c546 | 3130 | uint8_t MPU6050::getDMPConfig1() { |
lixianyu | 0:a4d8f5b3c546 | 3131 | I2Cdev::readByte(devAddr, MPU6050_RA_DMP_CFG_1, buffer); |
lixianyu | 0:a4d8f5b3c546 | 3132 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 3133 | } |
lixianyu | 0:a4d8f5b3c546 | 3134 | void MPU6050::setDMPConfig1(uint8_t config) { |
lixianyu | 0:a4d8f5b3c546 | 3135 | I2Cdev::writeByte(devAddr, MPU6050_RA_DMP_CFG_1, config); |
lixianyu | 0:a4d8f5b3c546 | 3136 | } |
lixianyu | 0:a4d8f5b3c546 | 3137 | |
lixianyu | 0:a4d8f5b3c546 | 3138 | // DMP_CFG_2 register |
lixianyu | 0:a4d8f5b3c546 | 3139 | |
lixianyu | 0:a4d8f5b3c546 | 3140 | uint8_t MPU6050::getDMPConfig2() { |
lixianyu | 0:a4d8f5b3c546 | 3141 | I2Cdev::readByte(devAddr, MPU6050_RA_DMP_CFG_2, buffer); |
lixianyu | 0:a4d8f5b3c546 | 3142 | return buffer[0]; |
lixianyu | 0:a4d8f5b3c546 | 3143 | } |
lixianyu | 0:a4d8f5b3c546 | 3144 | void MPU6050::setDMPConfig2(uint8_t config) { |
lixianyu | 0:a4d8f5b3c546 | 3145 | I2Cdev::writeByte(devAddr, MPU6050_RA_DMP_CFG_2, config); |
lixianyu | 0:a4d8f5b3c546 | 3146 | } |