mbed code for Farrari board
Dependencies: DDRO_Farrari mbed
Fork of DDRO_Farrari by
mmap.h
00001 // SRAM Limits 00002 #define IMEM_MIN 0x00000000 00003 #define IMEM_MAX 0x00010000 00004 #define DMEM_MIN 0x20000000 00005 #define DMEM_MAX 0x2002C000 00006 00007 // Redefine Imem addr from 0x10000000 to 0x00000000 00008 #define set_imem 0x44000008 00009 00010 // GPIO Memory Mapped IO 00011 // R/W/Set all at once 00012 #define GPIO_VAL 0x44001000 00013 #define GPIO_DIR 0x44001004 00014 #define GPIO_MASK 0x4400108 00015 #define GPIO_INT 0x4400100c 00016 // R/W/Set individually start addresses 00017 #define GPIO_VAL_AR 0x4400_1100 00018 #define GPIO_DIR_AR 0x4400_1200 00019 #define GPIO_INT_AR 0x4400_1300 00020 00021 // Counter 00022 #define reset_the_count 0x44010010 00023 #define the_count_31_0 0x44010000 00024 #define the_count_63_32 0x44010004 00025 #define the_thresh_31_0 0x44010008 00026 #define the_thresh_63_32 0x4401000c 00027 #define en_count 0x44010014 00028 00029 // Not used 00030 #define use_scan 0x44100000 00031 00032 // Ring oscillator clock 00033 #define en_ring_osc 0x44100004 00034 #define ring_osc_reset 0x44100008 00035 #define ring_osc_clksel 0x4410000c 00036 00037 // Clock selection 00038 #define intclk_source 0x44100010 00039 #define int_div_by 0x44100014/////////////////////////////////////// 00040 #define ext_div_by 0x44100018/////////////////////////////////////// 00041 #define extclk_source 0x4410001c 00042 00043 /* 00044 always @* 00045 begin 00046 case (intclk_source) 00047 2'b00 : HCLK = HCLK_EXT; 00048 2'b01 : HCLK = ring_osc_HCLK; 00049 2'b10 : HCLK = PLL_PLLOUTA; 00050 2'b11 : HCLK = PLL_PLLOUTB; 00051 default : HCLK = HCLK_EXT; 00052 endcase 00053 end 00054 00055 00056 00057 always @* 00058 begin 00059 case (extclk_source) 00060 2'b00 : HCLK_div_down = HCLK_EXT; 00061 2'b01 : HCLK_div_down = HCLK_divider; 00062 2'b10 : HCLK_div_down = PLL_PLLOUTA; 00063 2'b11 : HCLK_div_down = PLL_PLLOUTB; 00064 default : HCLK_div_down = HCLK_EXT; 00065 endcase 00066 end 00067 00068 always @* 00069 begin 00070 case (ext_div_by) 00071 4'd0 : HCLK_divider = HCLK_div_2; 00072 4'd1 : HCLK_divider = HCLK_div_2; 00073 4'd2 : HCLK_divider = HCLK_div_4; 00074 4'd3 : HCLK_divider = HCLK_div_8; 00075 4'd4 : HCLK_divider = HCLK_div_16; 00076 4'd5 : HCLK_divider = HCLK_div_32; 00077 4'd6 : HCLK_divider = HCLK_div_64; 00078 4'd7 : HCLK_divider = HCLK_div_128; 00079 4'd8 : HCLK_divider = HCLK_div_256; 00080 4'd9 : HCLK_divider = HCLK_div_512; 00081 4'd10 : HCLK_divider = HCLK_div_1024; 00082 4'd11 : HCLK_divider = HCLK_div_2048; 00083 4'd12 : HCLK_divider = HCLK_div_4096; 00084 4'd13 : HCLK_divider = HCLK_div_8192; 00085 4'd14 : HCLK_divider = HCLK_div_16384; 00086 4'd15 : HCLK_divider = HCLK_div_32768; 00087 default : HCLK_divider = HCLK_div_2; 00088 endcase 00089 end 00090 00091 */ 00092 00093 // Resets 00094 #define reset_reg 0x44000004 00095 #define RESET_scan 0x44100020 00096 #define CORERESET_scan 0x44100024 00097 00098 // DDRO 00099 #define ddro_syn_en 0x44100028 00100 #define ddro_inv_en 0x4410002c 00101 #define ddro_ref_src 0x44100030 00102 #define ddro_samp_src 0x44100034 00103 #define ddro_start 0x44100038 00104 #define ddro_threshold 0x4410003c 00105 #define ddro_pad_out 0x44100040////////////////////////////////////////// 00106 #define ddro_div_by 0x44100044/////////////////////////////////////////// 00107 #define ddro_done 0x44100060 00108 #define ddro_count 0x44100064 00109 00110 /* 00111 reg ref_clk; 00112 always @* 00113 begin 00114 case(ref_src) 00115 5'h0: ref_clk = HCLK; 00116 5'h1: ref_clk = ring_osc_HCLK; 00117 5'h2: ref_clk = PLL_REFCLK; 00118 5'h3: ref_clk = syn_out[0]; 00119 5'h4: ref_clk = syn_out[1]; 00120 5'h5: ref_clk = syn_out[2]; 00121 5'h6: ref_clk = syn_out[3]; 00122 5'h7: ref_clk = syn_out[4]; 00123 5'h8: ref_clk = syn_out[5]; 00124 5'h9: ref_clk = syn_out[6]; 00125 5'ha: ref_clk = syn_out[7]; 00126 5'hb: ref_clk = syn_out[8]; 00127 5'hc: ref_clk = inv_out[0]; 00128 5'hd: ref_clk = inv_out[1]; 00129 5'he: ref_clk = inv_out[2]; 00130 5'hf: ref_clk = inv_out[3]; 00131 5'h10: ref_clk = inv_out[4]; 00132 5'h11: ref_clk = inv_out[5]; 00133 5'h12: ref_clk = inv_out[6]; 00134 5'h13: ref_clk = inv_out[7]; 00135 5'h14: ref_clk = inv_out[8]; 00136 5'h15: ref_clk = inv_out[9]; 00137 5'h16: ref_clk = OXIDE_CLK; 00138 5'h17: ref_clk = PMOS_CLK; 00139 5'h18: ref_clk = NMOS_CLK; 00140 5'h19: ref_clk = TEMP_CLK; 00141 default: ref_clk = HCLK; 00142 endcase 00143 end 00144 */ 00145 00146 // Sensors 00147 #define sensor_disable 0x44100048 00148 #define sensor_oxide_stress 0x4410004c 00149 #define sensor_reset 0x44100050 00150 #define sensor_start 0x44100054 00151 #define sensor_sel 0x44100058 00152 #define sensor_done 0x44100068 00153 #define sensor_bank_24_0 0x4410006c 00154 #define sensor_bank_49_25 0x44100070 00155 #define sensor_bank_74_50 0x44100074 00156 #define sensor_bank_99_75 0x44100078 00157 00158 // ECC 00159 #define ecc_mode 0x4410005c 00160 #define imem_sec 0x4410007c 00161 #define imem_ded 0x44100080 00162 #define dmem_sec 0x44100084 00163 #define dmem_ded 0x44100088 00164 00165 // PLL Settings 00166 #define do_pll_reset 0x44020000 00167 #define PLL_DCOBYPASS 0x4410008c 00168 #define PLL_FFENABLE 0x44100090 00169 #define PLL_FFSLEWRATE 0x44100094 00170 #define PLL_FFTUNE 0x44100098 00171 #define PLL_INTFBK 0x4410009c 00172 #define PLL_LFTUNE_32_0 0x441000a0 00173 #define PLL_LFTUNE_40_32 0x441000a4 00174 #define PLL_LOCKSEL 0x441000a8 00175 #define PLL_LOCKTUNE 0x441000ac 00176 #define PLL_MULTFRAC 0x441000b0 00177 #define PLL_MULTINT 0x441000b4 00178 #define PLL_PLLBYPASS 0x441000b8 00179 #define PLL_PREDIV 0x441000bc 00180 #define PLL_RANGEA 0x441000c0 00181 #define PLL_RANGEB 0x441000c4 00182 #define PLL_RESET 0x441000c8 00183 #define PLL_SDORDER 0x441000cc 00184 #define PLL_SLEEP 0x441000d0 00185 #define PLL_STOPCLKA 0x441000d4 00186 #define PLL_STOPCLKB 0x441000d8 00187 #define PLL_CE0CCSEFCG 0x441000dc 00188 #define PLL_CE0CCTBON 0x441000e0 00189 #define PLL_CE0MPGSE 0x441000e4 00190 #define PLL_CE0TESTM3 0x441000e8 00191 #define PLL_CE1CCB 0x441000ec 00192 #define PLL_CE1MPGC1 0x441000f0 00193 #define PLL_PLH 0x441000f4 00194 #define PLL_TESTDIAG 0x441000f8 00195 #define PLL_TESTSEL 0x441000fc 00196 #define PLL_TSTCLKSEL 0x44100100 00197 #define PLL_GPTRSI 0x44100104 00198 #define PLL_DLT 0x44100108 00199 #define PLL_VCITUNE 0x4410010c 00200 #define PLL_VCVISEL 0x44100110 00201 #define PLL_VCVTUNE 0x44100114 00202 #define PLL_PLLLOCK 0x44100118 00203 #define PLL_PLLSYNCA 0x4410011c 00204 #define PLL_PLLSYNCB 0x44100120 00205 #define PLL_GPTRSO 0x44100124 00206 #define PLL_OBSERVE 0x44100128 00207 00208 // SRAM settings 00209 #define imem_ARWY 0x4410012c 00210 #define imem_DBWY 0x44100130 00211 #define imem_MICLOCKMODE 0x44100134 00212 #define imem_MIEMAS 0x44100138 00213 #define imem_MIEMAW 0x4410013c 00214 #define imem_MIEMAWASS 0x44100140 00215 #define imem_MIFLOOD 0x44100144 00216 #define imem_MIPGDISABLE 0x44100148 00217 #define imem_MITESTM1 0x4410014c 00218 #define imem_MITESTM3 0x44100150 00219 #define imem_MIWASSD 0x44100154 00220 #define imem_MIWRTM 0x44100158 00221 #define imem_TAB 0x4410015c 00222 #define imem_TAC 0x44100160 00223 #define imem_TAD0 0x44100164 00224 #define imem_TAW 0x44100168 00225 #define imem_TBW 0x4410016c 00226 #define imem_TD 0x44100170 00227 #define imem_TDEEPSLEEP 0x44100174 00228 #define imem_TQ 0x44100178 00229 #define imem_TWRITE 0x4410017c 00230 #define imem_TREAD 0x44100180 00231 #define imem_CR 0x44100184 00232 #define imem_CRE 0x44100188 00233 #define imem_RR 0x4410018c 00234 #define imem_RRE 0x44100190 00235 #define dmem_ARWY 0x44100194 00236 #define dmem_DBWY 0x44100198 00237 #define dmem_MICLOCKMODE 0x4410019c 00238 #define dmem_MIEMAS 0x441001a0 00239 #define dmem_MIEMAW 0x441001a4 00240 #define dmem_MIEMAWASS 0x441001a8 00241 #define dmem_MIFLOOD 0x441001ac 00242 #define dmem_MIPGDISABLE 0x441001b0 00243 #define dmem_MITESTM1 0x441001b4 00244 #define dmem_MITESTM3 0x441001b8 00245 #define dmem_MIWASSD 0x441001bc 00246 #define dmem_MIWRTM 0x441001c0 00247 #define dmem_TAB 0x441001c4 00248 #define dmem_TAC 0x441001c8 00249 #define dmem_TAD0 0x441001cc 00250 #define dmem_TAW 0x441001d0 00251 #define dmem_TBW 0x441001d4 00252 #define dmem_TD 0x441001d8 00253 #define dmem_TDEEPSLEEP 0x441001dc 00254 #define dmem_TQ 0x441001e0 00255 #define dmem_TWRITE 0x441001e4 00256 #define dmem_TREAD 0x441001e8 00257 #define dmem_CR 0x441001ec 00258 #define dmem_CRE 0x441001f0 00259 #define dmem_RR 0x441001f4 00260 #define dmem_RRE 0x441001f8
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