Tatsuki Fukuda
秋月販売のL3GD20使用8pinDIPジャイロセンサーモジュールのライブラリです。 FIFOを使って等間隔データの読み込みができます。 構造体のポインタをreadメソッドに渡すと値が入ります。 <今後の予定> ・レジスタへのアクセスの整理整頓 ・データレート/HighLowのフィルター/分解能の設定メソッド ・mbedピン変化割り込みによるデータ取得(おそらく関数ポインタを割り込み処理のメソッドに渡してもらう) ・読み取りデータにフィルターをかける。 ・データ取得の高速化
Revision 0:a07d3c1c7d2d, committed 2014-04-03
- Comitter:
- lelect
- Date:
- Thu Apr 03 12:26:20 2014 +0000
- Commit message:
- <L3GD20 SPI class(unused interrupt)>; you can use normal mode and FIFO mode(only change fifo configration,cannot change other configration); I'm going to use the interrupt other class.
Changed in this revision
diff -r 000000000000 -r a07d3c1c7d2d L3GD20.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/L3GD20.cpp Thu Apr 03 12:26:20 2014 +0000
@@ -0,0 +1,150 @@
+#include "mbed.h"
+#include "L3GD20.h"
+L3GD20::L3GD20(PinName miso, PinName mosi, PinName scl, PinName cs/*, PinName interrupt1=NC, PinName interrupt2=NC*/)
+ :_spi(miso,mosi,scl)
+ ,_cs(cs)
+{
+ _spi.format(8,3);
+ _spi.frequency(10000000);
+ int val;
+ read(null,&val);
+ read(WhoAmI,&val);
+ if(val==0x0F)
+ printf("L3GD20 is OK\r\n");
+ else
+ printf("Where is L3GD20\r\n");
+ configReadOut();
+ statusReadOut();
+
+}
+void L3GD20::write(RESISTER reg,int val)
+{
+ _cs=0;
+ _spi.write(reg);
+ _spi.write(val);
+ _cs=1;
+}
+void L3GD20::read(RESISTER reg,int* val)
+{
+ _cs=0;
+ _spi.write(READ|reg);
+ (*val)=_spi.write(0x00);
+ _cs=1;
+}
+void L3GD20::start(DIRECTION enable)
+{
+ _config.CTRL_REG1.B.Enable=enable;
+ _config.CTRL_REG1.b.PD=1;
+ write(CtrlReg1,_config.CTRL_REG1.word);
+}
+void L3GD20::stop()
+{
+ _config.CTRL_REG1.word=_config.CTRL_REG1.word&0xF0;
+ write(CtrlReg1,_config.CTRL_REG1.word);
+}
+void L3GD20::sleep()
+{
+ _config.CTRL_REG1.word=_config.CTRL_REG1.word&0xF8;
+ write(CtrlReg1,_config.CTRL_REG1.word);
+}
+void L3GD20::read(anglerrates* val,DIRECTION direction)
+{
+ if(direction&X) {
+ int x_l,x_h;
+ read(OutXL,&x_l);
+ read(OutXH,&x_h);
+ val->X=(x_l)|(x_h<<8);
+ }
+ if(direction&Y) {
+ int y_l,y_h;
+ read(OutYL,&y_l);
+ read(OutYH,&y_h);
+ val->Y=(y_l)|(y_h<<8);
+ }
+ if(direction&Z) {
+ int z_l,z_h;
+ read(OutZL,&z_l);
+ read(OutZH,&z_h);
+ val->Z=(z_l)|(z_h<<8);
+ }
+ if(_config.CTRL_REG4.B.FS==0x00) {
+ val->x=8.75*(float)val->X;
+ val->y=8.75*(float)val->Y;
+ val->z=8.75*(float)val->Z;
+ } else if(_config.CTRL_REG4.B.FS==0x01) {
+ val->x=17.5*(float)val->X;
+ val->y=17.5*(float)val->Y;
+ val->z=17.5*(float)val->Z;
+ } else if((_config.CTRL_REG4.B.FS==0x10)|(_config.CTRL_REG4.B.FS==0x11)) {
+ val->x=70.0*(float)val->X;
+ val->y=70.0*(float)val->Y;
+ val->z=70.0*(float)val->Z;
+ }
+}
+int L3GD20::readTemperature()
+{
+ read(OutTemp,&_status.OUT_TEMP);
+ return _status.OUT_TEMP;
+}
+void L3GD20::enableFIFO(FIFO_mode mode,FIFOstatus interrupt,const int threshold)
+{
+ _config.CTRL_REG5.b.FIFO_EN=1;
+ if(interrupt&empty) {
+ _config.CTRL_REG3.b.I2_Empty=1;
+ } else if(interrupt&watermark) {
+ _config.CTRL_REG3.b.I2_WTM=1;
+ } else if(interrupt&overrun) {
+ _config.CTRL_REG3.b.I2_ORun=1;
+ }
+ _config.FIFO_CTRL_REG.B.FM=mode;
+ if((0<threshold)&&(threshold<31)) {
+ _config.FIFO_CTRL_REG.B.WTM=threshold;
+ } else {
+ _config.FIFO_CTRL_REG.B.WTM=30;
+ }
+ write(CtrlReg3,_config.CTRL_REG3.word);
+ write(CtrlReg5,_config.CTRL_REG5.word);
+ write(FIFOCtrlReg,_config.FIFO_CTRL_REG.word);
+}
+void L3GD20::updateFIFO(void)
+{
+ read(FIFOSrcReg,&_status.FIFO_SRC_REG.word);
+ read(FIFOCtrlReg,&_config.FIFO_CTRL_REG.word);
+
+ if(_status.FIFO_SRC_REG.b.WTM) {
+ FIFO.status=watermark;
+ } else if(_status.FIFO_SRC_REG.b.EMPTY) {
+ FIFO.status=empty;
+ } else if(_status.FIFO_SRC_REG.b.OVR) {
+ FIFO.status=overrun;
+ } else {
+ FIFO.status=none;
+ }
+ FIFO.level=_status.FIFO_SRC_REG.B.FSS;
+}
+void L3GD20::configReadOut(void)
+{
+ read(CtrlReg1,&_config.CTRL_REG1.word);
+ read(CtrlReg2,&_config.CTRL_REG2.word);
+ read(CtrlReg3,&_config.CTRL_REG3.word);
+ read(CtrlReg4,&_config.CTRL_REG4.word);
+ read(CtrlReg5,&_config.CTRL_REG5.word);
+ read(Reference,&_config.REF_DATACAP.word);
+ read(FIFOCtrlReg,&_config.FIFO_CTRL_REG.word);
+ read(INT1Cfg,&_config.INT1_CFG.word);
+ read(INT1ThsXH,&_config.INT1_TSH_XH.word);
+ read(INT1ThsXL,&_config.INT1_TSH_XL.word);
+ read(INT1ThsYH,&_config.INT1_TSH_YH.word);
+ read(INT1ThsYL,&_config.INT1_TSH_YL.word);
+ read(INT1ThsZH,&_config.INT1_TSH_ZH.word);
+ read(INT1ThsZL,&_config.INT1_TSH_ZL.word);
+ read(INT1Duration,&_config.INT1_DURATION.word);
+}
+
+void L3GD20::statusReadOut(void)
+{
+ read(OutTemp,&_status.OUT_TEMP);
+ read(StatusReg,&_status.STATUS_REG);
+ read(FIFOSrcReg,&_status.FIFO_SRC_REG.word);
+ read(INT1Src,&_status.INT1_SRC);
+}
diff -r 000000000000 -r a07d3c1c7d2d L3GD20.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/L3GD20.h Thu Apr 03 12:26:20 2014 +0000
@@ -0,0 +1,126 @@
+#ifndef MBED_SPI
+#define MBED_SPI
+#include "mbed.h"
+#include "L3GD20_Resister.h"
+typedef struct {
+ int16_t X;
+ int16_t Y;
+ int16_t Z;
+ float x;
+ float y;
+ float z;
+} anglerrates;
+class L3GD20
+{
+public:
+ L3GD20(PinName miso, PinName mosi, PinName scl, PinName cs/*, PinName interrupt1=NC, PinName interrupt2=NC*/);
+ typedef enum {
+ null=0x00
+ ,WhoAmI=0x0F
+ ,CtrlReg1=0x20
+ ,CtrlReg2=0x21
+ ,CtrlReg3=0x22
+ ,CtrlReg4=0x23
+ ,CtrlReg5=0x24
+ ,Reference=0x25
+ ,OutTemp=0x26
+ ,StatusReg=0x27
+ ,OutXL=0x28
+ ,OutXH=0x29
+ ,OutYL=0x2A
+ ,OutYH=0x2B
+ ,OutZL=0x2C
+ ,OutZH=0x2D
+ ,FIFOCtrlReg=0x2E
+ ,FIFOSrcReg=0x2F
+ ,INT1Cfg=0x30
+ ,INT1Src=0x31
+ ,INT1ThsXH=0x32
+ ,INT1ThsXL=0x33
+ ,INT1ThsYH=0x34
+ ,INT1ThsYL=0x35
+ ,INT1ThsZH=0x36
+ ,INT1ThsZL=0x37
+ ,INT1Duration=0x38
+ ,READ=0x80
+ } RESISTER;
+ typedef enum {
+ Y=0x1
+ ,X=0x1<<1
+ ,Z=0x1<<2
+ ,XY=X|Y
+ ,XZ=X|Z
+ ,YZ=Y|Z
+ ,XYZ=X|Y|Z
+ } DIRECTION;
+
+
+ void start(DIRECTION enable);
+ void stop();
+ void sleep();
+ void read(anglerrates* val,DIRECTION direction);
+ int readTemperature();
+ typedef enum {
+ BYPASSmode=0x0
+ ,FIFOmode
+ ,STREAMmode
+ ,STREAMtoFIFOmode
+ ,BYPASStoSTREAMmode
+ } FIFO_mode;
+ typedef enum {
+ none=0
+ ,empty
+ ,watermark
+ ,overrun
+ } FIFOstatus;
+ struct tagFIFO {
+ FIFOstatus status;
+ int level;
+ } FIFO;
+ void enableFIFO(FIFO_mode mode,FIFOstatus interrupt,const int threshold);
+ void updateFIFO(void);
+ struct config {
+ //read and write resister
+ union CTRL_REG1 CTRL_REG1;
+ union CTRL_REG2 CTRL_REG2;
+ union CTRL_REG3 CTRL_REG3;
+ union CTRL_REG4 CTRL_REG4;
+ union CTRL_REG5 CTRL_REG5;
+ union REF_DATACAP REF_DATACAP;
+ union OUT_TEMP OUT_TEMP;
+ union STATUS_REG STATUS_REG;
+ union FIFO_CTRL_REG FIFO_CTRL_REG;
+ union INT1_CFG INT1_CFG;
+ union INT1_TSH_XH INT1_TSH_XH;
+ union INT1_TSH_XL INT1_TSH_XL;
+ union INT1_TSH_YH INT1_TSH_YH;
+ union INT1_TSH_YL INT1_TSH_YL;
+ union INT1_TSH_ZH INT1_TSH_ZH;
+ union INT1_TSH_ZL INT1_TSH_ZL;
+ union INT1_DURATION INT1_DURATION;
+ } _config;
+ struct status {
+ //read only resister
+ int OUT_TEMP;
+ int STATUS_REG;
+ union FIFO_SRC_REG FIFO_SRC_REG;
+ int INT1_SRC;
+ } _status;
+ void configReadOut(void);
+ void statusReadOut(void);
+protected:
+ void write(RESISTER reg,int val);
+ void read(RESISTER reg,int* val);
+ /*
+ void datarate(uint8_t rate,uint8_t bandwidth);
+ void setDataFormat();
+ void filter(uint8_t mode,uint8_t frequency);
+ void channelSource(uint8_t channnel,uint8_t dataSelection,uint8_t interruptSelection);
+ void FIFO(uint8_t mode,uint8_t watermark);
+ void interrupt(uint8_t source,uint8_t threthold,uint8_t duration,uint8_t Wait);
+ */
+ SPI _spi;
+ DigitalOut _cs;
+};
+
+#endif
\ No newline at end of file
diff -r 000000000000 -r a07d3c1c7d2d L3GD20_Resister.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/L3GD20_Resister.h Thu Apr 03 12:26:20 2014 +0000
@@ -0,0 +1,349 @@
+#ifndef L3GD20_RESISTER_MAP
+#define L3GD20_RESISTER_MAP
+
+union CTRL_REG1 {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned Yen:1;
+ unsigned Xen:1;
+ unsigned Zen:1;
+ unsigned PD:1;
+ unsigned BW0:1;
+ unsigned BW1:1;
+ unsigned DR0:1;
+ unsigned DR1:1;
+ } b;
+ struct {
+ unsigned Enable:3;
+ unsigned PD:1;
+ unsigned BW:2;
+ unsigned DR:2;
+ } B;
+};
+union CTRL_REG2 {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned HPCF0:1;
+ unsigned HPCF1:1;
+ unsigned HPCF2:1;
+ unsigned HPCF3:1;
+ unsigned HPM0:1;
+ unsigned HPM1:1;
+ unsigned :2;
+ } b;
+ struct {
+ unsigned HPCF:4;
+ unsigned HPM:2;
+ unsigned none:2;
+ } B;
+};
+union CTRL_REG3 {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned I2_Empty:1;
+ unsigned I2_ORun:1;
+ unsigned I2_WTM:1;
+ unsigned I2_DRDY:1;
+ unsigned PP_OD:1;
+ unsigned H_Lactive:1;
+ unsigned I1_Boot:1;
+ unsigned I1_Int1:1;
+ } b;
+};
+union CTRL_REG4 {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned SIM:1;
+ unsigned none:2;
+ unsigned nil:1;
+ unsigned FS0:1;
+ unsigned FS1:1;
+ unsigned BLE:1;
+ unsigned BDU:1;
+ } b;
+ struct {
+ unsigned SIM:1;
+ unsigned none:2;
+ unsigned nil:1;
+ unsigned FS:2;
+ unsigned BLE:1;
+ unsigned BDU:1;
+ } B;
+};
+union CTRL_REG5 {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned Out_Sel0:1;
+ unsigned Out_Sel1:1;
+ unsigned INT_Sel0:1;
+ unsigned INT_Sel1:1;
+ unsigned HPen:1;
+ unsigned nil:1;
+ unsigned FIFO_EN:1;
+ unsigned BOOT:1;
+ } b;
+ struct {
+ unsigned Out_Sel:2;
+ unsigned INT_Sel:2;
+ unsigned HPen:1;
+ unsigned nil:1;
+ unsigned FIFO_EN:1;
+ unsigned BOOT:1;
+ } B;
+};
+union REF_DATACAP {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned Ref0:1;
+ unsigned Ref1:1;
+ unsigned Ref2:1;
+ unsigned Ref3:1;
+ unsigned Ref4:1;
+ unsigned Ref5:1;
+ unsigned Ref6:1;
+ unsigned Ref7:1;
+ } b;
+ struct {
+ unsigned Ref:8;
+ } B;
+};
+union OUT_TEMP {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned Temp0:1;
+ unsigned Temp1:1;
+ unsigned Temp2:1;
+ unsigned Temp3:1;
+ unsigned Temp4:1;
+ unsigned Temp5:1;
+ unsigned Temp6:1;
+ unsigned Temp7:1;
+ } b;
+ struct {
+ unsigned Temp:8;
+ } B;
+};
+union STATUS_REG {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned XDA:1;
+ unsigned YDA:1;
+ unsigned ZDA:1;
+ unsigned ZYXDA:1;
+ unsigned XOR:1;
+ unsigned YOR:1;
+ unsigned ZOR:1;
+ unsigned XYZOR:1;
+ } b;
+};
+union FIFO_CTRL_REG {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned WTM0:1;
+ unsigned WTM1:1;
+ unsigned WTM2:1;
+ unsigned WTM3:1;
+ unsigned WTM4:1;
+ unsigned FM0:1;
+ unsigned FM1:1;
+ unsigned FM2:1;
+ } b;
+ struct {
+ unsigned WTM:5;
+ unsigned FM:3;
+ } B;
+};
+union FIFO_SRC_REG {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned FSS0:1;
+ unsigned FSS1:1;
+ unsigned FSS2:1;
+ unsigned FSS3:1;
+ unsigned FSS4:1;
+ unsigned EMPTY:1;
+ unsigned OVR:1;
+ unsigned WTM:1;
+ } b;
+ struct {
+ unsigned FSS:5;
+ unsigned EMPTY:1;
+ unsigned OVR:1;
+ unsigned WTM:1;
+ } B;
+};
+union INT1_CFG {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned XLIE:1;
+ unsigned XHIE:1;
+ unsigned YLIE:1;
+ unsigned YHIE:1;
+ unsigned ZLIE:1;
+ unsigned ZHIE:1;
+ unsigned LIR:1;
+ unsigned ANDOR:1;
+ } b;
+};
+union INT1_TSH_XH {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned THSX8:1;
+ unsigned THSX9:1;
+ unsigned THSX10:1;
+ unsigned THSX11:1;
+ unsigned THSX12:1;
+ unsigned THSX13:1;
+ unsigned THSX14:1;
+ unsigned nil:1;
+ } b;
+ struct {
+ unsigned THSH:7;
+ } B;
+};
+union INT1_TSH_XL {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned THSX0:1;
+ unsigned THSX1:1;
+ unsigned THSX2:1;
+ unsigned THSX3:1;
+ unsigned THSX4:1;
+ unsigned THSX5:1;
+ unsigned THSX6:1;
+ unsigned THSX7:1;
+ } b;
+ struct {
+ unsigned THSL:7;
+ } B;
+};
+union INT1_TSH_YH {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned THSY8:1;
+ unsigned THSY9:1;
+ unsigned THSY10:1;
+ unsigned THSY11:1;
+ unsigned THSY12:1;
+ unsigned THSY13:1;
+ unsigned THSY14:1;
+ unsigned nil:1;
+ } b;
+ struct {
+ unsigned THSH:7;
+ } B;
+};
+union INT1_TSH_YL {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned THSY0:1;
+ unsigned THSY1:1;
+ unsigned THSY2:1;
+ unsigned THSY3:1;
+ unsigned THSY4:1;
+ unsigned THSY5:1;
+ unsigned THSY6:1;
+ unsigned THSY7:1;
+ } b;
+ struct {
+ unsigned THSL:7;
+ } B;
+};
+union INT1_TSH_ZH {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned THSZ8:1;
+ unsigned THSZ9:1;
+ unsigned THSZ10:1;
+ unsigned THSZ11:1;
+ unsigned THSZ12:1;
+ unsigned THSZ13:1;
+ unsigned THSZ14:1;
+ unsigned nil:1;
+ } b;
+ struct {
+ unsigned THSH:7;
+ } B;
+};
+union INT1_TSH_ZL {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned THSZ0:1;
+ unsigned THSZ1:1;
+ unsigned THSZ2:1;
+ unsigned THSZ3:1;
+ unsigned THSZ4:1;
+ unsigned THSZ5:1;
+ unsigned THSZ6:1;
+ unsigned THSZ7:1;
+ } b;
+ struct {
+ unsigned THSL:7;
+ } B;
+};
+union INT1_DURATION {
+ int word;
+ uint8_t byte;
+ struct {
+ unsigned D0:1;
+ unsigned D1:1;
+ unsigned D2:1;
+ unsigned D3:1;
+ unsigned D4:1;
+ unsigned D5:1;
+ unsigned D6:1;
+ unsigned WAIT:1;
+ } b;
+ struct {
+ unsigned D:6;
+ unsigned WAIT:1;
+ } B;
+};
+/*
+#define L3GD20_READ 0x80
+#define L3GD20_WHO_AM_I 0x0F
+#define L3GD20_CTRL_REG1 0x20
+#define L3GD20_CTRL_REG2 0x21
+#define L3GD20_CTRL_REG3 0x22
+#define L3GD20_CTRL_REG4 0x23
+#define L3GD20_CTRL_REG5 0x24
+#define L3GD20_REFERENCE 0x25
+#define L3GD20_OUT_TEMP 0x26
+#define L3GD20_STATUS_REG 0x27
+#define L3GD20_OUT_X_L 0x28
+#define L3GD20_OUT_X_H 0x29
+#define L3GD20_OUT_Y_L 0x2A
+#define L3GD20_OUT_Y_H 0x2B
+#define L3GD20_OUT_Z_L 0x2C
+#define L3GD20_OUT_Z_H 0x2D
+#define L3GD20_FIFO_CTRL_REG 0x2E
+#define L3GD20_FIFO_SRC_REG 0x2F
+#define L3GD20_INT1_CFG 0x30
+#define L3GD20_INT1_SRC 0x31
+#define L3GD20_INT1_THS_XH 0x32
+#define L3GD20_INT1_THS_XL 0x33
+#define L3GD20_INT1_THS_YH 0x34
+#define L3GD20_INT1_THS_YL 0x35
+#define L3GD20_INT1_THS_ZH 0x36
+#define L3GD20_INT1_THS_ZL 0x37
+#define L3GD20_INT1_DURATION 0x38
+*/
+
+#endif
\ No newline at end of file