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targets/cmsis/TARGET_Freescale/TARGET_K20D5M/MK20D5.h@68:41613245dfd7, 2013-12-26 (annotated)

Committer:
mbed_official
Date:
Thu Dec 26 13:00:06 2013 +0000
Revision:
68:41613245dfd7
Synchronized with git revision fba199a9c4445231b0f38e1e113c118182635546



Full URL: https://github.com/mbedmicro/mbed/commit/fba199a9c4445231b0f38e1e113c118182635546/



target K20D5M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 68:41613245dfd7 1 /*
mbed_official 68:41613245dfd7 2 ** ###################################################################
mbed_official 68:41613245dfd7 3 ** Compilers: ARM Compiler
mbed_official 68:41613245dfd7 4 ** Freescale C/C++ for Embedded ARM
mbed_official 68:41613245dfd7 5 ** GNU C Compiler
mbed_official 68:41613245dfd7 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 68:41613245dfd7 7 **
mbed_official 68:41613245dfd7 8 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
mbed_official 68:41613245dfd7 9 ** K20P32M50SF0RM Rev. 1, Oct 2011
mbed_official 68:41613245dfd7 10 ** K20P48M50SF0RM Rev. 1, Oct 2011
mbed_official 68:41613245dfd7 11 **
mbed_official 68:41613245dfd7 12 ** Version: rev. 2.0, 2012-03-19
mbed_official 68:41613245dfd7 13 **
mbed_official 68:41613245dfd7 14 ** Abstract:
mbed_official 68:41613245dfd7 15 ** CMSIS Peripheral Access Layer for MK20D5
mbed_official 68:41613245dfd7 16 **
mbed_official 68:41613245dfd7 17 ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
mbed_official 68:41613245dfd7 18 **
mbed_official 68:41613245dfd7 19 ** http: www.freescale.com
mbed_official 68:41613245dfd7 20 ** mail: support@freescale.com
mbed_official 68:41613245dfd7 21 **
mbed_official 68:41613245dfd7 22 ** Revisions:
mbed_official 68:41613245dfd7 23 ** - rev. 1.0 (2011-12-15)
mbed_official 68:41613245dfd7 24 ** Initial version
mbed_official 68:41613245dfd7 25 ** - rev. 2.0 (2012-03-19)
mbed_official 68:41613245dfd7 26 ** PDB Peripheral register structure updated.
mbed_official 68:41613245dfd7 27 ** DMA Registers and bits for unsupported DMA channels removed.
mbed_official 68:41613245dfd7 28 **
mbed_official 68:41613245dfd7 29 ** ###################################################################
mbed_official 68:41613245dfd7 30 */
mbed_official 68:41613245dfd7 31
mbed_official 68:41613245dfd7 32 /**
mbed_official 68:41613245dfd7 33 * @file MK20D5.h
mbed_official 68:41613245dfd7 34 * @version 2.0
mbed_official 68:41613245dfd7 35 * @date 2012-03-19
mbed_official 68:41613245dfd7 36 * @brief CMSIS Peripheral Access Layer for MK20D5
mbed_official 68:41613245dfd7 37 *
mbed_official 68:41613245dfd7 38 * CMSIS Peripheral Access Layer for MK20D5
mbed_official 68:41613245dfd7 39 */
mbed_official 68:41613245dfd7 40
mbed_official 68:41613245dfd7 41 #if !defined(MK20D5_H_)
mbed_official 68:41613245dfd7 42 #define MK20D5_H_ /**< Symbol preventing repeated inclusion */
mbed_official 68:41613245dfd7 43
mbed_official 68:41613245dfd7 44 /** Memory map major version (memory maps with equal major version number are
mbed_official 68:41613245dfd7 45 * compatible) */
mbed_official 68:41613245dfd7 46 #define MCU_MEM_MAP_VERSION 0x0200u
mbed_official 68:41613245dfd7 47 /** Memory map minor version */
mbed_official 68:41613245dfd7 48 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
mbed_official 68:41613245dfd7 49
mbed_official 68:41613245dfd7 50 /**
mbed_official 68:41613245dfd7 51 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 68:41613245dfd7 52 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
mbed_official 68:41613245dfd7 53 * @param Reg Register to access.
mbed_official 68:41613245dfd7 54 * @param Bit Bit number to access.
mbed_official 68:41613245dfd7 55 * @return Value of the targeted bit in the bit band region.
mbed_official 68:41613245dfd7 56 */
mbed_official 68:41613245dfd7 57 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
mbed_official 68:41613245dfd7 58
mbed_official 68:41613245dfd7 59 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 60 -- Interrupt vector numbers
mbed_official 68:41613245dfd7 61 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 62
mbed_official 68:41613245dfd7 63 /**
mbed_official 68:41613245dfd7 64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 68:41613245dfd7 65 * @{
mbed_official 68:41613245dfd7 66 */
mbed_official 68:41613245dfd7 67
mbed_official 68:41613245dfd7 68 /** Interrupt Number Definitions */
mbed_official 68:41613245dfd7 69 typedef enum IRQn {
mbed_official 68:41613245dfd7 70 /* Core interrupts */
mbed_official 68:41613245dfd7 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 68:41613245dfd7 72 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
mbed_official 68:41613245dfd7 73 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
mbed_official 68:41613245dfd7 74 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
mbed_official 68:41613245dfd7 75 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
mbed_official 68:41613245dfd7 76 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
mbed_official 68:41613245dfd7 77 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
mbed_official 68:41613245dfd7 78 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
mbed_official 68:41613245dfd7 79
mbed_official 68:41613245dfd7 80 /* Device specific interrupts */
mbed_official 68:41613245dfd7 81 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
mbed_official 68:41613245dfd7 82 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
mbed_official 68:41613245dfd7 83 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
mbed_official 68:41613245dfd7 84 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
mbed_official 68:41613245dfd7 85 DMA_Error_IRQn = 4, /**< DMA error interrupt */
mbed_official 68:41613245dfd7 86 Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
mbed_official 68:41613245dfd7 87 FTFL_IRQn = 6, /**< FTFL interrupt */
mbed_official 68:41613245dfd7 88 Read_Collision_IRQn = 7, /**< Read collision interrupt */
mbed_official 68:41613245dfd7 89 LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 68:41613245dfd7 90 LLW_IRQn = 9, /**< Low Leakage Wakeup */
mbed_official 68:41613245dfd7 91 Watchdog_IRQn = 10, /**< WDOG interrupt */
mbed_official 68:41613245dfd7 92 I2C0_IRQn = 11, /**< I2C0 interrupt */
mbed_official 68:41613245dfd7 93 SPI0_IRQn = 12, /**< SPI0 interrupt */
mbed_official 68:41613245dfd7 94 I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
mbed_official 68:41613245dfd7 95 I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
mbed_official 68:41613245dfd7 96 UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
mbed_official 68:41613245dfd7 97 UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
mbed_official 68:41613245dfd7 98 UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
mbed_official 68:41613245dfd7 99 UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
mbed_official 68:41613245dfd7 100 UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
mbed_official 68:41613245dfd7 101 UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
mbed_official 68:41613245dfd7 102 UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
mbed_official 68:41613245dfd7 103 ADC0_IRQn = 22, /**< ADC0 interrupt */
mbed_official 68:41613245dfd7 104 CMP0_IRQn = 23, /**< CMP0 interrupt */
mbed_official 68:41613245dfd7 105 CMP1_IRQn = 24, /**< CMP1 interrupt */
mbed_official 68:41613245dfd7 106 FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
mbed_official 68:41613245dfd7 107 FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
mbed_official 68:41613245dfd7 108 CMT_IRQn = 27, /**< CMT interrupt */
mbed_official 68:41613245dfd7 109 RTC_IRQn = 28, /**< RTC interrupt */
mbed_official 68:41613245dfd7 110 RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
mbed_official 68:41613245dfd7 111 PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
mbed_official 68:41613245dfd7 112 PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
mbed_official 68:41613245dfd7 113 PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
mbed_official 68:41613245dfd7 114 PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
mbed_official 68:41613245dfd7 115 PDB0_IRQn = 34, /**< PDB0 interrupt */
mbed_official 68:41613245dfd7 116 USB0_IRQn = 35, /**< USB0 interrupt */
mbed_official 68:41613245dfd7 117 USBDCD_IRQn = 36, /**< USBDCD interrupt */
mbed_official 68:41613245dfd7 118 TSI0_IRQn = 37, /**< TSI0 interrupt */
mbed_official 68:41613245dfd7 119 MCG_IRQn = 38, /**< MCG interrupt */
mbed_official 68:41613245dfd7 120 LPTimer_IRQn = 39, /**< LPTimer interrupt */
mbed_official 68:41613245dfd7 121 PORTA_IRQn = 40, /**< Port A interrupt */
mbed_official 68:41613245dfd7 122 PORTB_IRQn = 41, /**< Port B interrupt */
mbed_official 68:41613245dfd7 123 PORTC_IRQn = 42, /**< Port C interrupt */
mbed_official 68:41613245dfd7 124 PORTD_IRQn = 43, /**< Port D interrupt */
mbed_official 68:41613245dfd7 125 PORTE_IRQn = 44, /**< Port E interrupt */
mbed_official 68:41613245dfd7 126 SWI_IRQn = 45 /**< Software interrupt */
mbed_official 68:41613245dfd7 127 } IRQn_Type;
mbed_official 68:41613245dfd7 128
mbed_official 68:41613245dfd7 129 /**
mbed_official 68:41613245dfd7 130 * @}
mbed_official 68:41613245dfd7 131 */ /* end of group Interrupt_vector_numbers */
mbed_official 68:41613245dfd7 132
mbed_official 68:41613245dfd7 133
mbed_official 68:41613245dfd7 134 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 135 -- Cortex M4 Core Configuration
mbed_official 68:41613245dfd7 136 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 137
mbed_official 68:41613245dfd7 138 /**
mbed_official 68:41613245dfd7 139 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
mbed_official 68:41613245dfd7 140 * @{
mbed_official 68:41613245dfd7 141 */
mbed_official 68:41613245dfd7 142
mbed_official 68:41613245dfd7 143 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 68:41613245dfd7 144 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
mbed_official 68:41613245dfd7 145 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 68:41613245dfd7 146
mbed_official 68:41613245dfd7 147 #include "core_cm4.h" /* Core Peripheral Access Layer */
mbed_official 68:41613245dfd7 148 #include "system_MK20D5.h" /* Device specific configuration file */
mbed_official 68:41613245dfd7 149
mbed_official 68:41613245dfd7 150 /**
mbed_official 68:41613245dfd7 151 * @}
mbed_official 68:41613245dfd7 152 */ /* end of group Cortex_Core_Configuration */
mbed_official 68:41613245dfd7 153
mbed_official 68:41613245dfd7 154
mbed_official 68:41613245dfd7 155 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 156 -- Device Peripheral Access Layer
mbed_official 68:41613245dfd7 157 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 158
mbed_official 68:41613245dfd7 159 /**
mbed_official 68:41613245dfd7 160 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 68:41613245dfd7 161 * @{
mbed_official 68:41613245dfd7 162 */
mbed_official 68:41613245dfd7 163
mbed_official 68:41613245dfd7 164
mbed_official 68:41613245dfd7 165 /*
mbed_official 68:41613245dfd7 166 ** Start of section using anonymous unions
mbed_official 68:41613245dfd7 167 */
mbed_official 68:41613245dfd7 168
mbed_official 68:41613245dfd7 169 #if defined(__ARMCC_VERSION)
mbed_official 68:41613245dfd7 170 #pragma push
mbed_official 68:41613245dfd7 171 #pragma anon_unions
mbed_official 68:41613245dfd7 172 #elif defined(__CWCC__)
mbed_official 68:41613245dfd7 173 #pragma push
mbed_official 68:41613245dfd7 174 #pragma cpp_extensions on
mbed_official 68:41613245dfd7 175 #elif defined(__GNUC__)
mbed_official 68:41613245dfd7 176 /* anonymous unions are enabled by default */
mbed_official 68:41613245dfd7 177 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 68:41613245dfd7 178 #pragma language=extended
mbed_official 68:41613245dfd7 179 #else
mbed_official 68:41613245dfd7 180 #error Not supported compiler type
mbed_official 68:41613245dfd7 181 #endif
mbed_official 68:41613245dfd7 182
mbed_official 68:41613245dfd7 183 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 184 -- ADC Peripheral Access Layer
mbed_official 68:41613245dfd7 185 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 186
mbed_official 68:41613245dfd7 187 /**
mbed_official 68:41613245dfd7 188 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 68:41613245dfd7 189 * @{
mbed_official 68:41613245dfd7 190 */
mbed_official 68:41613245dfd7 191
mbed_official 68:41613245dfd7 192 /** ADC - Register Layout Typedef */
mbed_official 68:41613245dfd7 193 typedef struct {
mbed_official 68:41613245dfd7 194 __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 68:41613245dfd7 195 __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
mbed_official 68:41613245dfd7 196 __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
mbed_official 68:41613245dfd7 197 __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
mbed_official 68:41613245dfd7 198 __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
mbed_official 68:41613245dfd7 199 __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
mbed_official 68:41613245dfd7 200 __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
mbed_official 68:41613245dfd7 201 __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
mbed_official 68:41613245dfd7 202 __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
mbed_official 68:41613245dfd7 203 __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
mbed_official 68:41613245dfd7 204 __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
mbed_official 68:41613245dfd7 205 __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
mbed_official 68:41613245dfd7 206 __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
mbed_official 68:41613245dfd7 207 __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
mbed_official 68:41613245dfd7 208 __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
mbed_official 68:41613245dfd7 209 __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
mbed_official 68:41613245dfd7 210 __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
mbed_official 68:41613245dfd7 211 __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
mbed_official 68:41613245dfd7 212 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 213 __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
mbed_official 68:41613245dfd7 214 __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
mbed_official 68:41613245dfd7 215 __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
mbed_official 68:41613245dfd7 216 __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
mbed_official 68:41613245dfd7 217 __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
mbed_official 68:41613245dfd7 218 __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
mbed_official 68:41613245dfd7 219 __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
mbed_official 68:41613245dfd7 220 } ADC_Type;
mbed_official 68:41613245dfd7 221
mbed_official 68:41613245dfd7 222 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 223 -- ADC Register Masks
mbed_official 68:41613245dfd7 224 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 225
mbed_official 68:41613245dfd7 226 /**
mbed_official 68:41613245dfd7 227 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 68:41613245dfd7 228 * @{
mbed_official 68:41613245dfd7 229 */
mbed_official 68:41613245dfd7 230
mbed_official 68:41613245dfd7 231 /* SC1 Bit Fields */
mbed_official 68:41613245dfd7 232 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 68:41613245dfd7 233 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 68:41613245dfd7 234 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 68:41613245dfd7 235 #define ADC_SC1_DIFF_MASK 0x20u
mbed_official 68:41613245dfd7 236 #define ADC_SC1_DIFF_SHIFT 5
mbed_official 68:41613245dfd7 237 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 68:41613245dfd7 238 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 68:41613245dfd7 239 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 68:41613245dfd7 240 #define ADC_SC1_COCO_SHIFT 7
mbed_official 68:41613245dfd7 241 /* CFG1 Bit Fields */
mbed_official 68:41613245dfd7 242 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 68:41613245dfd7 243 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 68:41613245dfd7 244 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 68:41613245dfd7 245 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 68:41613245dfd7 246 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 68:41613245dfd7 247 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 68:41613245dfd7 248 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 68:41613245dfd7 249 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 68:41613245dfd7 250 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 68:41613245dfd7 251 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 68:41613245dfd7 252 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 68:41613245dfd7 253 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 68:41613245dfd7 254 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 68:41613245dfd7 255 /* CFG2 Bit Fields */
mbed_official 68:41613245dfd7 256 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 68:41613245dfd7 257 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 68:41613245dfd7 258 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 68:41613245dfd7 259 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 68:41613245dfd7 260 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 68:41613245dfd7 261 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 68:41613245dfd7 262 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 68:41613245dfd7 263 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 68:41613245dfd7 264 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 68:41613245dfd7 265 /* R Bit Fields */
mbed_official 68:41613245dfd7 266 #define ADC_R_D_MASK 0xFFFFu
mbed_official 68:41613245dfd7 267 #define ADC_R_D_SHIFT 0
mbed_official 68:41613245dfd7 268 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 68:41613245dfd7 269 /* CV1 Bit Fields */
mbed_official 68:41613245dfd7 270 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 68:41613245dfd7 271 #define ADC_CV1_CV_SHIFT 0
mbed_official 68:41613245dfd7 272 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 68:41613245dfd7 273 /* CV2 Bit Fields */
mbed_official 68:41613245dfd7 274 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 68:41613245dfd7 275 #define ADC_CV2_CV_SHIFT 0
mbed_official 68:41613245dfd7 276 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 68:41613245dfd7 277 /* SC2 Bit Fields */
mbed_official 68:41613245dfd7 278 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 68:41613245dfd7 279 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 68:41613245dfd7 280 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 68:41613245dfd7 281 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 68:41613245dfd7 282 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 68:41613245dfd7 283 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 68:41613245dfd7 284 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 68:41613245dfd7 285 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 68:41613245dfd7 286 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 68:41613245dfd7 287 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 68:41613245dfd7 288 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 68:41613245dfd7 289 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 68:41613245dfd7 290 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 68:41613245dfd7 291 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 68:41613245dfd7 292 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 68:41613245dfd7 293 /* SC3 Bit Fields */
mbed_official 68:41613245dfd7 294 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 68:41613245dfd7 295 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 68:41613245dfd7 296 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 68:41613245dfd7 297 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 68:41613245dfd7 298 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 68:41613245dfd7 299 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 68:41613245dfd7 300 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 68:41613245dfd7 301 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 68:41613245dfd7 302 #define ADC_SC3_CALF_SHIFT 6
mbed_official 68:41613245dfd7 303 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 68:41613245dfd7 304 #define ADC_SC3_CAL_SHIFT 7
mbed_official 68:41613245dfd7 305 /* OFS Bit Fields */
mbed_official 68:41613245dfd7 306 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 68:41613245dfd7 307 #define ADC_OFS_OFS_SHIFT 0
mbed_official 68:41613245dfd7 308 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 68:41613245dfd7 309 /* PG Bit Fields */
mbed_official 68:41613245dfd7 310 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 68:41613245dfd7 311 #define ADC_PG_PG_SHIFT 0
mbed_official 68:41613245dfd7 312 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 68:41613245dfd7 313 /* MG Bit Fields */
mbed_official 68:41613245dfd7 314 #define ADC_MG_MG_MASK 0xFFFFu
mbed_official 68:41613245dfd7 315 #define ADC_MG_MG_SHIFT 0
mbed_official 68:41613245dfd7 316 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mbed_official 68:41613245dfd7 317 /* CLPD Bit Fields */
mbed_official 68:41613245dfd7 318 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 68:41613245dfd7 319 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 68:41613245dfd7 320 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 68:41613245dfd7 321 /* CLPS Bit Fields */
mbed_official 68:41613245dfd7 322 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 68:41613245dfd7 323 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 68:41613245dfd7 324 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 68:41613245dfd7 325 /* CLP4 Bit Fields */
mbed_official 68:41613245dfd7 326 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 68:41613245dfd7 327 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 68:41613245dfd7 328 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 68:41613245dfd7 329 /* CLP3 Bit Fields */
mbed_official 68:41613245dfd7 330 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 68:41613245dfd7 331 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 68:41613245dfd7 332 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 68:41613245dfd7 333 /* CLP2 Bit Fields */
mbed_official 68:41613245dfd7 334 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 68:41613245dfd7 335 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 68:41613245dfd7 336 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 68:41613245dfd7 337 /* CLP1 Bit Fields */
mbed_official 68:41613245dfd7 338 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 68:41613245dfd7 339 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 68:41613245dfd7 340 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 68:41613245dfd7 341 /* CLP0 Bit Fields */
mbed_official 68:41613245dfd7 342 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 68:41613245dfd7 343 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 68:41613245dfd7 344 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 68:41613245dfd7 345 /* CLMD Bit Fields */
mbed_official 68:41613245dfd7 346 #define ADC_CLMD_CLMD_MASK 0x3Fu
mbed_official 68:41613245dfd7 347 #define ADC_CLMD_CLMD_SHIFT 0
mbed_official 68:41613245dfd7 348 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mbed_official 68:41613245dfd7 349 /* CLMS Bit Fields */
mbed_official 68:41613245dfd7 350 #define ADC_CLMS_CLMS_MASK 0x3Fu
mbed_official 68:41613245dfd7 351 #define ADC_CLMS_CLMS_SHIFT 0
mbed_official 68:41613245dfd7 352 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mbed_official 68:41613245dfd7 353 /* CLM4 Bit Fields */
mbed_official 68:41613245dfd7 354 #define ADC_CLM4_CLM4_MASK 0x3FFu
mbed_official 68:41613245dfd7 355 #define ADC_CLM4_CLM4_SHIFT 0
mbed_official 68:41613245dfd7 356 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mbed_official 68:41613245dfd7 357 /* CLM3 Bit Fields */
mbed_official 68:41613245dfd7 358 #define ADC_CLM3_CLM3_MASK 0x1FFu
mbed_official 68:41613245dfd7 359 #define ADC_CLM3_CLM3_SHIFT 0
mbed_official 68:41613245dfd7 360 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mbed_official 68:41613245dfd7 361 /* CLM2 Bit Fields */
mbed_official 68:41613245dfd7 362 #define ADC_CLM2_CLM2_MASK 0xFFu
mbed_official 68:41613245dfd7 363 #define ADC_CLM2_CLM2_SHIFT 0
mbed_official 68:41613245dfd7 364 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mbed_official 68:41613245dfd7 365 /* CLM1 Bit Fields */
mbed_official 68:41613245dfd7 366 #define ADC_CLM1_CLM1_MASK 0x7Fu
mbed_official 68:41613245dfd7 367 #define ADC_CLM1_CLM1_SHIFT 0
mbed_official 68:41613245dfd7 368 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mbed_official 68:41613245dfd7 369 /* CLM0 Bit Fields */
mbed_official 68:41613245dfd7 370 #define ADC_CLM0_CLM0_MASK 0x3Fu
mbed_official 68:41613245dfd7 371 #define ADC_CLM0_CLM0_SHIFT 0
mbed_official 68:41613245dfd7 372 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mbed_official 68:41613245dfd7 373
mbed_official 68:41613245dfd7 374 /**
mbed_official 68:41613245dfd7 375 * @}
mbed_official 68:41613245dfd7 376 */ /* end of group ADC_Register_Masks */
mbed_official 68:41613245dfd7 377
mbed_official 68:41613245dfd7 378
mbed_official 68:41613245dfd7 379 /* ADC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 380 /** Peripheral ADC0 base address */
mbed_official 68:41613245dfd7 381 #define ADC0_BASE (0x4003B000u)
mbed_official 68:41613245dfd7 382 /** Peripheral ADC0 base pointer */
mbed_official 68:41613245dfd7 383 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 68:41613245dfd7 384
mbed_official 68:41613245dfd7 385 /**
mbed_official 68:41613245dfd7 386 * @}
mbed_official 68:41613245dfd7 387 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 388
mbed_official 68:41613245dfd7 389
mbed_official 68:41613245dfd7 390 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 391 -- CMP Peripheral Access Layer
mbed_official 68:41613245dfd7 392 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 393
mbed_official 68:41613245dfd7 394 /**
mbed_official 68:41613245dfd7 395 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 68:41613245dfd7 396 * @{
mbed_official 68:41613245dfd7 397 */
mbed_official 68:41613245dfd7 398
mbed_official 68:41613245dfd7 399 /** CMP - Register Layout Typedef */
mbed_official 68:41613245dfd7 400 typedef struct {
mbed_official 68:41613245dfd7 401 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 68:41613245dfd7 402 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 68:41613245dfd7 403 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 68:41613245dfd7 404 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 68:41613245dfd7 405 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 68:41613245dfd7 406 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 68:41613245dfd7 407 } CMP_Type;
mbed_official 68:41613245dfd7 408
mbed_official 68:41613245dfd7 409 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 410 -- CMP Register Masks
mbed_official 68:41613245dfd7 411 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 412
mbed_official 68:41613245dfd7 413 /**
mbed_official 68:41613245dfd7 414 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 68:41613245dfd7 415 * @{
mbed_official 68:41613245dfd7 416 */
mbed_official 68:41613245dfd7 417
mbed_official 68:41613245dfd7 418 /* CR0 Bit Fields */
mbed_official 68:41613245dfd7 419 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 68:41613245dfd7 420 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 68:41613245dfd7 421 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 68:41613245dfd7 422 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 68:41613245dfd7 423 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 68:41613245dfd7 424 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 68:41613245dfd7 425 /* CR1 Bit Fields */
mbed_official 68:41613245dfd7 426 #define CMP_CR1_EN_MASK 0x1u
mbed_official 68:41613245dfd7 427 #define CMP_CR1_EN_SHIFT 0
mbed_official 68:41613245dfd7 428 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 68:41613245dfd7 429 #define CMP_CR1_OPE_SHIFT 1
mbed_official 68:41613245dfd7 430 #define CMP_CR1_COS_MASK 0x4u
mbed_official 68:41613245dfd7 431 #define CMP_CR1_COS_SHIFT 2
mbed_official 68:41613245dfd7 432 #define CMP_CR1_INV_MASK 0x8u
mbed_official 68:41613245dfd7 433 #define CMP_CR1_INV_SHIFT 3
mbed_official 68:41613245dfd7 434 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 68:41613245dfd7 435 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 68:41613245dfd7 436 #define CMP_CR1_WE_MASK 0x40u
mbed_official 68:41613245dfd7 437 #define CMP_CR1_WE_SHIFT 6
mbed_official 68:41613245dfd7 438 #define CMP_CR1_SE_MASK 0x80u
mbed_official 68:41613245dfd7 439 #define CMP_CR1_SE_SHIFT 7
mbed_official 68:41613245dfd7 440 /* FPR Bit Fields */
mbed_official 68:41613245dfd7 441 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 68:41613245dfd7 442 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 68:41613245dfd7 443 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 68:41613245dfd7 444 /* SCR Bit Fields */
mbed_official 68:41613245dfd7 445 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 68:41613245dfd7 446 #define CMP_SCR_COUT_SHIFT 0
mbed_official 68:41613245dfd7 447 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 68:41613245dfd7 448 #define CMP_SCR_CFF_SHIFT 1
mbed_official 68:41613245dfd7 449 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 68:41613245dfd7 450 #define CMP_SCR_CFR_SHIFT 2
mbed_official 68:41613245dfd7 451 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 68:41613245dfd7 452 #define CMP_SCR_IEF_SHIFT 3
mbed_official 68:41613245dfd7 453 #define CMP_SCR_IER_MASK 0x10u
mbed_official 68:41613245dfd7 454 #define CMP_SCR_IER_SHIFT 4
mbed_official 68:41613245dfd7 455 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 68:41613245dfd7 456 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 68:41613245dfd7 457 /* DACCR Bit Fields */
mbed_official 68:41613245dfd7 458 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 68:41613245dfd7 459 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 68:41613245dfd7 460 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 68:41613245dfd7 461 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 68:41613245dfd7 462 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 68:41613245dfd7 463 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 68:41613245dfd7 464 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 68:41613245dfd7 465 /* MUXCR Bit Fields */
mbed_official 68:41613245dfd7 466 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 68:41613245dfd7 467 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 68:41613245dfd7 468 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 68:41613245dfd7 469 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 68:41613245dfd7 470 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 68:41613245dfd7 471 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 68:41613245dfd7 472
mbed_official 68:41613245dfd7 473 /**
mbed_official 68:41613245dfd7 474 * @}
mbed_official 68:41613245dfd7 475 */ /* end of group CMP_Register_Masks */
mbed_official 68:41613245dfd7 476
mbed_official 68:41613245dfd7 477
mbed_official 68:41613245dfd7 478 /* CMP - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 479 /** Peripheral CMP0 base address */
mbed_official 68:41613245dfd7 480 #define CMP0_BASE (0x40073000u)
mbed_official 68:41613245dfd7 481 /** Peripheral CMP0 base pointer */
mbed_official 68:41613245dfd7 482 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 68:41613245dfd7 483 /** Peripheral CMP1 base address */
mbed_official 68:41613245dfd7 484 #define CMP1_BASE (0x40073008u)
mbed_official 68:41613245dfd7 485 /** Peripheral CMP1 base pointer */
mbed_official 68:41613245dfd7 486 #define CMP1 ((CMP_Type *)CMP1_BASE)
mbed_official 68:41613245dfd7 487
mbed_official 68:41613245dfd7 488 /**
mbed_official 68:41613245dfd7 489 * @}
mbed_official 68:41613245dfd7 490 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 491
mbed_official 68:41613245dfd7 492
mbed_official 68:41613245dfd7 493 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 494 -- CMT Peripheral Access Layer
mbed_official 68:41613245dfd7 495 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 496
mbed_official 68:41613245dfd7 497 /**
mbed_official 68:41613245dfd7 498 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
mbed_official 68:41613245dfd7 499 * @{
mbed_official 68:41613245dfd7 500 */
mbed_official 68:41613245dfd7 501
mbed_official 68:41613245dfd7 502 /** CMT - Register Layout Typedef */
mbed_official 68:41613245dfd7 503 typedef struct {
mbed_official 68:41613245dfd7 504 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
mbed_official 68:41613245dfd7 505 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
mbed_official 68:41613245dfd7 506 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
mbed_official 68:41613245dfd7 507 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
mbed_official 68:41613245dfd7 508 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
mbed_official 68:41613245dfd7 509 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
mbed_official 68:41613245dfd7 510 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
mbed_official 68:41613245dfd7 511 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
mbed_official 68:41613245dfd7 512 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
mbed_official 68:41613245dfd7 513 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
mbed_official 68:41613245dfd7 514 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
mbed_official 68:41613245dfd7 515 __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
mbed_official 68:41613245dfd7 516 } CMT_Type;
mbed_official 68:41613245dfd7 517
mbed_official 68:41613245dfd7 518 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 519 -- CMT Register Masks
mbed_official 68:41613245dfd7 520 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 521
mbed_official 68:41613245dfd7 522 /**
mbed_official 68:41613245dfd7 523 * @addtogroup CMT_Register_Masks CMT Register Masks
mbed_official 68:41613245dfd7 524 * @{
mbed_official 68:41613245dfd7 525 */
mbed_official 68:41613245dfd7 526
mbed_official 68:41613245dfd7 527 /* CGH1 Bit Fields */
mbed_official 68:41613245dfd7 528 #define CMT_CGH1_PH_MASK 0xFFu
mbed_official 68:41613245dfd7 529 #define CMT_CGH1_PH_SHIFT 0
mbed_official 68:41613245dfd7 530 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
mbed_official 68:41613245dfd7 531 /* CGL1 Bit Fields */
mbed_official 68:41613245dfd7 532 #define CMT_CGL1_PL_MASK 0xFFu
mbed_official 68:41613245dfd7 533 #define CMT_CGL1_PL_SHIFT 0
mbed_official 68:41613245dfd7 534 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
mbed_official 68:41613245dfd7 535 /* CGH2 Bit Fields */
mbed_official 68:41613245dfd7 536 #define CMT_CGH2_SH_MASK 0xFFu
mbed_official 68:41613245dfd7 537 #define CMT_CGH2_SH_SHIFT 0
mbed_official 68:41613245dfd7 538 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
mbed_official 68:41613245dfd7 539 /* CGL2 Bit Fields */
mbed_official 68:41613245dfd7 540 #define CMT_CGL2_SL_MASK 0xFFu
mbed_official 68:41613245dfd7 541 #define CMT_CGL2_SL_SHIFT 0
mbed_official 68:41613245dfd7 542 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
mbed_official 68:41613245dfd7 543 /* OC Bit Fields */
mbed_official 68:41613245dfd7 544 #define CMT_OC_IROPEN_MASK 0x20u
mbed_official 68:41613245dfd7 545 #define CMT_OC_IROPEN_SHIFT 5
mbed_official 68:41613245dfd7 546 #define CMT_OC_CMTPOL_MASK 0x40u
mbed_official 68:41613245dfd7 547 #define CMT_OC_CMTPOL_SHIFT 6
mbed_official 68:41613245dfd7 548 #define CMT_OC_IROL_MASK 0x80u
mbed_official 68:41613245dfd7 549 #define CMT_OC_IROL_SHIFT 7
mbed_official 68:41613245dfd7 550 /* MSC Bit Fields */
mbed_official 68:41613245dfd7 551 #define CMT_MSC_MCGEN_MASK 0x1u
mbed_official 68:41613245dfd7 552 #define CMT_MSC_MCGEN_SHIFT 0
mbed_official 68:41613245dfd7 553 #define CMT_MSC_EOCIE_MASK 0x2u
mbed_official 68:41613245dfd7 554 #define CMT_MSC_EOCIE_SHIFT 1
mbed_official 68:41613245dfd7 555 #define CMT_MSC_FSK_MASK 0x4u
mbed_official 68:41613245dfd7 556 #define CMT_MSC_FSK_SHIFT 2
mbed_official 68:41613245dfd7 557 #define CMT_MSC_BASE_MASK 0x8u
mbed_official 68:41613245dfd7 558 #define CMT_MSC_BASE_SHIFT 3
mbed_official 68:41613245dfd7 559 #define CMT_MSC_EXSPC_MASK 0x10u
mbed_official 68:41613245dfd7 560 #define CMT_MSC_EXSPC_SHIFT 4
mbed_official 68:41613245dfd7 561 #define CMT_MSC_CMTDIV_MASK 0x60u
mbed_official 68:41613245dfd7 562 #define CMT_MSC_CMTDIV_SHIFT 5
mbed_official 68:41613245dfd7 563 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
mbed_official 68:41613245dfd7 564 #define CMT_MSC_EOCF_MASK 0x80u
mbed_official 68:41613245dfd7 565 #define CMT_MSC_EOCF_SHIFT 7
mbed_official 68:41613245dfd7 566 /* CMD1 Bit Fields */
mbed_official 68:41613245dfd7 567 #define CMT_CMD1_MB_MASK 0xFFu
mbed_official 68:41613245dfd7 568 #define CMT_CMD1_MB_SHIFT 0
mbed_official 68:41613245dfd7 569 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
mbed_official 68:41613245dfd7 570 /* CMD2 Bit Fields */
mbed_official 68:41613245dfd7 571 #define CMT_CMD2_MB_MASK 0xFFu
mbed_official 68:41613245dfd7 572 #define CMT_CMD2_MB_SHIFT 0
mbed_official 68:41613245dfd7 573 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
mbed_official 68:41613245dfd7 574 /* CMD3 Bit Fields */
mbed_official 68:41613245dfd7 575 #define CMT_CMD3_SB_MASK 0xFFu
mbed_official 68:41613245dfd7 576 #define CMT_CMD3_SB_SHIFT 0
mbed_official 68:41613245dfd7 577 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
mbed_official 68:41613245dfd7 578 /* CMD4 Bit Fields */
mbed_official 68:41613245dfd7 579 #define CMT_CMD4_SB_MASK 0xFFu
mbed_official 68:41613245dfd7 580 #define CMT_CMD4_SB_SHIFT 0
mbed_official 68:41613245dfd7 581 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
mbed_official 68:41613245dfd7 582 /* PPS Bit Fields */
mbed_official 68:41613245dfd7 583 #define CMT_PPS_PPSDIV_MASK 0xFu
mbed_official 68:41613245dfd7 584 #define CMT_PPS_PPSDIV_SHIFT 0
mbed_official 68:41613245dfd7 585 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
mbed_official 68:41613245dfd7 586 /* DMA Bit Fields */
mbed_official 68:41613245dfd7 587 #define CMT_DMA_DMA_MASK 0x1u
mbed_official 68:41613245dfd7 588 #define CMT_DMA_DMA_SHIFT 0
mbed_official 68:41613245dfd7 589
mbed_official 68:41613245dfd7 590 /**
mbed_official 68:41613245dfd7 591 * @}
mbed_official 68:41613245dfd7 592 */ /* end of group CMT_Register_Masks */
mbed_official 68:41613245dfd7 593
mbed_official 68:41613245dfd7 594
mbed_official 68:41613245dfd7 595 /* CMT - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 596 /** Peripheral CMT base address */
mbed_official 68:41613245dfd7 597 #define CMT_BASE (0x40062000u)
mbed_official 68:41613245dfd7 598 /** Peripheral CMT base pointer */
mbed_official 68:41613245dfd7 599 #define CMT ((CMT_Type *)CMT_BASE)
mbed_official 68:41613245dfd7 600
mbed_official 68:41613245dfd7 601 /**
mbed_official 68:41613245dfd7 602 * @}
mbed_official 68:41613245dfd7 603 */ /* end of group CMT_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 604
mbed_official 68:41613245dfd7 605
mbed_official 68:41613245dfd7 606 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 607 -- CRC Peripheral Access Layer
mbed_official 68:41613245dfd7 608 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 609
mbed_official 68:41613245dfd7 610 /**
mbed_official 68:41613245dfd7 611 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
mbed_official 68:41613245dfd7 612 * @{
mbed_official 68:41613245dfd7 613 */
mbed_official 68:41613245dfd7 614
mbed_official 68:41613245dfd7 615 /** CRC - Register Layout Typedef */
mbed_official 68:41613245dfd7 616 typedef struct {
mbed_official 68:41613245dfd7 617 union { /* offset: 0x0 */
mbed_official 68:41613245dfd7 618 struct { /* offset: 0x0 */
mbed_official 68:41613245dfd7 619 __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
mbed_official 68:41613245dfd7 620 __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
mbed_official 68:41613245dfd7 621 } ACCESS16BIT;
mbed_official 68:41613245dfd7 622 __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
mbed_official 68:41613245dfd7 623 struct { /* offset: 0x0 */
mbed_official 68:41613245dfd7 624 __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
mbed_official 68:41613245dfd7 625 __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
mbed_official 68:41613245dfd7 626 __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
mbed_official 68:41613245dfd7 627 __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
mbed_official 68:41613245dfd7 628 } ACCESS8BIT;
mbed_official 68:41613245dfd7 629 };
mbed_official 68:41613245dfd7 630 union { /* offset: 0x4 */
mbed_official 68:41613245dfd7 631 struct { /* offset: 0x4 */
mbed_official 68:41613245dfd7 632 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
mbed_official 68:41613245dfd7 633 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
mbed_official 68:41613245dfd7 634 } GPOLY_ACCESS16BIT;
mbed_official 68:41613245dfd7 635 __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
mbed_official 68:41613245dfd7 636 struct { /* offset: 0x4 */
mbed_official 68:41613245dfd7 637 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
mbed_official 68:41613245dfd7 638 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
mbed_official 68:41613245dfd7 639 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
mbed_official 68:41613245dfd7 640 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
mbed_official 68:41613245dfd7 641 } GPOLY_ACCESS8BIT;
mbed_official 68:41613245dfd7 642 };
mbed_official 68:41613245dfd7 643 union { /* offset: 0x8 */
mbed_official 68:41613245dfd7 644 __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
mbed_official 68:41613245dfd7 645 struct { /* offset: 0x8 */
mbed_official 68:41613245dfd7 646 uint8_t RESERVED_0[3];
mbed_official 68:41613245dfd7 647 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
mbed_official 68:41613245dfd7 648 } CTRL_ACCESS8BIT;
mbed_official 68:41613245dfd7 649 };
mbed_official 68:41613245dfd7 650 } CRC_Type;
mbed_official 68:41613245dfd7 651
mbed_official 68:41613245dfd7 652 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 653 -- CRC Register Masks
mbed_official 68:41613245dfd7 654 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 655
mbed_official 68:41613245dfd7 656 /**
mbed_official 68:41613245dfd7 657 * @addtogroup CRC_Register_Masks CRC Register Masks
mbed_official 68:41613245dfd7 658 * @{
mbed_official 68:41613245dfd7 659 */
mbed_official 68:41613245dfd7 660
mbed_official 68:41613245dfd7 661 /* CRCL Bit Fields */
mbed_official 68:41613245dfd7 662 #define CRC_CRCL_CRCL_MASK 0xFFFFu
mbed_official 68:41613245dfd7 663 #define CRC_CRCL_CRCL_SHIFT 0
mbed_official 68:41613245dfd7 664 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
mbed_official 68:41613245dfd7 665 /* CRCH Bit Fields */
mbed_official 68:41613245dfd7 666 #define CRC_CRCH_CRCH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 667 #define CRC_CRCH_CRCH_SHIFT 0
mbed_official 68:41613245dfd7 668 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
mbed_official 68:41613245dfd7 669 /* CRC Bit Fields */
mbed_official 68:41613245dfd7 670 #define CRC_CRC_LL_MASK 0xFFu
mbed_official 68:41613245dfd7 671 #define CRC_CRC_LL_SHIFT 0
mbed_official 68:41613245dfd7 672 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
mbed_official 68:41613245dfd7 673 #define CRC_CRC_LU_MASK 0xFF00u
mbed_official 68:41613245dfd7 674 #define CRC_CRC_LU_SHIFT 8
mbed_official 68:41613245dfd7 675 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
mbed_official 68:41613245dfd7 676 #define CRC_CRC_HL_MASK 0xFF0000u
mbed_official 68:41613245dfd7 677 #define CRC_CRC_HL_SHIFT 16
mbed_official 68:41613245dfd7 678 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
mbed_official 68:41613245dfd7 679 #define CRC_CRC_HU_MASK 0xFF000000u
mbed_official 68:41613245dfd7 680 #define CRC_CRC_HU_SHIFT 24
mbed_official 68:41613245dfd7 681 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
mbed_official 68:41613245dfd7 682 /* CRCLL Bit Fields */
mbed_official 68:41613245dfd7 683 #define CRC_CRCLL_CRCLL_MASK 0xFFu
mbed_official 68:41613245dfd7 684 #define CRC_CRCLL_CRCLL_SHIFT 0
mbed_official 68:41613245dfd7 685 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
mbed_official 68:41613245dfd7 686 /* CRCLU Bit Fields */
mbed_official 68:41613245dfd7 687 #define CRC_CRCLU_CRCLU_MASK 0xFFu
mbed_official 68:41613245dfd7 688 #define CRC_CRCLU_CRCLU_SHIFT 0
mbed_official 68:41613245dfd7 689 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
mbed_official 68:41613245dfd7 690 /* CRCHL Bit Fields */
mbed_official 68:41613245dfd7 691 #define CRC_CRCHL_CRCHL_MASK 0xFFu
mbed_official 68:41613245dfd7 692 #define CRC_CRCHL_CRCHL_SHIFT 0
mbed_official 68:41613245dfd7 693 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
mbed_official 68:41613245dfd7 694 /* CRCHU Bit Fields */
mbed_official 68:41613245dfd7 695 #define CRC_CRCHU_CRCHU_MASK 0xFFu
mbed_official 68:41613245dfd7 696 #define CRC_CRCHU_CRCHU_SHIFT 0
mbed_official 68:41613245dfd7 697 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
mbed_official 68:41613245dfd7 698 /* GPOLYL Bit Fields */
mbed_official 68:41613245dfd7 699 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
mbed_official 68:41613245dfd7 700 #define CRC_GPOLYL_GPOLYL_SHIFT 0
mbed_official 68:41613245dfd7 701 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
mbed_official 68:41613245dfd7 702 /* GPOLYH Bit Fields */
mbed_official 68:41613245dfd7 703 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 704 #define CRC_GPOLYH_GPOLYH_SHIFT 0
mbed_official 68:41613245dfd7 705 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
mbed_official 68:41613245dfd7 706 /* GPOLY Bit Fields */
mbed_official 68:41613245dfd7 707 #define CRC_GPOLY_LOW_MASK 0xFFFFu
mbed_official 68:41613245dfd7 708 #define CRC_GPOLY_LOW_SHIFT 0
mbed_official 68:41613245dfd7 709 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
mbed_official 68:41613245dfd7 710 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 711 #define CRC_GPOLY_HIGH_SHIFT 16
mbed_official 68:41613245dfd7 712 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
mbed_official 68:41613245dfd7 713 /* GPOLYLL Bit Fields */
mbed_official 68:41613245dfd7 714 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
mbed_official 68:41613245dfd7 715 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
mbed_official 68:41613245dfd7 716 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
mbed_official 68:41613245dfd7 717 /* GPOLYLU Bit Fields */
mbed_official 68:41613245dfd7 718 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
mbed_official 68:41613245dfd7 719 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
mbed_official 68:41613245dfd7 720 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
mbed_official 68:41613245dfd7 721 /* GPOLYHL Bit Fields */
mbed_official 68:41613245dfd7 722 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
mbed_official 68:41613245dfd7 723 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
mbed_official 68:41613245dfd7 724 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
mbed_official 68:41613245dfd7 725 /* GPOLYHU Bit Fields */
mbed_official 68:41613245dfd7 726 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
mbed_official 68:41613245dfd7 727 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
mbed_official 68:41613245dfd7 728 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
mbed_official 68:41613245dfd7 729 /* CTRL Bit Fields */
mbed_official 68:41613245dfd7 730 #define CRC_CTRL_TCRC_MASK 0x1000000u
mbed_official 68:41613245dfd7 731 #define CRC_CTRL_TCRC_SHIFT 24
mbed_official 68:41613245dfd7 732 #define CRC_CTRL_WAS_MASK 0x2000000u
mbed_official 68:41613245dfd7 733 #define CRC_CTRL_WAS_SHIFT 25
mbed_official 68:41613245dfd7 734 #define CRC_CTRL_FXOR_MASK 0x4000000u
mbed_official 68:41613245dfd7 735 #define CRC_CTRL_FXOR_SHIFT 26
mbed_official 68:41613245dfd7 736 #define CRC_CTRL_TOTR_MASK 0x30000000u
mbed_official 68:41613245dfd7 737 #define CRC_CTRL_TOTR_SHIFT 28
mbed_official 68:41613245dfd7 738 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
mbed_official 68:41613245dfd7 739 #define CRC_CTRL_TOT_MASK 0xC0000000u
mbed_official 68:41613245dfd7 740 #define CRC_CTRL_TOT_SHIFT 30
mbed_official 68:41613245dfd7 741 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
mbed_official 68:41613245dfd7 742 /* CTRLHU Bit Fields */
mbed_official 68:41613245dfd7 743 #define CRC_CTRLHU_TCRC_MASK 0x1u
mbed_official 68:41613245dfd7 744 #define CRC_CTRLHU_TCRC_SHIFT 0
mbed_official 68:41613245dfd7 745 #define CRC_CTRLHU_WAS_MASK 0x2u
mbed_official 68:41613245dfd7 746 #define CRC_CTRLHU_WAS_SHIFT 1
mbed_official 68:41613245dfd7 747 #define CRC_CTRLHU_FXOR_MASK 0x4u
mbed_official 68:41613245dfd7 748 #define CRC_CTRLHU_FXOR_SHIFT 2
mbed_official 68:41613245dfd7 749 #define CRC_CTRLHU_TOTR_MASK 0x30u
mbed_official 68:41613245dfd7 750 #define CRC_CTRLHU_TOTR_SHIFT 4
mbed_official 68:41613245dfd7 751 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
mbed_official 68:41613245dfd7 752 #define CRC_CTRLHU_TOT_MASK 0xC0u
mbed_official 68:41613245dfd7 753 #define CRC_CTRLHU_TOT_SHIFT 6
mbed_official 68:41613245dfd7 754 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
mbed_official 68:41613245dfd7 755
mbed_official 68:41613245dfd7 756 /**
mbed_official 68:41613245dfd7 757 * @}
mbed_official 68:41613245dfd7 758 */ /* end of group CRC_Register_Masks */
mbed_official 68:41613245dfd7 759
mbed_official 68:41613245dfd7 760
mbed_official 68:41613245dfd7 761 /* CRC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 762 /** Peripheral CRC base address */
mbed_official 68:41613245dfd7 763 #define CRC_BASE (0x40032000u)
mbed_official 68:41613245dfd7 764 /** Peripheral CRC base pointer */
mbed_official 68:41613245dfd7 765 #define CRC0 ((CRC_Type *)CRC_BASE)
mbed_official 68:41613245dfd7 766
mbed_official 68:41613245dfd7 767 /**
mbed_official 68:41613245dfd7 768 * @}
mbed_official 68:41613245dfd7 769 */ /* end of group CRC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 770
mbed_official 68:41613245dfd7 771
mbed_official 68:41613245dfd7 772 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 773 -- DMA Peripheral Access Layer
mbed_official 68:41613245dfd7 774 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 775
mbed_official 68:41613245dfd7 776 /**
mbed_official 68:41613245dfd7 777 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 68:41613245dfd7 778 * @{
mbed_official 68:41613245dfd7 779 */
mbed_official 68:41613245dfd7 780
mbed_official 68:41613245dfd7 781 /** DMA - Register Layout Typedef */
mbed_official 68:41613245dfd7 782 typedef struct {
mbed_official 68:41613245dfd7 783 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 784 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
mbed_official 68:41613245dfd7 785 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 786 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
mbed_official 68:41613245dfd7 787 uint8_t RESERVED_1[4];
mbed_official 68:41613245dfd7 788 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
mbed_official 68:41613245dfd7 789 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
mbed_official 68:41613245dfd7 790 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
mbed_official 68:41613245dfd7 791 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
mbed_official 68:41613245dfd7 792 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
mbed_official 68:41613245dfd7 793 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
mbed_official 68:41613245dfd7 794 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
mbed_official 68:41613245dfd7 795 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
mbed_official 68:41613245dfd7 796 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
mbed_official 68:41613245dfd7 797 uint8_t RESERVED_2[4];
mbed_official 68:41613245dfd7 798 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
mbed_official 68:41613245dfd7 799 uint8_t RESERVED_3[4];
mbed_official 68:41613245dfd7 800 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
mbed_official 68:41613245dfd7 801 uint8_t RESERVED_4[4];
mbed_official 68:41613245dfd7 802 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
mbed_official 68:41613245dfd7 803 uint8_t RESERVED_5[200];
mbed_official 68:41613245dfd7 804 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
mbed_official 68:41613245dfd7 805 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
mbed_official 68:41613245dfd7 806 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
mbed_official 68:41613245dfd7 807 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
mbed_official 68:41613245dfd7 808 uint8_t RESERVED_6[3836];
mbed_official 68:41613245dfd7 809 struct { /* offset: 0x1000, array step: 0x20 */
mbed_official 68:41613245dfd7 810 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
mbed_official 68:41613245dfd7 811 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
mbed_official 68:41613245dfd7 812 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
mbed_official 68:41613245dfd7 813 union { /* offset: 0x1008, array step: 0x20 */
mbed_official 68:41613245dfd7 814 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 68:41613245dfd7 815 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 68:41613245dfd7 816 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
mbed_official 68:41613245dfd7 817 };
mbed_official 68:41613245dfd7 818 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
mbed_official 68:41613245dfd7 819 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
mbed_official 68:41613245dfd7 820 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
mbed_official 68:41613245dfd7 821 union { /* offset: 0x1016, array step: 0x20 */
mbed_official 68:41613245dfd7 822 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
mbed_official 68:41613245dfd7 823 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
mbed_official 68:41613245dfd7 824 };
mbed_official 68:41613245dfd7 825 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
mbed_official 68:41613245dfd7 826 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
mbed_official 68:41613245dfd7 827 union { /* offset: 0x101E, array step: 0x20 */
mbed_official 68:41613245dfd7 828 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
mbed_official 68:41613245dfd7 829 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
mbed_official 68:41613245dfd7 830 };
mbed_official 68:41613245dfd7 831 } TCD[4];
mbed_official 68:41613245dfd7 832 } DMA_Type;
mbed_official 68:41613245dfd7 833
mbed_official 68:41613245dfd7 834 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 835 -- DMA Register Masks
mbed_official 68:41613245dfd7 836 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 837
mbed_official 68:41613245dfd7 838 /**
mbed_official 68:41613245dfd7 839 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 68:41613245dfd7 840 * @{
mbed_official 68:41613245dfd7 841 */
mbed_official 68:41613245dfd7 842
mbed_official 68:41613245dfd7 843 /* CR Bit Fields */
mbed_official 68:41613245dfd7 844 #define DMA_CR_EDBG_MASK 0x2u
mbed_official 68:41613245dfd7 845 #define DMA_CR_EDBG_SHIFT 1
mbed_official 68:41613245dfd7 846 #define DMA_CR_ERCA_MASK 0x4u
mbed_official 68:41613245dfd7 847 #define DMA_CR_ERCA_SHIFT 2
mbed_official 68:41613245dfd7 848 #define DMA_CR_HOE_MASK 0x10u
mbed_official 68:41613245dfd7 849 #define DMA_CR_HOE_SHIFT 4
mbed_official 68:41613245dfd7 850 #define DMA_CR_HALT_MASK 0x20u
mbed_official 68:41613245dfd7 851 #define DMA_CR_HALT_SHIFT 5
mbed_official 68:41613245dfd7 852 #define DMA_CR_CLM_MASK 0x40u
mbed_official 68:41613245dfd7 853 #define DMA_CR_CLM_SHIFT 6
mbed_official 68:41613245dfd7 854 #define DMA_CR_EMLM_MASK 0x80u
mbed_official 68:41613245dfd7 855 #define DMA_CR_EMLM_SHIFT 7
mbed_official 68:41613245dfd7 856 #define DMA_CR_ECX_MASK 0x10000u
mbed_official 68:41613245dfd7 857 #define DMA_CR_ECX_SHIFT 16
mbed_official 68:41613245dfd7 858 #define DMA_CR_CX_MASK 0x20000u
mbed_official 68:41613245dfd7 859 #define DMA_CR_CX_SHIFT 17
mbed_official 68:41613245dfd7 860 /* ES Bit Fields */
mbed_official 68:41613245dfd7 861 #define DMA_ES_DBE_MASK 0x1u
mbed_official 68:41613245dfd7 862 #define DMA_ES_DBE_SHIFT 0
mbed_official 68:41613245dfd7 863 #define DMA_ES_SBE_MASK 0x2u
mbed_official 68:41613245dfd7 864 #define DMA_ES_SBE_SHIFT 1
mbed_official 68:41613245dfd7 865 #define DMA_ES_SGE_MASK 0x4u
mbed_official 68:41613245dfd7 866 #define DMA_ES_SGE_SHIFT 2
mbed_official 68:41613245dfd7 867 #define DMA_ES_NCE_MASK 0x8u
mbed_official 68:41613245dfd7 868 #define DMA_ES_NCE_SHIFT 3
mbed_official 68:41613245dfd7 869 #define DMA_ES_DOE_MASK 0x10u
mbed_official 68:41613245dfd7 870 #define DMA_ES_DOE_SHIFT 4
mbed_official 68:41613245dfd7 871 #define DMA_ES_DAE_MASK 0x20u
mbed_official 68:41613245dfd7 872 #define DMA_ES_DAE_SHIFT 5
mbed_official 68:41613245dfd7 873 #define DMA_ES_SOE_MASK 0x40u
mbed_official 68:41613245dfd7 874 #define DMA_ES_SOE_SHIFT 6
mbed_official 68:41613245dfd7 875 #define DMA_ES_SAE_MASK 0x80u
mbed_official 68:41613245dfd7 876 #define DMA_ES_SAE_SHIFT 7
mbed_official 68:41613245dfd7 877 #define DMA_ES_ERRCHN_MASK 0xF00u
mbed_official 68:41613245dfd7 878 #define DMA_ES_ERRCHN_SHIFT 8
mbed_official 68:41613245dfd7 879 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
mbed_official 68:41613245dfd7 880 #define DMA_ES_CPE_MASK 0x4000u
mbed_official 68:41613245dfd7 881 #define DMA_ES_CPE_SHIFT 14
mbed_official 68:41613245dfd7 882 #define DMA_ES_ECX_MASK 0x10000u
mbed_official 68:41613245dfd7 883 #define DMA_ES_ECX_SHIFT 16
mbed_official 68:41613245dfd7 884 #define DMA_ES_VLD_MASK 0x80000000u
mbed_official 68:41613245dfd7 885 #define DMA_ES_VLD_SHIFT 31
mbed_official 68:41613245dfd7 886 /* ERQ Bit Fields */
mbed_official 68:41613245dfd7 887 #define DMA_ERQ_ERQ0_MASK 0x1u
mbed_official 68:41613245dfd7 888 #define DMA_ERQ_ERQ0_SHIFT 0
mbed_official 68:41613245dfd7 889 #define DMA_ERQ_ERQ1_MASK 0x2u
mbed_official 68:41613245dfd7 890 #define DMA_ERQ_ERQ1_SHIFT 1
mbed_official 68:41613245dfd7 891 #define DMA_ERQ_ERQ2_MASK 0x4u
mbed_official 68:41613245dfd7 892 #define DMA_ERQ_ERQ2_SHIFT 2
mbed_official 68:41613245dfd7 893 #define DMA_ERQ_ERQ3_MASK 0x8u
mbed_official 68:41613245dfd7 894 #define DMA_ERQ_ERQ3_SHIFT 3
mbed_official 68:41613245dfd7 895 /* EEI Bit Fields */
mbed_official 68:41613245dfd7 896 #define DMA_EEI_EEI0_MASK 0x1u
mbed_official 68:41613245dfd7 897 #define DMA_EEI_EEI0_SHIFT 0
mbed_official 68:41613245dfd7 898 #define DMA_EEI_EEI1_MASK 0x2u
mbed_official 68:41613245dfd7 899 #define DMA_EEI_EEI1_SHIFT 1
mbed_official 68:41613245dfd7 900 #define DMA_EEI_EEI2_MASK 0x4u
mbed_official 68:41613245dfd7 901 #define DMA_EEI_EEI2_SHIFT 2
mbed_official 68:41613245dfd7 902 #define DMA_EEI_EEI3_MASK 0x8u
mbed_official 68:41613245dfd7 903 #define DMA_EEI_EEI3_SHIFT 3
mbed_official 68:41613245dfd7 904 /* CEEI Bit Fields */
mbed_official 68:41613245dfd7 905 #define DMA_CEEI_CEEI_MASK 0xFu
mbed_official 68:41613245dfd7 906 #define DMA_CEEI_CEEI_SHIFT 0
mbed_official 68:41613245dfd7 907 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
mbed_official 68:41613245dfd7 908 #define DMA_CEEI_CAEE_MASK 0x40u
mbed_official 68:41613245dfd7 909 #define DMA_CEEI_CAEE_SHIFT 6
mbed_official 68:41613245dfd7 910 #define DMA_CEEI_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 911 #define DMA_CEEI_NOP_SHIFT 7
mbed_official 68:41613245dfd7 912 /* SEEI Bit Fields */
mbed_official 68:41613245dfd7 913 #define DMA_SEEI_SEEI_MASK 0xFu
mbed_official 68:41613245dfd7 914 #define DMA_SEEI_SEEI_SHIFT 0
mbed_official 68:41613245dfd7 915 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
mbed_official 68:41613245dfd7 916 #define DMA_SEEI_SAEE_MASK 0x40u
mbed_official 68:41613245dfd7 917 #define DMA_SEEI_SAEE_SHIFT 6
mbed_official 68:41613245dfd7 918 #define DMA_SEEI_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 919 #define DMA_SEEI_NOP_SHIFT 7
mbed_official 68:41613245dfd7 920 /* CERQ Bit Fields */
mbed_official 68:41613245dfd7 921 #define DMA_CERQ_CERQ_MASK 0xFu
mbed_official 68:41613245dfd7 922 #define DMA_CERQ_CERQ_SHIFT 0
mbed_official 68:41613245dfd7 923 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
mbed_official 68:41613245dfd7 924 #define DMA_CERQ_CAER_MASK 0x40u
mbed_official 68:41613245dfd7 925 #define DMA_CERQ_CAER_SHIFT 6
mbed_official 68:41613245dfd7 926 #define DMA_CERQ_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 927 #define DMA_CERQ_NOP_SHIFT 7
mbed_official 68:41613245dfd7 928 /* SERQ Bit Fields */
mbed_official 68:41613245dfd7 929 #define DMA_SERQ_SERQ_MASK 0xFu
mbed_official 68:41613245dfd7 930 #define DMA_SERQ_SERQ_SHIFT 0
mbed_official 68:41613245dfd7 931 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
mbed_official 68:41613245dfd7 932 #define DMA_SERQ_SAER_MASK 0x40u
mbed_official 68:41613245dfd7 933 #define DMA_SERQ_SAER_SHIFT 6
mbed_official 68:41613245dfd7 934 #define DMA_SERQ_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 935 #define DMA_SERQ_NOP_SHIFT 7
mbed_official 68:41613245dfd7 936 /* CDNE Bit Fields */
mbed_official 68:41613245dfd7 937 #define DMA_CDNE_CDNE_MASK 0xFu
mbed_official 68:41613245dfd7 938 #define DMA_CDNE_CDNE_SHIFT 0
mbed_official 68:41613245dfd7 939 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
mbed_official 68:41613245dfd7 940 #define DMA_CDNE_CADN_MASK 0x40u
mbed_official 68:41613245dfd7 941 #define DMA_CDNE_CADN_SHIFT 6
mbed_official 68:41613245dfd7 942 #define DMA_CDNE_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 943 #define DMA_CDNE_NOP_SHIFT 7
mbed_official 68:41613245dfd7 944 /* SSRT Bit Fields */
mbed_official 68:41613245dfd7 945 #define DMA_SSRT_SSRT_MASK 0xFu
mbed_official 68:41613245dfd7 946 #define DMA_SSRT_SSRT_SHIFT 0
mbed_official 68:41613245dfd7 947 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
mbed_official 68:41613245dfd7 948 #define DMA_SSRT_SAST_MASK 0x40u
mbed_official 68:41613245dfd7 949 #define DMA_SSRT_SAST_SHIFT 6
mbed_official 68:41613245dfd7 950 #define DMA_SSRT_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 951 #define DMA_SSRT_NOP_SHIFT 7
mbed_official 68:41613245dfd7 952 /* CERR Bit Fields */
mbed_official 68:41613245dfd7 953 #define DMA_CERR_CERR_MASK 0xFu
mbed_official 68:41613245dfd7 954 #define DMA_CERR_CERR_SHIFT 0
mbed_official 68:41613245dfd7 955 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
mbed_official 68:41613245dfd7 956 #define DMA_CERR_CAEI_MASK 0x40u
mbed_official 68:41613245dfd7 957 #define DMA_CERR_CAEI_SHIFT 6
mbed_official 68:41613245dfd7 958 #define DMA_CERR_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 959 #define DMA_CERR_NOP_SHIFT 7
mbed_official 68:41613245dfd7 960 /* CINT Bit Fields */
mbed_official 68:41613245dfd7 961 #define DMA_CINT_CINT_MASK 0xFu
mbed_official 68:41613245dfd7 962 #define DMA_CINT_CINT_SHIFT 0
mbed_official 68:41613245dfd7 963 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
mbed_official 68:41613245dfd7 964 #define DMA_CINT_CAIR_MASK 0x40u
mbed_official 68:41613245dfd7 965 #define DMA_CINT_CAIR_SHIFT 6
mbed_official 68:41613245dfd7 966 #define DMA_CINT_NOP_MASK 0x80u
mbed_official 68:41613245dfd7 967 #define DMA_CINT_NOP_SHIFT 7
mbed_official 68:41613245dfd7 968 /* INT Bit Fields */
mbed_official 68:41613245dfd7 969 #define DMA_INT_INT0_MASK 0x1u
mbed_official 68:41613245dfd7 970 #define DMA_INT_INT0_SHIFT 0
mbed_official 68:41613245dfd7 971 #define DMA_INT_INT1_MASK 0x2u
mbed_official 68:41613245dfd7 972 #define DMA_INT_INT1_SHIFT 1
mbed_official 68:41613245dfd7 973 #define DMA_INT_INT2_MASK 0x4u
mbed_official 68:41613245dfd7 974 #define DMA_INT_INT2_SHIFT 2
mbed_official 68:41613245dfd7 975 #define DMA_INT_INT3_MASK 0x8u
mbed_official 68:41613245dfd7 976 #define DMA_INT_INT3_SHIFT 3
mbed_official 68:41613245dfd7 977 /* ERR Bit Fields */
mbed_official 68:41613245dfd7 978 #define DMA_ERR_ERR0_MASK 0x1u
mbed_official 68:41613245dfd7 979 #define DMA_ERR_ERR0_SHIFT 0
mbed_official 68:41613245dfd7 980 #define DMA_ERR_ERR1_MASK 0x2u
mbed_official 68:41613245dfd7 981 #define DMA_ERR_ERR1_SHIFT 1
mbed_official 68:41613245dfd7 982 #define DMA_ERR_ERR2_MASK 0x4u
mbed_official 68:41613245dfd7 983 #define DMA_ERR_ERR2_SHIFT 2
mbed_official 68:41613245dfd7 984 #define DMA_ERR_ERR3_MASK 0x8u
mbed_official 68:41613245dfd7 985 #define DMA_ERR_ERR3_SHIFT 3
mbed_official 68:41613245dfd7 986 /* HRS Bit Fields */
mbed_official 68:41613245dfd7 987 #define DMA_HRS_HRS0_MASK 0x1u
mbed_official 68:41613245dfd7 988 #define DMA_HRS_HRS0_SHIFT 0
mbed_official 68:41613245dfd7 989 #define DMA_HRS_HRS1_MASK 0x2u
mbed_official 68:41613245dfd7 990 #define DMA_HRS_HRS1_SHIFT 1
mbed_official 68:41613245dfd7 991 #define DMA_HRS_HRS2_MASK 0x4u
mbed_official 68:41613245dfd7 992 #define DMA_HRS_HRS2_SHIFT 2
mbed_official 68:41613245dfd7 993 #define DMA_HRS_HRS3_MASK 0x8u
mbed_official 68:41613245dfd7 994 #define DMA_HRS_HRS3_SHIFT 3
mbed_official 68:41613245dfd7 995 /* DCHPRI3 Bit Fields */
mbed_official 68:41613245dfd7 996 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
mbed_official 68:41613245dfd7 997 #define DMA_DCHPRI3_CHPRI_SHIFT 0
mbed_official 68:41613245dfd7 998 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
mbed_official 68:41613245dfd7 999 #define DMA_DCHPRI3_DPA_MASK 0x40u
mbed_official 68:41613245dfd7 1000 #define DMA_DCHPRI3_DPA_SHIFT 6
mbed_official 68:41613245dfd7 1001 #define DMA_DCHPRI3_ECP_MASK 0x80u
mbed_official 68:41613245dfd7 1002 #define DMA_DCHPRI3_ECP_SHIFT 7
mbed_official 68:41613245dfd7 1003 /* DCHPRI2 Bit Fields */
mbed_official 68:41613245dfd7 1004 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
mbed_official 68:41613245dfd7 1005 #define DMA_DCHPRI2_CHPRI_SHIFT 0
mbed_official 68:41613245dfd7 1006 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
mbed_official 68:41613245dfd7 1007 #define DMA_DCHPRI2_DPA_MASK 0x40u
mbed_official 68:41613245dfd7 1008 #define DMA_DCHPRI2_DPA_SHIFT 6
mbed_official 68:41613245dfd7 1009 #define DMA_DCHPRI2_ECP_MASK 0x80u
mbed_official 68:41613245dfd7 1010 #define DMA_DCHPRI2_ECP_SHIFT 7
mbed_official 68:41613245dfd7 1011 /* DCHPRI1 Bit Fields */
mbed_official 68:41613245dfd7 1012 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
mbed_official 68:41613245dfd7 1013 #define DMA_DCHPRI1_CHPRI_SHIFT 0
mbed_official 68:41613245dfd7 1014 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
mbed_official 68:41613245dfd7 1015 #define DMA_DCHPRI1_DPA_MASK 0x40u
mbed_official 68:41613245dfd7 1016 #define DMA_DCHPRI1_DPA_SHIFT 6
mbed_official 68:41613245dfd7 1017 #define DMA_DCHPRI1_ECP_MASK 0x80u
mbed_official 68:41613245dfd7 1018 #define DMA_DCHPRI1_ECP_SHIFT 7
mbed_official 68:41613245dfd7 1019 /* DCHPRI0 Bit Fields */
mbed_official 68:41613245dfd7 1020 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
mbed_official 68:41613245dfd7 1021 #define DMA_DCHPRI0_CHPRI_SHIFT 0
mbed_official 68:41613245dfd7 1022 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
mbed_official 68:41613245dfd7 1023 #define DMA_DCHPRI0_DPA_MASK 0x40u
mbed_official 68:41613245dfd7 1024 #define DMA_DCHPRI0_DPA_SHIFT 6
mbed_official 68:41613245dfd7 1025 #define DMA_DCHPRI0_ECP_MASK 0x80u
mbed_official 68:41613245dfd7 1026 #define DMA_DCHPRI0_ECP_SHIFT 7
mbed_official 68:41613245dfd7 1027 /* SADDR Bit Fields */
mbed_official 68:41613245dfd7 1028 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1029 #define DMA_SADDR_SADDR_SHIFT 0
mbed_official 68:41613245dfd7 1030 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
mbed_official 68:41613245dfd7 1031 /* SOFF Bit Fields */
mbed_official 68:41613245dfd7 1032 #define DMA_SOFF_SOFF_MASK 0xFFFFu
mbed_official 68:41613245dfd7 1033 #define DMA_SOFF_SOFF_SHIFT 0
mbed_official 68:41613245dfd7 1034 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
mbed_official 68:41613245dfd7 1035 /* ATTR Bit Fields */
mbed_official 68:41613245dfd7 1036 #define DMA_ATTR_DSIZE_MASK 0x7u
mbed_official 68:41613245dfd7 1037 #define DMA_ATTR_DSIZE_SHIFT 0
mbed_official 68:41613245dfd7 1038 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
mbed_official 68:41613245dfd7 1039 #define DMA_ATTR_DMOD_MASK 0xF8u
mbed_official 68:41613245dfd7 1040 #define DMA_ATTR_DMOD_SHIFT 3
mbed_official 68:41613245dfd7 1041 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
mbed_official 68:41613245dfd7 1042 #define DMA_ATTR_SSIZE_MASK 0x700u
mbed_official 68:41613245dfd7 1043 #define DMA_ATTR_SSIZE_SHIFT 8
mbed_official 68:41613245dfd7 1044 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
mbed_official 68:41613245dfd7 1045 #define DMA_ATTR_SMOD_MASK 0xF800u
mbed_official 68:41613245dfd7 1046 #define DMA_ATTR_SMOD_SHIFT 11
mbed_official 68:41613245dfd7 1047 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
mbed_official 68:41613245dfd7 1048 /* NBYTES_MLNO Bit Fields */
mbed_official 68:41613245dfd7 1049 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1050 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
mbed_official 68:41613245dfd7 1051 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
mbed_official 68:41613245dfd7 1052 /* NBYTES_MLOFFNO Bit Fields */
mbed_official 68:41613245dfd7 1053 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
mbed_official 68:41613245dfd7 1054 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
mbed_official 68:41613245dfd7 1055 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
mbed_official 68:41613245dfd7 1056 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
mbed_official 68:41613245dfd7 1057 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
mbed_official 68:41613245dfd7 1058 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
mbed_official 68:41613245dfd7 1059 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
mbed_official 68:41613245dfd7 1060 /* NBYTES_MLOFFYES Bit Fields */
mbed_official 68:41613245dfd7 1061 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
mbed_official 68:41613245dfd7 1062 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
mbed_official 68:41613245dfd7 1063 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
mbed_official 68:41613245dfd7 1064 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
mbed_official 68:41613245dfd7 1065 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
mbed_official 68:41613245dfd7 1066 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
mbed_official 68:41613245dfd7 1067 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
mbed_official 68:41613245dfd7 1068 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
mbed_official 68:41613245dfd7 1069 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
mbed_official 68:41613245dfd7 1070 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
mbed_official 68:41613245dfd7 1071 /* SLAST Bit Fields */
mbed_official 68:41613245dfd7 1072 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1073 #define DMA_SLAST_SLAST_SHIFT 0
mbed_official 68:41613245dfd7 1074 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
mbed_official 68:41613245dfd7 1075 /* DADDR Bit Fields */
mbed_official 68:41613245dfd7 1076 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1077 #define DMA_DADDR_DADDR_SHIFT 0
mbed_official 68:41613245dfd7 1078 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
mbed_official 68:41613245dfd7 1079 /* DOFF Bit Fields */
mbed_official 68:41613245dfd7 1080 #define DMA_DOFF_DOFF_MASK 0xFFFFu
mbed_official 68:41613245dfd7 1081 #define DMA_DOFF_DOFF_SHIFT 0
mbed_official 68:41613245dfd7 1082 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
mbed_official 68:41613245dfd7 1083 /* CITER_ELINKNO Bit Fields */
mbed_official 68:41613245dfd7 1084 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
mbed_official 68:41613245dfd7 1085 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
mbed_official 68:41613245dfd7 1086 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
mbed_official 68:41613245dfd7 1087 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
mbed_official 68:41613245dfd7 1088 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
mbed_official 68:41613245dfd7 1089 /* CITER_ELINKYES Bit Fields */
mbed_official 68:41613245dfd7 1090 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
mbed_official 68:41613245dfd7 1091 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
mbed_official 68:41613245dfd7 1092 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
mbed_official 68:41613245dfd7 1093 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
mbed_official 68:41613245dfd7 1094 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
mbed_official 68:41613245dfd7 1095 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
mbed_official 68:41613245dfd7 1096 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
mbed_official 68:41613245dfd7 1097 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
mbed_official 68:41613245dfd7 1098 /* DLAST_SGA Bit Fields */
mbed_official 68:41613245dfd7 1099 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1100 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
mbed_official 68:41613245dfd7 1101 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
mbed_official 68:41613245dfd7 1102 /* CSR Bit Fields */
mbed_official 68:41613245dfd7 1103 #define DMA_CSR_START_MASK 0x1u
mbed_official 68:41613245dfd7 1104 #define DMA_CSR_START_SHIFT 0
mbed_official 68:41613245dfd7 1105 #define DMA_CSR_INTMAJOR_MASK 0x2u
mbed_official 68:41613245dfd7 1106 #define DMA_CSR_INTMAJOR_SHIFT 1
mbed_official 68:41613245dfd7 1107 #define DMA_CSR_INTHALF_MASK 0x4u
mbed_official 68:41613245dfd7 1108 #define DMA_CSR_INTHALF_SHIFT 2
mbed_official 68:41613245dfd7 1109 #define DMA_CSR_DREQ_MASK 0x8u
mbed_official 68:41613245dfd7 1110 #define DMA_CSR_DREQ_SHIFT 3
mbed_official 68:41613245dfd7 1111 #define DMA_CSR_ESG_MASK 0x10u
mbed_official 68:41613245dfd7 1112 #define DMA_CSR_ESG_SHIFT 4
mbed_official 68:41613245dfd7 1113 #define DMA_CSR_MAJORELINK_MASK 0x20u
mbed_official 68:41613245dfd7 1114 #define DMA_CSR_MAJORELINK_SHIFT 5
mbed_official 68:41613245dfd7 1115 #define DMA_CSR_ACTIVE_MASK 0x40u
mbed_official 68:41613245dfd7 1116 #define DMA_CSR_ACTIVE_SHIFT 6
mbed_official 68:41613245dfd7 1117 #define DMA_CSR_DONE_MASK 0x80u
mbed_official 68:41613245dfd7 1118 #define DMA_CSR_DONE_SHIFT 7
mbed_official 68:41613245dfd7 1119 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
mbed_official 68:41613245dfd7 1120 #define DMA_CSR_MAJORLINKCH_SHIFT 8
mbed_official 68:41613245dfd7 1121 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
mbed_official 68:41613245dfd7 1122 #define DMA_CSR_BWC_MASK 0xC000u
mbed_official 68:41613245dfd7 1123 #define DMA_CSR_BWC_SHIFT 14
mbed_official 68:41613245dfd7 1124 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
mbed_official 68:41613245dfd7 1125 /* BITER_ELINKNO Bit Fields */
mbed_official 68:41613245dfd7 1126 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
mbed_official 68:41613245dfd7 1127 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
mbed_official 68:41613245dfd7 1128 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
mbed_official 68:41613245dfd7 1129 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
mbed_official 68:41613245dfd7 1130 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
mbed_official 68:41613245dfd7 1131 /* BITER_ELINKYES Bit Fields */
mbed_official 68:41613245dfd7 1132 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
mbed_official 68:41613245dfd7 1133 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
mbed_official 68:41613245dfd7 1134 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
mbed_official 68:41613245dfd7 1135 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
mbed_official 68:41613245dfd7 1136 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
mbed_official 68:41613245dfd7 1137 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
mbed_official 68:41613245dfd7 1138 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
mbed_official 68:41613245dfd7 1139 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
mbed_official 68:41613245dfd7 1140
mbed_official 68:41613245dfd7 1141 /**
mbed_official 68:41613245dfd7 1142 * @}
mbed_official 68:41613245dfd7 1143 */ /* end of group DMA_Register_Masks */
mbed_official 68:41613245dfd7 1144
mbed_official 68:41613245dfd7 1145
mbed_official 68:41613245dfd7 1146 /* DMA - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 1147 /** Peripheral DMA base address */
mbed_official 68:41613245dfd7 1148 #define DMA_BASE (0x40008000u)
mbed_official 68:41613245dfd7 1149 /** Peripheral DMA base pointer */
mbed_official 68:41613245dfd7 1150 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 68:41613245dfd7 1151
mbed_official 68:41613245dfd7 1152 /**
mbed_official 68:41613245dfd7 1153 * @}
mbed_official 68:41613245dfd7 1154 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 1155
mbed_official 68:41613245dfd7 1156
mbed_official 68:41613245dfd7 1157 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1158 -- DMAMUX Peripheral Access Layer
mbed_official 68:41613245dfd7 1159 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1160
mbed_official 68:41613245dfd7 1161 /**
mbed_official 68:41613245dfd7 1162 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 68:41613245dfd7 1163 * @{
mbed_official 68:41613245dfd7 1164 */
mbed_official 68:41613245dfd7 1165
mbed_official 68:41613245dfd7 1166 /** DMAMUX - Register Layout Typedef */
mbed_official 68:41613245dfd7 1167 typedef struct {
mbed_official 68:41613245dfd7 1168 __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
mbed_official 68:41613245dfd7 1169 } DMAMUX_Type;
mbed_official 68:41613245dfd7 1170
mbed_official 68:41613245dfd7 1171 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1172 -- DMAMUX Register Masks
mbed_official 68:41613245dfd7 1173 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1174
mbed_official 68:41613245dfd7 1175 /**
mbed_official 68:41613245dfd7 1176 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 68:41613245dfd7 1177 * @{
mbed_official 68:41613245dfd7 1178 */
mbed_official 68:41613245dfd7 1179
mbed_official 68:41613245dfd7 1180 /* CHCFG Bit Fields */
mbed_official 68:41613245dfd7 1181 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 68:41613245dfd7 1182 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 68:41613245dfd7 1183 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 68:41613245dfd7 1184 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 68:41613245dfd7 1185 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 68:41613245dfd7 1186 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 68:41613245dfd7 1187 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 68:41613245dfd7 1188
mbed_official 68:41613245dfd7 1189 /**
mbed_official 68:41613245dfd7 1190 * @}
mbed_official 68:41613245dfd7 1191 */ /* end of group DMAMUX_Register_Masks */
mbed_official 68:41613245dfd7 1192
mbed_official 68:41613245dfd7 1193
mbed_official 68:41613245dfd7 1194 /* DMAMUX - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 1195 /** Peripheral DMAMUX base address */
mbed_official 68:41613245dfd7 1196 #define DMAMUX_BASE (0x40021000u)
mbed_official 68:41613245dfd7 1197 /** Peripheral DMAMUX base pointer */
mbed_official 68:41613245dfd7 1198 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
mbed_official 68:41613245dfd7 1199
mbed_official 68:41613245dfd7 1200 /**
mbed_official 68:41613245dfd7 1201 * @}
mbed_official 68:41613245dfd7 1202 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 1203
mbed_official 68:41613245dfd7 1204
mbed_official 68:41613245dfd7 1205 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1206 -- EWM Peripheral Access Layer
mbed_official 68:41613245dfd7 1207 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1208
mbed_official 68:41613245dfd7 1209 /**
mbed_official 68:41613245dfd7 1210 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
mbed_official 68:41613245dfd7 1211 * @{
mbed_official 68:41613245dfd7 1212 */
mbed_official 68:41613245dfd7 1213
mbed_official 68:41613245dfd7 1214 /** EWM - Register Layout Typedef */
mbed_official 68:41613245dfd7 1215 typedef struct {
mbed_official 68:41613245dfd7 1216 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 1217 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
mbed_official 68:41613245dfd7 1218 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
mbed_official 68:41613245dfd7 1219 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
mbed_official 68:41613245dfd7 1220 } EWM_Type;
mbed_official 68:41613245dfd7 1221
mbed_official 68:41613245dfd7 1222 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1223 -- EWM Register Masks
mbed_official 68:41613245dfd7 1224 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1225
mbed_official 68:41613245dfd7 1226 /**
mbed_official 68:41613245dfd7 1227 * @addtogroup EWM_Register_Masks EWM Register Masks
mbed_official 68:41613245dfd7 1228 * @{
mbed_official 68:41613245dfd7 1229 */
mbed_official 68:41613245dfd7 1230
mbed_official 68:41613245dfd7 1231 /* CTRL Bit Fields */
mbed_official 68:41613245dfd7 1232 #define EWM_CTRL_EWMEN_MASK 0x1u
mbed_official 68:41613245dfd7 1233 #define EWM_CTRL_EWMEN_SHIFT 0
mbed_official 68:41613245dfd7 1234 #define EWM_CTRL_ASSIN_MASK 0x2u
mbed_official 68:41613245dfd7 1235 #define EWM_CTRL_ASSIN_SHIFT 1
mbed_official 68:41613245dfd7 1236 #define EWM_CTRL_INEN_MASK 0x4u
mbed_official 68:41613245dfd7 1237 #define EWM_CTRL_INEN_SHIFT 2
mbed_official 68:41613245dfd7 1238 #define EWM_CTRL_INTEN_MASK 0x8u
mbed_official 68:41613245dfd7 1239 #define EWM_CTRL_INTEN_SHIFT 3
mbed_official 68:41613245dfd7 1240 /* SERV Bit Fields */
mbed_official 68:41613245dfd7 1241 #define EWM_SERV_SERVICE_MASK 0xFFu
mbed_official 68:41613245dfd7 1242 #define EWM_SERV_SERVICE_SHIFT 0
mbed_official 68:41613245dfd7 1243 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
mbed_official 68:41613245dfd7 1244 /* CMPL Bit Fields */
mbed_official 68:41613245dfd7 1245 #define EWM_CMPL_COMPAREL_MASK 0xFFu
mbed_official 68:41613245dfd7 1246 #define EWM_CMPL_COMPAREL_SHIFT 0
mbed_official 68:41613245dfd7 1247 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
mbed_official 68:41613245dfd7 1248 /* CMPH Bit Fields */
mbed_official 68:41613245dfd7 1249 #define EWM_CMPH_COMPAREH_MASK 0xFFu
mbed_official 68:41613245dfd7 1250 #define EWM_CMPH_COMPAREH_SHIFT 0
mbed_official 68:41613245dfd7 1251 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
mbed_official 68:41613245dfd7 1252
mbed_official 68:41613245dfd7 1253 /**
mbed_official 68:41613245dfd7 1254 * @}
mbed_official 68:41613245dfd7 1255 */ /* end of group EWM_Register_Masks */
mbed_official 68:41613245dfd7 1256
mbed_official 68:41613245dfd7 1257
mbed_official 68:41613245dfd7 1258 /* EWM - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 1259 /** Peripheral EWM base address */
mbed_official 68:41613245dfd7 1260 #define EWM_BASE (0x40061000u)
mbed_official 68:41613245dfd7 1261 /** Peripheral EWM base pointer */
mbed_official 68:41613245dfd7 1262 #define EWM ((EWM_Type *)EWM_BASE)
mbed_official 68:41613245dfd7 1263
mbed_official 68:41613245dfd7 1264 /**
mbed_official 68:41613245dfd7 1265 * @}
mbed_official 68:41613245dfd7 1266 */ /* end of group EWM_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 1267
mbed_official 68:41613245dfd7 1268
mbed_official 68:41613245dfd7 1269 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1270 -- FMC Peripheral Access Layer
mbed_official 68:41613245dfd7 1271 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1272
mbed_official 68:41613245dfd7 1273 /**
mbed_official 68:41613245dfd7 1274 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
mbed_official 68:41613245dfd7 1275 * @{
mbed_official 68:41613245dfd7 1276 */
mbed_official 68:41613245dfd7 1277
mbed_official 68:41613245dfd7 1278 /** FMC - Register Layout Typedef */
mbed_official 68:41613245dfd7 1279 typedef struct {
mbed_official 68:41613245dfd7 1280 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
mbed_official 68:41613245dfd7 1281 __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
mbed_official 68:41613245dfd7 1282 uint8_t RESERVED_0[248];
mbed_official 68:41613245dfd7 1283 struct { /* offset: 0x100, array step: 0x20 */
mbed_official 68:41613245dfd7 1284 __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
mbed_official 68:41613245dfd7 1285 uint8_t RESERVED_0[24];
mbed_official 68:41613245dfd7 1286 } TAG_WAY[4];
mbed_official 68:41613245dfd7 1287 uint8_t RESERVED_1[132];
mbed_official 68:41613245dfd7 1288 struct { /* offset: 0x204, array step: 0x8 */
mbed_official 68:41613245dfd7 1289 __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
mbed_official 68:41613245dfd7 1290 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 1291 } DATAW0S[2];
mbed_official 68:41613245dfd7 1292 uint8_t RESERVED_2[48];
mbed_official 68:41613245dfd7 1293 struct { /* offset: 0x244, array step: 0x8 */
mbed_official 68:41613245dfd7 1294 __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
mbed_official 68:41613245dfd7 1295 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 1296 } DATAW1S[2];
mbed_official 68:41613245dfd7 1297 uint8_t RESERVED_3[48];
mbed_official 68:41613245dfd7 1298 struct { /* offset: 0x284, array step: 0x8 */
mbed_official 68:41613245dfd7 1299 __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
mbed_official 68:41613245dfd7 1300 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 1301 } DATAW2S[2];
mbed_official 68:41613245dfd7 1302 uint8_t RESERVED_4[48];
mbed_official 68:41613245dfd7 1303 struct { /* offset: 0x2C4, array step: 0x8 */
mbed_official 68:41613245dfd7 1304 __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
mbed_official 68:41613245dfd7 1305 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 1306 } DATAW3S[2];
mbed_official 68:41613245dfd7 1307 } FMC_Type;
mbed_official 68:41613245dfd7 1308
mbed_official 68:41613245dfd7 1309 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1310 -- FMC Register Masks
mbed_official 68:41613245dfd7 1311 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1312
mbed_official 68:41613245dfd7 1313 /**
mbed_official 68:41613245dfd7 1314 * @addtogroup FMC_Register_Masks FMC Register Masks
mbed_official 68:41613245dfd7 1315 * @{
mbed_official 68:41613245dfd7 1316 */
mbed_official 68:41613245dfd7 1317
mbed_official 68:41613245dfd7 1318 /* PFAPR Bit Fields */
mbed_official 68:41613245dfd7 1319 #define FMC_PFAPR_M0AP_MASK 0x3u
mbed_official 68:41613245dfd7 1320 #define FMC_PFAPR_M0AP_SHIFT 0
mbed_official 68:41613245dfd7 1321 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
mbed_official 68:41613245dfd7 1322 #define FMC_PFAPR_M1AP_MASK 0xCu
mbed_official 68:41613245dfd7 1323 #define FMC_PFAPR_M1AP_SHIFT 2
mbed_official 68:41613245dfd7 1324 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
mbed_official 68:41613245dfd7 1325 #define FMC_PFAPR_M2AP_MASK 0x30u
mbed_official 68:41613245dfd7 1326 #define FMC_PFAPR_M2AP_SHIFT 4
mbed_official 68:41613245dfd7 1327 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
mbed_official 68:41613245dfd7 1328 #define FMC_PFAPR_M3AP_MASK 0xC0u
mbed_official 68:41613245dfd7 1329 #define FMC_PFAPR_M3AP_SHIFT 6
mbed_official 68:41613245dfd7 1330 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
mbed_official 68:41613245dfd7 1331 #define FMC_PFAPR_M0PFD_MASK 0x10000u
mbed_official 68:41613245dfd7 1332 #define FMC_PFAPR_M0PFD_SHIFT 16
mbed_official 68:41613245dfd7 1333 #define FMC_PFAPR_M1PFD_MASK 0x20000u
mbed_official 68:41613245dfd7 1334 #define FMC_PFAPR_M1PFD_SHIFT 17
mbed_official 68:41613245dfd7 1335 #define FMC_PFAPR_M2PFD_MASK 0x40000u
mbed_official 68:41613245dfd7 1336 #define FMC_PFAPR_M2PFD_SHIFT 18
mbed_official 68:41613245dfd7 1337 #define FMC_PFAPR_M3PFD_MASK 0x80000u
mbed_official 68:41613245dfd7 1338 #define FMC_PFAPR_M3PFD_SHIFT 19
mbed_official 68:41613245dfd7 1339 /* PFB0CR Bit Fields */
mbed_official 68:41613245dfd7 1340 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
mbed_official 68:41613245dfd7 1341 #define FMC_PFB0CR_B0SEBE_SHIFT 0
mbed_official 68:41613245dfd7 1342 #define FMC_PFB0CR_B0IPE_MASK 0x2u
mbed_official 68:41613245dfd7 1343 #define FMC_PFB0CR_B0IPE_SHIFT 1
mbed_official 68:41613245dfd7 1344 #define FMC_PFB0CR_B0DPE_MASK 0x4u
mbed_official 68:41613245dfd7 1345 #define FMC_PFB0CR_B0DPE_SHIFT 2
mbed_official 68:41613245dfd7 1346 #define FMC_PFB0CR_B0ICE_MASK 0x8u
mbed_official 68:41613245dfd7 1347 #define FMC_PFB0CR_B0ICE_SHIFT 3
mbed_official 68:41613245dfd7 1348 #define FMC_PFB0CR_B0DCE_MASK 0x10u
mbed_official 68:41613245dfd7 1349 #define FMC_PFB0CR_B0DCE_SHIFT 4
mbed_official 68:41613245dfd7 1350 #define FMC_PFB0CR_CRC_MASK 0xE0u
mbed_official 68:41613245dfd7 1351 #define FMC_PFB0CR_CRC_SHIFT 5
mbed_official 68:41613245dfd7 1352 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
mbed_official 68:41613245dfd7 1353 #define FMC_PFB0CR_B0MW_MASK 0x60000u
mbed_official 68:41613245dfd7 1354 #define FMC_PFB0CR_B0MW_SHIFT 17
mbed_official 68:41613245dfd7 1355 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
mbed_official 68:41613245dfd7 1356 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
mbed_official 68:41613245dfd7 1357 #define FMC_PFB0CR_S_B_INV_SHIFT 19
mbed_official 68:41613245dfd7 1358 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
mbed_official 68:41613245dfd7 1359 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
mbed_official 68:41613245dfd7 1360 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
mbed_official 68:41613245dfd7 1361 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
mbed_official 68:41613245dfd7 1362 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
mbed_official 68:41613245dfd7 1363 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
mbed_official 68:41613245dfd7 1364 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
mbed_official 68:41613245dfd7 1365 #define FMC_PFB0CR_B0RWSC_SHIFT 28
mbed_official 68:41613245dfd7 1366 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
mbed_official 68:41613245dfd7 1367 /* TAGVD Bit Fields */
mbed_official 68:41613245dfd7 1368 #define FMC_TAGVD_valid_MASK 0x1u
mbed_official 68:41613245dfd7 1369 #define FMC_TAGVD_valid_SHIFT 0
mbed_official 68:41613245dfd7 1370 #define FMC_TAGVD_tag_MASK 0x7FFC0u
mbed_official 68:41613245dfd7 1371 #define FMC_TAGVD_tag_SHIFT 6
mbed_official 68:41613245dfd7 1372 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
mbed_official 68:41613245dfd7 1373 /* DATAW0S Bit Fields */
mbed_official 68:41613245dfd7 1374 #define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1375 #define FMC_DATAW0S_data_SHIFT 0
mbed_official 68:41613245dfd7 1376 #define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
mbed_official 68:41613245dfd7 1377 /* DATAW1S Bit Fields */
mbed_official 68:41613245dfd7 1378 #define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1379 #define FMC_DATAW1S_data_SHIFT 0
mbed_official 68:41613245dfd7 1380 #define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
mbed_official 68:41613245dfd7 1381 /* DATAW2S Bit Fields */
mbed_official 68:41613245dfd7 1382 #define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1383 #define FMC_DATAW2S_data_SHIFT 0
mbed_official 68:41613245dfd7 1384 #define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
mbed_official 68:41613245dfd7 1385 /* DATAW3S Bit Fields */
mbed_official 68:41613245dfd7 1386 #define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 1387 #define FMC_DATAW3S_data_SHIFT 0
mbed_official 68:41613245dfd7 1388 #define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
mbed_official 68:41613245dfd7 1389
mbed_official 68:41613245dfd7 1390 /**
mbed_official 68:41613245dfd7 1391 * @}
mbed_official 68:41613245dfd7 1392 */ /* end of group FMC_Register_Masks */
mbed_official 68:41613245dfd7 1393
mbed_official 68:41613245dfd7 1394
mbed_official 68:41613245dfd7 1395 /* FMC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 1396 /** Peripheral FMC base address */
mbed_official 68:41613245dfd7 1397 #define FMC_BASE (0x4001F000u)
mbed_official 68:41613245dfd7 1398 /** Peripheral FMC base pointer */
mbed_official 68:41613245dfd7 1399 #define FMC ((FMC_Type *)FMC_BASE)
mbed_official 68:41613245dfd7 1400
mbed_official 68:41613245dfd7 1401 /**
mbed_official 68:41613245dfd7 1402 * @}
mbed_official 68:41613245dfd7 1403 */ /* end of group FMC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 1404
mbed_official 68:41613245dfd7 1405
mbed_official 68:41613245dfd7 1406 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1407 -- FTFL Peripheral Access Layer
mbed_official 68:41613245dfd7 1408 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1409
mbed_official 68:41613245dfd7 1410 /**
mbed_official 68:41613245dfd7 1411 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
mbed_official 68:41613245dfd7 1412 * @{
mbed_official 68:41613245dfd7 1413 */
mbed_official 68:41613245dfd7 1414
mbed_official 68:41613245dfd7 1415 /** FTFL - Register Layout Typedef */
mbed_official 68:41613245dfd7 1416 typedef struct {
mbed_official 68:41613245dfd7 1417 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 68:41613245dfd7 1418 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 68:41613245dfd7 1419 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 68:41613245dfd7 1420 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 68:41613245dfd7 1421 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 68:41613245dfd7 1422 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 68:41613245dfd7 1423 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 68:41613245dfd7 1424 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 68:41613245dfd7 1425 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 68:41613245dfd7 1426 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 68:41613245dfd7 1427 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 68:41613245dfd7 1428 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 68:41613245dfd7 1429 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 68:41613245dfd7 1430 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 68:41613245dfd7 1431 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 68:41613245dfd7 1432 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 68:41613245dfd7 1433 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 68:41613245dfd7 1434 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 68:41613245dfd7 1435 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 68:41613245dfd7 1436 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 68:41613245dfd7 1437 uint8_t RESERVED_0[2];
mbed_official 68:41613245dfd7 1438 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
mbed_official 68:41613245dfd7 1439 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
mbed_official 68:41613245dfd7 1440 } FTFL_Type;
mbed_official 68:41613245dfd7 1441
mbed_official 68:41613245dfd7 1442 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1443 -- FTFL Register Masks
mbed_official 68:41613245dfd7 1444 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1445
mbed_official 68:41613245dfd7 1446 /**
mbed_official 68:41613245dfd7 1447 * @addtogroup FTFL_Register_Masks FTFL Register Masks
mbed_official 68:41613245dfd7 1448 * @{
mbed_official 68:41613245dfd7 1449 */
mbed_official 68:41613245dfd7 1450
mbed_official 68:41613245dfd7 1451 /* FSTAT Bit Fields */
mbed_official 68:41613245dfd7 1452 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 68:41613245dfd7 1453 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
mbed_official 68:41613245dfd7 1454 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
mbed_official 68:41613245dfd7 1455 #define FTFL_FSTAT_FPVIOL_SHIFT 4
mbed_official 68:41613245dfd7 1456 #define FTFL_FSTAT_ACCERR_MASK 0x20u
mbed_official 68:41613245dfd7 1457 #define FTFL_FSTAT_ACCERR_SHIFT 5
mbed_official 68:41613245dfd7 1458 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 68:41613245dfd7 1459 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
mbed_official 68:41613245dfd7 1460 #define FTFL_FSTAT_CCIF_MASK 0x80u
mbed_official 68:41613245dfd7 1461 #define FTFL_FSTAT_CCIF_SHIFT 7
mbed_official 68:41613245dfd7 1462 /* FCNFG Bit Fields */
mbed_official 68:41613245dfd7 1463 #define FTFL_FCNFG_EEERDY_MASK 0x1u
mbed_official 68:41613245dfd7 1464 #define FTFL_FCNFG_EEERDY_SHIFT 0
mbed_official 68:41613245dfd7 1465 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
mbed_official 68:41613245dfd7 1466 #define FTFL_FCNFG_RAMRDY_SHIFT 1
mbed_official 68:41613245dfd7 1467 #define FTFL_FCNFG_PFLSH_MASK 0x4u
mbed_official 68:41613245dfd7 1468 #define FTFL_FCNFG_PFLSH_SHIFT 2
mbed_official 68:41613245dfd7 1469 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 68:41613245dfd7 1470 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
mbed_official 68:41613245dfd7 1471 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 68:41613245dfd7 1472 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
mbed_official 68:41613245dfd7 1473 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 68:41613245dfd7 1474 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 68:41613245dfd7 1475 #define FTFL_FCNFG_CCIE_MASK 0x80u
mbed_official 68:41613245dfd7 1476 #define FTFL_FCNFG_CCIE_SHIFT 7
mbed_official 68:41613245dfd7 1477 /* FSEC Bit Fields */
mbed_official 68:41613245dfd7 1478 #define FTFL_FSEC_SEC_MASK 0x3u
mbed_official 68:41613245dfd7 1479 #define FTFL_FSEC_SEC_SHIFT 0
mbed_official 68:41613245dfd7 1480 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
mbed_official 68:41613245dfd7 1481 #define FTFL_FSEC_FSLACC_MASK 0xCu
mbed_official 68:41613245dfd7 1482 #define FTFL_FSEC_FSLACC_SHIFT 2
mbed_official 68:41613245dfd7 1483 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
mbed_official 68:41613245dfd7 1484 #define FTFL_FSEC_MEEN_MASK 0x30u
mbed_official 68:41613245dfd7 1485 #define FTFL_FSEC_MEEN_SHIFT 4
mbed_official 68:41613245dfd7 1486 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
mbed_official 68:41613245dfd7 1487 #define FTFL_FSEC_KEYEN_MASK 0xC0u
mbed_official 68:41613245dfd7 1488 #define FTFL_FSEC_KEYEN_SHIFT 6
mbed_official 68:41613245dfd7 1489 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
mbed_official 68:41613245dfd7 1490 /* FOPT Bit Fields */
mbed_official 68:41613245dfd7 1491 #define FTFL_FOPT_OPT_MASK 0xFFu
mbed_official 68:41613245dfd7 1492 #define FTFL_FOPT_OPT_SHIFT 0
mbed_official 68:41613245dfd7 1493 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
mbed_official 68:41613245dfd7 1494 /* FCCOB3 Bit Fields */
mbed_official 68:41613245dfd7 1495 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1496 #define FTFL_FCCOB3_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1497 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
mbed_official 68:41613245dfd7 1498 /* FCCOB2 Bit Fields */
mbed_official 68:41613245dfd7 1499 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1500 #define FTFL_FCCOB2_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1501 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
mbed_official 68:41613245dfd7 1502 /* FCCOB1 Bit Fields */
mbed_official 68:41613245dfd7 1503 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1504 #define FTFL_FCCOB1_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1505 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
mbed_official 68:41613245dfd7 1506 /* FCCOB0 Bit Fields */
mbed_official 68:41613245dfd7 1507 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1508 #define FTFL_FCCOB0_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1509 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
mbed_official 68:41613245dfd7 1510 /* FCCOB7 Bit Fields */
mbed_official 68:41613245dfd7 1511 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1512 #define FTFL_FCCOB7_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1513 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
mbed_official 68:41613245dfd7 1514 /* FCCOB6 Bit Fields */
mbed_official 68:41613245dfd7 1515 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1516 #define FTFL_FCCOB6_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1517 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
mbed_official 68:41613245dfd7 1518 /* FCCOB5 Bit Fields */
mbed_official 68:41613245dfd7 1519 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1520 #define FTFL_FCCOB5_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1521 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
mbed_official 68:41613245dfd7 1522 /* FCCOB4 Bit Fields */
mbed_official 68:41613245dfd7 1523 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1524 #define FTFL_FCCOB4_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1525 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
mbed_official 68:41613245dfd7 1526 /* FCCOBB Bit Fields */
mbed_official 68:41613245dfd7 1527 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1528 #define FTFL_FCCOBB_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1529 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
mbed_official 68:41613245dfd7 1530 /* FCCOBA Bit Fields */
mbed_official 68:41613245dfd7 1531 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1532 #define FTFL_FCCOBA_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1533 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
mbed_official 68:41613245dfd7 1534 /* FCCOB9 Bit Fields */
mbed_official 68:41613245dfd7 1535 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1536 #define FTFL_FCCOB9_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1537 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
mbed_official 68:41613245dfd7 1538 /* FCCOB8 Bit Fields */
mbed_official 68:41613245dfd7 1539 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 68:41613245dfd7 1540 #define FTFL_FCCOB8_CCOBn_SHIFT 0
mbed_official 68:41613245dfd7 1541 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
mbed_official 68:41613245dfd7 1542 /* FPROT3 Bit Fields */
mbed_official 68:41613245dfd7 1543 #define FTFL_FPROT3_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 1544 #define FTFL_FPROT3_PROT_SHIFT 0
mbed_official 68:41613245dfd7 1545 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
mbed_official 68:41613245dfd7 1546 /* FPROT2 Bit Fields */
mbed_official 68:41613245dfd7 1547 #define FTFL_FPROT2_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 1548 #define FTFL_FPROT2_PROT_SHIFT 0
mbed_official 68:41613245dfd7 1549 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
mbed_official 68:41613245dfd7 1550 /* FPROT1 Bit Fields */
mbed_official 68:41613245dfd7 1551 #define FTFL_FPROT1_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 1552 #define FTFL_FPROT1_PROT_SHIFT 0
mbed_official 68:41613245dfd7 1553 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
mbed_official 68:41613245dfd7 1554 /* FPROT0 Bit Fields */
mbed_official 68:41613245dfd7 1555 #define FTFL_FPROT0_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 1556 #define FTFL_FPROT0_PROT_SHIFT 0
mbed_official 68:41613245dfd7 1557 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
mbed_official 68:41613245dfd7 1558 /* FEPROT Bit Fields */
mbed_official 68:41613245dfd7 1559 #define FTFL_FEPROT_EPROT_MASK 0xFFu
mbed_official 68:41613245dfd7 1560 #define FTFL_FEPROT_EPROT_SHIFT 0
mbed_official 68:41613245dfd7 1561 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
mbed_official 68:41613245dfd7 1562 /* FDPROT Bit Fields */
mbed_official 68:41613245dfd7 1563 #define FTFL_FDPROT_DPROT_MASK 0xFFu
mbed_official 68:41613245dfd7 1564 #define FTFL_FDPROT_DPROT_SHIFT 0
mbed_official 68:41613245dfd7 1565 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
mbed_official 68:41613245dfd7 1566
mbed_official 68:41613245dfd7 1567 /**
mbed_official 68:41613245dfd7 1568 * @}
mbed_official 68:41613245dfd7 1569 */ /* end of group FTFL_Register_Masks */
mbed_official 68:41613245dfd7 1570
mbed_official 68:41613245dfd7 1571
mbed_official 68:41613245dfd7 1572 /* FTFL - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 1573 /** Peripheral FTFL base address */
mbed_official 68:41613245dfd7 1574 #define FTFL_BASE (0x40020000u)
mbed_official 68:41613245dfd7 1575 /** Peripheral FTFL base pointer */
mbed_official 68:41613245dfd7 1576 #define FTFL ((FTFL_Type *)FTFL_BASE)
mbed_official 68:41613245dfd7 1577
mbed_official 68:41613245dfd7 1578 /**
mbed_official 68:41613245dfd7 1579 * @}
mbed_official 68:41613245dfd7 1580 */ /* end of group FTFL_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 1581
mbed_official 68:41613245dfd7 1582
mbed_official 68:41613245dfd7 1583 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1584 -- FTM Peripheral Access Layer
mbed_official 68:41613245dfd7 1585 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1586
mbed_official 68:41613245dfd7 1587 /**
mbed_official 68:41613245dfd7 1588 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
mbed_official 68:41613245dfd7 1589 * @{
mbed_official 68:41613245dfd7 1590 */
mbed_official 68:41613245dfd7 1591
mbed_official 68:41613245dfd7 1592 /** FTM - Register Layout Typedef */
mbed_official 68:41613245dfd7 1593 typedef struct {
mbed_official 68:41613245dfd7 1594 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
mbed_official 68:41613245dfd7 1595 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 68:41613245dfd7 1596 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 68:41613245dfd7 1597 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 68:41613245dfd7 1598 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
mbed_official 68:41613245dfd7 1599 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 68:41613245dfd7 1600 } CONTROLS[8];
mbed_official 68:41613245dfd7 1601 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
mbed_official 68:41613245dfd7 1602 __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
mbed_official 68:41613245dfd7 1603 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
mbed_official 68:41613245dfd7 1604 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
mbed_official 68:41613245dfd7 1605 __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
mbed_official 68:41613245dfd7 1606 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
mbed_official 68:41613245dfd7 1607 __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
mbed_official 68:41613245dfd7 1608 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
mbed_official 68:41613245dfd7 1609 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
mbed_official 68:41613245dfd7 1610 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
mbed_official 68:41613245dfd7 1611 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
mbed_official 68:41613245dfd7 1612 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
mbed_official 68:41613245dfd7 1613 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
mbed_official 68:41613245dfd7 1614 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
mbed_official 68:41613245dfd7 1615 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 68:41613245dfd7 1616 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
mbed_official 68:41613245dfd7 1617 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
mbed_official 68:41613245dfd7 1618 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
mbed_official 68:41613245dfd7 1619 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
mbed_official 68:41613245dfd7 1620 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
mbed_official 68:41613245dfd7 1621 } FTM_Type;
mbed_official 68:41613245dfd7 1622
mbed_official 68:41613245dfd7 1623 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 1624 -- FTM Register Masks
mbed_official 68:41613245dfd7 1625 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 1626
mbed_official 68:41613245dfd7 1627 /**
mbed_official 68:41613245dfd7 1628 * @addtogroup FTM_Register_Masks FTM Register Masks
mbed_official 68:41613245dfd7 1629 * @{
mbed_official 68:41613245dfd7 1630 */
mbed_official 68:41613245dfd7 1631
mbed_official 68:41613245dfd7 1632 /* SC Bit Fields */
mbed_official 68:41613245dfd7 1633 #define FTM_SC_PS_MASK 0x7u
mbed_official 68:41613245dfd7 1634 #define FTM_SC_PS_SHIFT 0
mbed_official 68:41613245dfd7 1635 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
mbed_official 68:41613245dfd7 1636 #define FTM_SC_CLKS_MASK 0x18u
mbed_official 68:41613245dfd7 1637 #define FTM_SC_CLKS_SHIFT 3
mbed_official 68:41613245dfd7 1638 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
mbed_official 68:41613245dfd7 1639 #define FTM_SC_CPWMS_MASK 0x20u
mbed_official 68:41613245dfd7 1640 #define FTM_SC_CPWMS_SHIFT 5
mbed_official 68:41613245dfd7 1641 #define FTM_SC_TOIE_MASK 0x40u
mbed_official 68:41613245dfd7 1642 #define FTM_SC_TOIE_SHIFT 6
mbed_official 68:41613245dfd7 1643 #define FTM_SC_TOF_MASK 0x80u
mbed_official 68:41613245dfd7 1644 #define FTM_SC_TOF_SHIFT 7
mbed_official 68:41613245dfd7 1645 /* CNT Bit Fields */
mbed_official 68:41613245dfd7 1646 #define FTM_CNT_COUNT_MASK 0xFFFFu
mbed_official 68:41613245dfd7 1647 #define FTM_CNT_COUNT_SHIFT 0
mbed_official 68:41613245dfd7 1648 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
mbed_official 68:41613245dfd7 1649 /* MOD Bit Fields */
mbed_official 68:41613245dfd7 1650 #define FTM_MOD_MOD_MASK 0xFFFFu
mbed_official 68:41613245dfd7 1651 #define FTM_MOD_MOD_SHIFT 0
mbed_official 68:41613245dfd7 1652 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
mbed_official 68:41613245dfd7 1653 /* CnSC Bit Fields */
mbed_official 68:41613245dfd7 1654 #define FTM_CnSC_DMA_MASK 0x1u
mbed_official 68:41613245dfd7 1655 #define FTM_CnSC_DMA_SHIFT 0
mbed_official 68:41613245dfd7 1656 #define FTM_CnSC_ELSA_MASK 0x4u
mbed_official 68:41613245dfd7 1657 #define FTM_CnSC_ELSA_SHIFT 2
mbed_official 68:41613245dfd7 1658 #define FTM_CnSC_ELSB_MASK 0x8u
mbed_official 68:41613245dfd7 1659 #define FTM_CnSC_ELSB_SHIFT 3
mbed_official 68:41613245dfd7 1660 #define FTM_CnSC_MSA_MASK 0x10u
mbed_official 68:41613245dfd7 1661 #define FTM_CnSC_MSA_SHIFT 4
mbed_official 68:41613245dfd7 1662 #define FTM_CnSC_MSB_MASK 0x20u
mbed_official 68:41613245dfd7 1663 #define FTM_CnSC_MSB_SHIFT 5
mbed_official 68:41613245dfd7 1664 #define FTM_CnSC_CHIE_MASK 0x40u
mbed_official 68:41613245dfd7 1665 #define FTM_CnSC_CHIE_SHIFT 6
mbed_official 68:41613245dfd7 1666 #define FTM_CnSC_CHF_MASK 0x80u
mbed_official 68:41613245dfd7 1667 #define FTM_CnSC_CHF_SHIFT 7
mbed_official 68:41613245dfd7 1668 /* CnV Bit Fields */
mbed_official 68:41613245dfd7 1669 #define FTM_CnV_VAL_MASK 0xFFFFu
mbed_official 68:41613245dfd7 1670 #define FTM_CnV_VAL_SHIFT 0
mbed_official 68:41613245dfd7 1671 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
mbed_official 68:41613245dfd7 1672 /* CNTIN Bit Fields */
mbed_official 68:41613245dfd7 1673 #define FTM_CNTIN_INIT_MASK 0xFFFFu
mbed_official 68:41613245dfd7 1674 #define FTM_CNTIN_INIT_SHIFT 0
mbed_official 68:41613245dfd7 1675 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
mbed_official 68:41613245dfd7 1676 /* STATUS Bit Fields */
mbed_official 68:41613245dfd7 1677 #define FTM_STATUS_CH0F_MASK 0x1u
mbed_official 68:41613245dfd7 1678 #define FTM_STATUS_CH0F_SHIFT 0
mbed_official 68:41613245dfd7 1679 #define FTM_STATUS_CH1F_MASK 0x2u
mbed_official 68:41613245dfd7 1680 #define FTM_STATUS_CH1F_SHIFT 1
mbed_official 68:41613245dfd7 1681 #define FTM_STATUS_CH2F_MASK 0x4u
mbed_official 68:41613245dfd7 1682 #define FTM_STATUS_CH2F_SHIFT 2
mbed_official 68:41613245dfd7 1683 #define FTM_STATUS_CH3F_MASK 0x8u
mbed_official 68:41613245dfd7 1684 #define FTM_STATUS_CH3F_SHIFT 3
mbed_official 68:41613245dfd7 1685 #define FTM_STATUS_CH4F_MASK 0x10u
mbed_official 68:41613245dfd7 1686 #define FTM_STATUS_CH4F_SHIFT 4
mbed_official 68:41613245dfd7 1687 #define FTM_STATUS_CH5F_MASK 0x20u
mbed_official 68:41613245dfd7 1688 #define FTM_STATUS_CH5F_SHIFT 5
mbed_official 68:41613245dfd7 1689 #define FTM_STATUS_CH6F_MASK 0x40u
mbed_official 68:41613245dfd7 1690 #define FTM_STATUS_CH6F_SHIFT 6
mbed_official 68:41613245dfd7 1691 #define FTM_STATUS_CH7F_MASK 0x80u
mbed_official 68:41613245dfd7 1692 #define FTM_STATUS_CH7F_SHIFT 7
mbed_official 68:41613245dfd7 1693 /* MODE Bit Fields */
mbed_official 68:41613245dfd7 1694 #define FTM_MODE_FTMEN_MASK 0x1u
mbed_official 68:41613245dfd7 1695 #define FTM_MODE_FTMEN_SHIFT 0
mbed_official 68:41613245dfd7 1696 #define FTM_MODE_INIT_MASK 0x2u
mbed_official 68:41613245dfd7 1697 #define FTM_MODE_INIT_SHIFT 1
mbed_official 68:41613245dfd7 1698 #define FTM_MODE_WPDIS_MASK 0x4u
mbed_official 68:41613245dfd7 1699 #define FTM_MODE_WPDIS_SHIFT 2
mbed_official 68:41613245dfd7 1700 #define FTM_MODE_PWMSYNC_MASK 0x8u
mbed_official 68:41613245dfd7 1701 #define FTM_MODE_PWMSYNC_SHIFT 3
mbed_official 68:41613245dfd7 1702 #define FTM_MODE_CAPTEST_MASK 0x10u
mbed_official 68:41613245dfd7 1703 #define FTM_MODE_CAPTEST_SHIFT 4
mbed_official 68:41613245dfd7 1704 #define FTM_MODE_FAULTM_MASK 0x60u
mbed_official 68:41613245dfd7 1705 #define FTM_MODE_FAULTM_SHIFT 5
mbed_official 68:41613245dfd7 1706 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
mbed_official 68:41613245dfd7 1707 #define FTM_MODE_FAULTIE_MASK 0x80u
mbed_official 68:41613245dfd7 1708 #define FTM_MODE_FAULTIE_SHIFT 7
mbed_official 68:41613245dfd7 1709 /* SYNC Bit Fields */
mbed_official 68:41613245dfd7 1710 #define FTM_SYNC_CNTMIN_MASK 0x1u
mbed_official 68:41613245dfd7 1711 #define FTM_SYNC_CNTMIN_SHIFT 0
mbed_official 68:41613245dfd7 1712 #define FTM_SYNC_CNTMAX_MASK 0x2u
mbed_official 68:41613245dfd7 1713 #define FTM_SYNC_CNTMAX_SHIFT 1
mbed_official 68:41613245dfd7 1714 #define FTM_SYNC_REINIT_MASK 0x4u
mbed_official 68:41613245dfd7 1715 #define FTM_SYNC_REINIT_SHIFT 2
mbed_official 68:41613245dfd7 1716 #define FTM_SYNC_SYNCHOM_MASK 0x8u
mbed_official 68:41613245dfd7 1717 #define FTM_SYNC_SYNCHOM_SHIFT 3
mbed_official 68:41613245dfd7 1718 #define FTM_SYNC_TRIG0_MASK 0x10u
mbed_official 68:41613245dfd7 1719 #define FTM_SYNC_TRIG0_SHIFT 4
mbed_official 68:41613245dfd7 1720 #define FTM_SYNC_TRIG1_MASK 0x20u
mbed_official 68:41613245dfd7 1721 #define FTM_SYNC_TRIG1_SHIFT 5
mbed_official 68:41613245dfd7 1722 #define FTM_SYNC_TRIG2_MASK 0x40u
mbed_official 68:41613245dfd7 1723 #define FTM_SYNC_TRIG2_SHIFT 6
mbed_official 68:41613245dfd7 1724 #define FTM_SYNC_SWSYNC_MASK 0x80u
mbed_official 68:41613245dfd7 1725 #define FTM_SYNC_SWSYNC_SHIFT 7
mbed_official 68:41613245dfd7 1726 /* OUTINIT Bit Fields */
mbed_official 68:41613245dfd7 1727 #define FTM_OUTINIT_CH0OI_MASK 0x1u
mbed_official 68:41613245dfd7 1728 #define FTM_OUTINIT_CH0OI_SHIFT 0
mbed_official 68:41613245dfd7 1729 #define FTM_OUTINIT_CH1OI_MASK 0x2u
mbed_official 68:41613245dfd7 1730 #define FTM_OUTINIT_CH1OI_SHIFT 1
mbed_official 68:41613245dfd7 1731 #define FTM_OUTINIT_CH2OI_MASK 0x4u
mbed_official 68:41613245dfd7 1732 #define FTM_OUTINIT_CH2OI_SHIFT 2
mbed_official 68:41613245dfd7 1733 #define FTM_OUTINIT_CH3OI_MASK 0x8u
mbed_official 68:41613245dfd7 1734 #define FTM_OUTINIT_CH3OI_SHIFT 3
mbed_official 68:41613245dfd7 1735 #define FTM_OUTINIT_CH4OI_MASK 0x10u
mbed_official 68:41613245dfd7 1736 #define FTM_OUTINIT_CH4OI_SHIFT 4
mbed_official 68:41613245dfd7 1737 #define FTM_OUTINIT_CH5OI_MASK 0x20u
mbed_official 68:41613245dfd7 1738 #define FTM_OUTINIT_CH5OI_SHIFT 5
mbed_official 68:41613245dfd7 1739 #define FTM_OUTINIT_CH6OI_MASK 0x40u
mbed_official 68:41613245dfd7 1740 #define FTM_OUTINIT_CH6OI_SHIFT 6
mbed_official 68:41613245dfd7 1741 #define FTM_OUTINIT_CH7OI_MASK 0x80u
mbed_official 68:41613245dfd7 1742 #define FTM_OUTINIT_CH7OI_SHIFT 7
mbed_official 68:41613245dfd7 1743 /* OUTMASK Bit Fields */
mbed_official 68:41613245dfd7 1744 #define FTM_OUTMASK_CH0OM_MASK 0x1u
mbed_official 68:41613245dfd7 1745 #define FTM_OUTMASK_CH0OM_SHIFT 0
mbed_official 68:41613245dfd7 1746 #define FTM_OUTMASK_CH1OM_MASK 0x2u
mbed_official 68:41613245dfd7 1747 #define FTM_OUTMASK_CH1OM_SHIFT 1
mbed_official 68:41613245dfd7 1748 #define FTM_OUTMASK_CH2OM_MASK 0x4u
mbed_official 68:41613245dfd7 1749 #define FTM_OUTMASK_CH2OM_SHIFT 2
mbed_official 68:41613245dfd7 1750 #define FTM_OUTMASK_CH3OM_MASK 0x8u
mbed_official 68:41613245dfd7 1751 #define FTM_OUTMASK_CH3OM_SHIFT 3
mbed_official 68:41613245dfd7 1752 #define FTM_OUTMASK_CH4OM_MASK 0x10u
mbed_official 68:41613245dfd7 1753 #define FTM_OUTMASK_CH4OM_SHIFT 4
mbed_official 68:41613245dfd7 1754 #define FTM_OUTMASK_CH5OM_MASK 0x20u
mbed_official 68:41613245dfd7 1755 #define FTM_OUTMASK_CH5OM_SHIFT 5
mbed_official 68:41613245dfd7 1756 #define FTM_OUTMASK_CH6OM_MASK 0x40u
mbed_official 68:41613245dfd7 1757 #define FTM_OUTMASK_CH6OM_SHIFT 6
mbed_official 68:41613245dfd7 1758 #define FTM_OUTMASK_CH7OM_MASK 0x80u
mbed_official 68:41613245dfd7 1759 #define FTM_OUTMASK_CH7OM_SHIFT 7
mbed_official 68:41613245dfd7 1760 /* COMBINE Bit Fields */
mbed_official 68:41613245dfd7 1761 #define FTM_COMBINE_COMBINE0_MASK 0x1u
mbed_official 68:41613245dfd7 1762 #define FTM_COMBINE_COMBINE0_SHIFT 0
mbed_official 68:41613245dfd7 1763 #define FTM_COMBINE_COMP0_MASK 0x2u
mbed_official 68:41613245dfd7 1764 #define FTM_COMBINE_COMP0_SHIFT 1
mbed_official 68:41613245dfd7 1765 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
mbed_official 68:41613245dfd7 1766 #define FTM_COMBINE_DECAPEN0_SHIFT 2
mbed_official 68:41613245dfd7 1767 #define FTM_COMBINE_DECAP0_MASK 0x8u
mbed_official 68:41613245dfd7 1768 #define FTM_COMBINE_DECAP0_SHIFT 3
mbed_official 68:41613245dfd7 1769 #define FTM_COMBINE_DTEN0_MASK 0x10u
mbed_official 68:41613245dfd7 1770 #define FTM_COMBINE_DTEN0_SHIFT 4
mbed_official 68:41613245dfd7 1771 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
mbed_official 68:41613245dfd7 1772 #define FTM_COMBINE_SYNCEN0_SHIFT 5
mbed_official 68:41613245dfd7 1773 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
mbed_official 68:41613245dfd7 1774 #define FTM_COMBINE_FAULTEN0_SHIFT 6
mbed_official 68:41613245dfd7 1775 #define FTM_COMBINE_COMBINE1_MASK 0x100u
mbed_official 68:41613245dfd7 1776 #define FTM_COMBINE_COMBINE1_SHIFT 8
mbed_official 68:41613245dfd7 1777 #define FTM_COMBINE_COMP1_MASK 0x200u
mbed_official 68:41613245dfd7 1778 #define FTM_COMBINE_COMP1_SHIFT 9
mbed_official 68:41613245dfd7 1779 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
mbed_official 68:41613245dfd7 1780 #define FTM_COMBINE_DECAPEN1_SHIFT 10
mbed_official 68:41613245dfd7 1781 #define FTM_COMBINE_DECAP1_MASK 0x800u
mbed_official 68:41613245dfd7 1782 #define FTM_COMBINE_DECAP1_SHIFT 11
mbed_official 68:41613245dfd7 1783 #define FTM_COMBINE_DTEN1_MASK 0x1000u
mbed_official 68:41613245dfd7 1784 #define FTM_COMBINE_DTEN1_SHIFT 12
mbed_official 68:41613245dfd7 1785 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
mbed_official 68:41613245dfd7 1786 #define FTM_COMBINE_SYNCEN1_SHIFT 13
mbed_official 68:41613245dfd7 1787 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
mbed_official 68:41613245dfd7 1788 #define FTM_COMBINE_FAULTEN1_SHIFT 14
mbed_official 68:41613245dfd7 1789 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
mbed_official 68:41613245dfd7 1790 #define FTM_COMBINE_COMBINE2_SHIFT 16
mbed_official 68:41613245dfd7 1791 #define FTM_COMBINE_COMP2_MASK 0x20000u
mbed_official 68:41613245dfd7 1792 #define FTM_COMBINE_COMP2_SHIFT 17
mbed_official 68:41613245dfd7 1793 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
mbed_official 68:41613245dfd7 1794 #define FTM_COMBINE_DECAPEN2_SHIFT 18
mbed_official 68:41613245dfd7 1795 #define FTM_COMBINE_DECAP2_MASK 0x80000u
mbed_official 68:41613245dfd7 1796 #define FTM_COMBINE_DECAP2_SHIFT 19
mbed_official 68:41613245dfd7 1797 #define FTM_COMBINE_DTEN2_MASK 0x100000u
mbed_official 68:41613245dfd7 1798 #define FTM_COMBINE_DTEN2_SHIFT 20
mbed_official 68:41613245dfd7 1799 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
mbed_official 68:41613245dfd7 1800 #define FTM_COMBINE_SYNCEN2_SHIFT 21
mbed_official 68:41613245dfd7 1801 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
mbed_official 68:41613245dfd7 1802 #define FTM_COMBINE_FAULTEN2_SHIFT 22
mbed_official 68:41613245dfd7 1803 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
mbed_official 68:41613245dfd7 1804 #define FTM_COMBINE_COMBINE3_SHIFT 24
mbed_official 68:41613245dfd7 1805 #define FTM_COMBINE_COMP3_MASK 0x2000000u
mbed_official 68:41613245dfd7 1806 #define FTM_COMBINE_COMP3_SHIFT 25
mbed_official 68:41613245dfd7 1807 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
mbed_official 68:41613245dfd7 1808 #define FTM_COMBINE_DECAPEN3_SHIFT 26
mbed_official 68:41613245dfd7 1809 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
mbed_official 68:41613245dfd7 1810 #define FTM_COMBINE_DECAP3_SHIFT 27
mbed_official 68:41613245dfd7 1811 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
mbed_official 68:41613245dfd7 1812 #define FTM_COMBINE_DTEN3_SHIFT 28
mbed_official 68:41613245dfd7 1813 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
mbed_official 68:41613245dfd7 1814 #define FTM_COMBINE_SYNCEN3_SHIFT 29
mbed_official 68:41613245dfd7 1815 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
mbed_official 68:41613245dfd7 1816 #define FTM_COMBINE_FAULTEN3_SHIFT 30
mbed_official 68:41613245dfd7 1817 /* DEADTIME Bit Fields */
mbed_official 68:41613245dfd7 1818 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
mbed_official 68:41613245dfd7 1819 #define FTM_DEADTIME_DTVAL_SHIFT 0
mbed_official 68:41613245dfd7 1820 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
mbed_official 68:41613245dfd7 1821 #define FTM_DEADTIME_DTPS_MASK 0xC0u
mbed_official 68:41613245dfd7 1822 #define FTM_DEADTIME_DTPS_SHIFT 6
mbed_official 68:41613245dfd7 1823 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
mbed_official 68:41613245dfd7 1824 /* EXTTRIG Bit Fields */
mbed_official 68:41613245dfd7 1825 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
mbed_official 68:41613245dfd7 1826 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
mbed_official 68:41613245dfd7 1827 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
mbed_official 68:41613245dfd7 1828 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
mbed_official 68:41613245dfd7 1829 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
mbed_official 68:41613245dfd7 1830 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
mbed_official 68:41613245dfd7 1831 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
mbed_official 68:41613245dfd7 1832 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
mbed_official 68:41613245dfd7 1833 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
mbed_official 68:41613245dfd7 1834 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
mbed_official 68:41613245dfd7 1835 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
mbed_official 68:41613245dfd7 1836 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
mbed_official 68:41613245dfd7 1837 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
mbed_official 68:41613245dfd7 1838 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
mbed_official 68:41613245dfd7 1839 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
mbed_official 68:41613245dfd7 1840 #define FTM_EXTTRIG_TRIGF_SHIFT 7
mbed_official 68:41613245dfd7 1841 /* POL Bit Fields */
mbed_official 68:41613245dfd7 1842 #define FTM_POL_POL0_MASK 0x1u
mbed_official 68:41613245dfd7 1843 #define FTM_POL_POL0_SHIFT 0
mbed_official 68:41613245dfd7 1844 #define FTM_POL_POL1_MASK 0x2u
mbed_official 68:41613245dfd7 1845 #define FTM_POL_POL1_SHIFT 1
mbed_official 68:41613245dfd7 1846 #define FTM_POL_POL2_MASK 0x4u
mbed_official 68:41613245dfd7 1847 #define FTM_POL_POL2_SHIFT 2
mbed_official 68:41613245dfd7 1848 #define FTM_POL_POL3_MASK 0x8u
mbed_official 68:41613245dfd7 1849 #define FTM_POL_POL3_SHIFT 3
mbed_official 68:41613245dfd7 1850 #define FTM_POL_POL4_MASK 0x10u
mbed_official 68:41613245dfd7 1851 #define FTM_POL_POL4_SHIFT 4
mbed_official 68:41613245dfd7 1852 #define FTM_POL_POL5_MASK 0x20u
mbed_official 68:41613245dfd7 1853 #define FTM_POL_POL5_SHIFT 5
mbed_official 68:41613245dfd7 1854 #define FTM_POL_POL6_MASK 0x40u
mbed_official 68:41613245dfd7 1855 #define FTM_POL_POL6_SHIFT 6
mbed_official 68:41613245dfd7 1856 #define FTM_POL_POL7_MASK 0x80u
mbed_official 68:41613245dfd7 1857 #define FTM_POL_POL7_SHIFT 7
mbed_official 68:41613245dfd7 1858 /* FMS Bit Fields */
mbed_official 68:41613245dfd7 1859 #define FTM_FMS_FAULTF0_MASK 0x1u
mbed_official 68:41613245dfd7 1860 #define FTM_FMS_FAULTF0_SHIFT 0
mbed_official 68:41613245dfd7 1861 #define FTM_FMS_FAULTF1_MASK 0x2u
mbed_official 68:41613245dfd7 1862 #define FTM_FMS_FAULTF1_SHIFT 1
mbed_official 68:41613245dfd7 1863 #define FTM_FMS_FAULTF2_MASK 0x4u
mbed_official 68:41613245dfd7 1864 #define FTM_FMS_FAULTF2_SHIFT 2
mbed_official 68:41613245dfd7 1865 #define FTM_FMS_FAULTF3_MASK 0x8u
mbed_official 68:41613245dfd7 1866 #define FTM_FMS_FAULTF3_SHIFT 3
mbed_official 68:41613245dfd7 1867 #define FTM_FMS_FAULTIN_MASK 0x20u
mbed_official 68:41613245dfd7 1868 #define FTM_FMS_FAULTIN_SHIFT 5
mbed_official 68:41613245dfd7 1869 #define FTM_FMS_WPEN_MASK 0x40u
mbed_official 68:41613245dfd7 1870 #define FTM_FMS_WPEN_SHIFT 6
mbed_official 68:41613245dfd7 1871 #define FTM_FMS_FAULTF_MASK 0x80u
mbed_official 68:41613245dfd7 1872 #define FTM_FMS_FAULTF_SHIFT 7
mbed_official 68:41613245dfd7 1873 /* FILTER Bit Fields */
mbed_official 68:41613245dfd7 1874 #define FTM_FILTER_CH0FVAL_MASK 0xFu
mbed_official 68:41613245dfd7 1875 #define FTM_FILTER_CH0FVAL_SHIFT 0
mbed_official 68:41613245dfd7 1876 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
mbed_official 68:41613245dfd7 1877 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
mbed_official 68:41613245dfd7 1878 #define FTM_FILTER_CH1FVAL_SHIFT 4
mbed_official 68:41613245dfd7 1879 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
mbed_official 68:41613245dfd7 1880 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
mbed_official 68:41613245dfd7 1881 #define FTM_FILTER_CH2FVAL_SHIFT 8
mbed_official 68:41613245dfd7 1882 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
mbed_official 68:41613245dfd7 1883 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
mbed_official 68:41613245dfd7 1884 #define FTM_FILTER_CH3FVAL_SHIFT 12
mbed_official 68:41613245dfd7 1885 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
mbed_official 68:41613245dfd7 1886 /* FLTCTRL Bit Fields */
mbed_official 68:41613245dfd7 1887 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
mbed_official 68:41613245dfd7 1888 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
mbed_official 68:41613245dfd7 1889 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
mbed_official 68:41613245dfd7 1890 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
mbed_official 68:41613245dfd7 1891 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
mbed_official 68:41613245dfd7 1892 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
mbed_official 68:41613245dfd7 1893 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
mbed_official 68:41613245dfd7 1894 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
mbed_official 68:41613245dfd7 1895 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
mbed_official 68:41613245dfd7 1896 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
mbed_official 68:41613245dfd7 1897 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
mbed_official 68:41613245dfd7 1898 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
mbed_official 68:41613245dfd7 1899 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
mbed_official 68:41613245dfd7 1900 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
mbed_official 68:41613245dfd7 1901 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
mbed_official 68:41613245dfd7 1902 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
mbed_official 68:41613245dfd7 1903 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
mbed_official 68:41613245dfd7 1904 #define FTM_FLTCTRL_FFVAL_SHIFT 8
mbed_official 68:41613245dfd7 1905 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
mbed_official 68:41613245dfd7 1906 /* QDCTRL Bit Fields */
mbed_official 68:41613245dfd7 1907 #define FTM_QDCTRL_QUADEN_MASK 0x1u
mbed_official 68:41613245dfd7 1908 #define FTM_QDCTRL_QUADEN_SHIFT 0
mbed_official 68:41613245dfd7 1909 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
mbed_official 68:41613245dfd7 1910 #define FTM_QDCTRL_TOFDIR_SHIFT 1
mbed_official 68:41613245dfd7 1911 #define FTM_QDCTRL_QUADIR_MASK 0x4u
mbed_official 68:41613245dfd7 1912 #define FTM_QDCTRL_QUADIR_SHIFT 2
mbed_official 68:41613245dfd7 1913 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
mbed_official 68:41613245dfd7 1914 #define FTM_QDCTRL_QUADMODE_SHIFT 3
mbed_official 68:41613245dfd7 1915 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
mbed_official 68:41613245dfd7 1916 #define FTM_QDCTRL_PHBPOL_SHIFT 4
mbed_official 68:41613245dfd7 1917 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
mbed_official 68:41613245dfd7 1918 #define FTM_QDCTRL_PHAPOL_SHIFT 5
mbed_official 68:41613245dfd7 1919 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
mbed_official 68:41613245dfd7 1920 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
mbed_official 68:41613245dfd7 1921 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
mbed_official 68:41613245dfd7 1922 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
mbed_official 68:41613245dfd7 1923 /* CONF Bit Fields */
mbed_official 68:41613245dfd7 1924 #define FTM_CONF_NUMTOF_MASK 0x1Fu
mbed_official 68:41613245dfd7 1925 #define FTM_CONF_NUMTOF_SHIFT 0
mbed_official 68:41613245dfd7 1926 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
mbed_official 68:41613245dfd7 1927 #define FTM_CONF_BDMMODE_MASK 0xC0u
mbed_official 68:41613245dfd7 1928 #define FTM_CONF_BDMMODE_SHIFT 6
mbed_official 68:41613245dfd7 1929 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
mbed_official 68:41613245dfd7 1930 #define FTM_CONF_GTBEEN_MASK 0x200u
mbed_official 68:41613245dfd7 1931 #define FTM_CONF_GTBEEN_SHIFT 9
mbed_official 68:41613245dfd7 1932 #define FTM_CONF_GTBEOUT_MASK 0x400u
mbed_official 68:41613245dfd7 1933 #define FTM_CONF_GTBEOUT_SHIFT 10
mbed_official 68:41613245dfd7 1934 /* FLTPOL Bit Fields */
mbed_official 68:41613245dfd7 1935 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
mbed_official 68:41613245dfd7 1936 #define FTM_FLTPOL_FLT0POL_SHIFT 0
mbed_official 68:41613245dfd7 1937 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
mbed_official 68:41613245dfd7 1938 #define FTM_FLTPOL_FLT1POL_SHIFT 1
mbed_official 68:41613245dfd7 1939 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
mbed_official 68:41613245dfd7 1940 #define FTM_FLTPOL_FLT2POL_SHIFT 2
mbed_official 68:41613245dfd7 1941 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
mbed_official 68:41613245dfd7 1942 #define FTM_FLTPOL_FLT3POL_SHIFT 3
mbed_official 68:41613245dfd7 1943 /* SYNCONF Bit Fields */
mbed_official 68:41613245dfd7 1944 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
mbed_official 68:41613245dfd7 1945 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
mbed_official 68:41613245dfd7 1946 #define FTM_SYNCONF_CNTINC_MASK 0x4u
mbed_official 68:41613245dfd7 1947 #define FTM_SYNCONF_CNTINC_SHIFT 2
mbed_official 68:41613245dfd7 1948 #define FTM_SYNCONF_INVC_MASK 0x10u
mbed_official 68:41613245dfd7 1949 #define FTM_SYNCONF_INVC_SHIFT 4
mbed_official 68:41613245dfd7 1950 #define FTM_SYNCONF_SWOC_MASK 0x20u
mbed_official 68:41613245dfd7 1951 #define FTM_SYNCONF_SWOC_SHIFT 5
mbed_official 68:41613245dfd7 1952 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
mbed_official 68:41613245dfd7 1953 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
mbed_official 68:41613245dfd7 1954 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
mbed_official 68:41613245dfd7 1955 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
mbed_official 68:41613245dfd7 1956 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
mbed_official 68:41613245dfd7 1957 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
mbed_official 68:41613245dfd7 1958 #define FTM_SYNCONF_SWOM_MASK 0x400u
mbed_official 68:41613245dfd7 1959 #define FTM_SYNCONF_SWOM_SHIFT 10
mbed_official 68:41613245dfd7 1960 #define FTM_SYNCONF_SWINVC_MASK 0x800u
mbed_official 68:41613245dfd7 1961 #define FTM_SYNCONF_SWINVC_SHIFT 11
mbed_official 68:41613245dfd7 1962 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
mbed_official 68:41613245dfd7 1963 #define FTM_SYNCONF_SWSOC_SHIFT 12
mbed_official 68:41613245dfd7 1964 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
mbed_official 68:41613245dfd7 1965 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
mbed_official 68:41613245dfd7 1966 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
mbed_official 68:41613245dfd7 1967 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
mbed_official 68:41613245dfd7 1968 #define FTM_SYNCONF_HWOM_MASK 0x40000u
mbed_official 68:41613245dfd7 1969 #define FTM_SYNCONF_HWOM_SHIFT 18
mbed_official 68:41613245dfd7 1970 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
mbed_official 68:41613245dfd7 1971 #define FTM_SYNCONF_HWINVC_SHIFT 19
mbed_official 68:41613245dfd7 1972 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
mbed_official 68:41613245dfd7 1973 #define FTM_SYNCONF_HWSOC_SHIFT 20
mbed_official 68:41613245dfd7 1974 /* INVCTRL Bit Fields */
mbed_official 68:41613245dfd7 1975 #define FTM_INVCTRL_INV0EN_MASK 0x1u
mbed_official 68:41613245dfd7 1976 #define FTM_INVCTRL_INV0EN_SHIFT 0
mbed_official 68:41613245dfd7 1977 #define FTM_INVCTRL_INV1EN_MASK 0x2u
mbed_official 68:41613245dfd7 1978 #define FTM_INVCTRL_INV1EN_SHIFT 1
mbed_official 68:41613245dfd7 1979 #define FTM_INVCTRL_INV2EN_MASK 0x4u
mbed_official 68:41613245dfd7 1980 #define FTM_INVCTRL_INV2EN_SHIFT 2
mbed_official 68:41613245dfd7 1981 #define FTM_INVCTRL_INV3EN_MASK 0x8u
mbed_official 68:41613245dfd7 1982 #define FTM_INVCTRL_INV3EN_SHIFT 3
mbed_official 68:41613245dfd7 1983 /* SWOCTRL Bit Fields */
mbed_official 68:41613245dfd7 1984 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
mbed_official 68:41613245dfd7 1985 #define FTM_SWOCTRL_CH0OC_SHIFT 0
mbed_official 68:41613245dfd7 1986 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
mbed_official 68:41613245dfd7 1987 #define FTM_SWOCTRL_CH1OC_SHIFT 1
mbed_official 68:41613245dfd7 1988 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
mbed_official 68:41613245dfd7 1989 #define FTM_SWOCTRL_CH2OC_SHIFT 2
mbed_official 68:41613245dfd7 1990 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
mbed_official 68:41613245dfd7 1991 #define FTM_SWOCTRL_CH3OC_SHIFT 3
mbed_official 68:41613245dfd7 1992 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
mbed_official 68:41613245dfd7 1993 #define FTM_SWOCTRL_CH4OC_SHIFT 4
mbed_official 68:41613245dfd7 1994 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
mbed_official 68:41613245dfd7 1995 #define FTM_SWOCTRL_CH5OC_SHIFT 5
mbed_official 68:41613245dfd7 1996 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
mbed_official 68:41613245dfd7 1997 #define FTM_SWOCTRL_CH6OC_SHIFT 6
mbed_official 68:41613245dfd7 1998 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
mbed_official 68:41613245dfd7 1999 #define FTM_SWOCTRL_CH7OC_SHIFT 7
mbed_official 68:41613245dfd7 2000 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
mbed_official 68:41613245dfd7 2001 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
mbed_official 68:41613245dfd7 2002 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
mbed_official 68:41613245dfd7 2003 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
mbed_official 68:41613245dfd7 2004 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
mbed_official 68:41613245dfd7 2005 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
mbed_official 68:41613245dfd7 2006 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
mbed_official 68:41613245dfd7 2007 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
mbed_official 68:41613245dfd7 2008 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
mbed_official 68:41613245dfd7 2009 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
mbed_official 68:41613245dfd7 2010 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
mbed_official 68:41613245dfd7 2011 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
mbed_official 68:41613245dfd7 2012 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
mbed_official 68:41613245dfd7 2013 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
mbed_official 68:41613245dfd7 2014 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
mbed_official 68:41613245dfd7 2015 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
mbed_official 68:41613245dfd7 2016 /* PWMLOAD Bit Fields */
mbed_official 68:41613245dfd7 2017 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
mbed_official 68:41613245dfd7 2018 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
mbed_official 68:41613245dfd7 2019 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
mbed_official 68:41613245dfd7 2020 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
mbed_official 68:41613245dfd7 2021 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
mbed_official 68:41613245dfd7 2022 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
mbed_official 68:41613245dfd7 2023 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
mbed_official 68:41613245dfd7 2024 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
mbed_official 68:41613245dfd7 2025 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
mbed_official 68:41613245dfd7 2026 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
mbed_official 68:41613245dfd7 2027 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
mbed_official 68:41613245dfd7 2028 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
mbed_official 68:41613245dfd7 2029 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
mbed_official 68:41613245dfd7 2030 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
mbed_official 68:41613245dfd7 2031 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
mbed_official 68:41613245dfd7 2032 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
mbed_official 68:41613245dfd7 2033 #define FTM_PWMLOAD_LDOK_MASK 0x200u
mbed_official 68:41613245dfd7 2034 #define FTM_PWMLOAD_LDOK_SHIFT 9
mbed_official 68:41613245dfd7 2035
mbed_official 68:41613245dfd7 2036 /**
mbed_official 68:41613245dfd7 2037 * @}
mbed_official 68:41613245dfd7 2038 */ /* end of group FTM_Register_Masks */
mbed_official 68:41613245dfd7 2039
mbed_official 68:41613245dfd7 2040
mbed_official 68:41613245dfd7 2041 /* FTM - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 2042 /** Peripheral FTM0 base address */
mbed_official 68:41613245dfd7 2043 #define FTM0_BASE (0x40038000u)
mbed_official 68:41613245dfd7 2044 /** Peripheral FTM0 base pointer */
mbed_official 68:41613245dfd7 2045 #define FTM0 ((FTM_Type *)FTM0_BASE)
mbed_official 68:41613245dfd7 2046 /** Peripheral FTM1 base address */
mbed_official 68:41613245dfd7 2047 #define FTM1_BASE (0x40039000u)
mbed_official 68:41613245dfd7 2048 /** Peripheral FTM1 base pointer */
mbed_official 68:41613245dfd7 2049 #define FTM1 ((FTM_Type *)FTM1_BASE)
mbed_official 68:41613245dfd7 2050
mbed_official 68:41613245dfd7 2051 /**
mbed_official 68:41613245dfd7 2052 * @}
mbed_official 68:41613245dfd7 2053 */ /* end of group FTM_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 2054
mbed_official 68:41613245dfd7 2055
mbed_official 68:41613245dfd7 2056 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2057 -- GPIO Peripheral Access Layer
mbed_official 68:41613245dfd7 2058 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2059
mbed_official 68:41613245dfd7 2060 /**
mbed_official 68:41613245dfd7 2061 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 68:41613245dfd7 2062 * @{
mbed_official 68:41613245dfd7 2063 */
mbed_official 68:41613245dfd7 2064
mbed_official 68:41613245dfd7 2065 /** GPIO - Register Layout Typedef */
mbed_official 68:41613245dfd7 2066 typedef struct {
mbed_official 68:41613245dfd7 2067 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 68:41613245dfd7 2068 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 68:41613245dfd7 2069 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 68:41613245dfd7 2070 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 68:41613245dfd7 2071 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 68:41613245dfd7 2072 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 68:41613245dfd7 2073 } GPIO_Type;
mbed_official 68:41613245dfd7 2074
mbed_official 68:41613245dfd7 2075 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2076 -- GPIO Register Masks
mbed_official 68:41613245dfd7 2077 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2078
mbed_official 68:41613245dfd7 2079 /**
mbed_official 68:41613245dfd7 2080 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 68:41613245dfd7 2081 * @{
mbed_official 68:41613245dfd7 2082 */
mbed_official 68:41613245dfd7 2083
mbed_official 68:41613245dfd7 2084 /* PDOR Bit Fields */
mbed_official 68:41613245dfd7 2085 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2086 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 68:41613245dfd7 2087 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 68:41613245dfd7 2088 /* PSOR Bit Fields */
mbed_official 68:41613245dfd7 2089 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2090 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 68:41613245dfd7 2091 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 68:41613245dfd7 2092 /* PCOR Bit Fields */
mbed_official 68:41613245dfd7 2093 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2094 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 68:41613245dfd7 2095 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 68:41613245dfd7 2096 /* PTOR Bit Fields */
mbed_official 68:41613245dfd7 2097 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2098 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 68:41613245dfd7 2099 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 68:41613245dfd7 2100 /* PDIR Bit Fields */
mbed_official 68:41613245dfd7 2101 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2102 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 68:41613245dfd7 2103 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 68:41613245dfd7 2104 /* PDDR Bit Fields */
mbed_official 68:41613245dfd7 2105 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2106 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 68:41613245dfd7 2107 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 68:41613245dfd7 2108
mbed_official 68:41613245dfd7 2109 /**
mbed_official 68:41613245dfd7 2110 * @}
mbed_official 68:41613245dfd7 2111 */ /* end of group GPIO_Register_Masks */
mbed_official 68:41613245dfd7 2112
mbed_official 68:41613245dfd7 2113
mbed_official 68:41613245dfd7 2114 /* GPIO - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 2115 /** Peripheral PTA base address */
mbed_official 68:41613245dfd7 2116 #define PTA_BASE (0x400FF000u)
mbed_official 68:41613245dfd7 2117 /** Peripheral PTA base pointer */
mbed_official 68:41613245dfd7 2118 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 68:41613245dfd7 2119 /** Peripheral PTB base address */
mbed_official 68:41613245dfd7 2120 #define PTB_BASE (0x400FF040u)
mbed_official 68:41613245dfd7 2121 /** Peripheral PTB base pointer */
mbed_official 68:41613245dfd7 2122 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 68:41613245dfd7 2123 /** Peripheral PTC base address */
mbed_official 68:41613245dfd7 2124 #define PTC_BASE (0x400FF080u)
mbed_official 68:41613245dfd7 2125 /** Peripheral PTC base pointer */
mbed_official 68:41613245dfd7 2126 #define PTC ((GPIO_Type *)PTC_BASE)
mbed_official 68:41613245dfd7 2127 /** Peripheral PTD base address */
mbed_official 68:41613245dfd7 2128 #define PTD_BASE (0x400FF0C0u)
mbed_official 68:41613245dfd7 2129 /** Peripheral PTD base pointer */
mbed_official 68:41613245dfd7 2130 #define PTD ((GPIO_Type *)PTD_BASE)
mbed_official 68:41613245dfd7 2131 /** Peripheral PTE base address */
mbed_official 68:41613245dfd7 2132 #define PTE_BASE (0x400FF100u)
mbed_official 68:41613245dfd7 2133 /** Peripheral PTE base pointer */
mbed_official 68:41613245dfd7 2134 #define PTE ((GPIO_Type *)PTE_BASE)
mbed_official 68:41613245dfd7 2135
mbed_official 68:41613245dfd7 2136 /**
mbed_official 68:41613245dfd7 2137 * @}
mbed_official 68:41613245dfd7 2138 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 2139
mbed_official 68:41613245dfd7 2140
mbed_official 68:41613245dfd7 2141 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2142 -- I2C Peripheral Access Layer
mbed_official 68:41613245dfd7 2143 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2144
mbed_official 68:41613245dfd7 2145 /**
mbed_official 68:41613245dfd7 2146 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 68:41613245dfd7 2147 * @{
mbed_official 68:41613245dfd7 2148 */
mbed_official 68:41613245dfd7 2149
mbed_official 68:41613245dfd7 2150 /** I2C - Register Layout Typedef */
mbed_official 68:41613245dfd7 2151 typedef struct {
mbed_official 68:41613245dfd7 2152 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 68:41613245dfd7 2153 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 68:41613245dfd7 2154 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 68:41613245dfd7 2155 __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
mbed_official 68:41613245dfd7 2156 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 68:41613245dfd7 2157 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 68:41613245dfd7 2158 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 68:41613245dfd7 2159 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 68:41613245dfd7 2160 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 68:41613245dfd7 2161 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 68:41613245dfd7 2162 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 68:41613245dfd7 2163 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 68:41613245dfd7 2164 } I2C_Type;
mbed_official 68:41613245dfd7 2165
mbed_official 68:41613245dfd7 2166 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2167 -- I2C Register Masks
mbed_official 68:41613245dfd7 2168 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2169
mbed_official 68:41613245dfd7 2170 /**
mbed_official 68:41613245dfd7 2171 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 68:41613245dfd7 2172 * @{
mbed_official 68:41613245dfd7 2173 */
mbed_official 68:41613245dfd7 2174
mbed_official 68:41613245dfd7 2175 /* A1 Bit Fields */
mbed_official 68:41613245dfd7 2176 #define I2C_A1_AD_MASK 0xFEu
mbed_official 68:41613245dfd7 2177 #define I2C_A1_AD_SHIFT 1
mbed_official 68:41613245dfd7 2178 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 68:41613245dfd7 2179 /* F Bit Fields */
mbed_official 68:41613245dfd7 2180 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 68:41613245dfd7 2181 #define I2C_F_ICR_SHIFT 0
mbed_official 68:41613245dfd7 2182 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 68:41613245dfd7 2183 #define I2C_F_MULT_MASK 0xC0u
mbed_official 68:41613245dfd7 2184 #define I2C_F_MULT_SHIFT 6
mbed_official 68:41613245dfd7 2185 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 68:41613245dfd7 2186 /* C1 Bit Fields */
mbed_official 68:41613245dfd7 2187 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 68:41613245dfd7 2188 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 68:41613245dfd7 2189 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 68:41613245dfd7 2190 #define I2C_C1_WUEN_SHIFT 1
mbed_official 68:41613245dfd7 2191 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 68:41613245dfd7 2192 #define I2C_C1_RSTA_SHIFT 2
mbed_official 68:41613245dfd7 2193 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 68:41613245dfd7 2194 #define I2C_C1_TXAK_SHIFT 3
mbed_official 68:41613245dfd7 2195 #define I2C_C1_TX_MASK 0x10u
mbed_official 68:41613245dfd7 2196 #define I2C_C1_TX_SHIFT 4
mbed_official 68:41613245dfd7 2197 #define I2C_C1_MST_MASK 0x20u
mbed_official 68:41613245dfd7 2198 #define I2C_C1_MST_SHIFT 5
mbed_official 68:41613245dfd7 2199 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 68:41613245dfd7 2200 #define I2C_C1_IICIE_SHIFT 6
mbed_official 68:41613245dfd7 2201 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 68:41613245dfd7 2202 #define I2C_C1_IICEN_SHIFT 7
mbed_official 68:41613245dfd7 2203 /* S Bit Fields */
mbed_official 68:41613245dfd7 2204 #define I2C_S_RXAK_MASK 0x1u
mbed_official 68:41613245dfd7 2205 #define I2C_S_RXAK_SHIFT 0
mbed_official 68:41613245dfd7 2206 #define I2C_S_IICIF_MASK 0x2u
mbed_official 68:41613245dfd7 2207 #define I2C_S_IICIF_SHIFT 1
mbed_official 68:41613245dfd7 2208 #define I2C_S_SRW_MASK 0x4u
mbed_official 68:41613245dfd7 2209 #define I2C_S_SRW_SHIFT 2
mbed_official 68:41613245dfd7 2210 #define I2C_S_RAM_MASK 0x8u
mbed_official 68:41613245dfd7 2211 #define I2C_S_RAM_SHIFT 3
mbed_official 68:41613245dfd7 2212 #define I2C_S_ARBL_MASK 0x10u
mbed_official 68:41613245dfd7 2213 #define I2C_S_ARBL_SHIFT 4
mbed_official 68:41613245dfd7 2214 #define I2C_S_BUSY_MASK 0x20u
mbed_official 68:41613245dfd7 2215 #define I2C_S_BUSY_SHIFT 5
mbed_official 68:41613245dfd7 2216 #define I2C_S_IAAS_MASK 0x40u
mbed_official 68:41613245dfd7 2217 #define I2C_S_IAAS_SHIFT 6
mbed_official 68:41613245dfd7 2218 #define I2C_S_TCF_MASK 0x80u
mbed_official 68:41613245dfd7 2219 #define I2C_S_TCF_SHIFT 7
mbed_official 68:41613245dfd7 2220 /* D Bit Fields */
mbed_official 68:41613245dfd7 2221 #define I2C_D_DATA_MASK 0xFFu
mbed_official 68:41613245dfd7 2222 #define I2C_D_DATA_SHIFT 0
mbed_official 68:41613245dfd7 2223 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 68:41613245dfd7 2224 /* C2 Bit Fields */
mbed_official 68:41613245dfd7 2225 #define I2C_C2_AD_MASK 0x7u
mbed_official 68:41613245dfd7 2226 #define I2C_C2_AD_SHIFT 0
mbed_official 68:41613245dfd7 2227 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 68:41613245dfd7 2228 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 68:41613245dfd7 2229 #define I2C_C2_RMEN_SHIFT 3
mbed_official 68:41613245dfd7 2230 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 68:41613245dfd7 2231 #define I2C_C2_SBRC_SHIFT 4
mbed_official 68:41613245dfd7 2232 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 68:41613245dfd7 2233 #define I2C_C2_HDRS_SHIFT 5
mbed_official 68:41613245dfd7 2234 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 68:41613245dfd7 2235 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 68:41613245dfd7 2236 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 68:41613245dfd7 2237 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 68:41613245dfd7 2238 /* FLT Bit Fields */
mbed_official 68:41613245dfd7 2239 #define I2C_FLT_FLT_MASK 0x1Fu
mbed_official 68:41613245dfd7 2240 #define I2C_FLT_FLT_SHIFT 0
mbed_official 68:41613245dfd7 2241 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 68:41613245dfd7 2242 /* RA Bit Fields */
mbed_official 68:41613245dfd7 2243 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 68:41613245dfd7 2244 #define I2C_RA_RAD_SHIFT 1
mbed_official 68:41613245dfd7 2245 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 68:41613245dfd7 2246 /* SMB Bit Fields */
mbed_official 68:41613245dfd7 2247 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 68:41613245dfd7 2248 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 68:41613245dfd7 2249 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 68:41613245dfd7 2250 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 68:41613245dfd7 2251 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 68:41613245dfd7 2252 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 68:41613245dfd7 2253 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 68:41613245dfd7 2254 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 68:41613245dfd7 2255 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 68:41613245dfd7 2256 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 68:41613245dfd7 2257 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 68:41613245dfd7 2258 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 68:41613245dfd7 2259 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 68:41613245dfd7 2260 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 68:41613245dfd7 2261 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 68:41613245dfd7 2262 #define I2C_SMB_FACK_SHIFT 7
mbed_official 68:41613245dfd7 2263 /* A2 Bit Fields */
mbed_official 68:41613245dfd7 2264 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 68:41613245dfd7 2265 #define I2C_A2_SAD_SHIFT 1
mbed_official 68:41613245dfd7 2266 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 68:41613245dfd7 2267 /* SLTH Bit Fields */
mbed_official 68:41613245dfd7 2268 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 68:41613245dfd7 2269 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 68:41613245dfd7 2270 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 68:41613245dfd7 2271 /* SLTL Bit Fields */
mbed_official 68:41613245dfd7 2272 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 68:41613245dfd7 2273 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 68:41613245dfd7 2274 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 68:41613245dfd7 2275
mbed_official 68:41613245dfd7 2276 /**
mbed_official 68:41613245dfd7 2277 * @}
mbed_official 68:41613245dfd7 2278 */ /* end of group I2C_Register_Masks */
mbed_official 68:41613245dfd7 2279
mbed_official 68:41613245dfd7 2280
mbed_official 68:41613245dfd7 2281 /* I2C - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 2282 /** Peripheral I2C0 base address */
mbed_official 68:41613245dfd7 2283 #define I2C0_BASE (0x40066000u)
mbed_official 68:41613245dfd7 2284 /** Peripheral I2C0 base pointer */
mbed_official 68:41613245dfd7 2285 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 68:41613245dfd7 2286
mbed_official 68:41613245dfd7 2287 /**
mbed_official 68:41613245dfd7 2288 * @}
mbed_official 68:41613245dfd7 2289 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 2290
mbed_official 68:41613245dfd7 2291
mbed_official 68:41613245dfd7 2292 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2293 -- I2S Peripheral Access Layer
mbed_official 68:41613245dfd7 2294 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2295
mbed_official 68:41613245dfd7 2296 /**
mbed_official 68:41613245dfd7 2297 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 68:41613245dfd7 2298 * @{
mbed_official 68:41613245dfd7 2299 */
mbed_official 68:41613245dfd7 2300
mbed_official 68:41613245dfd7 2301 /** I2S - Register Layout Typedef */
mbed_official 68:41613245dfd7 2302 typedef struct {
mbed_official 68:41613245dfd7 2303 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 2304 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
mbed_official 68:41613245dfd7 2305 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 68:41613245dfd7 2306 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 68:41613245dfd7 2307 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 68:41613245dfd7 2308 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 68:41613245dfd7 2309 uint8_t RESERVED_0[8];
mbed_official 68:41613245dfd7 2310 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 68:41613245dfd7 2311 uint8_t RESERVED_1[24];
mbed_official 68:41613245dfd7 2312 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
mbed_official 68:41613245dfd7 2313 uint8_t RESERVED_2[24];
mbed_official 68:41613245dfd7 2314 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 68:41613245dfd7 2315 uint8_t RESERVED_3[28];
mbed_official 68:41613245dfd7 2316 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 68:41613245dfd7 2317 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
mbed_official 68:41613245dfd7 2318 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 68:41613245dfd7 2319 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 68:41613245dfd7 2320 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 68:41613245dfd7 2321 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 68:41613245dfd7 2322 uint8_t RESERVED_4[8];
mbed_official 68:41613245dfd7 2323 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 68:41613245dfd7 2324 uint8_t RESERVED_5[24];
mbed_official 68:41613245dfd7 2325 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
mbed_official 68:41613245dfd7 2326 uint8_t RESERVED_6[24];
mbed_official 68:41613245dfd7 2327 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 68:41613245dfd7 2328 uint8_t RESERVED_7[28];
mbed_official 68:41613245dfd7 2329 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 68:41613245dfd7 2330 __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
mbed_official 68:41613245dfd7 2331 } I2S_Type;
mbed_official 68:41613245dfd7 2332
mbed_official 68:41613245dfd7 2333 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2334 -- I2S Register Masks
mbed_official 68:41613245dfd7 2335 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2336
mbed_official 68:41613245dfd7 2337 /**
mbed_official 68:41613245dfd7 2338 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 68:41613245dfd7 2339 * @{
mbed_official 68:41613245dfd7 2340 */
mbed_official 68:41613245dfd7 2341
mbed_official 68:41613245dfd7 2342 /* TCSR Bit Fields */
mbed_official 68:41613245dfd7 2343 #define I2S_TCSR_FRDE_MASK 0x1u
mbed_official 68:41613245dfd7 2344 #define I2S_TCSR_FRDE_SHIFT 0
mbed_official 68:41613245dfd7 2345 #define I2S_TCSR_FWDE_MASK 0x2u
mbed_official 68:41613245dfd7 2346 #define I2S_TCSR_FWDE_SHIFT 1
mbed_official 68:41613245dfd7 2347 #define I2S_TCSR_FRIE_MASK 0x100u
mbed_official 68:41613245dfd7 2348 #define I2S_TCSR_FRIE_SHIFT 8
mbed_official 68:41613245dfd7 2349 #define I2S_TCSR_FWIE_MASK 0x200u
mbed_official 68:41613245dfd7 2350 #define I2S_TCSR_FWIE_SHIFT 9
mbed_official 68:41613245dfd7 2351 #define I2S_TCSR_FEIE_MASK 0x400u
mbed_official 68:41613245dfd7 2352 #define I2S_TCSR_FEIE_SHIFT 10
mbed_official 68:41613245dfd7 2353 #define I2S_TCSR_SEIE_MASK 0x800u
mbed_official 68:41613245dfd7 2354 #define I2S_TCSR_SEIE_SHIFT 11
mbed_official 68:41613245dfd7 2355 #define I2S_TCSR_WSIE_MASK 0x1000u
mbed_official 68:41613245dfd7 2356 #define I2S_TCSR_WSIE_SHIFT 12
mbed_official 68:41613245dfd7 2357 #define I2S_TCSR_FRF_MASK 0x10000u
mbed_official 68:41613245dfd7 2358 #define I2S_TCSR_FRF_SHIFT 16
mbed_official 68:41613245dfd7 2359 #define I2S_TCSR_FWF_MASK 0x20000u
mbed_official 68:41613245dfd7 2360 #define I2S_TCSR_FWF_SHIFT 17
mbed_official 68:41613245dfd7 2361 #define I2S_TCSR_FEF_MASK 0x40000u
mbed_official 68:41613245dfd7 2362 #define I2S_TCSR_FEF_SHIFT 18
mbed_official 68:41613245dfd7 2363 #define I2S_TCSR_SEF_MASK 0x80000u
mbed_official 68:41613245dfd7 2364 #define I2S_TCSR_SEF_SHIFT 19
mbed_official 68:41613245dfd7 2365 #define I2S_TCSR_WSF_MASK 0x100000u
mbed_official 68:41613245dfd7 2366 #define I2S_TCSR_WSF_SHIFT 20
mbed_official 68:41613245dfd7 2367 #define I2S_TCSR_SR_MASK 0x1000000u
mbed_official 68:41613245dfd7 2368 #define I2S_TCSR_SR_SHIFT 24
mbed_official 68:41613245dfd7 2369 #define I2S_TCSR_FR_MASK 0x2000000u
mbed_official 68:41613245dfd7 2370 #define I2S_TCSR_FR_SHIFT 25
mbed_official 68:41613245dfd7 2371 #define I2S_TCSR_BCE_MASK 0x10000000u
mbed_official 68:41613245dfd7 2372 #define I2S_TCSR_BCE_SHIFT 28
mbed_official 68:41613245dfd7 2373 #define I2S_TCSR_DBGE_MASK 0x20000000u
mbed_official 68:41613245dfd7 2374 #define I2S_TCSR_DBGE_SHIFT 29
mbed_official 68:41613245dfd7 2375 #define I2S_TCSR_STOPE_MASK 0x40000000u
mbed_official 68:41613245dfd7 2376 #define I2S_TCSR_STOPE_SHIFT 30
mbed_official 68:41613245dfd7 2377 #define I2S_TCSR_TE_MASK 0x80000000u
mbed_official 68:41613245dfd7 2378 #define I2S_TCSR_TE_SHIFT 31
mbed_official 68:41613245dfd7 2379 /* TCR1 Bit Fields */
mbed_official 68:41613245dfd7 2380 #define I2S_TCR1_TFW_MASK 0x7u
mbed_official 68:41613245dfd7 2381 #define I2S_TCR1_TFW_SHIFT 0
mbed_official 68:41613245dfd7 2382 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
mbed_official 68:41613245dfd7 2383 /* TCR2 Bit Fields */
mbed_official 68:41613245dfd7 2384 #define I2S_TCR2_DIV_MASK 0xFFu
mbed_official 68:41613245dfd7 2385 #define I2S_TCR2_DIV_SHIFT 0
mbed_official 68:41613245dfd7 2386 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mbed_official 68:41613245dfd7 2387 #define I2S_TCR2_BCD_MASK 0x1000000u
mbed_official 68:41613245dfd7 2388 #define I2S_TCR2_BCD_SHIFT 24
mbed_official 68:41613245dfd7 2389 #define I2S_TCR2_BCP_MASK 0x2000000u
mbed_official 68:41613245dfd7 2390 #define I2S_TCR2_BCP_SHIFT 25
mbed_official 68:41613245dfd7 2391 #define I2S_TCR2_MSEL_MASK 0xC000000u
mbed_official 68:41613245dfd7 2392 #define I2S_TCR2_MSEL_SHIFT 26
mbed_official 68:41613245dfd7 2393 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
mbed_official 68:41613245dfd7 2394 #define I2S_TCR2_BCI_MASK 0x10000000u
mbed_official 68:41613245dfd7 2395 #define I2S_TCR2_BCI_SHIFT 28
mbed_official 68:41613245dfd7 2396 #define I2S_TCR2_BCS_MASK 0x20000000u
mbed_official 68:41613245dfd7 2397 #define I2S_TCR2_BCS_SHIFT 29
mbed_official 68:41613245dfd7 2398 #define I2S_TCR2_SYNC_MASK 0xC0000000u
mbed_official 68:41613245dfd7 2399 #define I2S_TCR2_SYNC_SHIFT 30
mbed_official 68:41613245dfd7 2400 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
mbed_official 68:41613245dfd7 2401 /* TCR3 Bit Fields */
mbed_official 68:41613245dfd7 2402 #define I2S_TCR3_WDFL_MASK 0x1Fu
mbed_official 68:41613245dfd7 2403 #define I2S_TCR3_WDFL_SHIFT 0
mbed_official 68:41613245dfd7 2404 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
mbed_official 68:41613245dfd7 2405 #define I2S_TCR3_TCE_MASK 0x30000u
mbed_official 68:41613245dfd7 2406 #define I2S_TCR3_TCE_SHIFT 16
mbed_official 68:41613245dfd7 2407 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
mbed_official 68:41613245dfd7 2408 /* TCR4 Bit Fields */
mbed_official 68:41613245dfd7 2409 #define I2S_TCR4_FSD_MASK 0x1u
mbed_official 68:41613245dfd7 2410 #define I2S_TCR4_FSD_SHIFT 0
mbed_official 68:41613245dfd7 2411 #define I2S_TCR4_FSP_MASK 0x2u
mbed_official 68:41613245dfd7 2412 #define I2S_TCR4_FSP_SHIFT 1
mbed_official 68:41613245dfd7 2413 #define I2S_TCR4_FSE_MASK 0x8u
mbed_official 68:41613245dfd7 2414 #define I2S_TCR4_FSE_SHIFT 3
mbed_official 68:41613245dfd7 2415 #define I2S_TCR4_MF_MASK 0x10u
mbed_official 68:41613245dfd7 2416 #define I2S_TCR4_MF_SHIFT 4
mbed_official 68:41613245dfd7 2417 #define I2S_TCR4_SYWD_MASK 0x1F00u
mbed_official 68:41613245dfd7 2418 #define I2S_TCR4_SYWD_SHIFT 8
mbed_official 68:41613245dfd7 2419 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mbed_official 68:41613245dfd7 2420 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
mbed_official 68:41613245dfd7 2421 #define I2S_TCR4_FRSZ_SHIFT 16
mbed_official 68:41613245dfd7 2422 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
mbed_official 68:41613245dfd7 2423 /* TCR5 Bit Fields */
mbed_official 68:41613245dfd7 2424 #define I2S_TCR5_FBT_MASK 0x1F00u
mbed_official 68:41613245dfd7 2425 #define I2S_TCR5_FBT_SHIFT 8
mbed_official 68:41613245dfd7 2426 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mbed_official 68:41613245dfd7 2427 #define I2S_TCR5_W0W_MASK 0x1F0000u
mbed_official 68:41613245dfd7 2428 #define I2S_TCR5_W0W_SHIFT 16
mbed_official 68:41613245dfd7 2429 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mbed_official 68:41613245dfd7 2430 #define I2S_TCR5_WNW_MASK 0x1F000000u
mbed_official 68:41613245dfd7 2431 #define I2S_TCR5_WNW_SHIFT 24
mbed_official 68:41613245dfd7 2432 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mbed_official 68:41613245dfd7 2433 /* TDR Bit Fields */
mbed_official 68:41613245dfd7 2434 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2435 #define I2S_TDR_TDR_SHIFT 0
mbed_official 68:41613245dfd7 2436 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mbed_official 68:41613245dfd7 2437 /* TFR Bit Fields */
mbed_official 68:41613245dfd7 2438 #define I2S_TFR_RFP_MASK 0xFu
mbed_official 68:41613245dfd7 2439 #define I2S_TFR_RFP_SHIFT 0
mbed_official 68:41613245dfd7 2440 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
mbed_official 68:41613245dfd7 2441 #define I2S_TFR_WFP_MASK 0xF0000u
mbed_official 68:41613245dfd7 2442 #define I2S_TFR_WFP_SHIFT 16
mbed_official 68:41613245dfd7 2443 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
mbed_official 68:41613245dfd7 2444 /* TMR Bit Fields */
mbed_official 68:41613245dfd7 2445 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2446 #define I2S_TMR_TWM_SHIFT 0
mbed_official 68:41613245dfd7 2447 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mbed_official 68:41613245dfd7 2448 /* RCSR Bit Fields */
mbed_official 68:41613245dfd7 2449 #define I2S_RCSR_FRDE_MASK 0x1u
mbed_official 68:41613245dfd7 2450 #define I2S_RCSR_FRDE_SHIFT 0
mbed_official 68:41613245dfd7 2451 #define I2S_RCSR_FWDE_MASK 0x2u
mbed_official 68:41613245dfd7 2452 #define I2S_RCSR_FWDE_SHIFT 1
mbed_official 68:41613245dfd7 2453 #define I2S_RCSR_FRIE_MASK 0x100u
mbed_official 68:41613245dfd7 2454 #define I2S_RCSR_FRIE_SHIFT 8
mbed_official 68:41613245dfd7 2455 #define I2S_RCSR_FWIE_MASK 0x200u
mbed_official 68:41613245dfd7 2456 #define I2S_RCSR_FWIE_SHIFT 9
mbed_official 68:41613245dfd7 2457 #define I2S_RCSR_FEIE_MASK 0x400u
mbed_official 68:41613245dfd7 2458 #define I2S_RCSR_FEIE_SHIFT 10
mbed_official 68:41613245dfd7 2459 #define I2S_RCSR_SEIE_MASK 0x800u
mbed_official 68:41613245dfd7 2460 #define I2S_RCSR_SEIE_SHIFT 11
mbed_official 68:41613245dfd7 2461 #define I2S_RCSR_WSIE_MASK 0x1000u
mbed_official 68:41613245dfd7 2462 #define I2S_RCSR_WSIE_SHIFT 12
mbed_official 68:41613245dfd7 2463 #define I2S_RCSR_FRF_MASK 0x10000u
mbed_official 68:41613245dfd7 2464 #define I2S_RCSR_FRF_SHIFT 16
mbed_official 68:41613245dfd7 2465 #define I2S_RCSR_FWF_MASK 0x20000u
mbed_official 68:41613245dfd7 2466 #define I2S_RCSR_FWF_SHIFT 17
mbed_official 68:41613245dfd7 2467 #define I2S_RCSR_FEF_MASK 0x40000u
mbed_official 68:41613245dfd7 2468 #define I2S_RCSR_FEF_SHIFT 18
mbed_official 68:41613245dfd7 2469 #define I2S_RCSR_SEF_MASK 0x80000u
mbed_official 68:41613245dfd7 2470 #define I2S_RCSR_SEF_SHIFT 19
mbed_official 68:41613245dfd7 2471 #define I2S_RCSR_WSF_MASK 0x100000u
mbed_official 68:41613245dfd7 2472 #define I2S_RCSR_WSF_SHIFT 20
mbed_official 68:41613245dfd7 2473 #define I2S_RCSR_SR_MASK 0x1000000u
mbed_official 68:41613245dfd7 2474 #define I2S_RCSR_SR_SHIFT 24
mbed_official 68:41613245dfd7 2475 #define I2S_RCSR_FR_MASK 0x2000000u
mbed_official 68:41613245dfd7 2476 #define I2S_RCSR_FR_SHIFT 25
mbed_official 68:41613245dfd7 2477 #define I2S_RCSR_BCE_MASK 0x10000000u
mbed_official 68:41613245dfd7 2478 #define I2S_RCSR_BCE_SHIFT 28
mbed_official 68:41613245dfd7 2479 #define I2S_RCSR_DBGE_MASK 0x20000000u
mbed_official 68:41613245dfd7 2480 #define I2S_RCSR_DBGE_SHIFT 29
mbed_official 68:41613245dfd7 2481 #define I2S_RCSR_STOPE_MASK 0x40000000u
mbed_official 68:41613245dfd7 2482 #define I2S_RCSR_STOPE_SHIFT 30
mbed_official 68:41613245dfd7 2483 #define I2S_RCSR_RE_MASK 0x80000000u
mbed_official 68:41613245dfd7 2484 #define I2S_RCSR_RE_SHIFT 31
mbed_official 68:41613245dfd7 2485 /* RCR1 Bit Fields */
mbed_official 68:41613245dfd7 2486 #define I2S_RCR1_RFW_MASK 0x7u
mbed_official 68:41613245dfd7 2487 #define I2S_RCR1_RFW_SHIFT 0
mbed_official 68:41613245dfd7 2488 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
mbed_official 68:41613245dfd7 2489 /* RCR2 Bit Fields */
mbed_official 68:41613245dfd7 2490 #define I2S_RCR2_DIV_MASK 0xFFu
mbed_official 68:41613245dfd7 2491 #define I2S_RCR2_DIV_SHIFT 0
mbed_official 68:41613245dfd7 2492 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mbed_official 68:41613245dfd7 2493 #define I2S_RCR2_BCD_MASK 0x1000000u
mbed_official 68:41613245dfd7 2494 #define I2S_RCR2_BCD_SHIFT 24
mbed_official 68:41613245dfd7 2495 #define I2S_RCR2_BCP_MASK 0x2000000u
mbed_official 68:41613245dfd7 2496 #define I2S_RCR2_BCP_SHIFT 25
mbed_official 68:41613245dfd7 2497 #define I2S_RCR2_MSEL_MASK 0xC000000u
mbed_official 68:41613245dfd7 2498 #define I2S_RCR2_MSEL_SHIFT 26
mbed_official 68:41613245dfd7 2499 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
mbed_official 68:41613245dfd7 2500 #define I2S_RCR2_BCI_MASK 0x10000000u
mbed_official 68:41613245dfd7 2501 #define I2S_RCR2_BCI_SHIFT 28
mbed_official 68:41613245dfd7 2502 #define I2S_RCR2_BCS_MASK 0x20000000u
mbed_official 68:41613245dfd7 2503 #define I2S_RCR2_BCS_SHIFT 29
mbed_official 68:41613245dfd7 2504 #define I2S_RCR2_SYNC_MASK 0xC0000000u
mbed_official 68:41613245dfd7 2505 #define I2S_RCR2_SYNC_SHIFT 30
mbed_official 68:41613245dfd7 2506 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
mbed_official 68:41613245dfd7 2507 /* RCR3 Bit Fields */
mbed_official 68:41613245dfd7 2508 #define I2S_RCR3_WDFL_MASK 0x1Fu
mbed_official 68:41613245dfd7 2509 #define I2S_RCR3_WDFL_SHIFT 0
mbed_official 68:41613245dfd7 2510 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
mbed_official 68:41613245dfd7 2511 #define I2S_RCR3_RCE_MASK 0x30000u
mbed_official 68:41613245dfd7 2512 #define I2S_RCR3_RCE_SHIFT 16
mbed_official 68:41613245dfd7 2513 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
mbed_official 68:41613245dfd7 2514 /* RCR4 Bit Fields */
mbed_official 68:41613245dfd7 2515 #define I2S_RCR4_FSD_MASK 0x1u
mbed_official 68:41613245dfd7 2516 #define I2S_RCR4_FSD_SHIFT 0
mbed_official 68:41613245dfd7 2517 #define I2S_RCR4_FSP_MASK 0x2u
mbed_official 68:41613245dfd7 2518 #define I2S_RCR4_FSP_SHIFT 1
mbed_official 68:41613245dfd7 2519 #define I2S_RCR4_FSE_MASK 0x8u
mbed_official 68:41613245dfd7 2520 #define I2S_RCR4_FSE_SHIFT 3
mbed_official 68:41613245dfd7 2521 #define I2S_RCR4_MF_MASK 0x10u
mbed_official 68:41613245dfd7 2522 #define I2S_RCR4_MF_SHIFT 4
mbed_official 68:41613245dfd7 2523 #define I2S_RCR4_SYWD_MASK 0x1F00u
mbed_official 68:41613245dfd7 2524 #define I2S_RCR4_SYWD_SHIFT 8
mbed_official 68:41613245dfd7 2525 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mbed_official 68:41613245dfd7 2526 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
mbed_official 68:41613245dfd7 2527 #define I2S_RCR4_FRSZ_SHIFT 16
mbed_official 68:41613245dfd7 2528 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
mbed_official 68:41613245dfd7 2529 /* RCR5 Bit Fields */
mbed_official 68:41613245dfd7 2530 #define I2S_RCR5_FBT_MASK 0x1F00u
mbed_official 68:41613245dfd7 2531 #define I2S_RCR5_FBT_SHIFT 8
mbed_official 68:41613245dfd7 2532 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mbed_official 68:41613245dfd7 2533 #define I2S_RCR5_W0W_MASK 0x1F0000u
mbed_official 68:41613245dfd7 2534 #define I2S_RCR5_W0W_SHIFT 16
mbed_official 68:41613245dfd7 2535 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mbed_official 68:41613245dfd7 2536 #define I2S_RCR5_WNW_MASK 0x1F000000u
mbed_official 68:41613245dfd7 2537 #define I2S_RCR5_WNW_SHIFT 24
mbed_official 68:41613245dfd7 2538 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mbed_official 68:41613245dfd7 2539 /* RDR Bit Fields */
mbed_official 68:41613245dfd7 2540 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2541 #define I2S_RDR_RDR_SHIFT 0
mbed_official 68:41613245dfd7 2542 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mbed_official 68:41613245dfd7 2543 /* RFR Bit Fields */
mbed_official 68:41613245dfd7 2544 #define I2S_RFR_RFP_MASK 0xFu
mbed_official 68:41613245dfd7 2545 #define I2S_RFR_RFP_SHIFT 0
mbed_official 68:41613245dfd7 2546 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
mbed_official 68:41613245dfd7 2547 #define I2S_RFR_WFP_MASK 0xF0000u
mbed_official 68:41613245dfd7 2548 #define I2S_RFR_WFP_SHIFT 16
mbed_official 68:41613245dfd7 2549 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
mbed_official 68:41613245dfd7 2550 /* RMR Bit Fields */
mbed_official 68:41613245dfd7 2551 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 2552 #define I2S_RMR_RWM_SHIFT 0
mbed_official 68:41613245dfd7 2553 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mbed_official 68:41613245dfd7 2554 /* MCR Bit Fields */
mbed_official 68:41613245dfd7 2555 #define I2S_MCR_MICS_MASK 0x3000000u
mbed_official 68:41613245dfd7 2556 #define I2S_MCR_MICS_SHIFT 24
mbed_official 68:41613245dfd7 2557 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mbed_official 68:41613245dfd7 2558 #define I2S_MCR_MOE_MASK 0x40000000u
mbed_official 68:41613245dfd7 2559 #define I2S_MCR_MOE_SHIFT 30
mbed_official 68:41613245dfd7 2560 #define I2S_MCR_DUF_MASK 0x80000000u
mbed_official 68:41613245dfd7 2561 #define I2S_MCR_DUF_SHIFT 31
mbed_official 68:41613245dfd7 2562 /* MDR Bit Fields */
mbed_official 68:41613245dfd7 2563 #define I2S_MDR_DIVIDE_MASK 0xFFFu
mbed_official 68:41613245dfd7 2564 #define I2S_MDR_DIVIDE_SHIFT 0
mbed_official 68:41613245dfd7 2565 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
mbed_official 68:41613245dfd7 2566 #define I2S_MDR_FRACT_MASK 0xFF000u
mbed_official 68:41613245dfd7 2567 #define I2S_MDR_FRACT_SHIFT 12
mbed_official 68:41613245dfd7 2568 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
mbed_official 68:41613245dfd7 2569
mbed_official 68:41613245dfd7 2570 /**
mbed_official 68:41613245dfd7 2571 * @}
mbed_official 68:41613245dfd7 2572 */ /* end of group I2S_Register_Masks */
mbed_official 68:41613245dfd7 2573
mbed_official 68:41613245dfd7 2574
mbed_official 68:41613245dfd7 2575 /* I2S - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 2576 /** Peripheral I2S0 base address */
mbed_official 68:41613245dfd7 2577 #define I2S0_BASE (0x4002F000u)
mbed_official 68:41613245dfd7 2578 /** Peripheral I2S0 base pointer */
mbed_official 68:41613245dfd7 2579 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 68:41613245dfd7 2580
mbed_official 68:41613245dfd7 2581 /**
mbed_official 68:41613245dfd7 2582 * @}
mbed_official 68:41613245dfd7 2583 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 2584
mbed_official 68:41613245dfd7 2585
mbed_official 68:41613245dfd7 2586 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2587 -- LLWU Peripheral Access Layer
mbed_official 68:41613245dfd7 2588 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2589
mbed_official 68:41613245dfd7 2590 /**
mbed_official 68:41613245dfd7 2591 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 68:41613245dfd7 2592 * @{
mbed_official 68:41613245dfd7 2593 */
mbed_official 68:41613245dfd7 2594
mbed_official 68:41613245dfd7 2595 /** LLWU - Register Layout Typedef */
mbed_official 68:41613245dfd7 2596 typedef struct {
mbed_official 68:41613245dfd7 2597 __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
mbed_official 68:41613245dfd7 2598 __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
mbed_official 68:41613245dfd7 2599 __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
mbed_official 68:41613245dfd7 2600 __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
mbed_official 68:41613245dfd7 2601 __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
mbed_official 68:41613245dfd7 2602 __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
mbed_official 68:41613245dfd7 2603 __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
mbed_official 68:41613245dfd7 2604 __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
mbed_official 68:41613245dfd7 2605 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
mbed_official 68:41613245dfd7 2606 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
mbed_official 68:41613245dfd7 2607 __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
mbed_official 68:41613245dfd7 2608 } LLWU_Type;
mbed_official 68:41613245dfd7 2609
mbed_official 68:41613245dfd7 2610 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2611 -- LLWU Register Masks
mbed_official 68:41613245dfd7 2612 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2613
mbed_official 68:41613245dfd7 2614 /**
mbed_official 68:41613245dfd7 2615 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 68:41613245dfd7 2616 * @{
mbed_official 68:41613245dfd7 2617 */
mbed_official 68:41613245dfd7 2618
mbed_official 68:41613245dfd7 2619 /* PE1 Bit Fields */
mbed_official 68:41613245dfd7 2620 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 68:41613245dfd7 2621 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 68:41613245dfd7 2622 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 68:41613245dfd7 2623 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 68:41613245dfd7 2624 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 68:41613245dfd7 2625 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 68:41613245dfd7 2626 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 68:41613245dfd7 2627 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 68:41613245dfd7 2628 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 68:41613245dfd7 2629 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 68:41613245dfd7 2630 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 68:41613245dfd7 2631 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 68:41613245dfd7 2632 /* PE2 Bit Fields */
mbed_official 68:41613245dfd7 2633 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 68:41613245dfd7 2634 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 68:41613245dfd7 2635 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 68:41613245dfd7 2636 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 68:41613245dfd7 2637 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 68:41613245dfd7 2638 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 68:41613245dfd7 2639 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 68:41613245dfd7 2640 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 68:41613245dfd7 2641 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 68:41613245dfd7 2642 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 68:41613245dfd7 2643 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 68:41613245dfd7 2644 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 68:41613245dfd7 2645 /* PE3 Bit Fields */
mbed_official 68:41613245dfd7 2646 #define LLWU_PE3_WUPE8_MASK 0x3u
mbed_official 68:41613245dfd7 2647 #define LLWU_PE3_WUPE8_SHIFT 0
mbed_official 68:41613245dfd7 2648 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mbed_official 68:41613245dfd7 2649 #define LLWU_PE3_WUPE9_MASK 0xCu
mbed_official 68:41613245dfd7 2650 #define LLWU_PE3_WUPE9_SHIFT 2
mbed_official 68:41613245dfd7 2651 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mbed_official 68:41613245dfd7 2652 #define LLWU_PE3_WUPE10_MASK 0x30u
mbed_official 68:41613245dfd7 2653 #define LLWU_PE3_WUPE10_SHIFT 4
mbed_official 68:41613245dfd7 2654 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mbed_official 68:41613245dfd7 2655 #define LLWU_PE3_WUPE11_MASK 0xC0u
mbed_official 68:41613245dfd7 2656 #define LLWU_PE3_WUPE11_SHIFT 6
mbed_official 68:41613245dfd7 2657 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mbed_official 68:41613245dfd7 2658 /* PE4 Bit Fields */
mbed_official 68:41613245dfd7 2659 #define LLWU_PE4_WUPE12_MASK 0x3u
mbed_official 68:41613245dfd7 2660 #define LLWU_PE4_WUPE12_SHIFT 0
mbed_official 68:41613245dfd7 2661 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mbed_official 68:41613245dfd7 2662 #define LLWU_PE4_WUPE13_MASK 0xCu
mbed_official 68:41613245dfd7 2663 #define LLWU_PE4_WUPE13_SHIFT 2
mbed_official 68:41613245dfd7 2664 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mbed_official 68:41613245dfd7 2665 #define LLWU_PE4_WUPE14_MASK 0x30u
mbed_official 68:41613245dfd7 2666 #define LLWU_PE4_WUPE14_SHIFT 4
mbed_official 68:41613245dfd7 2667 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mbed_official 68:41613245dfd7 2668 #define LLWU_PE4_WUPE15_MASK 0xC0u
mbed_official 68:41613245dfd7 2669 #define LLWU_PE4_WUPE15_SHIFT 6
mbed_official 68:41613245dfd7 2670 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mbed_official 68:41613245dfd7 2671 /* ME Bit Fields */
mbed_official 68:41613245dfd7 2672 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 68:41613245dfd7 2673 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 68:41613245dfd7 2674 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 68:41613245dfd7 2675 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 68:41613245dfd7 2676 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 68:41613245dfd7 2677 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 68:41613245dfd7 2678 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 68:41613245dfd7 2679 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 68:41613245dfd7 2680 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 68:41613245dfd7 2681 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 68:41613245dfd7 2682 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 68:41613245dfd7 2683 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 68:41613245dfd7 2684 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 68:41613245dfd7 2685 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 68:41613245dfd7 2686 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 68:41613245dfd7 2687 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 68:41613245dfd7 2688 /* F1 Bit Fields */
mbed_official 68:41613245dfd7 2689 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 68:41613245dfd7 2690 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 68:41613245dfd7 2691 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 68:41613245dfd7 2692 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 68:41613245dfd7 2693 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 68:41613245dfd7 2694 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 68:41613245dfd7 2695 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 68:41613245dfd7 2696 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 68:41613245dfd7 2697 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 68:41613245dfd7 2698 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 68:41613245dfd7 2699 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 68:41613245dfd7 2700 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 68:41613245dfd7 2701 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 68:41613245dfd7 2702 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 68:41613245dfd7 2703 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 68:41613245dfd7 2704 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 68:41613245dfd7 2705 /* F2 Bit Fields */
mbed_official 68:41613245dfd7 2706 #define LLWU_F2_WUF8_MASK 0x1u
mbed_official 68:41613245dfd7 2707 #define LLWU_F2_WUF8_SHIFT 0
mbed_official 68:41613245dfd7 2708 #define LLWU_F2_WUF9_MASK 0x2u
mbed_official 68:41613245dfd7 2709 #define LLWU_F2_WUF9_SHIFT 1
mbed_official 68:41613245dfd7 2710 #define LLWU_F2_WUF10_MASK 0x4u
mbed_official 68:41613245dfd7 2711 #define LLWU_F2_WUF10_SHIFT 2
mbed_official 68:41613245dfd7 2712 #define LLWU_F2_WUF11_MASK 0x8u
mbed_official 68:41613245dfd7 2713 #define LLWU_F2_WUF11_SHIFT 3
mbed_official 68:41613245dfd7 2714 #define LLWU_F2_WUF12_MASK 0x10u
mbed_official 68:41613245dfd7 2715 #define LLWU_F2_WUF12_SHIFT 4
mbed_official 68:41613245dfd7 2716 #define LLWU_F2_WUF13_MASK 0x20u
mbed_official 68:41613245dfd7 2717 #define LLWU_F2_WUF13_SHIFT 5
mbed_official 68:41613245dfd7 2718 #define LLWU_F2_WUF14_MASK 0x40u
mbed_official 68:41613245dfd7 2719 #define LLWU_F2_WUF14_SHIFT 6
mbed_official 68:41613245dfd7 2720 #define LLWU_F2_WUF15_MASK 0x80u
mbed_official 68:41613245dfd7 2721 #define LLWU_F2_WUF15_SHIFT 7
mbed_official 68:41613245dfd7 2722 /* F3 Bit Fields */
mbed_official 68:41613245dfd7 2723 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 68:41613245dfd7 2724 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 68:41613245dfd7 2725 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 68:41613245dfd7 2726 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 68:41613245dfd7 2727 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 68:41613245dfd7 2728 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 68:41613245dfd7 2729 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 68:41613245dfd7 2730 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 68:41613245dfd7 2731 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 68:41613245dfd7 2732 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 68:41613245dfd7 2733 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 68:41613245dfd7 2734 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 68:41613245dfd7 2735 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 68:41613245dfd7 2736 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 68:41613245dfd7 2737 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 68:41613245dfd7 2738 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 68:41613245dfd7 2739 /* FILT1 Bit Fields */
mbed_official 68:41613245dfd7 2740 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 68:41613245dfd7 2741 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 68:41613245dfd7 2742 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 68:41613245dfd7 2743 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 68:41613245dfd7 2744 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 68:41613245dfd7 2745 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 68:41613245dfd7 2746 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 68:41613245dfd7 2747 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 68:41613245dfd7 2748 /* FILT2 Bit Fields */
mbed_official 68:41613245dfd7 2749 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 68:41613245dfd7 2750 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 68:41613245dfd7 2751 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 68:41613245dfd7 2752 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 68:41613245dfd7 2753 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 68:41613245dfd7 2754 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 68:41613245dfd7 2755 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 68:41613245dfd7 2756 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 68:41613245dfd7 2757 /* RST Bit Fields */
mbed_official 68:41613245dfd7 2758 #define LLWU_RST_RSTFILT_MASK 0x1u
mbed_official 68:41613245dfd7 2759 #define LLWU_RST_RSTFILT_SHIFT 0
mbed_official 68:41613245dfd7 2760 #define LLWU_RST_LLRSTE_MASK 0x2u
mbed_official 68:41613245dfd7 2761 #define LLWU_RST_LLRSTE_SHIFT 1
mbed_official 68:41613245dfd7 2762
mbed_official 68:41613245dfd7 2763 /**
mbed_official 68:41613245dfd7 2764 * @}
mbed_official 68:41613245dfd7 2765 */ /* end of group LLWU_Register_Masks */
mbed_official 68:41613245dfd7 2766
mbed_official 68:41613245dfd7 2767
mbed_official 68:41613245dfd7 2768 /* LLWU - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 2769 /** Peripheral LLWU base address */
mbed_official 68:41613245dfd7 2770 #define LLWU_BASE (0x4007C000u)
mbed_official 68:41613245dfd7 2771 /** Peripheral LLWU base pointer */
mbed_official 68:41613245dfd7 2772 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 68:41613245dfd7 2773
mbed_official 68:41613245dfd7 2774 /**
mbed_official 68:41613245dfd7 2775 * @}
mbed_official 68:41613245dfd7 2776 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 2777
mbed_official 68:41613245dfd7 2778
mbed_official 68:41613245dfd7 2779 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2780 -- LPTMR Peripheral Access Layer
mbed_official 68:41613245dfd7 2781 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2782
mbed_official 68:41613245dfd7 2783 /**
mbed_official 68:41613245dfd7 2784 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 68:41613245dfd7 2785 * @{
mbed_official 68:41613245dfd7 2786 */
mbed_official 68:41613245dfd7 2787
mbed_official 68:41613245dfd7 2788 /** LPTMR - Register Layout Typedef */
mbed_official 68:41613245dfd7 2789 typedef struct {
mbed_official 68:41613245dfd7 2790 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 68:41613245dfd7 2791 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 68:41613245dfd7 2792 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 68:41613245dfd7 2793 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 68:41613245dfd7 2794 } LPTMR_Type;
mbed_official 68:41613245dfd7 2795
mbed_official 68:41613245dfd7 2796 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2797 -- LPTMR Register Masks
mbed_official 68:41613245dfd7 2798 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2799
mbed_official 68:41613245dfd7 2800 /**
mbed_official 68:41613245dfd7 2801 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 68:41613245dfd7 2802 * @{
mbed_official 68:41613245dfd7 2803 */
mbed_official 68:41613245dfd7 2804
mbed_official 68:41613245dfd7 2805 /* CSR Bit Fields */
mbed_official 68:41613245dfd7 2806 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 68:41613245dfd7 2807 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 68:41613245dfd7 2808 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 68:41613245dfd7 2809 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 68:41613245dfd7 2810 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 68:41613245dfd7 2811 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 68:41613245dfd7 2812 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 68:41613245dfd7 2813 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 68:41613245dfd7 2814 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 68:41613245dfd7 2815 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 68:41613245dfd7 2816 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 68:41613245dfd7 2817 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 68:41613245dfd7 2818 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 68:41613245dfd7 2819 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 68:41613245dfd7 2820 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 68:41613245dfd7 2821 /* PSR Bit Fields */
mbed_official 68:41613245dfd7 2822 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 68:41613245dfd7 2823 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 68:41613245dfd7 2824 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 68:41613245dfd7 2825 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 68:41613245dfd7 2826 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 68:41613245dfd7 2827 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 68:41613245dfd7 2828 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 68:41613245dfd7 2829 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 68:41613245dfd7 2830 /* CMR Bit Fields */
mbed_official 68:41613245dfd7 2831 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 68:41613245dfd7 2832 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 68:41613245dfd7 2833 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 68:41613245dfd7 2834 /* CNR Bit Fields */
mbed_official 68:41613245dfd7 2835 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 68:41613245dfd7 2836 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 68:41613245dfd7 2837 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 68:41613245dfd7 2838
mbed_official 68:41613245dfd7 2839 /**
mbed_official 68:41613245dfd7 2840 * @}
mbed_official 68:41613245dfd7 2841 */ /* end of group LPTMR_Register_Masks */
mbed_official 68:41613245dfd7 2842
mbed_official 68:41613245dfd7 2843
mbed_official 68:41613245dfd7 2844 /* LPTMR - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 2845 /** Peripheral LPTMR0 base address */
mbed_official 68:41613245dfd7 2846 #define LPTMR0_BASE (0x40040000u)
mbed_official 68:41613245dfd7 2847 /** Peripheral LPTMR0 base pointer */
mbed_official 68:41613245dfd7 2848 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 68:41613245dfd7 2849
mbed_official 68:41613245dfd7 2850 /**
mbed_official 68:41613245dfd7 2851 * @}
mbed_official 68:41613245dfd7 2852 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 2853
mbed_official 68:41613245dfd7 2854
mbed_official 68:41613245dfd7 2855 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2856 -- MCG Peripheral Access Layer
mbed_official 68:41613245dfd7 2857 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2858
mbed_official 68:41613245dfd7 2859 /**
mbed_official 68:41613245dfd7 2860 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 68:41613245dfd7 2861 * @{
mbed_official 68:41613245dfd7 2862 */
mbed_official 68:41613245dfd7 2863
mbed_official 68:41613245dfd7 2864 /** MCG - Register Layout Typedef */
mbed_official 68:41613245dfd7 2865 typedef struct {
mbed_official 68:41613245dfd7 2866 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 68:41613245dfd7 2867 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 68:41613245dfd7 2868 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 68:41613245dfd7 2869 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 68:41613245dfd7 2870 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 68:41613245dfd7 2871 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 68:41613245dfd7 2872 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 68:41613245dfd7 2873 uint8_t RESERVED_0[1];
mbed_official 68:41613245dfd7 2874 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 68:41613245dfd7 2875 uint8_t RESERVED_1[1];
mbed_official 68:41613245dfd7 2876 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 68:41613245dfd7 2877 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 68:41613245dfd7 2878 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mbed_official 68:41613245dfd7 2879 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mbed_official 68:41613245dfd7 2880 } MCG_Type;
mbed_official 68:41613245dfd7 2881
mbed_official 68:41613245dfd7 2882 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 2883 -- MCG Register Masks
mbed_official 68:41613245dfd7 2884 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 2885
mbed_official 68:41613245dfd7 2886 /**
mbed_official 68:41613245dfd7 2887 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 68:41613245dfd7 2888 * @{
mbed_official 68:41613245dfd7 2889 */
mbed_official 68:41613245dfd7 2890
mbed_official 68:41613245dfd7 2891 /* C1 Bit Fields */
mbed_official 68:41613245dfd7 2892 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 68:41613245dfd7 2893 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 68:41613245dfd7 2894 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 68:41613245dfd7 2895 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 68:41613245dfd7 2896 #define MCG_C1_IREFS_MASK 0x4u
mbed_official 68:41613245dfd7 2897 #define MCG_C1_IREFS_SHIFT 2
mbed_official 68:41613245dfd7 2898 #define MCG_C1_FRDIV_MASK 0x38u
mbed_official 68:41613245dfd7 2899 #define MCG_C1_FRDIV_SHIFT 3
mbed_official 68:41613245dfd7 2900 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mbed_official 68:41613245dfd7 2901 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 68:41613245dfd7 2902 #define MCG_C1_CLKS_SHIFT 6
mbed_official 68:41613245dfd7 2903 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 68:41613245dfd7 2904 /* C2 Bit Fields */
mbed_official 68:41613245dfd7 2905 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 68:41613245dfd7 2906 #define MCG_C2_IRCS_SHIFT 0
mbed_official 68:41613245dfd7 2907 #define MCG_C2_LP_MASK 0x2u
mbed_official 68:41613245dfd7 2908 #define MCG_C2_LP_SHIFT 1
mbed_official 68:41613245dfd7 2909 #define MCG_C2_EREFS0_MASK 0x4u
mbed_official 68:41613245dfd7 2910 #define MCG_C2_EREFS0_SHIFT 2
mbed_official 68:41613245dfd7 2911 #define MCG_C2_HGO0_MASK 0x8u
mbed_official 68:41613245dfd7 2912 #define MCG_C2_HGO0_SHIFT 3
mbed_official 68:41613245dfd7 2913 #define MCG_C2_RANGE0_MASK 0x30u
mbed_official 68:41613245dfd7 2914 #define MCG_C2_RANGE0_SHIFT 4
mbed_official 68:41613245dfd7 2915 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
mbed_official 68:41613245dfd7 2916 #define MCG_C2_LOCRE0_MASK 0x80u
mbed_official 68:41613245dfd7 2917 #define MCG_C2_LOCRE0_SHIFT 7
mbed_official 68:41613245dfd7 2918 /* C3 Bit Fields */
mbed_official 68:41613245dfd7 2919 #define MCG_C3_SCTRIM_MASK 0xFFu
mbed_official 68:41613245dfd7 2920 #define MCG_C3_SCTRIM_SHIFT 0
mbed_official 68:41613245dfd7 2921 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mbed_official 68:41613245dfd7 2922 /* C4 Bit Fields */
mbed_official 68:41613245dfd7 2923 #define MCG_C4_SCFTRIM_MASK 0x1u
mbed_official 68:41613245dfd7 2924 #define MCG_C4_SCFTRIM_SHIFT 0
mbed_official 68:41613245dfd7 2925 #define MCG_C4_FCTRIM_MASK 0x1Eu
mbed_official 68:41613245dfd7 2926 #define MCG_C4_FCTRIM_SHIFT 1
mbed_official 68:41613245dfd7 2927 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mbed_official 68:41613245dfd7 2928 #define MCG_C4_DRST_DRS_MASK 0x60u
mbed_official 68:41613245dfd7 2929 #define MCG_C4_DRST_DRS_SHIFT 5
mbed_official 68:41613245dfd7 2930 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mbed_official 68:41613245dfd7 2931 #define MCG_C4_DMX32_MASK 0x80u
mbed_official 68:41613245dfd7 2932 #define MCG_C4_DMX32_SHIFT 7
mbed_official 68:41613245dfd7 2933 /* C5 Bit Fields */
mbed_official 68:41613245dfd7 2934 #define MCG_C5_PRDIV0_MASK 0x1Fu
mbed_official 68:41613245dfd7 2935 #define MCG_C5_PRDIV0_SHIFT 0
mbed_official 68:41613245dfd7 2936 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
mbed_official 68:41613245dfd7 2937 #define MCG_C5_PLLSTEN0_MASK 0x20u
mbed_official 68:41613245dfd7 2938 #define MCG_C5_PLLSTEN0_SHIFT 5
mbed_official 68:41613245dfd7 2939 #define MCG_C5_PLLCLKEN0_MASK 0x40u
mbed_official 68:41613245dfd7 2940 #define MCG_C5_PLLCLKEN0_SHIFT 6
mbed_official 68:41613245dfd7 2941 /* C6 Bit Fields */
mbed_official 68:41613245dfd7 2942 #define MCG_C6_VDIV0_MASK 0x1Fu
mbed_official 68:41613245dfd7 2943 #define MCG_C6_VDIV0_SHIFT 0
mbed_official 68:41613245dfd7 2944 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
mbed_official 68:41613245dfd7 2945 #define MCG_C6_CME0_MASK 0x20u
mbed_official 68:41613245dfd7 2946 #define MCG_C6_CME0_SHIFT 5
mbed_official 68:41613245dfd7 2947 #define MCG_C6_PLLS_MASK 0x40u
mbed_official 68:41613245dfd7 2948 #define MCG_C6_PLLS_SHIFT 6
mbed_official 68:41613245dfd7 2949 #define MCG_C6_LOLIE0_MASK 0x80u
mbed_official 68:41613245dfd7 2950 #define MCG_C6_LOLIE0_SHIFT 7
mbed_official 68:41613245dfd7 2951 /* S Bit Fields */
mbed_official 68:41613245dfd7 2952 #define MCG_S_IRCST_MASK 0x1u
mbed_official 68:41613245dfd7 2953 #define MCG_S_IRCST_SHIFT 0
mbed_official 68:41613245dfd7 2954 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 68:41613245dfd7 2955 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 68:41613245dfd7 2956 #define MCG_S_CLKST_MASK 0xCu
mbed_official 68:41613245dfd7 2957 #define MCG_S_CLKST_SHIFT 2
mbed_official 68:41613245dfd7 2958 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 68:41613245dfd7 2959 #define MCG_S_IREFST_MASK 0x10u
mbed_official 68:41613245dfd7 2960 #define MCG_S_IREFST_SHIFT 4
mbed_official 68:41613245dfd7 2961 #define MCG_S_PLLST_MASK 0x20u
mbed_official 68:41613245dfd7 2962 #define MCG_S_PLLST_SHIFT 5
mbed_official 68:41613245dfd7 2963 #define MCG_S_LOCK0_MASK 0x40u
mbed_official 68:41613245dfd7 2964 #define MCG_S_LOCK0_SHIFT 6
mbed_official 68:41613245dfd7 2965 #define MCG_S_LOLS0_MASK 0x80u
mbed_official 68:41613245dfd7 2966 #define MCG_S_LOLS0_SHIFT 7
mbed_official 68:41613245dfd7 2967 /* SC Bit Fields */
mbed_official 68:41613245dfd7 2968 #define MCG_SC_LOCS0_MASK 0x1u
mbed_official 68:41613245dfd7 2969 #define MCG_SC_LOCS0_SHIFT 0
mbed_official 68:41613245dfd7 2970 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 68:41613245dfd7 2971 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 68:41613245dfd7 2972 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 68:41613245dfd7 2973 #define MCG_SC_FLTPRSRV_MASK 0x10u
mbed_official 68:41613245dfd7 2974 #define MCG_SC_FLTPRSRV_SHIFT 4
mbed_official 68:41613245dfd7 2975 #define MCG_SC_ATMF_MASK 0x20u
mbed_official 68:41613245dfd7 2976 #define MCG_SC_ATMF_SHIFT 5
mbed_official 68:41613245dfd7 2977 #define MCG_SC_ATMS_MASK 0x40u
mbed_official 68:41613245dfd7 2978 #define MCG_SC_ATMS_SHIFT 6
mbed_official 68:41613245dfd7 2979 #define MCG_SC_ATME_MASK 0x80u
mbed_official 68:41613245dfd7 2980 #define MCG_SC_ATME_SHIFT 7
mbed_official 68:41613245dfd7 2981 /* ATCVH Bit Fields */
mbed_official 68:41613245dfd7 2982 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mbed_official 68:41613245dfd7 2983 #define MCG_ATCVH_ATCVH_SHIFT 0
mbed_official 68:41613245dfd7 2984 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mbed_official 68:41613245dfd7 2985 /* ATCVL Bit Fields */
mbed_official 68:41613245dfd7 2986 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mbed_official 68:41613245dfd7 2987 #define MCG_ATCVL_ATCVL_SHIFT 0
mbed_official 68:41613245dfd7 2988 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mbed_official 68:41613245dfd7 2989 /* C7 Bit Fields */
mbed_official 68:41613245dfd7 2990 #define MCG_C7_OSCSEL_MASK 0x1u
mbed_official 68:41613245dfd7 2991 #define MCG_C7_OSCSEL_SHIFT 0
mbed_official 68:41613245dfd7 2992 /* C8 Bit Fields */
mbed_official 68:41613245dfd7 2993 #define MCG_C8_LOCS1_MASK 0x1u
mbed_official 68:41613245dfd7 2994 #define MCG_C8_LOCS1_SHIFT 0
mbed_official 68:41613245dfd7 2995 #define MCG_C8_CME1_MASK 0x20u
mbed_official 68:41613245dfd7 2996 #define MCG_C8_CME1_SHIFT 5
mbed_official 68:41613245dfd7 2997 #define MCG_C8_LOLRE_MASK 0x40u
mbed_official 68:41613245dfd7 2998 #define MCG_C8_LOLRE_SHIFT 6
mbed_official 68:41613245dfd7 2999 #define MCG_C8_LOCRE1_MASK 0x80u
mbed_official 68:41613245dfd7 3000 #define MCG_C8_LOCRE1_SHIFT 7
mbed_official 68:41613245dfd7 3001
mbed_official 68:41613245dfd7 3002 /**
mbed_official 68:41613245dfd7 3003 * @}
mbed_official 68:41613245dfd7 3004 */ /* end of group MCG_Register_Masks */
mbed_official 68:41613245dfd7 3005
mbed_official 68:41613245dfd7 3006
mbed_official 68:41613245dfd7 3007 /* MCG - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3008 /** Peripheral MCG base address */
mbed_official 68:41613245dfd7 3009 #define MCG_BASE (0x40064000u)
mbed_official 68:41613245dfd7 3010 /** Peripheral MCG base pointer */
mbed_official 68:41613245dfd7 3011 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 68:41613245dfd7 3012
mbed_official 68:41613245dfd7 3013 /**
mbed_official 68:41613245dfd7 3014 * @}
mbed_official 68:41613245dfd7 3015 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3016
mbed_official 68:41613245dfd7 3017
mbed_official 68:41613245dfd7 3018 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3019 -- NV Peripheral Access Layer
mbed_official 68:41613245dfd7 3020 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3021
mbed_official 68:41613245dfd7 3022 /**
mbed_official 68:41613245dfd7 3023 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 68:41613245dfd7 3024 * @{
mbed_official 68:41613245dfd7 3025 */
mbed_official 68:41613245dfd7 3026
mbed_official 68:41613245dfd7 3027 /** NV - Register Layout Typedef */
mbed_official 68:41613245dfd7 3028 typedef struct {
mbed_official 68:41613245dfd7 3029 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 68:41613245dfd7 3030 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 68:41613245dfd7 3031 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 68:41613245dfd7 3032 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 68:41613245dfd7 3033 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 68:41613245dfd7 3034 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 68:41613245dfd7 3035 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 68:41613245dfd7 3036 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 68:41613245dfd7 3037 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 68:41613245dfd7 3038 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 68:41613245dfd7 3039 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 68:41613245dfd7 3040 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 68:41613245dfd7 3041 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 68:41613245dfd7 3042 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 68:41613245dfd7 3043 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
mbed_official 68:41613245dfd7 3044 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
mbed_official 68:41613245dfd7 3045 } NV_Type;
mbed_official 68:41613245dfd7 3046
mbed_official 68:41613245dfd7 3047 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3048 -- NV Register Masks
mbed_official 68:41613245dfd7 3049 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3050
mbed_official 68:41613245dfd7 3051 /**
mbed_official 68:41613245dfd7 3052 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 68:41613245dfd7 3053 * @{
mbed_official 68:41613245dfd7 3054 */
mbed_official 68:41613245dfd7 3055
mbed_official 68:41613245dfd7 3056 /* BACKKEY3 Bit Fields */
mbed_official 68:41613245dfd7 3057 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3058 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3059 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 68:41613245dfd7 3060 /* BACKKEY2 Bit Fields */
mbed_official 68:41613245dfd7 3061 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3062 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3063 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 68:41613245dfd7 3064 /* BACKKEY1 Bit Fields */
mbed_official 68:41613245dfd7 3065 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3066 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3067 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 68:41613245dfd7 3068 /* BACKKEY0 Bit Fields */
mbed_official 68:41613245dfd7 3069 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3070 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3071 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 68:41613245dfd7 3072 /* BACKKEY7 Bit Fields */
mbed_official 68:41613245dfd7 3073 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3074 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3075 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 68:41613245dfd7 3076 /* BACKKEY6 Bit Fields */
mbed_official 68:41613245dfd7 3077 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3078 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3079 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 68:41613245dfd7 3080 /* BACKKEY5 Bit Fields */
mbed_official 68:41613245dfd7 3081 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3082 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3083 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 68:41613245dfd7 3084 /* BACKKEY4 Bit Fields */
mbed_official 68:41613245dfd7 3085 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 68:41613245dfd7 3086 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 68:41613245dfd7 3087 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 68:41613245dfd7 3088 /* FPROT3 Bit Fields */
mbed_official 68:41613245dfd7 3089 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 3090 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 68:41613245dfd7 3091 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 68:41613245dfd7 3092 /* FPROT2 Bit Fields */
mbed_official 68:41613245dfd7 3093 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 3094 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 68:41613245dfd7 3095 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 68:41613245dfd7 3096 /* FPROT1 Bit Fields */
mbed_official 68:41613245dfd7 3097 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 3098 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 68:41613245dfd7 3099 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 68:41613245dfd7 3100 /* FPROT0 Bit Fields */
mbed_official 68:41613245dfd7 3101 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 68:41613245dfd7 3102 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 68:41613245dfd7 3103 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 68:41613245dfd7 3104 /* FSEC Bit Fields */
mbed_official 68:41613245dfd7 3105 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 68:41613245dfd7 3106 #define NV_FSEC_SEC_SHIFT 0
mbed_official 68:41613245dfd7 3107 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 68:41613245dfd7 3108 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 68:41613245dfd7 3109 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 68:41613245dfd7 3110 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 68:41613245dfd7 3111 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 68:41613245dfd7 3112 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 68:41613245dfd7 3113 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 68:41613245dfd7 3114 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 68:41613245dfd7 3115 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 68:41613245dfd7 3116 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 68:41613245dfd7 3117 /* FOPT Bit Fields */
mbed_official 68:41613245dfd7 3118 #define NV_FOPT_LPBOOT_MASK 0x1u
mbed_official 68:41613245dfd7 3119 #define NV_FOPT_LPBOOT_SHIFT 0
mbed_official 68:41613245dfd7 3120 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
mbed_official 68:41613245dfd7 3121 #define NV_FOPT_EZPORT_DIS_SHIFT 1
mbed_official 68:41613245dfd7 3122 /* FEPROT Bit Fields */
mbed_official 68:41613245dfd7 3123 #define NV_FEPROT_EPROT_MASK 0xFFu
mbed_official 68:41613245dfd7 3124 #define NV_FEPROT_EPROT_SHIFT 0
mbed_official 68:41613245dfd7 3125 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
mbed_official 68:41613245dfd7 3126 /* FDPROT Bit Fields */
mbed_official 68:41613245dfd7 3127 #define NV_FDPROT_DPROT_MASK 0xFFu
mbed_official 68:41613245dfd7 3128 #define NV_FDPROT_DPROT_SHIFT 0
mbed_official 68:41613245dfd7 3129 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
mbed_official 68:41613245dfd7 3130
mbed_official 68:41613245dfd7 3131 /**
mbed_official 68:41613245dfd7 3132 * @}
mbed_official 68:41613245dfd7 3133 */ /* end of group NV_Register_Masks */
mbed_official 68:41613245dfd7 3134
mbed_official 68:41613245dfd7 3135
mbed_official 68:41613245dfd7 3136 /* NV - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3137 /** Peripheral FTFL_FlashConfig base address */
mbed_official 68:41613245dfd7 3138 #define FTFL_FlashConfig_BASE (0x400u)
mbed_official 68:41613245dfd7 3139 /** Peripheral FTFL_FlashConfig base pointer */
mbed_official 68:41613245dfd7 3140 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
mbed_official 68:41613245dfd7 3141
mbed_official 68:41613245dfd7 3142 /**
mbed_official 68:41613245dfd7 3143 * @}
mbed_official 68:41613245dfd7 3144 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3145
mbed_official 68:41613245dfd7 3146
mbed_official 68:41613245dfd7 3147 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3148 -- OSC Peripheral Access Layer
mbed_official 68:41613245dfd7 3149 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3150
mbed_official 68:41613245dfd7 3151 /**
mbed_official 68:41613245dfd7 3152 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 68:41613245dfd7 3153 * @{
mbed_official 68:41613245dfd7 3154 */
mbed_official 68:41613245dfd7 3155
mbed_official 68:41613245dfd7 3156 /** OSC - Register Layout Typedef */
mbed_official 68:41613245dfd7 3157 typedef struct {
mbed_official 68:41613245dfd7 3158 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 3159 } OSC_Type;
mbed_official 68:41613245dfd7 3160
mbed_official 68:41613245dfd7 3161 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3162 -- OSC Register Masks
mbed_official 68:41613245dfd7 3163 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3164
mbed_official 68:41613245dfd7 3165 /**
mbed_official 68:41613245dfd7 3166 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 68:41613245dfd7 3167 * @{
mbed_official 68:41613245dfd7 3168 */
mbed_official 68:41613245dfd7 3169
mbed_official 68:41613245dfd7 3170 /* CR Bit Fields */
mbed_official 68:41613245dfd7 3171 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 68:41613245dfd7 3172 #define OSC_CR_SC16P_SHIFT 0
mbed_official 68:41613245dfd7 3173 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 68:41613245dfd7 3174 #define OSC_CR_SC8P_SHIFT 1
mbed_official 68:41613245dfd7 3175 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 68:41613245dfd7 3176 #define OSC_CR_SC4P_SHIFT 2
mbed_official 68:41613245dfd7 3177 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 68:41613245dfd7 3178 #define OSC_CR_SC2P_SHIFT 3
mbed_official 68:41613245dfd7 3179 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 68:41613245dfd7 3180 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 68:41613245dfd7 3181 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 68:41613245dfd7 3182 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 68:41613245dfd7 3183
mbed_official 68:41613245dfd7 3184 /**
mbed_official 68:41613245dfd7 3185 * @}
mbed_official 68:41613245dfd7 3186 */ /* end of group OSC_Register_Masks */
mbed_official 68:41613245dfd7 3187
mbed_official 68:41613245dfd7 3188
mbed_official 68:41613245dfd7 3189 /* OSC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3190 /** Peripheral OSC0 base address */
mbed_official 68:41613245dfd7 3191 #define OSC0_BASE (0x40065000u)
mbed_official 68:41613245dfd7 3192 /** Peripheral OSC0 base pointer */
mbed_official 68:41613245dfd7 3193 #define OSC0 ((OSC_Type *)OSC0_BASE)
mbed_official 68:41613245dfd7 3194
mbed_official 68:41613245dfd7 3195 /**
mbed_official 68:41613245dfd7 3196 * @}
mbed_official 68:41613245dfd7 3197 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3198
mbed_official 68:41613245dfd7 3199
mbed_official 68:41613245dfd7 3200 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3201 -- PDB Peripheral Access Layer
mbed_official 68:41613245dfd7 3202 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3203
mbed_official 68:41613245dfd7 3204 /**
mbed_official 68:41613245dfd7 3205 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
mbed_official 68:41613245dfd7 3206 * @{
mbed_official 68:41613245dfd7 3207 */
mbed_official 68:41613245dfd7 3208
mbed_official 68:41613245dfd7 3209 /** PDB - Register Layout Typedef */
mbed_official 68:41613245dfd7 3210 typedef struct {
mbed_official 68:41613245dfd7 3211 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 3212 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
mbed_official 68:41613245dfd7 3213 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
mbed_official 68:41613245dfd7 3214 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
mbed_official 68:41613245dfd7 3215 struct { /* offset: 0x10, array step: 0x10 */
mbed_official 68:41613245dfd7 3216 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
mbed_official 68:41613245dfd7 3217 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
mbed_official 68:41613245dfd7 3218 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
mbed_official 68:41613245dfd7 3219 } CH[1];
mbed_official 68:41613245dfd7 3220 uint8_t RESERVED_0[368];
mbed_official 68:41613245dfd7 3221 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
mbed_official 68:41613245dfd7 3222 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
mbed_official 68:41613245dfd7 3223 } PDB_Type;
mbed_official 68:41613245dfd7 3224
mbed_official 68:41613245dfd7 3225 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3226 -- PDB Register Masks
mbed_official 68:41613245dfd7 3227 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3228
mbed_official 68:41613245dfd7 3229 /**
mbed_official 68:41613245dfd7 3230 * @addtogroup PDB_Register_Masks PDB Register Masks
mbed_official 68:41613245dfd7 3231 * @{
mbed_official 68:41613245dfd7 3232 */
mbed_official 68:41613245dfd7 3233
mbed_official 68:41613245dfd7 3234 /* SC Bit Fields */
mbed_official 68:41613245dfd7 3235 #define PDB_SC_LDOK_MASK 0x1u
mbed_official 68:41613245dfd7 3236 #define PDB_SC_LDOK_SHIFT 0
mbed_official 68:41613245dfd7 3237 #define PDB_SC_CONT_MASK 0x2u
mbed_official 68:41613245dfd7 3238 #define PDB_SC_CONT_SHIFT 1
mbed_official 68:41613245dfd7 3239 #define PDB_SC_MULT_MASK 0xCu
mbed_official 68:41613245dfd7 3240 #define PDB_SC_MULT_SHIFT 2
mbed_official 68:41613245dfd7 3241 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
mbed_official 68:41613245dfd7 3242 #define PDB_SC_PDBIE_MASK 0x20u
mbed_official 68:41613245dfd7 3243 #define PDB_SC_PDBIE_SHIFT 5
mbed_official 68:41613245dfd7 3244 #define PDB_SC_PDBIF_MASK 0x40u
mbed_official 68:41613245dfd7 3245 #define PDB_SC_PDBIF_SHIFT 6
mbed_official 68:41613245dfd7 3246 #define PDB_SC_PDBEN_MASK 0x80u
mbed_official 68:41613245dfd7 3247 #define PDB_SC_PDBEN_SHIFT 7
mbed_official 68:41613245dfd7 3248 #define PDB_SC_TRGSEL_MASK 0xF00u
mbed_official 68:41613245dfd7 3249 #define PDB_SC_TRGSEL_SHIFT 8
mbed_official 68:41613245dfd7 3250 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
mbed_official 68:41613245dfd7 3251 #define PDB_SC_PRESCALER_MASK 0x7000u
mbed_official 68:41613245dfd7 3252 #define PDB_SC_PRESCALER_SHIFT 12
mbed_official 68:41613245dfd7 3253 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
mbed_official 68:41613245dfd7 3254 #define PDB_SC_DMAEN_MASK 0x8000u
mbed_official 68:41613245dfd7 3255 #define PDB_SC_DMAEN_SHIFT 15
mbed_official 68:41613245dfd7 3256 #define PDB_SC_SWTRIG_MASK 0x10000u
mbed_official 68:41613245dfd7 3257 #define PDB_SC_SWTRIG_SHIFT 16
mbed_official 68:41613245dfd7 3258 #define PDB_SC_PDBEIE_MASK 0x20000u
mbed_official 68:41613245dfd7 3259 #define PDB_SC_PDBEIE_SHIFT 17
mbed_official 68:41613245dfd7 3260 #define PDB_SC_LDMOD_MASK 0xC0000u
mbed_official 68:41613245dfd7 3261 #define PDB_SC_LDMOD_SHIFT 18
mbed_official 68:41613245dfd7 3262 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
mbed_official 68:41613245dfd7 3263 /* MOD Bit Fields */
mbed_official 68:41613245dfd7 3264 #define PDB_MOD_MOD_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3265 #define PDB_MOD_MOD_SHIFT 0
mbed_official 68:41613245dfd7 3266 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
mbed_official 68:41613245dfd7 3267 /* CNT Bit Fields */
mbed_official 68:41613245dfd7 3268 #define PDB_CNT_CNT_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3269 #define PDB_CNT_CNT_SHIFT 0
mbed_official 68:41613245dfd7 3270 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
mbed_official 68:41613245dfd7 3271 /* IDLY Bit Fields */
mbed_official 68:41613245dfd7 3272 #define PDB_IDLY_IDLY_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3273 #define PDB_IDLY_IDLY_SHIFT 0
mbed_official 68:41613245dfd7 3274 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
mbed_official 68:41613245dfd7 3275 /* C1 Bit Fields */
mbed_official 68:41613245dfd7 3276 #define PDB_C1_EN_MASK 0xFFu
mbed_official 68:41613245dfd7 3277 #define PDB_C1_EN_SHIFT 0
mbed_official 68:41613245dfd7 3278 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
mbed_official 68:41613245dfd7 3279 #define PDB_C1_TOS_MASK 0xFF00u
mbed_official 68:41613245dfd7 3280 #define PDB_C1_TOS_SHIFT 8
mbed_official 68:41613245dfd7 3281 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
mbed_official 68:41613245dfd7 3282 #define PDB_C1_BB_MASK 0xFF0000u
mbed_official 68:41613245dfd7 3283 #define PDB_C1_BB_SHIFT 16
mbed_official 68:41613245dfd7 3284 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
mbed_official 68:41613245dfd7 3285 /* S Bit Fields */
mbed_official 68:41613245dfd7 3286 #define PDB_S_ERR_MASK 0xFFu
mbed_official 68:41613245dfd7 3287 #define PDB_S_ERR_SHIFT 0
mbed_official 68:41613245dfd7 3288 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
mbed_official 68:41613245dfd7 3289 #define PDB_S_CF_MASK 0xFF0000u
mbed_official 68:41613245dfd7 3290 #define PDB_S_CF_SHIFT 16
mbed_official 68:41613245dfd7 3291 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
mbed_official 68:41613245dfd7 3292 /* DLY Bit Fields */
mbed_official 68:41613245dfd7 3293 #define PDB_DLY_DLY_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3294 #define PDB_DLY_DLY_SHIFT 0
mbed_official 68:41613245dfd7 3295 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
mbed_official 68:41613245dfd7 3296 /* POEN Bit Fields */
mbed_official 68:41613245dfd7 3297 #define PDB_POEN_POEN_MASK 0xFFu
mbed_official 68:41613245dfd7 3298 #define PDB_POEN_POEN_SHIFT 0
mbed_official 68:41613245dfd7 3299 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
mbed_official 68:41613245dfd7 3300 /* PODLY Bit Fields */
mbed_official 68:41613245dfd7 3301 #define PDB_PODLY_DLY2_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3302 #define PDB_PODLY_DLY2_SHIFT 0
mbed_official 68:41613245dfd7 3303 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
mbed_official 68:41613245dfd7 3304 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 3305 #define PDB_PODLY_DLY1_SHIFT 16
mbed_official 68:41613245dfd7 3306 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
mbed_official 68:41613245dfd7 3307
mbed_official 68:41613245dfd7 3308 /**
mbed_official 68:41613245dfd7 3309 * @}
mbed_official 68:41613245dfd7 3310 */ /* end of group PDB_Register_Masks */
mbed_official 68:41613245dfd7 3311
mbed_official 68:41613245dfd7 3312
mbed_official 68:41613245dfd7 3313 /* PDB - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3314 /** Peripheral PDB0 base address */
mbed_official 68:41613245dfd7 3315 #define PDB0_BASE (0x40036000u)
mbed_official 68:41613245dfd7 3316 /** Peripheral PDB0 base pointer */
mbed_official 68:41613245dfd7 3317 #define PDB0 ((PDB_Type *)PDB0_BASE)
mbed_official 68:41613245dfd7 3318
mbed_official 68:41613245dfd7 3319 /**
mbed_official 68:41613245dfd7 3320 * @}
mbed_official 68:41613245dfd7 3321 */ /* end of group PDB_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3322
mbed_official 68:41613245dfd7 3323
mbed_official 68:41613245dfd7 3324 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3325 -- PIT Peripheral Access Layer
mbed_official 68:41613245dfd7 3326 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3327
mbed_official 68:41613245dfd7 3328 /**
mbed_official 68:41613245dfd7 3329 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 68:41613245dfd7 3330 * @{
mbed_official 68:41613245dfd7 3331 */
mbed_official 68:41613245dfd7 3332
mbed_official 68:41613245dfd7 3333 /** PIT - Register Layout Typedef */
mbed_official 68:41613245dfd7 3334 typedef struct {
mbed_official 68:41613245dfd7 3335 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 3336 uint8_t RESERVED_0[252];
mbed_official 68:41613245dfd7 3337 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 68:41613245dfd7 3338 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 68:41613245dfd7 3339 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 68:41613245dfd7 3340 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 68:41613245dfd7 3341 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 68:41613245dfd7 3342 } CHANNEL[4];
mbed_official 68:41613245dfd7 3343 } PIT_Type;
mbed_official 68:41613245dfd7 3344
mbed_official 68:41613245dfd7 3345 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3346 -- PIT Register Masks
mbed_official 68:41613245dfd7 3347 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3348
mbed_official 68:41613245dfd7 3349 /**
mbed_official 68:41613245dfd7 3350 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 68:41613245dfd7 3351 * @{
mbed_official 68:41613245dfd7 3352 */
mbed_official 68:41613245dfd7 3353
mbed_official 68:41613245dfd7 3354 /* MCR Bit Fields */
mbed_official 68:41613245dfd7 3355 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 68:41613245dfd7 3356 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 68:41613245dfd7 3357 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 68:41613245dfd7 3358 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 68:41613245dfd7 3359 /* LDVAL Bit Fields */
mbed_official 68:41613245dfd7 3360 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 3361 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 68:41613245dfd7 3362 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 68:41613245dfd7 3363 /* CVAL Bit Fields */
mbed_official 68:41613245dfd7 3364 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 3365 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 68:41613245dfd7 3366 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 68:41613245dfd7 3367 /* TCTRL Bit Fields */
mbed_official 68:41613245dfd7 3368 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 68:41613245dfd7 3369 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 68:41613245dfd7 3370 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 68:41613245dfd7 3371 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 68:41613245dfd7 3372 /* TFLG Bit Fields */
mbed_official 68:41613245dfd7 3373 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 68:41613245dfd7 3374 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 68:41613245dfd7 3375
mbed_official 68:41613245dfd7 3376 /**
mbed_official 68:41613245dfd7 3377 * @}
mbed_official 68:41613245dfd7 3378 */ /* end of group PIT_Register_Masks */
mbed_official 68:41613245dfd7 3379
mbed_official 68:41613245dfd7 3380
mbed_official 68:41613245dfd7 3381 /* PIT - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3382 /** Peripheral PIT base address */
mbed_official 68:41613245dfd7 3383 #define PIT_BASE (0x40037000u)
mbed_official 68:41613245dfd7 3384 /** Peripheral PIT base pointer */
mbed_official 68:41613245dfd7 3385 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 68:41613245dfd7 3386
mbed_official 68:41613245dfd7 3387 /**
mbed_official 68:41613245dfd7 3388 * @}
mbed_official 68:41613245dfd7 3389 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3390
mbed_official 68:41613245dfd7 3391
mbed_official 68:41613245dfd7 3392 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3393 -- PMC Peripheral Access Layer
mbed_official 68:41613245dfd7 3394 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3395
mbed_official 68:41613245dfd7 3396 /**
mbed_official 68:41613245dfd7 3397 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 68:41613245dfd7 3398 * @{
mbed_official 68:41613245dfd7 3399 */
mbed_official 68:41613245dfd7 3400
mbed_official 68:41613245dfd7 3401 /** PMC - Register Layout Typedef */
mbed_official 68:41613245dfd7 3402 typedef struct {
mbed_official 68:41613245dfd7 3403 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
mbed_official 68:41613245dfd7 3404 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
mbed_official 68:41613245dfd7 3405 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
mbed_official 68:41613245dfd7 3406 } PMC_Type;
mbed_official 68:41613245dfd7 3407
mbed_official 68:41613245dfd7 3408 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3409 -- PMC Register Masks
mbed_official 68:41613245dfd7 3410 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3411
mbed_official 68:41613245dfd7 3412 /**
mbed_official 68:41613245dfd7 3413 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 68:41613245dfd7 3414 * @{
mbed_official 68:41613245dfd7 3415 */
mbed_official 68:41613245dfd7 3416
mbed_official 68:41613245dfd7 3417 /* LVDSC1 Bit Fields */
mbed_official 68:41613245dfd7 3418 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 68:41613245dfd7 3419 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 68:41613245dfd7 3420 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 68:41613245dfd7 3421 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 68:41613245dfd7 3422 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 68:41613245dfd7 3423 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 68:41613245dfd7 3424 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 68:41613245dfd7 3425 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 68:41613245dfd7 3426 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 68:41613245dfd7 3427 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 68:41613245dfd7 3428 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 68:41613245dfd7 3429 /* LVDSC2 Bit Fields */
mbed_official 68:41613245dfd7 3430 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 68:41613245dfd7 3431 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 68:41613245dfd7 3432 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 68:41613245dfd7 3433 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 68:41613245dfd7 3434 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 68:41613245dfd7 3435 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 68:41613245dfd7 3436 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 68:41613245dfd7 3437 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 68:41613245dfd7 3438 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 68:41613245dfd7 3439 /* REGSC Bit Fields */
mbed_official 68:41613245dfd7 3440 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 68:41613245dfd7 3441 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 68:41613245dfd7 3442 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 68:41613245dfd7 3443 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 68:41613245dfd7 3444 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 68:41613245dfd7 3445 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 68:41613245dfd7 3446
mbed_official 68:41613245dfd7 3447 /**
mbed_official 68:41613245dfd7 3448 * @}
mbed_official 68:41613245dfd7 3449 */ /* end of group PMC_Register_Masks */
mbed_official 68:41613245dfd7 3450
mbed_official 68:41613245dfd7 3451
mbed_official 68:41613245dfd7 3452 /* PMC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3453 /** Peripheral PMC base address */
mbed_official 68:41613245dfd7 3454 #define PMC_BASE (0x4007D000u)
mbed_official 68:41613245dfd7 3455 /** Peripheral PMC base pointer */
mbed_official 68:41613245dfd7 3456 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 68:41613245dfd7 3457
mbed_official 68:41613245dfd7 3458 /**
mbed_official 68:41613245dfd7 3459 * @}
mbed_official 68:41613245dfd7 3460 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3461
mbed_official 68:41613245dfd7 3462
mbed_official 68:41613245dfd7 3463 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3464 -- PORT Peripheral Access Layer
mbed_official 68:41613245dfd7 3465 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3466
mbed_official 68:41613245dfd7 3467 /**
mbed_official 68:41613245dfd7 3468 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 68:41613245dfd7 3469 * @{
mbed_official 68:41613245dfd7 3470 */
mbed_official 68:41613245dfd7 3471
mbed_official 68:41613245dfd7 3472 /** PORT - Register Layout Typedef */
mbed_official 68:41613245dfd7 3473 typedef struct {
mbed_official 68:41613245dfd7 3474 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 68:41613245dfd7 3475 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 68:41613245dfd7 3476 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 68:41613245dfd7 3477 uint8_t RESERVED_0[24];
mbed_official 68:41613245dfd7 3478 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 68:41613245dfd7 3479 uint8_t RESERVED_1[28];
mbed_official 68:41613245dfd7 3480 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
mbed_official 68:41613245dfd7 3481 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
mbed_official 68:41613245dfd7 3482 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
mbed_official 68:41613245dfd7 3483 } PORT_Type;
mbed_official 68:41613245dfd7 3484
mbed_official 68:41613245dfd7 3485 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3486 -- PORT Register Masks
mbed_official 68:41613245dfd7 3487 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3488
mbed_official 68:41613245dfd7 3489 /**
mbed_official 68:41613245dfd7 3490 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 68:41613245dfd7 3491 * @{
mbed_official 68:41613245dfd7 3492 */
mbed_official 68:41613245dfd7 3493
mbed_official 68:41613245dfd7 3494 /* PCR Bit Fields */
mbed_official 68:41613245dfd7 3495 #define PORT_PCR_PS_MASK 0x1u
mbed_official 68:41613245dfd7 3496 #define PORT_PCR_PS_SHIFT 0
mbed_official 68:41613245dfd7 3497 #define PORT_PCR_PE_MASK 0x2u
mbed_official 68:41613245dfd7 3498 #define PORT_PCR_PE_SHIFT 1
mbed_official 68:41613245dfd7 3499 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 68:41613245dfd7 3500 #define PORT_PCR_SRE_SHIFT 2
mbed_official 68:41613245dfd7 3501 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 68:41613245dfd7 3502 #define PORT_PCR_PFE_SHIFT 4
mbed_official 68:41613245dfd7 3503 #define PORT_PCR_ODE_MASK 0x20u
mbed_official 68:41613245dfd7 3504 #define PORT_PCR_ODE_SHIFT 5
mbed_official 68:41613245dfd7 3505 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 68:41613245dfd7 3506 #define PORT_PCR_DSE_SHIFT 6
mbed_official 68:41613245dfd7 3507 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 68:41613245dfd7 3508 #define PORT_PCR_MUX_SHIFT 8
mbed_official 68:41613245dfd7 3509 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 68:41613245dfd7 3510 #define PORT_PCR_LK_MASK 0x8000u
mbed_official 68:41613245dfd7 3511 #define PORT_PCR_LK_SHIFT 15
mbed_official 68:41613245dfd7 3512 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 68:41613245dfd7 3513 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 68:41613245dfd7 3514 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 68:41613245dfd7 3515 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 68:41613245dfd7 3516 #define PORT_PCR_ISF_SHIFT 24
mbed_official 68:41613245dfd7 3517 /* GPCLR Bit Fields */
mbed_official 68:41613245dfd7 3518 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3519 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 68:41613245dfd7 3520 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 68:41613245dfd7 3521 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 3522 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 68:41613245dfd7 3523 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 68:41613245dfd7 3524 /* GPCHR Bit Fields */
mbed_official 68:41613245dfd7 3525 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3526 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 68:41613245dfd7 3527 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 68:41613245dfd7 3528 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 3529 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 68:41613245dfd7 3530 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 68:41613245dfd7 3531 /* ISFR Bit Fields */
mbed_official 68:41613245dfd7 3532 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 3533 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 68:41613245dfd7 3534 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 68:41613245dfd7 3535 /* DFER Bit Fields */
mbed_official 68:41613245dfd7 3536 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 3537 #define PORT_DFER_DFE_SHIFT 0
mbed_official 68:41613245dfd7 3538 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
mbed_official 68:41613245dfd7 3539 /* DFCR Bit Fields */
mbed_official 68:41613245dfd7 3540 #define PORT_DFCR_CS_MASK 0x1u
mbed_official 68:41613245dfd7 3541 #define PORT_DFCR_CS_SHIFT 0
mbed_official 68:41613245dfd7 3542 /* DFWR Bit Fields */
mbed_official 68:41613245dfd7 3543 #define PORT_DFWR_FILT_MASK 0x1Fu
mbed_official 68:41613245dfd7 3544 #define PORT_DFWR_FILT_SHIFT 0
mbed_official 68:41613245dfd7 3545 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
mbed_official 68:41613245dfd7 3546
mbed_official 68:41613245dfd7 3547 /**
mbed_official 68:41613245dfd7 3548 * @}
mbed_official 68:41613245dfd7 3549 */ /* end of group PORT_Register_Masks */
mbed_official 68:41613245dfd7 3550
mbed_official 68:41613245dfd7 3551
mbed_official 68:41613245dfd7 3552 /* PORT - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3553 /** Peripheral PORTA base address */
mbed_official 68:41613245dfd7 3554 #define PORTA_BASE (0x40049000u)
mbed_official 68:41613245dfd7 3555 /** Peripheral PORTA base pointer */
mbed_official 68:41613245dfd7 3556 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 68:41613245dfd7 3557 /** Peripheral PORTB base address */
mbed_official 68:41613245dfd7 3558 #define PORTB_BASE (0x4004A000u)
mbed_official 68:41613245dfd7 3559 /** Peripheral PORTB base pointer */
mbed_official 68:41613245dfd7 3560 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 68:41613245dfd7 3561 /** Peripheral PORTC base address */
mbed_official 68:41613245dfd7 3562 #define PORTC_BASE (0x4004B000u)
mbed_official 68:41613245dfd7 3563 /** Peripheral PORTC base pointer */
mbed_official 68:41613245dfd7 3564 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 68:41613245dfd7 3565 /** Peripheral PORTD base address */
mbed_official 68:41613245dfd7 3566 #define PORTD_BASE (0x4004C000u)
mbed_official 68:41613245dfd7 3567 /** Peripheral PORTD base pointer */
mbed_official 68:41613245dfd7 3568 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 68:41613245dfd7 3569 /** Peripheral PORTE base address */
mbed_official 68:41613245dfd7 3570 #define PORTE_BASE (0x4004D000u)
mbed_official 68:41613245dfd7 3571 /** Peripheral PORTE base pointer */
mbed_official 68:41613245dfd7 3572 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 68:41613245dfd7 3573
mbed_official 68:41613245dfd7 3574 /**
mbed_official 68:41613245dfd7 3575 * @}
mbed_official 68:41613245dfd7 3576 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3577
mbed_official 68:41613245dfd7 3578
mbed_official 68:41613245dfd7 3579 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3580 -- RCM Peripheral Access Layer
mbed_official 68:41613245dfd7 3581 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3582
mbed_official 68:41613245dfd7 3583 /**
mbed_official 68:41613245dfd7 3584 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 68:41613245dfd7 3585 * @{
mbed_official 68:41613245dfd7 3586 */
mbed_official 68:41613245dfd7 3587
mbed_official 68:41613245dfd7 3588 /** RCM - Register Layout Typedef */
mbed_official 68:41613245dfd7 3589 typedef struct {
mbed_official 68:41613245dfd7 3590 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 68:41613245dfd7 3591 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 68:41613245dfd7 3592 uint8_t RESERVED_0[2];
mbed_official 68:41613245dfd7 3593 __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
mbed_official 68:41613245dfd7 3594 __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
mbed_official 68:41613245dfd7 3595 uint8_t RESERVED_1[1];
mbed_official 68:41613245dfd7 3596 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
mbed_official 68:41613245dfd7 3597 } RCM_Type;
mbed_official 68:41613245dfd7 3598
mbed_official 68:41613245dfd7 3599 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3600 -- RCM Register Masks
mbed_official 68:41613245dfd7 3601 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3602
mbed_official 68:41613245dfd7 3603 /**
mbed_official 68:41613245dfd7 3604 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 68:41613245dfd7 3605 * @{
mbed_official 68:41613245dfd7 3606 */
mbed_official 68:41613245dfd7 3607
mbed_official 68:41613245dfd7 3608 /* SRS0 Bit Fields */
mbed_official 68:41613245dfd7 3609 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 68:41613245dfd7 3610 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 68:41613245dfd7 3611 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 68:41613245dfd7 3612 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 68:41613245dfd7 3613 #define RCM_SRS0_LOC_MASK 0x4u
mbed_official 68:41613245dfd7 3614 #define RCM_SRS0_LOC_SHIFT 2
mbed_official 68:41613245dfd7 3615 #define RCM_SRS0_LOL_MASK 0x8u
mbed_official 68:41613245dfd7 3616 #define RCM_SRS0_LOL_SHIFT 3
mbed_official 68:41613245dfd7 3617 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 68:41613245dfd7 3618 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 68:41613245dfd7 3619 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 68:41613245dfd7 3620 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 68:41613245dfd7 3621 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 68:41613245dfd7 3622 #define RCM_SRS0_POR_SHIFT 7
mbed_official 68:41613245dfd7 3623 /* SRS1 Bit Fields */
mbed_official 68:41613245dfd7 3624 #define RCM_SRS1_JTAG_MASK 0x1u
mbed_official 68:41613245dfd7 3625 #define RCM_SRS1_JTAG_SHIFT 0
mbed_official 68:41613245dfd7 3626 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 68:41613245dfd7 3627 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 68:41613245dfd7 3628 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 68:41613245dfd7 3629 #define RCM_SRS1_SW_SHIFT 2
mbed_official 68:41613245dfd7 3630 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 68:41613245dfd7 3631 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 68:41613245dfd7 3632 #define RCM_SRS1_EZPT_MASK 0x10u
mbed_official 68:41613245dfd7 3633 #define RCM_SRS1_EZPT_SHIFT 4
mbed_official 68:41613245dfd7 3634 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 68:41613245dfd7 3635 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 68:41613245dfd7 3636 /* RPFC Bit Fields */
mbed_official 68:41613245dfd7 3637 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 68:41613245dfd7 3638 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 68:41613245dfd7 3639 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 68:41613245dfd7 3640 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 68:41613245dfd7 3641 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 68:41613245dfd7 3642 /* RPFW Bit Fields */
mbed_official 68:41613245dfd7 3643 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 68:41613245dfd7 3644 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 68:41613245dfd7 3645 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 68:41613245dfd7 3646 /* MR Bit Fields */
mbed_official 68:41613245dfd7 3647 #define RCM_MR_EZP_MS_MASK 0x2u
mbed_official 68:41613245dfd7 3648 #define RCM_MR_EZP_MS_SHIFT 1
mbed_official 68:41613245dfd7 3649
mbed_official 68:41613245dfd7 3650 /**
mbed_official 68:41613245dfd7 3651 * @}
mbed_official 68:41613245dfd7 3652 */ /* end of group RCM_Register_Masks */
mbed_official 68:41613245dfd7 3653
mbed_official 68:41613245dfd7 3654
mbed_official 68:41613245dfd7 3655 /* RCM - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3656 /** Peripheral RCM base address */
mbed_official 68:41613245dfd7 3657 #define RCM_BASE (0x4007F000u)
mbed_official 68:41613245dfd7 3658 /** Peripheral RCM base pointer */
mbed_official 68:41613245dfd7 3659 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 68:41613245dfd7 3660
mbed_official 68:41613245dfd7 3661 /**
mbed_official 68:41613245dfd7 3662 * @}
mbed_official 68:41613245dfd7 3663 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3664
mbed_official 68:41613245dfd7 3665
mbed_official 68:41613245dfd7 3666 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3667 -- RFSYS Peripheral Access Layer
mbed_official 68:41613245dfd7 3668 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3669
mbed_official 68:41613245dfd7 3670 /**
mbed_official 68:41613245dfd7 3671 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
mbed_official 68:41613245dfd7 3672 * @{
mbed_official 68:41613245dfd7 3673 */
mbed_official 68:41613245dfd7 3674
mbed_official 68:41613245dfd7 3675 /** RFSYS - Register Layout Typedef */
mbed_official 68:41613245dfd7 3676 typedef struct {
mbed_official 68:41613245dfd7 3677 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
mbed_official 68:41613245dfd7 3678 } RFSYS_Type;
mbed_official 68:41613245dfd7 3679
mbed_official 68:41613245dfd7 3680 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3681 -- RFSYS Register Masks
mbed_official 68:41613245dfd7 3682 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3683
mbed_official 68:41613245dfd7 3684 /**
mbed_official 68:41613245dfd7 3685 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
mbed_official 68:41613245dfd7 3686 * @{
mbed_official 68:41613245dfd7 3687 */
mbed_official 68:41613245dfd7 3688
mbed_official 68:41613245dfd7 3689 /* REG Bit Fields */
mbed_official 68:41613245dfd7 3690 #define RFSYS_REG_LL_MASK 0xFFu
mbed_official 68:41613245dfd7 3691 #define RFSYS_REG_LL_SHIFT 0
mbed_official 68:41613245dfd7 3692 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
mbed_official 68:41613245dfd7 3693 #define RFSYS_REG_LH_MASK 0xFF00u
mbed_official 68:41613245dfd7 3694 #define RFSYS_REG_LH_SHIFT 8
mbed_official 68:41613245dfd7 3695 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
mbed_official 68:41613245dfd7 3696 #define RFSYS_REG_HL_MASK 0xFF0000u
mbed_official 68:41613245dfd7 3697 #define RFSYS_REG_HL_SHIFT 16
mbed_official 68:41613245dfd7 3698 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
mbed_official 68:41613245dfd7 3699 #define RFSYS_REG_HH_MASK 0xFF000000u
mbed_official 68:41613245dfd7 3700 #define RFSYS_REG_HH_SHIFT 24
mbed_official 68:41613245dfd7 3701 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
mbed_official 68:41613245dfd7 3702
mbed_official 68:41613245dfd7 3703 /**
mbed_official 68:41613245dfd7 3704 * @}
mbed_official 68:41613245dfd7 3705 */ /* end of group RFSYS_Register_Masks */
mbed_official 68:41613245dfd7 3706
mbed_official 68:41613245dfd7 3707
mbed_official 68:41613245dfd7 3708 /* RFSYS - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3709 /** Peripheral RFSYS base address */
mbed_official 68:41613245dfd7 3710 #define RFSYS_BASE (0x40041000u)
mbed_official 68:41613245dfd7 3711 /** Peripheral RFSYS base pointer */
mbed_official 68:41613245dfd7 3712 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
mbed_official 68:41613245dfd7 3713
mbed_official 68:41613245dfd7 3714 /**
mbed_official 68:41613245dfd7 3715 * @}
mbed_official 68:41613245dfd7 3716 */ /* end of group RFSYS_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3717
mbed_official 68:41613245dfd7 3718
mbed_official 68:41613245dfd7 3719 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3720 -- RFVBAT Peripheral Access Layer
mbed_official 68:41613245dfd7 3721 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3722
mbed_official 68:41613245dfd7 3723 /**
mbed_official 68:41613245dfd7 3724 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
mbed_official 68:41613245dfd7 3725 * @{
mbed_official 68:41613245dfd7 3726 */
mbed_official 68:41613245dfd7 3727
mbed_official 68:41613245dfd7 3728 /** RFVBAT - Register Layout Typedef */
mbed_official 68:41613245dfd7 3729 typedef struct {
mbed_official 68:41613245dfd7 3730 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
mbed_official 68:41613245dfd7 3731 } RFVBAT_Type;
mbed_official 68:41613245dfd7 3732
mbed_official 68:41613245dfd7 3733 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3734 -- RFVBAT Register Masks
mbed_official 68:41613245dfd7 3735 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3736
mbed_official 68:41613245dfd7 3737 /**
mbed_official 68:41613245dfd7 3738 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
mbed_official 68:41613245dfd7 3739 * @{
mbed_official 68:41613245dfd7 3740 */
mbed_official 68:41613245dfd7 3741
mbed_official 68:41613245dfd7 3742 /* REG Bit Fields */
mbed_official 68:41613245dfd7 3743 #define RFVBAT_REG_LL_MASK 0xFFu
mbed_official 68:41613245dfd7 3744 #define RFVBAT_REG_LL_SHIFT 0
mbed_official 68:41613245dfd7 3745 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
mbed_official 68:41613245dfd7 3746 #define RFVBAT_REG_LH_MASK 0xFF00u
mbed_official 68:41613245dfd7 3747 #define RFVBAT_REG_LH_SHIFT 8
mbed_official 68:41613245dfd7 3748 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
mbed_official 68:41613245dfd7 3749 #define RFVBAT_REG_HL_MASK 0xFF0000u
mbed_official 68:41613245dfd7 3750 #define RFVBAT_REG_HL_SHIFT 16
mbed_official 68:41613245dfd7 3751 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
mbed_official 68:41613245dfd7 3752 #define RFVBAT_REG_HH_MASK 0xFF000000u
mbed_official 68:41613245dfd7 3753 #define RFVBAT_REG_HH_SHIFT 24
mbed_official 68:41613245dfd7 3754 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
mbed_official 68:41613245dfd7 3755
mbed_official 68:41613245dfd7 3756 /**
mbed_official 68:41613245dfd7 3757 * @}
mbed_official 68:41613245dfd7 3758 */ /* end of group RFVBAT_Register_Masks */
mbed_official 68:41613245dfd7 3759
mbed_official 68:41613245dfd7 3760
mbed_official 68:41613245dfd7 3761 /* RFVBAT - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3762 /** Peripheral RFVBAT base address */
mbed_official 68:41613245dfd7 3763 #define RFVBAT_BASE (0x4003E000u)
mbed_official 68:41613245dfd7 3764 /** Peripheral RFVBAT base pointer */
mbed_official 68:41613245dfd7 3765 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
mbed_official 68:41613245dfd7 3766
mbed_official 68:41613245dfd7 3767 /**
mbed_official 68:41613245dfd7 3768 * @}
mbed_official 68:41613245dfd7 3769 */ /* end of group RFVBAT_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3770
mbed_official 68:41613245dfd7 3771
mbed_official 68:41613245dfd7 3772 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3773 -- RTC Peripheral Access Layer
mbed_official 68:41613245dfd7 3774 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3775
mbed_official 68:41613245dfd7 3776 /**
mbed_official 68:41613245dfd7 3777 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 68:41613245dfd7 3778 * @{
mbed_official 68:41613245dfd7 3779 */
mbed_official 68:41613245dfd7 3780
mbed_official 68:41613245dfd7 3781 /** RTC - Register Layout Typedef */
mbed_official 68:41613245dfd7 3782 typedef struct {
mbed_official 68:41613245dfd7 3783 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 68:41613245dfd7 3784 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 68:41613245dfd7 3785 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 68:41613245dfd7 3786 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 68:41613245dfd7 3787 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 68:41613245dfd7 3788 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 68:41613245dfd7 3789 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 68:41613245dfd7 3790 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 68:41613245dfd7 3791 uint8_t RESERVED_0[2016];
mbed_official 68:41613245dfd7 3792 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
mbed_official 68:41613245dfd7 3793 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
mbed_official 68:41613245dfd7 3794 } RTC_Type;
mbed_official 68:41613245dfd7 3795
mbed_official 68:41613245dfd7 3796 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3797 -- RTC Register Masks
mbed_official 68:41613245dfd7 3798 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3799
mbed_official 68:41613245dfd7 3800 /**
mbed_official 68:41613245dfd7 3801 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 68:41613245dfd7 3802 * @{
mbed_official 68:41613245dfd7 3803 */
mbed_official 68:41613245dfd7 3804
mbed_official 68:41613245dfd7 3805 /* TSR Bit Fields */
mbed_official 68:41613245dfd7 3806 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 3807 #define RTC_TSR_TSR_SHIFT 0
mbed_official 68:41613245dfd7 3808 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 68:41613245dfd7 3809 /* TPR Bit Fields */
mbed_official 68:41613245dfd7 3810 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 68:41613245dfd7 3811 #define RTC_TPR_TPR_SHIFT 0
mbed_official 68:41613245dfd7 3812 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 68:41613245dfd7 3813 /* TAR Bit Fields */
mbed_official 68:41613245dfd7 3814 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 3815 #define RTC_TAR_TAR_SHIFT 0
mbed_official 68:41613245dfd7 3816 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 68:41613245dfd7 3817 /* TCR Bit Fields */
mbed_official 68:41613245dfd7 3818 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 68:41613245dfd7 3819 #define RTC_TCR_TCR_SHIFT 0
mbed_official 68:41613245dfd7 3820 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 68:41613245dfd7 3821 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 68:41613245dfd7 3822 #define RTC_TCR_CIR_SHIFT 8
mbed_official 68:41613245dfd7 3823 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 68:41613245dfd7 3824 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 68:41613245dfd7 3825 #define RTC_TCR_TCV_SHIFT 16
mbed_official 68:41613245dfd7 3826 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 68:41613245dfd7 3827 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 68:41613245dfd7 3828 #define RTC_TCR_CIC_SHIFT 24
mbed_official 68:41613245dfd7 3829 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 68:41613245dfd7 3830 /* CR Bit Fields */
mbed_official 68:41613245dfd7 3831 #define RTC_CR_SWR_MASK 0x1u
mbed_official 68:41613245dfd7 3832 #define RTC_CR_SWR_SHIFT 0
mbed_official 68:41613245dfd7 3833 #define RTC_CR_WPE_MASK 0x2u
mbed_official 68:41613245dfd7 3834 #define RTC_CR_WPE_SHIFT 1
mbed_official 68:41613245dfd7 3835 #define RTC_CR_SUP_MASK 0x4u
mbed_official 68:41613245dfd7 3836 #define RTC_CR_SUP_SHIFT 2
mbed_official 68:41613245dfd7 3837 #define RTC_CR_UM_MASK 0x8u
mbed_official 68:41613245dfd7 3838 #define RTC_CR_UM_SHIFT 3
mbed_official 68:41613245dfd7 3839 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 68:41613245dfd7 3840 #define RTC_CR_OSCE_SHIFT 8
mbed_official 68:41613245dfd7 3841 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 68:41613245dfd7 3842 #define RTC_CR_CLKO_SHIFT 9
mbed_official 68:41613245dfd7 3843 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 68:41613245dfd7 3844 #define RTC_CR_SC16P_SHIFT 10
mbed_official 68:41613245dfd7 3845 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 68:41613245dfd7 3846 #define RTC_CR_SC8P_SHIFT 11
mbed_official 68:41613245dfd7 3847 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 68:41613245dfd7 3848 #define RTC_CR_SC4P_SHIFT 12
mbed_official 68:41613245dfd7 3849 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 68:41613245dfd7 3850 #define RTC_CR_SC2P_SHIFT 13
mbed_official 68:41613245dfd7 3851 /* SR Bit Fields */
mbed_official 68:41613245dfd7 3852 #define RTC_SR_TIF_MASK 0x1u
mbed_official 68:41613245dfd7 3853 #define RTC_SR_TIF_SHIFT 0
mbed_official 68:41613245dfd7 3854 #define RTC_SR_TOF_MASK 0x2u
mbed_official 68:41613245dfd7 3855 #define RTC_SR_TOF_SHIFT 1
mbed_official 68:41613245dfd7 3856 #define RTC_SR_TAF_MASK 0x4u
mbed_official 68:41613245dfd7 3857 #define RTC_SR_TAF_SHIFT 2
mbed_official 68:41613245dfd7 3858 #define RTC_SR_TCE_MASK 0x10u
mbed_official 68:41613245dfd7 3859 #define RTC_SR_TCE_SHIFT 4
mbed_official 68:41613245dfd7 3860 /* LR Bit Fields */
mbed_official 68:41613245dfd7 3861 #define RTC_LR_TCL_MASK 0x8u
mbed_official 68:41613245dfd7 3862 #define RTC_LR_TCL_SHIFT 3
mbed_official 68:41613245dfd7 3863 #define RTC_LR_CRL_MASK 0x10u
mbed_official 68:41613245dfd7 3864 #define RTC_LR_CRL_SHIFT 4
mbed_official 68:41613245dfd7 3865 #define RTC_LR_SRL_MASK 0x20u
mbed_official 68:41613245dfd7 3866 #define RTC_LR_SRL_SHIFT 5
mbed_official 68:41613245dfd7 3867 #define RTC_LR_LRL_MASK 0x40u
mbed_official 68:41613245dfd7 3868 #define RTC_LR_LRL_SHIFT 6
mbed_official 68:41613245dfd7 3869 /* IER Bit Fields */
mbed_official 68:41613245dfd7 3870 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 68:41613245dfd7 3871 #define RTC_IER_TIIE_SHIFT 0
mbed_official 68:41613245dfd7 3872 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 68:41613245dfd7 3873 #define RTC_IER_TOIE_SHIFT 1
mbed_official 68:41613245dfd7 3874 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 68:41613245dfd7 3875 #define RTC_IER_TAIE_SHIFT 2
mbed_official 68:41613245dfd7 3876 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 68:41613245dfd7 3877 #define RTC_IER_TSIE_SHIFT 4
mbed_official 68:41613245dfd7 3878 /* WAR Bit Fields */
mbed_official 68:41613245dfd7 3879 #define RTC_WAR_TSRW_MASK 0x1u
mbed_official 68:41613245dfd7 3880 #define RTC_WAR_TSRW_SHIFT 0
mbed_official 68:41613245dfd7 3881 #define RTC_WAR_TPRW_MASK 0x2u
mbed_official 68:41613245dfd7 3882 #define RTC_WAR_TPRW_SHIFT 1
mbed_official 68:41613245dfd7 3883 #define RTC_WAR_TARW_MASK 0x4u
mbed_official 68:41613245dfd7 3884 #define RTC_WAR_TARW_SHIFT 2
mbed_official 68:41613245dfd7 3885 #define RTC_WAR_TCRW_MASK 0x8u
mbed_official 68:41613245dfd7 3886 #define RTC_WAR_TCRW_SHIFT 3
mbed_official 68:41613245dfd7 3887 #define RTC_WAR_CRW_MASK 0x10u
mbed_official 68:41613245dfd7 3888 #define RTC_WAR_CRW_SHIFT 4
mbed_official 68:41613245dfd7 3889 #define RTC_WAR_SRW_MASK 0x20u
mbed_official 68:41613245dfd7 3890 #define RTC_WAR_SRW_SHIFT 5
mbed_official 68:41613245dfd7 3891 #define RTC_WAR_LRW_MASK 0x40u
mbed_official 68:41613245dfd7 3892 #define RTC_WAR_LRW_SHIFT 6
mbed_official 68:41613245dfd7 3893 #define RTC_WAR_IERW_MASK 0x80u
mbed_official 68:41613245dfd7 3894 #define RTC_WAR_IERW_SHIFT 7
mbed_official 68:41613245dfd7 3895 /* RAR Bit Fields */
mbed_official 68:41613245dfd7 3896 #define RTC_RAR_TSRR_MASK 0x1u
mbed_official 68:41613245dfd7 3897 #define RTC_RAR_TSRR_SHIFT 0
mbed_official 68:41613245dfd7 3898 #define RTC_RAR_TPRR_MASK 0x2u
mbed_official 68:41613245dfd7 3899 #define RTC_RAR_TPRR_SHIFT 1
mbed_official 68:41613245dfd7 3900 #define RTC_RAR_TARR_MASK 0x4u
mbed_official 68:41613245dfd7 3901 #define RTC_RAR_TARR_SHIFT 2
mbed_official 68:41613245dfd7 3902 #define RTC_RAR_TCRR_MASK 0x8u
mbed_official 68:41613245dfd7 3903 #define RTC_RAR_TCRR_SHIFT 3
mbed_official 68:41613245dfd7 3904 #define RTC_RAR_CRR_MASK 0x10u
mbed_official 68:41613245dfd7 3905 #define RTC_RAR_CRR_SHIFT 4
mbed_official 68:41613245dfd7 3906 #define RTC_RAR_SRR_MASK 0x20u
mbed_official 68:41613245dfd7 3907 #define RTC_RAR_SRR_SHIFT 5
mbed_official 68:41613245dfd7 3908 #define RTC_RAR_LRR_MASK 0x40u
mbed_official 68:41613245dfd7 3909 #define RTC_RAR_LRR_SHIFT 6
mbed_official 68:41613245dfd7 3910 #define RTC_RAR_IERR_MASK 0x80u
mbed_official 68:41613245dfd7 3911 #define RTC_RAR_IERR_SHIFT 7
mbed_official 68:41613245dfd7 3912
mbed_official 68:41613245dfd7 3913 /**
mbed_official 68:41613245dfd7 3914 * @}
mbed_official 68:41613245dfd7 3915 */ /* end of group RTC_Register_Masks */
mbed_official 68:41613245dfd7 3916
mbed_official 68:41613245dfd7 3917
mbed_official 68:41613245dfd7 3918 /* RTC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 3919 /** Peripheral RTC base address */
mbed_official 68:41613245dfd7 3920 #define RTC_BASE (0x4003D000u)
mbed_official 68:41613245dfd7 3921 /** Peripheral RTC base pointer */
mbed_official 68:41613245dfd7 3922 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 68:41613245dfd7 3923
mbed_official 68:41613245dfd7 3924 /**
mbed_official 68:41613245dfd7 3925 * @}
mbed_official 68:41613245dfd7 3926 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 3927
mbed_official 68:41613245dfd7 3928
mbed_official 68:41613245dfd7 3929 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3930 -- SIM Peripheral Access Layer
mbed_official 68:41613245dfd7 3931 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3932
mbed_official 68:41613245dfd7 3933 /**
mbed_official 68:41613245dfd7 3934 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 68:41613245dfd7 3935 * @{
mbed_official 68:41613245dfd7 3936 */
mbed_official 68:41613245dfd7 3937
mbed_official 68:41613245dfd7 3938 /** SIM - Register Layout Typedef */
mbed_official 68:41613245dfd7 3939 typedef struct {
mbed_official 68:41613245dfd7 3940 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 68:41613245dfd7 3941 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 68:41613245dfd7 3942 uint8_t RESERVED_0[4092];
mbed_official 68:41613245dfd7 3943 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 68:41613245dfd7 3944 uint8_t RESERVED_1[4];
mbed_official 68:41613245dfd7 3945 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 68:41613245dfd7 3946 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 68:41613245dfd7 3947 uint8_t RESERVED_2[4];
mbed_official 68:41613245dfd7 3948 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 68:41613245dfd7 3949 uint8_t RESERVED_3[8];
mbed_official 68:41613245dfd7 3950 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 68:41613245dfd7 3951 uint8_t RESERVED_4[12];
mbed_official 68:41613245dfd7 3952 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 68:41613245dfd7 3953 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 68:41613245dfd7 3954 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 68:41613245dfd7 3955 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 68:41613245dfd7 3956 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 68:41613245dfd7 3957 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
mbed_official 68:41613245dfd7 3958 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 68:41613245dfd7 3959 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 68:41613245dfd7 3960 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
mbed_official 68:41613245dfd7 3961 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 68:41613245dfd7 3962 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 68:41613245dfd7 3963 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 68:41613245dfd7 3964 } SIM_Type;
mbed_official 68:41613245dfd7 3965
mbed_official 68:41613245dfd7 3966 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 3967 -- SIM Register Masks
mbed_official 68:41613245dfd7 3968 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 3969
mbed_official 68:41613245dfd7 3970 /**
mbed_official 68:41613245dfd7 3971 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 68:41613245dfd7 3972 * @{
mbed_official 68:41613245dfd7 3973 */
mbed_official 68:41613245dfd7 3974
mbed_official 68:41613245dfd7 3975 /* SOPT1 Bit Fields */
mbed_official 68:41613245dfd7 3976 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
mbed_official 68:41613245dfd7 3977 #define SIM_SOPT1_RAMSIZE_SHIFT 12
mbed_official 68:41613245dfd7 3978 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
mbed_official 68:41613245dfd7 3979 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 68:41613245dfd7 3980 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 68:41613245dfd7 3981 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 68:41613245dfd7 3982 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mbed_official 68:41613245dfd7 3983 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mbed_official 68:41613245dfd7 3984 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mbed_official 68:41613245dfd7 3985 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mbed_official 68:41613245dfd7 3986 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mbed_official 68:41613245dfd7 3987 #define SIM_SOPT1_USBREGEN_SHIFT 31
mbed_official 68:41613245dfd7 3988 /* SOPT1CFG Bit Fields */
mbed_official 68:41613245dfd7 3989 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mbed_official 68:41613245dfd7 3990 #define SIM_SOPT1CFG_URWE_SHIFT 24
mbed_official 68:41613245dfd7 3991 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mbed_official 68:41613245dfd7 3992 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mbed_official 68:41613245dfd7 3993 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mbed_official 68:41613245dfd7 3994 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mbed_official 68:41613245dfd7 3995 /* SOPT2 Bit Fields */
mbed_official 68:41613245dfd7 3996 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 68:41613245dfd7 3997 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 68:41613245dfd7 3998 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 68:41613245dfd7 3999 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 68:41613245dfd7 4000 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 68:41613245dfd7 4001 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
mbed_official 68:41613245dfd7 4002 #define SIM_SOPT2_PTD7PAD_SHIFT 11
mbed_official 68:41613245dfd7 4003 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
mbed_official 68:41613245dfd7 4004 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
mbed_official 68:41613245dfd7 4005 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
mbed_official 68:41613245dfd7 4006 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
mbed_official 68:41613245dfd7 4007 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mbed_official 68:41613245dfd7 4008 #define SIM_SOPT2_USBSRC_SHIFT 18
mbed_official 68:41613245dfd7 4009 /* SOPT4 Bit Fields */
mbed_official 68:41613245dfd7 4010 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
mbed_official 68:41613245dfd7 4011 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
mbed_official 68:41613245dfd7 4012 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
mbed_official 68:41613245dfd7 4013 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
mbed_official 68:41613245dfd7 4014 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
mbed_official 68:41613245dfd7 4015 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
mbed_official 68:41613245dfd7 4016 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
mbed_official 68:41613245dfd7 4017 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
mbed_official 68:41613245dfd7 4018 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
mbed_official 68:41613245dfd7 4019 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
mbed_official 68:41613245dfd7 4020 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
mbed_official 68:41613245dfd7 4021 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
mbed_official 68:41613245dfd7 4022 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
mbed_official 68:41613245dfd7 4023 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
mbed_official 68:41613245dfd7 4024 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
mbed_official 68:41613245dfd7 4025 /* SOPT5 Bit Fields */
mbed_official 68:41613245dfd7 4026 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
mbed_official 68:41613245dfd7 4027 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mbed_official 68:41613245dfd7 4028 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
mbed_official 68:41613245dfd7 4029 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mbed_official 68:41613245dfd7 4030 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
mbed_official 68:41613245dfd7 4031 #define SIM_SOPT5_UART1TXSRC_MASK 0x10u
mbed_official 68:41613245dfd7 4032 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
mbed_official 68:41613245dfd7 4033 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
mbed_official 68:41613245dfd7 4034 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
mbed_official 68:41613245dfd7 4035 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
mbed_official 68:41613245dfd7 4036 /* SOPT7 Bit Fields */
mbed_official 68:41613245dfd7 4037 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 68:41613245dfd7 4038 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 68:41613245dfd7 4039 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 68:41613245dfd7 4040 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 68:41613245dfd7 4041 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 68:41613245dfd7 4042 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 68:41613245dfd7 4043 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 68:41613245dfd7 4044 /* SDID Bit Fields */
mbed_official 68:41613245dfd7 4045 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 68:41613245dfd7 4046 #define SIM_SDID_PINID_SHIFT 0
mbed_official 68:41613245dfd7 4047 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 68:41613245dfd7 4048 #define SIM_SDID_FAMID_MASK 0x70u
mbed_official 68:41613245dfd7 4049 #define SIM_SDID_FAMID_SHIFT 4
mbed_official 68:41613245dfd7 4050 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 68:41613245dfd7 4051 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 68:41613245dfd7 4052 #define SIM_SDID_REVID_SHIFT 12
mbed_official 68:41613245dfd7 4053 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 68:41613245dfd7 4054 /* SCGC4 Bit Fields */
mbed_official 68:41613245dfd7 4055 #define SIM_SCGC4_EWM_MASK 0x2u
mbed_official 68:41613245dfd7 4056 #define SIM_SCGC4_EWM_SHIFT 1
mbed_official 68:41613245dfd7 4057 #define SIM_SCGC4_CMT_MASK 0x4u
mbed_official 68:41613245dfd7 4058 #define SIM_SCGC4_CMT_SHIFT 2
mbed_official 68:41613245dfd7 4059 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 68:41613245dfd7 4060 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 68:41613245dfd7 4061 #define SIM_SCGC4_UART0_MASK 0x400u
mbed_official 68:41613245dfd7 4062 #define SIM_SCGC4_UART0_SHIFT 10
mbed_official 68:41613245dfd7 4063 #define SIM_SCGC4_UART1_MASK 0x800u
mbed_official 68:41613245dfd7 4064 #define SIM_SCGC4_UART1_SHIFT 11
mbed_official 68:41613245dfd7 4065 #define SIM_SCGC4_UART2_MASK 0x1000u
mbed_official 68:41613245dfd7 4066 #define SIM_SCGC4_UART2_SHIFT 12
mbed_official 68:41613245dfd7 4067 #define SIM_SCGC4_USBOTG_MASK 0x40000u
mbed_official 68:41613245dfd7 4068 #define SIM_SCGC4_USBOTG_SHIFT 18
mbed_official 68:41613245dfd7 4069 #define SIM_SCGC4_CMP_MASK 0x80000u
mbed_official 68:41613245dfd7 4070 #define SIM_SCGC4_CMP_SHIFT 19
mbed_official 68:41613245dfd7 4071 #define SIM_SCGC4_VREF_MASK 0x100000u
mbed_official 68:41613245dfd7 4072 #define SIM_SCGC4_VREF_SHIFT 20
mbed_official 68:41613245dfd7 4073 /* SCGC5 Bit Fields */
mbed_official 68:41613245dfd7 4074 #define SIM_SCGC5_LPTIMER_MASK 0x1u
mbed_official 68:41613245dfd7 4075 #define SIM_SCGC5_LPTIMER_SHIFT 0
mbed_official 68:41613245dfd7 4076 #define SIM_SCGC5_TSI_MASK 0x20u
mbed_official 68:41613245dfd7 4077 #define SIM_SCGC5_TSI_SHIFT 5
mbed_official 68:41613245dfd7 4078 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 68:41613245dfd7 4079 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 68:41613245dfd7 4080 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 68:41613245dfd7 4081 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 68:41613245dfd7 4082 #define SIM_SCGC5_PORTC_MASK 0x800u
mbed_official 68:41613245dfd7 4083 #define SIM_SCGC5_PORTC_SHIFT 11
mbed_official 68:41613245dfd7 4084 #define SIM_SCGC5_PORTD_MASK 0x1000u
mbed_official 68:41613245dfd7 4085 #define SIM_SCGC5_PORTD_SHIFT 12
mbed_official 68:41613245dfd7 4086 #define SIM_SCGC5_PORTE_MASK 0x2000u
mbed_official 68:41613245dfd7 4087 #define SIM_SCGC5_PORTE_SHIFT 13
mbed_official 68:41613245dfd7 4088 /* SCGC6 Bit Fields */
mbed_official 68:41613245dfd7 4089 #define SIM_SCGC6_FTFL_MASK 0x1u
mbed_official 68:41613245dfd7 4090 #define SIM_SCGC6_FTFL_SHIFT 0
mbed_official 68:41613245dfd7 4091 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 68:41613245dfd7 4092 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 68:41613245dfd7 4093 #define SIM_SCGC6_SPI0_MASK 0x1000u
mbed_official 68:41613245dfd7 4094 #define SIM_SCGC6_SPI0_SHIFT 12
mbed_official 68:41613245dfd7 4095 #define SIM_SCGC6_I2S_MASK 0x8000u
mbed_official 68:41613245dfd7 4096 #define SIM_SCGC6_I2S_SHIFT 15
mbed_official 68:41613245dfd7 4097 #define SIM_SCGC6_CRC_MASK 0x40000u
mbed_official 68:41613245dfd7 4098 #define SIM_SCGC6_CRC_SHIFT 18
mbed_official 68:41613245dfd7 4099 #define SIM_SCGC6_USBDCD_MASK 0x200000u
mbed_official 68:41613245dfd7 4100 #define SIM_SCGC6_USBDCD_SHIFT 21
mbed_official 68:41613245dfd7 4101 #define SIM_SCGC6_PDB_MASK 0x400000u
mbed_official 68:41613245dfd7 4102 #define SIM_SCGC6_PDB_SHIFT 22
mbed_official 68:41613245dfd7 4103 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 68:41613245dfd7 4104 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 68:41613245dfd7 4105 #define SIM_SCGC6_FTM0_MASK 0x1000000u
mbed_official 68:41613245dfd7 4106 #define SIM_SCGC6_FTM0_SHIFT 24
mbed_official 68:41613245dfd7 4107 #define SIM_SCGC6_FTM1_MASK 0x2000000u
mbed_official 68:41613245dfd7 4108 #define SIM_SCGC6_FTM1_SHIFT 25
mbed_official 68:41613245dfd7 4109 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 68:41613245dfd7 4110 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 68:41613245dfd7 4111 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 68:41613245dfd7 4112 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 68:41613245dfd7 4113 /* SCGC7 Bit Fields */
mbed_official 68:41613245dfd7 4114 #define SIM_SCGC7_DMA_MASK 0x2u
mbed_official 68:41613245dfd7 4115 #define SIM_SCGC7_DMA_SHIFT 1
mbed_official 68:41613245dfd7 4116 /* CLKDIV1 Bit Fields */
mbed_official 68:41613245dfd7 4117 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
mbed_official 68:41613245dfd7 4118 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 68:41613245dfd7 4119 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 68:41613245dfd7 4120 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
mbed_official 68:41613245dfd7 4121 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
mbed_official 68:41613245dfd7 4122 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
mbed_official 68:41613245dfd7 4123 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 68:41613245dfd7 4124 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 68:41613245dfd7 4125 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 68:41613245dfd7 4126 /* CLKDIV2 Bit Fields */
mbed_official 68:41613245dfd7 4127 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
mbed_official 68:41613245dfd7 4128 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
mbed_official 68:41613245dfd7 4129 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
mbed_official 68:41613245dfd7 4130 #define SIM_CLKDIV2_USBDIV_SHIFT 1
mbed_official 68:41613245dfd7 4131 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
mbed_official 68:41613245dfd7 4132 /* FCFG1 Bit Fields */
mbed_official 68:41613245dfd7 4133 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 68:41613245dfd7 4134 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 68:41613245dfd7 4135 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 68:41613245dfd7 4136 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 68:41613245dfd7 4137 #define SIM_FCFG1_DEPART_MASK 0xF00u
mbed_official 68:41613245dfd7 4138 #define SIM_FCFG1_DEPART_SHIFT 8
mbed_official 68:41613245dfd7 4139 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
mbed_official 68:41613245dfd7 4140 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
mbed_official 68:41613245dfd7 4141 #define SIM_FCFG1_EESIZE_SHIFT 16
mbed_official 68:41613245dfd7 4142 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
mbed_official 68:41613245dfd7 4143 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 68:41613245dfd7 4144 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 68:41613245dfd7 4145 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 68:41613245dfd7 4146 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
mbed_official 68:41613245dfd7 4147 #define SIM_FCFG1_NVMSIZE_SHIFT 28
mbed_official 68:41613245dfd7 4148 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
mbed_official 68:41613245dfd7 4149 /* FCFG2 Bit Fields */
mbed_official 68:41613245dfd7 4150 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mbed_official 68:41613245dfd7 4151 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mbed_official 68:41613245dfd7 4152 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mbed_official 68:41613245dfd7 4153 #define SIM_FCFG2_PFLSH_MASK 0x800000u
mbed_official 68:41613245dfd7 4154 #define SIM_FCFG2_PFLSH_SHIFT 23
mbed_official 68:41613245dfd7 4155 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 68:41613245dfd7 4156 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 68:41613245dfd7 4157 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 68:41613245dfd7 4158 /* UIDH Bit Fields */
mbed_official 68:41613245dfd7 4159 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4160 #define SIM_UIDH_UID_SHIFT 0
mbed_official 68:41613245dfd7 4161 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
mbed_official 68:41613245dfd7 4162 /* UIDMH Bit Fields */
mbed_official 68:41613245dfd7 4163 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4164 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 68:41613245dfd7 4165 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 68:41613245dfd7 4166 /* UIDML Bit Fields */
mbed_official 68:41613245dfd7 4167 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4168 #define SIM_UIDML_UID_SHIFT 0
mbed_official 68:41613245dfd7 4169 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 68:41613245dfd7 4170 /* UIDL Bit Fields */
mbed_official 68:41613245dfd7 4171 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4172 #define SIM_UIDL_UID_SHIFT 0
mbed_official 68:41613245dfd7 4173 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 68:41613245dfd7 4174
mbed_official 68:41613245dfd7 4175 /**
mbed_official 68:41613245dfd7 4176 * @}
mbed_official 68:41613245dfd7 4177 */ /* end of group SIM_Register_Masks */
mbed_official 68:41613245dfd7 4178
mbed_official 68:41613245dfd7 4179
mbed_official 68:41613245dfd7 4180 /* SIM - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 4181 /** Peripheral SIM base address */
mbed_official 68:41613245dfd7 4182 #define SIM_BASE (0x40047000u)
mbed_official 68:41613245dfd7 4183 /** Peripheral SIM base pointer */
mbed_official 68:41613245dfd7 4184 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 68:41613245dfd7 4185
mbed_official 68:41613245dfd7 4186 /**
mbed_official 68:41613245dfd7 4187 * @}
mbed_official 68:41613245dfd7 4188 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 4189
mbed_official 68:41613245dfd7 4190
mbed_official 68:41613245dfd7 4191 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4192 -- SMC Peripheral Access Layer
mbed_official 68:41613245dfd7 4193 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4194
mbed_official 68:41613245dfd7 4195 /**
mbed_official 68:41613245dfd7 4196 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 68:41613245dfd7 4197 * @{
mbed_official 68:41613245dfd7 4198 */
mbed_official 68:41613245dfd7 4199
mbed_official 68:41613245dfd7 4200 /** SMC - Register Layout Typedef */
mbed_official 68:41613245dfd7 4201 typedef struct {
mbed_official 68:41613245dfd7 4202 __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
mbed_official 68:41613245dfd7 4203 __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
mbed_official 68:41613245dfd7 4204 __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
mbed_official 68:41613245dfd7 4205 __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
mbed_official 68:41613245dfd7 4206 } SMC_Type;
mbed_official 68:41613245dfd7 4207
mbed_official 68:41613245dfd7 4208 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4209 -- SMC Register Masks
mbed_official 68:41613245dfd7 4210 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4211
mbed_official 68:41613245dfd7 4212 /**
mbed_official 68:41613245dfd7 4213 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 68:41613245dfd7 4214 * @{
mbed_official 68:41613245dfd7 4215 */
mbed_official 68:41613245dfd7 4216
mbed_official 68:41613245dfd7 4217 /* PMPROT Bit Fields */
mbed_official 68:41613245dfd7 4218 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 68:41613245dfd7 4219 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 68:41613245dfd7 4220 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 68:41613245dfd7 4221 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 68:41613245dfd7 4222 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 68:41613245dfd7 4223 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 68:41613245dfd7 4224 /* PMCTRL Bit Fields */
mbed_official 68:41613245dfd7 4225 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 68:41613245dfd7 4226 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 68:41613245dfd7 4227 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 68:41613245dfd7 4228 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 68:41613245dfd7 4229 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 68:41613245dfd7 4230 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 68:41613245dfd7 4231 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 68:41613245dfd7 4232 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 68:41613245dfd7 4233 #define SMC_PMCTRL_LPWUI_MASK 0x80u
mbed_official 68:41613245dfd7 4234 #define SMC_PMCTRL_LPWUI_SHIFT 7
mbed_official 68:41613245dfd7 4235 /* VLLSCTRL Bit Fields */
mbed_official 68:41613245dfd7 4236 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
mbed_official 68:41613245dfd7 4237 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
mbed_official 68:41613245dfd7 4238 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
mbed_official 68:41613245dfd7 4239 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
mbed_official 68:41613245dfd7 4240 #define SMC_VLLSCTRL_PORPO_SHIFT 5
mbed_official 68:41613245dfd7 4241 /* PMSTAT Bit Fields */
mbed_official 68:41613245dfd7 4242 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
mbed_official 68:41613245dfd7 4243 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 68:41613245dfd7 4244 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 68:41613245dfd7 4245
mbed_official 68:41613245dfd7 4246 /**
mbed_official 68:41613245dfd7 4247 * @}
mbed_official 68:41613245dfd7 4248 */ /* end of group SMC_Register_Masks */
mbed_official 68:41613245dfd7 4249
mbed_official 68:41613245dfd7 4250
mbed_official 68:41613245dfd7 4251 /* SMC - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 4252 /** Peripheral SMC base address */
mbed_official 68:41613245dfd7 4253 #define SMC_BASE (0x4007E000u)
mbed_official 68:41613245dfd7 4254 /** Peripheral SMC base pointer */
mbed_official 68:41613245dfd7 4255 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 68:41613245dfd7 4256
mbed_official 68:41613245dfd7 4257 /**
mbed_official 68:41613245dfd7 4258 * @}
mbed_official 68:41613245dfd7 4259 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 4260
mbed_official 68:41613245dfd7 4261
mbed_official 68:41613245dfd7 4262 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4263 -- SPI Peripheral Access Layer
mbed_official 68:41613245dfd7 4264 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4265
mbed_official 68:41613245dfd7 4266 /**
mbed_official 68:41613245dfd7 4267 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 68:41613245dfd7 4268 * @{
mbed_official 68:41613245dfd7 4269 */
mbed_official 68:41613245dfd7 4270
mbed_official 68:41613245dfd7 4271 /** SPI - Register Layout Typedef */
mbed_official 68:41613245dfd7 4272 typedef struct {
mbed_official 68:41613245dfd7 4273 __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
mbed_official 68:41613245dfd7 4274 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 4275 __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
mbed_official 68:41613245dfd7 4276 union { /* offset: 0xC */
mbed_official 68:41613245dfd7 4277 __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
mbed_official 68:41613245dfd7 4278 __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
mbed_official 68:41613245dfd7 4279 };
mbed_official 68:41613245dfd7 4280 uint8_t RESERVED_1[24];
mbed_official 68:41613245dfd7 4281 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
mbed_official 68:41613245dfd7 4282 __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
mbed_official 68:41613245dfd7 4283 union { /* offset: 0x34 */
mbed_official 68:41613245dfd7 4284 __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
mbed_official 68:41613245dfd7 4285 __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
mbed_official 68:41613245dfd7 4286 };
mbed_official 68:41613245dfd7 4287 __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
mbed_official 68:41613245dfd7 4288 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
mbed_official 68:41613245dfd7 4289 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
mbed_official 68:41613245dfd7 4290 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
mbed_official 68:41613245dfd7 4291 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
mbed_official 68:41613245dfd7 4292 uint8_t RESERVED_2[48];
mbed_official 68:41613245dfd7 4293 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
mbed_official 68:41613245dfd7 4294 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
mbed_official 68:41613245dfd7 4295 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
mbed_official 68:41613245dfd7 4296 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
mbed_official 68:41613245dfd7 4297 } SPI_Type;
mbed_official 68:41613245dfd7 4298
mbed_official 68:41613245dfd7 4299 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4300 -- SPI Register Masks
mbed_official 68:41613245dfd7 4301 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4302
mbed_official 68:41613245dfd7 4303 /**
mbed_official 68:41613245dfd7 4304 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 68:41613245dfd7 4305 * @{
mbed_official 68:41613245dfd7 4306 */
mbed_official 68:41613245dfd7 4307
mbed_official 68:41613245dfd7 4308 /* MCR Bit Fields */
mbed_official 68:41613245dfd7 4309 #define SPI_MCR_HALT_MASK 0x1u
mbed_official 68:41613245dfd7 4310 #define SPI_MCR_HALT_SHIFT 0
mbed_official 68:41613245dfd7 4311 #define SPI_MCR_SMPL_PT_MASK 0x300u
mbed_official 68:41613245dfd7 4312 #define SPI_MCR_SMPL_PT_SHIFT 8
mbed_official 68:41613245dfd7 4313 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
mbed_official 68:41613245dfd7 4314 #define SPI_MCR_CLR_RXF_MASK 0x400u
mbed_official 68:41613245dfd7 4315 #define SPI_MCR_CLR_RXF_SHIFT 10
mbed_official 68:41613245dfd7 4316 #define SPI_MCR_CLR_TXF_MASK 0x800u
mbed_official 68:41613245dfd7 4317 #define SPI_MCR_CLR_TXF_SHIFT 11
mbed_official 68:41613245dfd7 4318 #define SPI_MCR_DIS_RXF_MASK 0x1000u
mbed_official 68:41613245dfd7 4319 #define SPI_MCR_DIS_RXF_SHIFT 12
mbed_official 68:41613245dfd7 4320 #define SPI_MCR_DIS_TXF_MASK 0x2000u
mbed_official 68:41613245dfd7 4321 #define SPI_MCR_DIS_TXF_SHIFT 13
mbed_official 68:41613245dfd7 4322 #define SPI_MCR_MDIS_MASK 0x4000u
mbed_official 68:41613245dfd7 4323 #define SPI_MCR_MDIS_SHIFT 14
mbed_official 68:41613245dfd7 4324 #define SPI_MCR_DOZE_MASK 0x8000u
mbed_official 68:41613245dfd7 4325 #define SPI_MCR_DOZE_SHIFT 15
mbed_official 68:41613245dfd7 4326 #define SPI_MCR_PCSIS_MASK 0x3F0000u
mbed_official 68:41613245dfd7 4327 #define SPI_MCR_PCSIS_SHIFT 16
mbed_official 68:41613245dfd7 4328 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
mbed_official 68:41613245dfd7 4329 #define SPI_MCR_ROOE_MASK 0x1000000u
mbed_official 68:41613245dfd7 4330 #define SPI_MCR_ROOE_SHIFT 24
mbed_official 68:41613245dfd7 4331 #define SPI_MCR_PCSSE_MASK 0x2000000u
mbed_official 68:41613245dfd7 4332 #define SPI_MCR_PCSSE_SHIFT 25
mbed_official 68:41613245dfd7 4333 #define SPI_MCR_MTFE_MASK 0x4000000u
mbed_official 68:41613245dfd7 4334 #define SPI_MCR_MTFE_SHIFT 26
mbed_official 68:41613245dfd7 4335 #define SPI_MCR_FRZ_MASK 0x8000000u
mbed_official 68:41613245dfd7 4336 #define SPI_MCR_FRZ_SHIFT 27
mbed_official 68:41613245dfd7 4337 #define SPI_MCR_DCONF_MASK 0x30000000u
mbed_official 68:41613245dfd7 4338 #define SPI_MCR_DCONF_SHIFT 28
mbed_official 68:41613245dfd7 4339 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
mbed_official 68:41613245dfd7 4340 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
mbed_official 68:41613245dfd7 4341 #define SPI_MCR_CONT_SCKE_SHIFT 30
mbed_official 68:41613245dfd7 4342 #define SPI_MCR_MSTR_MASK 0x80000000u
mbed_official 68:41613245dfd7 4343 #define SPI_MCR_MSTR_SHIFT 31
mbed_official 68:41613245dfd7 4344 /* TCR Bit Fields */
mbed_official 68:41613245dfd7 4345 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4346 #define SPI_TCR_SPI_TCNT_SHIFT 16
mbed_official 68:41613245dfd7 4347 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
mbed_official 68:41613245dfd7 4348 /* CTAR Bit Fields */
mbed_official 68:41613245dfd7 4349 #define SPI_CTAR_BR_MASK 0xFu
mbed_official 68:41613245dfd7 4350 #define SPI_CTAR_BR_SHIFT 0
mbed_official 68:41613245dfd7 4351 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
mbed_official 68:41613245dfd7 4352 #define SPI_CTAR_DT_MASK 0xF0u
mbed_official 68:41613245dfd7 4353 #define SPI_CTAR_DT_SHIFT 4
mbed_official 68:41613245dfd7 4354 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
mbed_official 68:41613245dfd7 4355 #define SPI_CTAR_ASC_MASK 0xF00u
mbed_official 68:41613245dfd7 4356 #define SPI_CTAR_ASC_SHIFT 8
mbed_official 68:41613245dfd7 4357 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
mbed_official 68:41613245dfd7 4358 #define SPI_CTAR_CSSCK_MASK 0xF000u
mbed_official 68:41613245dfd7 4359 #define SPI_CTAR_CSSCK_SHIFT 12
mbed_official 68:41613245dfd7 4360 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
mbed_official 68:41613245dfd7 4361 #define SPI_CTAR_PBR_MASK 0x30000u
mbed_official 68:41613245dfd7 4362 #define SPI_CTAR_PBR_SHIFT 16
mbed_official 68:41613245dfd7 4363 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
mbed_official 68:41613245dfd7 4364 #define SPI_CTAR_PDT_MASK 0xC0000u
mbed_official 68:41613245dfd7 4365 #define SPI_CTAR_PDT_SHIFT 18
mbed_official 68:41613245dfd7 4366 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
mbed_official 68:41613245dfd7 4367 #define SPI_CTAR_PASC_MASK 0x300000u
mbed_official 68:41613245dfd7 4368 #define SPI_CTAR_PASC_SHIFT 20
mbed_official 68:41613245dfd7 4369 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
mbed_official 68:41613245dfd7 4370 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
mbed_official 68:41613245dfd7 4371 #define SPI_CTAR_PCSSCK_SHIFT 22
mbed_official 68:41613245dfd7 4372 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
mbed_official 68:41613245dfd7 4373 #define SPI_CTAR_LSBFE_MASK 0x1000000u
mbed_official 68:41613245dfd7 4374 #define SPI_CTAR_LSBFE_SHIFT 24
mbed_official 68:41613245dfd7 4375 #define SPI_CTAR_CPHA_MASK 0x2000000u
mbed_official 68:41613245dfd7 4376 #define SPI_CTAR_CPHA_SHIFT 25
mbed_official 68:41613245dfd7 4377 #define SPI_CTAR_CPOL_MASK 0x4000000u
mbed_official 68:41613245dfd7 4378 #define SPI_CTAR_CPOL_SHIFT 26
mbed_official 68:41613245dfd7 4379 #define SPI_CTAR_FMSZ_MASK 0x78000000u
mbed_official 68:41613245dfd7 4380 #define SPI_CTAR_FMSZ_SHIFT 27
mbed_official 68:41613245dfd7 4381 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
mbed_official 68:41613245dfd7 4382 #define SPI_CTAR_DBR_MASK 0x80000000u
mbed_official 68:41613245dfd7 4383 #define SPI_CTAR_DBR_SHIFT 31
mbed_official 68:41613245dfd7 4384 /* CTAR_SLAVE Bit Fields */
mbed_official 68:41613245dfd7 4385 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
mbed_official 68:41613245dfd7 4386 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
mbed_official 68:41613245dfd7 4387 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
mbed_official 68:41613245dfd7 4388 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
mbed_official 68:41613245dfd7 4389 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
mbed_official 68:41613245dfd7 4390 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
mbed_official 68:41613245dfd7 4391 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
mbed_official 68:41613245dfd7 4392 /* SR Bit Fields */
mbed_official 68:41613245dfd7 4393 #define SPI_SR_POPNXTPTR_MASK 0xFu
mbed_official 68:41613245dfd7 4394 #define SPI_SR_POPNXTPTR_SHIFT 0
mbed_official 68:41613245dfd7 4395 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
mbed_official 68:41613245dfd7 4396 #define SPI_SR_RXCTR_MASK 0xF0u
mbed_official 68:41613245dfd7 4397 #define SPI_SR_RXCTR_SHIFT 4
mbed_official 68:41613245dfd7 4398 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
mbed_official 68:41613245dfd7 4399 #define SPI_SR_TXNXTPTR_MASK 0xF00u
mbed_official 68:41613245dfd7 4400 #define SPI_SR_TXNXTPTR_SHIFT 8
mbed_official 68:41613245dfd7 4401 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
mbed_official 68:41613245dfd7 4402 #define SPI_SR_TXCTR_MASK 0xF000u
mbed_official 68:41613245dfd7 4403 #define SPI_SR_TXCTR_SHIFT 12
mbed_official 68:41613245dfd7 4404 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
mbed_official 68:41613245dfd7 4405 #define SPI_SR_RFDF_MASK 0x20000u
mbed_official 68:41613245dfd7 4406 #define SPI_SR_RFDF_SHIFT 17
mbed_official 68:41613245dfd7 4407 #define SPI_SR_RFOF_MASK 0x80000u
mbed_official 68:41613245dfd7 4408 #define SPI_SR_RFOF_SHIFT 19
mbed_official 68:41613245dfd7 4409 #define SPI_SR_TFFF_MASK 0x2000000u
mbed_official 68:41613245dfd7 4410 #define SPI_SR_TFFF_SHIFT 25
mbed_official 68:41613245dfd7 4411 #define SPI_SR_TFUF_MASK 0x8000000u
mbed_official 68:41613245dfd7 4412 #define SPI_SR_TFUF_SHIFT 27
mbed_official 68:41613245dfd7 4413 #define SPI_SR_EOQF_MASK 0x10000000u
mbed_official 68:41613245dfd7 4414 #define SPI_SR_EOQF_SHIFT 28
mbed_official 68:41613245dfd7 4415 #define SPI_SR_TXRXS_MASK 0x40000000u
mbed_official 68:41613245dfd7 4416 #define SPI_SR_TXRXS_SHIFT 30
mbed_official 68:41613245dfd7 4417 #define SPI_SR_TCF_MASK 0x80000000u
mbed_official 68:41613245dfd7 4418 #define SPI_SR_TCF_SHIFT 31
mbed_official 68:41613245dfd7 4419 /* RSER Bit Fields */
mbed_official 68:41613245dfd7 4420 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
mbed_official 68:41613245dfd7 4421 #define SPI_RSER_RFDF_DIRS_SHIFT 16
mbed_official 68:41613245dfd7 4422 #define SPI_RSER_RFDF_RE_MASK 0x20000u
mbed_official 68:41613245dfd7 4423 #define SPI_RSER_RFDF_RE_SHIFT 17
mbed_official 68:41613245dfd7 4424 #define SPI_RSER_RFOF_RE_MASK 0x80000u
mbed_official 68:41613245dfd7 4425 #define SPI_RSER_RFOF_RE_SHIFT 19
mbed_official 68:41613245dfd7 4426 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
mbed_official 68:41613245dfd7 4427 #define SPI_RSER_TFFF_DIRS_SHIFT 24
mbed_official 68:41613245dfd7 4428 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
mbed_official 68:41613245dfd7 4429 #define SPI_RSER_TFFF_RE_SHIFT 25
mbed_official 68:41613245dfd7 4430 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
mbed_official 68:41613245dfd7 4431 #define SPI_RSER_TFUF_RE_SHIFT 27
mbed_official 68:41613245dfd7 4432 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
mbed_official 68:41613245dfd7 4433 #define SPI_RSER_EOQF_RE_SHIFT 28
mbed_official 68:41613245dfd7 4434 #define SPI_RSER_TCF_RE_MASK 0x80000000u
mbed_official 68:41613245dfd7 4435 #define SPI_RSER_TCF_RE_SHIFT 31
mbed_official 68:41613245dfd7 4436 /* PUSHR Bit Fields */
mbed_official 68:41613245dfd7 4437 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4438 #define SPI_PUSHR_TXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4439 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
mbed_official 68:41613245dfd7 4440 #define SPI_PUSHR_PCS_MASK 0x3F0000u
mbed_official 68:41613245dfd7 4441 #define SPI_PUSHR_PCS_SHIFT 16
mbed_official 68:41613245dfd7 4442 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
mbed_official 68:41613245dfd7 4443 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
mbed_official 68:41613245dfd7 4444 #define SPI_PUSHR_CTCNT_SHIFT 26
mbed_official 68:41613245dfd7 4445 #define SPI_PUSHR_EOQ_MASK 0x8000000u
mbed_official 68:41613245dfd7 4446 #define SPI_PUSHR_EOQ_SHIFT 27
mbed_official 68:41613245dfd7 4447 #define SPI_PUSHR_CTAS_MASK 0x70000000u
mbed_official 68:41613245dfd7 4448 #define SPI_PUSHR_CTAS_SHIFT 28
mbed_official 68:41613245dfd7 4449 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
mbed_official 68:41613245dfd7 4450 #define SPI_PUSHR_CONT_MASK 0x80000000u
mbed_official 68:41613245dfd7 4451 #define SPI_PUSHR_CONT_SHIFT 31
mbed_official 68:41613245dfd7 4452 /* PUSHR_SLAVE Bit Fields */
mbed_official 68:41613245dfd7 4453 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4454 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4455 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
mbed_official 68:41613245dfd7 4456 /* POPR Bit Fields */
mbed_official 68:41613245dfd7 4457 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4458 #define SPI_POPR_RXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4459 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
mbed_official 68:41613245dfd7 4460 /* TXFR0 Bit Fields */
mbed_official 68:41613245dfd7 4461 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4462 #define SPI_TXFR0_TXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4463 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
mbed_official 68:41613245dfd7 4464 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4465 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
mbed_official 68:41613245dfd7 4466 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
mbed_official 68:41613245dfd7 4467 /* TXFR1 Bit Fields */
mbed_official 68:41613245dfd7 4468 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4469 #define SPI_TXFR1_TXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4470 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
mbed_official 68:41613245dfd7 4471 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4472 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
mbed_official 68:41613245dfd7 4473 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
mbed_official 68:41613245dfd7 4474 /* TXFR2 Bit Fields */
mbed_official 68:41613245dfd7 4475 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4476 #define SPI_TXFR2_TXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4477 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
mbed_official 68:41613245dfd7 4478 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4479 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
mbed_official 68:41613245dfd7 4480 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
mbed_official 68:41613245dfd7 4481 /* TXFR3 Bit Fields */
mbed_official 68:41613245dfd7 4482 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4483 #define SPI_TXFR3_TXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4484 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
mbed_official 68:41613245dfd7 4485 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4486 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
mbed_official 68:41613245dfd7 4487 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
mbed_official 68:41613245dfd7 4488 /* RXFR0 Bit Fields */
mbed_official 68:41613245dfd7 4489 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4490 #define SPI_RXFR0_RXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4491 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
mbed_official 68:41613245dfd7 4492 /* RXFR1 Bit Fields */
mbed_official 68:41613245dfd7 4493 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4494 #define SPI_RXFR1_RXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4495 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
mbed_official 68:41613245dfd7 4496 /* RXFR2 Bit Fields */
mbed_official 68:41613245dfd7 4497 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4498 #define SPI_RXFR2_RXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4499 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
mbed_official 68:41613245dfd7 4500 /* RXFR3 Bit Fields */
mbed_official 68:41613245dfd7 4501 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
mbed_official 68:41613245dfd7 4502 #define SPI_RXFR3_RXDATA_SHIFT 0
mbed_official 68:41613245dfd7 4503 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
mbed_official 68:41613245dfd7 4504
mbed_official 68:41613245dfd7 4505 /**
mbed_official 68:41613245dfd7 4506 * @}
mbed_official 68:41613245dfd7 4507 */ /* end of group SPI_Register_Masks */
mbed_official 68:41613245dfd7 4508
mbed_official 68:41613245dfd7 4509
mbed_official 68:41613245dfd7 4510 /* SPI - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 4511 /** Peripheral SPI0 base address */
mbed_official 68:41613245dfd7 4512 #define SPI0_BASE (0x4002C000u)
mbed_official 68:41613245dfd7 4513 /** Peripheral SPI0 base pointer */
mbed_official 68:41613245dfd7 4514 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 68:41613245dfd7 4515
mbed_official 68:41613245dfd7 4516 /**
mbed_official 68:41613245dfd7 4517 * @}
mbed_official 68:41613245dfd7 4518 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 4519
mbed_official 68:41613245dfd7 4520
mbed_official 68:41613245dfd7 4521 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4522 -- TSI Peripheral Access Layer
mbed_official 68:41613245dfd7 4523 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4524
mbed_official 68:41613245dfd7 4525 /**
mbed_official 68:41613245dfd7 4526 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
mbed_official 68:41613245dfd7 4527 * @{
mbed_official 68:41613245dfd7 4528 */
mbed_official 68:41613245dfd7 4529
mbed_official 68:41613245dfd7 4530 /** TSI - Register Layout Typedef */
mbed_official 68:41613245dfd7 4531 typedef struct {
mbed_official 68:41613245dfd7 4532 __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
mbed_official 68:41613245dfd7 4533 __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
mbed_official 68:41613245dfd7 4534 __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
mbed_official 68:41613245dfd7 4535 __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
mbed_official 68:41613245dfd7 4536 uint8_t RESERVED_0[240];
mbed_official 68:41613245dfd7 4537 __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
mbed_official 68:41613245dfd7 4538 __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
mbed_official 68:41613245dfd7 4539 __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
mbed_official 68:41613245dfd7 4540 __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
mbed_official 68:41613245dfd7 4541 __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
mbed_official 68:41613245dfd7 4542 __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
mbed_official 68:41613245dfd7 4543 __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
mbed_official 68:41613245dfd7 4544 __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
mbed_official 68:41613245dfd7 4545 __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
mbed_official 68:41613245dfd7 4546 } TSI_Type;
mbed_official 68:41613245dfd7 4547
mbed_official 68:41613245dfd7 4548 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4549 -- TSI Register Masks
mbed_official 68:41613245dfd7 4550 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4551
mbed_official 68:41613245dfd7 4552 /**
mbed_official 68:41613245dfd7 4553 * @addtogroup TSI_Register_Masks TSI Register Masks
mbed_official 68:41613245dfd7 4554 * @{
mbed_official 68:41613245dfd7 4555 */
mbed_official 68:41613245dfd7 4556
mbed_official 68:41613245dfd7 4557 /* GENCS Bit Fields */
mbed_official 68:41613245dfd7 4558 #define TSI_GENCS_STPE_MASK 0x1u
mbed_official 68:41613245dfd7 4559 #define TSI_GENCS_STPE_SHIFT 0
mbed_official 68:41613245dfd7 4560 #define TSI_GENCS_STM_MASK 0x2u
mbed_official 68:41613245dfd7 4561 #define TSI_GENCS_STM_SHIFT 1
mbed_official 68:41613245dfd7 4562 #define TSI_GENCS_ESOR_MASK 0x10u
mbed_official 68:41613245dfd7 4563 #define TSI_GENCS_ESOR_SHIFT 4
mbed_official 68:41613245dfd7 4564 #define TSI_GENCS_ERIE_MASK 0x20u
mbed_official 68:41613245dfd7 4565 #define TSI_GENCS_ERIE_SHIFT 5
mbed_official 68:41613245dfd7 4566 #define TSI_GENCS_TSIIE_MASK 0x40u
mbed_official 68:41613245dfd7 4567 #define TSI_GENCS_TSIIE_SHIFT 6
mbed_official 68:41613245dfd7 4568 #define TSI_GENCS_TSIEN_MASK 0x80u
mbed_official 68:41613245dfd7 4569 #define TSI_GENCS_TSIEN_SHIFT 7
mbed_official 68:41613245dfd7 4570 #define TSI_GENCS_SWTS_MASK 0x100u
mbed_official 68:41613245dfd7 4571 #define TSI_GENCS_SWTS_SHIFT 8
mbed_official 68:41613245dfd7 4572 #define TSI_GENCS_SCNIP_MASK 0x200u
mbed_official 68:41613245dfd7 4573 #define TSI_GENCS_SCNIP_SHIFT 9
mbed_official 68:41613245dfd7 4574 #define TSI_GENCS_OVRF_MASK 0x1000u
mbed_official 68:41613245dfd7 4575 #define TSI_GENCS_OVRF_SHIFT 12
mbed_official 68:41613245dfd7 4576 #define TSI_GENCS_EXTERF_MASK 0x2000u
mbed_official 68:41613245dfd7 4577 #define TSI_GENCS_EXTERF_SHIFT 13
mbed_official 68:41613245dfd7 4578 #define TSI_GENCS_OUTRGF_MASK 0x4000u
mbed_official 68:41613245dfd7 4579 #define TSI_GENCS_OUTRGF_SHIFT 14
mbed_official 68:41613245dfd7 4580 #define TSI_GENCS_EOSF_MASK 0x8000u
mbed_official 68:41613245dfd7 4581 #define TSI_GENCS_EOSF_SHIFT 15
mbed_official 68:41613245dfd7 4582 #define TSI_GENCS_PS_MASK 0x70000u
mbed_official 68:41613245dfd7 4583 #define TSI_GENCS_PS_SHIFT 16
mbed_official 68:41613245dfd7 4584 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
mbed_official 68:41613245dfd7 4585 #define TSI_GENCS_NSCN_MASK 0xF80000u
mbed_official 68:41613245dfd7 4586 #define TSI_GENCS_NSCN_SHIFT 19
mbed_official 68:41613245dfd7 4587 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
mbed_official 68:41613245dfd7 4588 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
mbed_official 68:41613245dfd7 4589 #define TSI_GENCS_LPSCNITV_SHIFT 24
mbed_official 68:41613245dfd7 4590 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
mbed_official 68:41613245dfd7 4591 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
mbed_official 68:41613245dfd7 4592 #define TSI_GENCS_LPCLKS_SHIFT 28
mbed_official 68:41613245dfd7 4593 /* SCANC Bit Fields */
mbed_official 68:41613245dfd7 4594 #define TSI_SCANC_AMPSC_MASK 0x7u
mbed_official 68:41613245dfd7 4595 #define TSI_SCANC_AMPSC_SHIFT 0
mbed_official 68:41613245dfd7 4596 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
mbed_official 68:41613245dfd7 4597 #define TSI_SCANC_AMCLKS_MASK 0x18u
mbed_official 68:41613245dfd7 4598 #define TSI_SCANC_AMCLKS_SHIFT 3
mbed_official 68:41613245dfd7 4599 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
mbed_official 68:41613245dfd7 4600 #define TSI_SCANC_SMOD_MASK 0xFF00u
mbed_official 68:41613245dfd7 4601 #define TSI_SCANC_SMOD_SHIFT 8
mbed_official 68:41613245dfd7 4602 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
mbed_official 68:41613245dfd7 4603 #define TSI_SCANC_EXTCHRG_MASK 0xF0000u
mbed_official 68:41613245dfd7 4604 #define TSI_SCANC_EXTCHRG_SHIFT 16
mbed_official 68:41613245dfd7 4605 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
mbed_official 68:41613245dfd7 4606 #define TSI_SCANC_REFCHRG_MASK 0xF000000u
mbed_official 68:41613245dfd7 4607 #define TSI_SCANC_REFCHRG_SHIFT 24
mbed_official 68:41613245dfd7 4608 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
mbed_official 68:41613245dfd7 4609 /* PEN Bit Fields */
mbed_official 68:41613245dfd7 4610 #define TSI_PEN_PEN0_MASK 0x1u
mbed_official 68:41613245dfd7 4611 #define TSI_PEN_PEN0_SHIFT 0
mbed_official 68:41613245dfd7 4612 #define TSI_PEN_PEN1_MASK 0x2u
mbed_official 68:41613245dfd7 4613 #define TSI_PEN_PEN1_SHIFT 1
mbed_official 68:41613245dfd7 4614 #define TSI_PEN_PEN2_MASK 0x4u
mbed_official 68:41613245dfd7 4615 #define TSI_PEN_PEN2_SHIFT 2
mbed_official 68:41613245dfd7 4616 #define TSI_PEN_PEN3_MASK 0x8u
mbed_official 68:41613245dfd7 4617 #define TSI_PEN_PEN3_SHIFT 3
mbed_official 68:41613245dfd7 4618 #define TSI_PEN_PEN4_MASK 0x10u
mbed_official 68:41613245dfd7 4619 #define TSI_PEN_PEN4_SHIFT 4
mbed_official 68:41613245dfd7 4620 #define TSI_PEN_PEN5_MASK 0x20u
mbed_official 68:41613245dfd7 4621 #define TSI_PEN_PEN5_SHIFT 5
mbed_official 68:41613245dfd7 4622 #define TSI_PEN_PEN6_MASK 0x40u
mbed_official 68:41613245dfd7 4623 #define TSI_PEN_PEN6_SHIFT 6
mbed_official 68:41613245dfd7 4624 #define TSI_PEN_PEN7_MASK 0x80u
mbed_official 68:41613245dfd7 4625 #define TSI_PEN_PEN7_SHIFT 7
mbed_official 68:41613245dfd7 4626 #define TSI_PEN_PEN8_MASK 0x100u
mbed_official 68:41613245dfd7 4627 #define TSI_PEN_PEN8_SHIFT 8
mbed_official 68:41613245dfd7 4628 #define TSI_PEN_PEN9_MASK 0x200u
mbed_official 68:41613245dfd7 4629 #define TSI_PEN_PEN9_SHIFT 9
mbed_official 68:41613245dfd7 4630 #define TSI_PEN_PEN10_MASK 0x400u
mbed_official 68:41613245dfd7 4631 #define TSI_PEN_PEN10_SHIFT 10
mbed_official 68:41613245dfd7 4632 #define TSI_PEN_PEN11_MASK 0x800u
mbed_official 68:41613245dfd7 4633 #define TSI_PEN_PEN11_SHIFT 11
mbed_official 68:41613245dfd7 4634 #define TSI_PEN_PEN12_MASK 0x1000u
mbed_official 68:41613245dfd7 4635 #define TSI_PEN_PEN12_SHIFT 12
mbed_official 68:41613245dfd7 4636 #define TSI_PEN_PEN13_MASK 0x2000u
mbed_official 68:41613245dfd7 4637 #define TSI_PEN_PEN13_SHIFT 13
mbed_official 68:41613245dfd7 4638 #define TSI_PEN_PEN14_MASK 0x4000u
mbed_official 68:41613245dfd7 4639 #define TSI_PEN_PEN14_SHIFT 14
mbed_official 68:41613245dfd7 4640 #define TSI_PEN_PEN15_MASK 0x8000u
mbed_official 68:41613245dfd7 4641 #define TSI_PEN_PEN15_SHIFT 15
mbed_official 68:41613245dfd7 4642 #define TSI_PEN_LPSP_MASK 0xF0000u
mbed_official 68:41613245dfd7 4643 #define TSI_PEN_LPSP_SHIFT 16
mbed_official 68:41613245dfd7 4644 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
mbed_official 68:41613245dfd7 4645 /* WUCNTR Bit Fields */
mbed_official 68:41613245dfd7 4646 #define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4647 #define TSI_WUCNTR_WUCNT_SHIFT 0
mbed_official 68:41613245dfd7 4648 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
mbed_official 68:41613245dfd7 4649 /* CNTR1 Bit Fields */
mbed_official 68:41613245dfd7 4650 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4651 #define TSI_CNTR1_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4652 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
mbed_official 68:41613245dfd7 4653 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4654 #define TSI_CNTR1_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4655 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
mbed_official 68:41613245dfd7 4656 /* CNTR3 Bit Fields */
mbed_official 68:41613245dfd7 4657 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4658 #define TSI_CNTR3_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4659 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
mbed_official 68:41613245dfd7 4660 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4661 #define TSI_CNTR3_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4662 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
mbed_official 68:41613245dfd7 4663 /* CNTR5 Bit Fields */
mbed_official 68:41613245dfd7 4664 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4665 #define TSI_CNTR5_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4666 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
mbed_official 68:41613245dfd7 4667 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4668 #define TSI_CNTR5_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4669 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
mbed_official 68:41613245dfd7 4670 /* CNTR7 Bit Fields */
mbed_official 68:41613245dfd7 4671 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4672 #define TSI_CNTR7_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4673 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
mbed_official 68:41613245dfd7 4674 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4675 #define TSI_CNTR7_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4676 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
mbed_official 68:41613245dfd7 4677 /* CNTR9 Bit Fields */
mbed_official 68:41613245dfd7 4678 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4679 #define TSI_CNTR9_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4680 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
mbed_official 68:41613245dfd7 4681 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4682 #define TSI_CNTR9_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4683 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
mbed_official 68:41613245dfd7 4684 /* CNTR11 Bit Fields */
mbed_official 68:41613245dfd7 4685 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4686 #define TSI_CNTR11_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4687 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
mbed_official 68:41613245dfd7 4688 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4689 #define TSI_CNTR11_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4690 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
mbed_official 68:41613245dfd7 4691 /* CNTR13 Bit Fields */
mbed_official 68:41613245dfd7 4692 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4693 #define TSI_CNTR13_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4694 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
mbed_official 68:41613245dfd7 4695 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4696 #define TSI_CNTR13_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4697 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
mbed_official 68:41613245dfd7 4698 /* CNTR15 Bit Fields */
mbed_official 68:41613245dfd7 4699 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4700 #define TSI_CNTR15_CTN1_SHIFT 0
mbed_official 68:41613245dfd7 4701 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
mbed_official 68:41613245dfd7 4702 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4703 #define TSI_CNTR15_CTN_SHIFT 16
mbed_official 68:41613245dfd7 4704 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
mbed_official 68:41613245dfd7 4705 /* THRESHOLD Bit Fields */
mbed_official 68:41613245dfd7 4706 #define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 4707 #define TSI_THRESHOLD_HTHH_SHIFT 0
mbed_official 68:41613245dfd7 4708 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
mbed_official 68:41613245dfd7 4709 #define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
mbed_official 68:41613245dfd7 4710 #define TSI_THRESHOLD_LTHH_SHIFT 16
mbed_official 68:41613245dfd7 4711 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
mbed_official 68:41613245dfd7 4712
mbed_official 68:41613245dfd7 4713 /**
mbed_official 68:41613245dfd7 4714 * @}
mbed_official 68:41613245dfd7 4715 */ /* end of group TSI_Register_Masks */
mbed_official 68:41613245dfd7 4716
mbed_official 68:41613245dfd7 4717
mbed_official 68:41613245dfd7 4718 /* TSI - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 4719 /** Peripheral TSI0 base address */
mbed_official 68:41613245dfd7 4720 #define TSI0_BASE (0x40045000u)
mbed_official 68:41613245dfd7 4721 /** Peripheral TSI0 base pointer */
mbed_official 68:41613245dfd7 4722 #define TSI0 ((TSI_Type *)TSI0_BASE)
mbed_official 68:41613245dfd7 4723
mbed_official 68:41613245dfd7 4724 /**
mbed_official 68:41613245dfd7 4725 * @}
mbed_official 68:41613245dfd7 4726 */ /* end of group TSI_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 4727
mbed_official 68:41613245dfd7 4728
mbed_official 68:41613245dfd7 4729 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4730 -- UART Peripheral Access Layer
mbed_official 68:41613245dfd7 4731 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4732
mbed_official 68:41613245dfd7 4733 /**
mbed_official 68:41613245dfd7 4734 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 68:41613245dfd7 4735 * @{
mbed_official 68:41613245dfd7 4736 */
mbed_official 68:41613245dfd7 4737
mbed_official 68:41613245dfd7 4738 /** UART - Register Layout Typedef */
mbed_official 68:41613245dfd7 4739 typedef struct {
mbed_official 68:41613245dfd7 4740 __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
mbed_official 68:41613245dfd7 4741 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
mbed_official 68:41613245dfd7 4742 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 68:41613245dfd7 4743 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 68:41613245dfd7 4744 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 68:41613245dfd7 4745 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 68:41613245dfd7 4746 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 68:41613245dfd7 4747 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 68:41613245dfd7 4748 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 68:41613245dfd7 4749 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 68:41613245dfd7 4750 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 68:41613245dfd7 4751 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 68:41613245dfd7 4752 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
mbed_official 68:41613245dfd7 4753 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
mbed_official 68:41613245dfd7 4754 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
mbed_official 68:41613245dfd7 4755 uint8_t RESERVED_0[1];
mbed_official 68:41613245dfd7 4756 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
mbed_official 68:41613245dfd7 4757 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
mbed_official 68:41613245dfd7 4758 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
mbed_official 68:41613245dfd7 4759 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
mbed_official 68:41613245dfd7 4760 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
mbed_official 68:41613245dfd7 4761 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
mbed_official 68:41613245dfd7 4762 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
mbed_official 68:41613245dfd7 4763 uint8_t RESERVED_1[1];
mbed_official 68:41613245dfd7 4764 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
mbed_official 68:41613245dfd7 4765 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
mbed_official 68:41613245dfd7 4766 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
mbed_official 68:41613245dfd7 4767 union { /* offset: 0x1B */
mbed_official 68:41613245dfd7 4768 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 68:41613245dfd7 4769 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 68:41613245dfd7 4770 };
mbed_official 68:41613245dfd7 4771 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
mbed_official 68:41613245dfd7 4772 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
mbed_official 68:41613245dfd7 4773 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
mbed_official 68:41613245dfd7 4774 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
mbed_official 68:41613245dfd7 4775 uint8_t RESERVED_2[1];
mbed_official 68:41613245dfd7 4776 __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
mbed_official 68:41613245dfd7 4777 __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
mbed_official 68:41613245dfd7 4778 __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
mbed_official 68:41613245dfd7 4779 __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
mbed_official 68:41613245dfd7 4780 __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
mbed_official 68:41613245dfd7 4781 __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
mbed_official 68:41613245dfd7 4782 __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
mbed_official 68:41613245dfd7 4783 __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
mbed_official 68:41613245dfd7 4784 __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
mbed_official 68:41613245dfd7 4785 __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
mbed_official 68:41613245dfd7 4786 __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
mbed_official 68:41613245dfd7 4787 __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
mbed_official 68:41613245dfd7 4788 __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
mbed_official 68:41613245dfd7 4789 __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
mbed_official 68:41613245dfd7 4790 __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
mbed_official 68:41613245dfd7 4791 __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
mbed_official 68:41613245dfd7 4792 __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
mbed_official 68:41613245dfd7 4793 } UART_Type;
mbed_official 68:41613245dfd7 4794
mbed_official 68:41613245dfd7 4795 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 4796 -- UART Register Masks
mbed_official 68:41613245dfd7 4797 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 4798
mbed_official 68:41613245dfd7 4799 /**
mbed_official 68:41613245dfd7 4800 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 68:41613245dfd7 4801 * @{
mbed_official 68:41613245dfd7 4802 */
mbed_official 68:41613245dfd7 4803
mbed_official 68:41613245dfd7 4804 /* BDH Bit Fields */
mbed_official 68:41613245dfd7 4805 #define UART_BDH_SBR_MASK 0x1Fu
mbed_official 68:41613245dfd7 4806 #define UART_BDH_SBR_SHIFT 0
mbed_official 68:41613245dfd7 4807 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mbed_official 68:41613245dfd7 4808 #define UART_BDH_RXEDGIE_MASK 0x40u
mbed_official 68:41613245dfd7 4809 #define UART_BDH_RXEDGIE_SHIFT 6
mbed_official 68:41613245dfd7 4810 #define UART_BDH_LBKDIE_MASK 0x80u
mbed_official 68:41613245dfd7 4811 #define UART_BDH_LBKDIE_SHIFT 7
mbed_official 68:41613245dfd7 4812 /* BDL Bit Fields */
mbed_official 68:41613245dfd7 4813 #define UART_BDL_SBR_MASK 0xFFu
mbed_official 68:41613245dfd7 4814 #define UART_BDL_SBR_SHIFT 0
mbed_official 68:41613245dfd7 4815 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mbed_official 68:41613245dfd7 4816 /* C1 Bit Fields */
mbed_official 68:41613245dfd7 4817 #define UART_C1_PT_MASK 0x1u
mbed_official 68:41613245dfd7 4818 #define UART_C1_PT_SHIFT 0
mbed_official 68:41613245dfd7 4819 #define UART_C1_PE_MASK 0x2u
mbed_official 68:41613245dfd7 4820 #define UART_C1_PE_SHIFT 1
mbed_official 68:41613245dfd7 4821 #define UART_C1_ILT_MASK 0x4u
mbed_official 68:41613245dfd7 4822 #define UART_C1_ILT_SHIFT 2
mbed_official 68:41613245dfd7 4823 #define UART_C1_WAKE_MASK 0x8u
mbed_official 68:41613245dfd7 4824 #define UART_C1_WAKE_SHIFT 3
mbed_official 68:41613245dfd7 4825 #define UART_C1_M_MASK 0x10u
mbed_official 68:41613245dfd7 4826 #define UART_C1_M_SHIFT 4
mbed_official 68:41613245dfd7 4827 #define UART_C1_RSRC_MASK 0x20u
mbed_official 68:41613245dfd7 4828 #define UART_C1_RSRC_SHIFT 5
mbed_official 68:41613245dfd7 4829 #define UART_C1_UARTSWAI_MASK 0x40u
mbed_official 68:41613245dfd7 4830 #define UART_C1_UARTSWAI_SHIFT 6
mbed_official 68:41613245dfd7 4831 #define UART_C1_LOOPS_MASK 0x80u
mbed_official 68:41613245dfd7 4832 #define UART_C1_LOOPS_SHIFT 7
mbed_official 68:41613245dfd7 4833 /* C2 Bit Fields */
mbed_official 68:41613245dfd7 4834 #define UART_C2_SBK_MASK 0x1u
mbed_official 68:41613245dfd7 4835 #define UART_C2_SBK_SHIFT 0
mbed_official 68:41613245dfd7 4836 #define UART_C2_RWU_MASK 0x2u
mbed_official 68:41613245dfd7 4837 #define UART_C2_RWU_SHIFT 1
mbed_official 68:41613245dfd7 4838 #define UART_C2_RE_MASK 0x4u
mbed_official 68:41613245dfd7 4839 #define UART_C2_RE_SHIFT 2
mbed_official 68:41613245dfd7 4840 #define UART_C2_TE_MASK 0x8u
mbed_official 68:41613245dfd7 4841 #define UART_C2_TE_SHIFT 3
mbed_official 68:41613245dfd7 4842 #define UART_C2_ILIE_MASK 0x10u
mbed_official 68:41613245dfd7 4843 #define UART_C2_ILIE_SHIFT 4
mbed_official 68:41613245dfd7 4844 #define UART_C2_RIE_MASK 0x20u
mbed_official 68:41613245dfd7 4845 #define UART_C2_RIE_SHIFT 5
mbed_official 68:41613245dfd7 4846 #define UART_C2_TCIE_MASK 0x40u
mbed_official 68:41613245dfd7 4847 #define UART_C2_TCIE_SHIFT 6
mbed_official 68:41613245dfd7 4848 #define UART_C2_TIE_MASK 0x80u
mbed_official 68:41613245dfd7 4849 #define UART_C2_TIE_SHIFT 7
mbed_official 68:41613245dfd7 4850 /* S1 Bit Fields */
mbed_official 68:41613245dfd7 4851 #define UART_S1_PF_MASK 0x1u
mbed_official 68:41613245dfd7 4852 #define UART_S1_PF_SHIFT 0
mbed_official 68:41613245dfd7 4853 #define UART_S1_FE_MASK 0x2u
mbed_official 68:41613245dfd7 4854 #define UART_S1_FE_SHIFT 1
mbed_official 68:41613245dfd7 4855 #define UART_S1_NF_MASK 0x4u
mbed_official 68:41613245dfd7 4856 #define UART_S1_NF_SHIFT 2
mbed_official 68:41613245dfd7 4857 #define UART_S1_OR_MASK 0x8u
mbed_official 68:41613245dfd7 4858 #define UART_S1_OR_SHIFT 3
mbed_official 68:41613245dfd7 4859 #define UART_S1_IDLE_MASK 0x10u
mbed_official 68:41613245dfd7 4860 #define UART_S1_IDLE_SHIFT 4
mbed_official 68:41613245dfd7 4861 #define UART_S1_RDRF_MASK 0x20u
mbed_official 68:41613245dfd7 4862 #define UART_S1_RDRF_SHIFT 5
mbed_official 68:41613245dfd7 4863 #define UART_S1_TC_MASK 0x40u
mbed_official 68:41613245dfd7 4864 #define UART_S1_TC_SHIFT 6
mbed_official 68:41613245dfd7 4865 #define UART_S1_TDRE_MASK 0x80u
mbed_official 68:41613245dfd7 4866 #define UART_S1_TDRE_SHIFT 7
mbed_official 68:41613245dfd7 4867 /* S2 Bit Fields */
mbed_official 68:41613245dfd7 4868 #define UART_S2_RAF_MASK 0x1u
mbed_official 68:41613245dfd7 4869 #define UART_S2_RAF_SHIFT 0
mbed_official 68:41613245dfd7 4870 #define UART_S2_LBKDE_MASK 0x2u
mbed_official 68:41613245dfd7 4871 #define UART_S2_LBKDE_SHIFT 1
mbed_official 68:41613245dfd7 4872 #define UART_S2_BRK13_MASK 0x4u
mbed_official 68:41613245dfd7 4873 #define UART_S2_BRK13_SHIFT 2
mbed_official 68:41613245dfd7 4874 #define UART_S2_RWUID_MASK 0x8u
mbed_official 68:41613245dfd7 4875 #define UART_S2_RWUID_SHIFT 3
mbed_official 68:41613245dfd7 4876 #define UART_S2_RXINV_MASK 0x10u
mbed_official 68:41613245dfd7 4877 #define UART_S2_RXINV_SHIFT 4
mbed_official 68:41613245dfd7 4878 #define UART_S2_MSBF_MASK 0x20u
mbed_official 68:41613245dfd7 4879 #define UART_S2_MSBF_SHIFT 5
mbed_official 68:41613245dfd7 4880 #define UART_S2_RXEDGIF_MASK 0x40u
mbed_official 68:41613245dfd7 4881 #define UART_S2_RXEDGIF_SHIFT 6
mbed_official 68:41613245dfd7 4882 #define UART_S2_LBKDIF_MASK 0x80u
mbed_official 68:41613245dfd7 4883 #define UART_S2_LBKDIF_SHIFT 7
mbed_official 68:41613245dfd7 4884 /* C3 Bit Fields */
mbed_official 68:41613245dfd7 4885 #define UART_C3_PEIE_MASK 0x1u
mbed_official 68:41613245dfd7 4886 #define UART_C3_PEIE_SHIFT 0
mbed_official 68:41613245dfd7 4887 #define UART_C3_FEIE_MASK 0x2u
mbed_official 68:41613245dfd7 4888 #define UART_C3_FEIE_SHIFT 1
mbed_official 68:41613245dfd7 4889 #define UART_C3_NEIE_MASK 0x4u
mbed_official 68:41613245dfd7 4890 #define UART_C3_NEIE_SHIFT 2
mbed_official 68:41613245dfd7 4891 #define UART_C3_ORIE_MASK 0x8u
mbed_official 68:41613245dfd7 4892 #define UART_C3_ORIE_SHIFT 3
mbed_official 68:41613245dfd7 4893 #define UART_C3_TXINV_MASK 0x10u
mbed_official 68:41613245dfd7 4894 #define UART_C3_TXINV_SHIFT 4
mbed_official 68:41613245dfd7 4895 #define UART_C3_TXDIR_MASK 0x20u
mbed_official 68:41613245dfd7 4896 #define UART_C3_TXDIR_SHIFT 5
mbed_official 68:41613245dfd7 4897 #define UART_C3_T8_MASK 0x40u
mbed_official 68:41613245dfd7 4898 #define UART_C3_T8_SHIFT 6
mbed_official 68:41613245dfd7 4899 #define UART_C3_R8_MASK 0x80u
mbed_official 68:41613245dfd7 4900 #define UART_C3_R8_SHIFT 7
mbed_official 68:41613245dfd7 4901 /* D Bit Fields */
mbed_official 68:41613245dfd7 4902 #define UART_D_RT_MASK 0xFFu
mbed_official 68:41613245dfd7 4903 #define UART_D_RT_SHIFT 0
mbed_official 68:41613245dfd7 4904 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
mbed_official 68:41613245dfd7 4905 /* MA1 Bit Fields */
mbed_official 68:41613245dfd7 4906 #define UART_MA1_MA_MASK 0xFFu
mbed_official 68:41613245dfd7 4907 #define UART_MA1_MA_SHIFT 0
mbed_official 68:41613245dfd7 4908 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
mbed_official 68:41613245dfd7 4909 /* MA2 Bit Fields */
mbed_official 68:41613245dfd7 4910 #define UART_MA2_MA_MASK 0xFFu
mbed_official 68:41613245dfd7 4911 #define UART_MA2_MA_SHIFT 0
mbed_official 68:41613245dfd7 4912 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
mbed_official 68:41613245dfd7 4913 /* C4 Bit Fields */
mbed_official 68:41613245dfd7 4914 #define UART_C4_BRFA_MASK 0x1Fu
mbed_official 68:41613245dfd7 4915 #define UART_C4_BRFA_SHIFT 0
mbed_official 68:41613245dfd7 4916 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
mbed_official 68:41613245dfd7 4917 #define UART_C4_M10_MASK 0x20u
mbed_official 68:41613245dfd7 4918 #define UART_C4_M10_SHIFT 5
mbed_official 68:41613245dfd7 4919 #define UART_C4_MAEN2_MASK 0x40u
mbed_official 68:41613245dfd7 4920 #define UART_C4_MAEN2_SHIFT 6
mbed_official 68:41613245dfd7 4921 #define UART_C4_MAEN1_MASK 0x80u
mbed_official 68:41613245dfd7 4922 #define UART_C4_MAEN1_SHIFT 7
mbed_official 68:41613245dfd7 4923 /* C5 Bit Fields */
mbed_official 68:41613245dfd7 4924 #define UART_C5_RDMAS_MASK 0x20u
mbed_official 68:41613245dfd7 4925 #define UART_C5_RDMAS_SHIFT 5
mbed_official 68:41613245dfd7 4926 #define UART_C5_TDMAS_MASK 0x80u
mbed_official 68:41613245dfd7 4927 #define UART_C5_TDMAS_SHIFT 7
mbed_official 68:41613245dfd7 4928 /* ED Bit Fields */
mbed_official 68:41613245dfd7 4929 #define UART_ED_PARITYE_MASK 0x40u
mbed_official 68:41613245dfd7 4930 #define UART_ED_PARITYE_SHIFT 6
mbed_official 68:41613245dfd7 4931 #define UART_ED_NOISY_MASK 0x80u
mbed_official 68:41613245dfd7 4932 #define UART_ED_NOISY_SHIFT 7
mbed_official 68:41613245dfd7 4933 /* MODEM Bit Fields */
mbed_official 68:41613245dfd7 4934 #define UART_MODEM_TXCTSE_MASK 0x1u
mbed_official 68:41613245dfd7 4935 #define UART_MODEM_TXCTSE_SHIFT 0
mbed_official 68:41613245dfd7 4936 #define UART_MODEM_TXRTSE_MASK 0x2u
mbed_official 68:41613245dfd7 4937 #define UART_MODEM_TXRTSE_SHIFT 1
mbed_official 68:41613245dfd7 4938 #define UART_MODEM_TXRTSPOL_MASK 0x4u
mbed_official 68:41613245dfd7 4939 #define UART_MODEM_TXRTSPOL_SHIFT 2
mbed_official 68:41613245dfd7 4940 #define UART_MODEM_RXRTSE_MASK 0x8u
mbed_official 68:41613245dfd7 4941 #define UART_MODEM_RXRTSE_SHIFT 3
mbed_official 68:41613245dfd7 4942 /* IR Bit Fields */
mbed_official 68:41613245dfd7 4943 #define UART_IR_TNP_MASK 0x3u
mbed_official 68:41613245dfd7 4944 #define UART_IR_TNP_SHIFT 0
mbed_official 68:41613245dfd7 4945 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
mbed_official 68:41613245dfd7 4946 #define UART_IR_IREN_MASK 0x4u
mbed_official 68:41613245dfd7 4947 #define UART_IR_IREN_SHIFT 2
mbed_official 68:41613245dfd7 4948 /* PFIFO Bit Fields */
mbed_official 68:41613245dfd7 4949 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
mbed_official 68:41613245dfd7 4950 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
mbed_official 68:41613245dfd7 4951 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
mbed_official 68:41613245dfd7 4952 #define UART_PFIFO_RXFE_MASK 0x8u
mbed_official 68:41613245dfd7 4953 #define UART_PFIFO_RXFE_SHIFT 3
mbed_official 68:41613245dfd7 4954 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
mbed_official 68:41613245dfd7 4955 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
mbed_official 68:41613245dfd7 4956 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
mbed_official 68:41613245dfd7 4957 #define UART_PFIFO_TXFE_MASK 0x80u
mbed_official 68:41613245dfd7 4958 #define UART_PFIFO_TXFE_SHIFT 7
mbed_official 68:41613245dfd7 4959 /* CFIFO Bit Fields */
mbed_official 68:41613245dfd7 4960 #define UART_CFIFO_RXUFE_MASK 0x1u
mbed_official 68:41613245dfd7 4961 #define UART_CFIFO_RXUFE_SHIFT 0
mbed_official 68:41613245dfd7 4962 #define UART_CFIFO_TXOFE_MASK 0x2u
mbed_official 68:41613245dfd7 4963 #define UART_CFIFO_TXOFE_SHIFT 1
mbed_official 68:41613245dfd7 4964 #define UART_CFIFO_RXFLUSH_MASK 0x40u
mbed_official 68:41613245dfd7 4965 #define UART_CFIFO_RXFLUSH_SHIFT 6
mbed_official 68:41613245dfd7 4966 #define UART_CFIFO_TXFLUSH_MASK 0x80u
mbed_official 68:41613245dfd7 4967 #define UART_CFIFO_TXFLUSH_SHIFT 7
mbed_official 68:41613245dfd7 4968 /* SFIFO Bit Fields */
mbed_official 68:41613245dfd7 4969 #define UART_SFIFO_RXUF_MASK 0x1u
mbed_official 68:41613245dfd7 4970 #define UART_SFIFO_RXUF_SHIFT 0
mbed_official 68:41613245dfd7 4971 #define UART_SFIFO_TXOF_MASK 0x2u
mbed_official 68:41613245dfd7 4972 #define UART_SFIFO_TXOF_SHIFT 1
mbed_official 68:41613245dfd7 4973 #define UART_SFIFO_RXEMPT_MASK 0x40u
mbed_official 68:41613245dfd7 4974 #define UART_SFIFO_RXEMPT_SHIFT 6
mbed_official 68:41613245dfd7 4975 #define UART_SFIFO_TXEMPT_MASK 0x80u
mbed_official 68:41613245dfd7 4976 #define UART_SFIFO_TXEMPT_SHIFT 7
mbed_official 68:41613245dfd7 4977 /* TWFIFO Bit Fields */
mbed_official 68:41613245dfd7 4978 #define UART_TWFIFO_TXWATER_MASK 0xFFu
mbed_official 68:41613245dfd7 4979 #define UART_TWFIFO_TXWATER_SHIFT 0
mbed_official 68:41613245dfd7 4980 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
mbed_official 68:41613245dfd7 4981 /* TCFIFO Bit Fields */
mbed_official 68:41613245dfd7 4982 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
mbed_official 68:41613245dfd7 4983 #define UART_TCFIFO_TXCOUNT_SHIFT 0
mbed_official 68:41613245dfd7 4984 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
mbed_official 68:41613245dfd7 4985 /* RWFIFO Bit Fields */
mbed_official 68:41613245dfd7 4986 #define UART_RWFIFO_RXWATER_MASK 0xFFu
mbed_official 68:41613245dfd7 4987 #define UART_RWFIFO_RXWATER_SHIFT 0
mbed_official 68:41613245dfd7 4988 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
mbed_official 68:41613245dfd7 4989 /* RCFIFO Bit Fields */
mbed_official 68:41613245dfd7 4990 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
mbed_official 68:41613245dfd7 4991 #define UART_RCFIFO_RXCOUNT_SHIFT 0
mbed_official 68:41613245dfd7 4992 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
mbed_official 68:41613245dfd7 4993 /* C7816 Bit Fields */
mbed_official 68:41613245dfd7 4994 #define UART_C7816_ISO_7816E_MASK 0x1u
mbed_official 68:41613245dfd7 4995 #define UART_C7816_ISO_7816E_SHIFT 0
mbed_official 68:41613245dfd7 4996 #define UART_C7816_TTYPE_MASK 0x2u
mbed_official 68:41613245dfd7 4997 #define UART_C7816_TTYPE_SHIFT 1
mbed_official 68:41613245dfd7 4998 #define UART_C7816_INIT_MASK 0x4u
mbed_official 68:41613245dfd7 4999 #define UART_C7816_INIT_SHIFT 2
mbed_official 68:41613245dfd7 5000 #define UART_C7816_ANACK_MASK 0x8u
mbed_official 68:41613245dfd7 5001 #define UART_C7816_ANACK_SHIFT 3
mbed_official 68:41613245dfd7 5002 #define UART_C7816_ONACK_MASK 0x10u
mbed_official 68:41613245dfd7 5003 #define UART_C7816_ONACK_SHIFT 4
mbed_official 68:41613245dfd7 5004 /* IE7816 Bit Fields */
mbed_official 68:41613245dfd7 5005 #define UART_IE7816_RXTE_MASK 0x1u
mbed_official 68:41613245dfd7 5006 #define UART_IE7816_RXTE_SHIFT 0
mbed_official 68:41613245dfd7 5007 #define UART_IE7816_TXTE_MASK 0x2u
mbed_official 68:41613245dfd7 5008 #define UART_IE7816_TXTE_SHIFT 1
mbed_official 68:41613245dfd7 5009 #define UART_IE7816_GTVE_MASK 0x4u
mbed_official 68:41613245dfd7 5010 #define UART_IE7816_GTVE_SHIFT 2
mbed_official 68:41613245dfd7 5011 #define UART_IE7816_INITDE_MASK 0x10u
mbed_official 68:41613245dfd7 5012 #define UART_IE7816_INITDE_SHIFT 4
mbed_official 68:41613245dfd7 5013 #define UART_IE7816_BWTE_MASK 0x20u
mbed_official 68:41613245dfd7 5014 #define UART_IE7816_BWTE_SHIFT 5
mbed_official 68:41613245dfd7 5015 #define UART_IE7816_CWTE_MASK 0x40u
mbed_official 68:41613245dfd7 5016 #define UART_IE7816_CWTE_SHIFT 6
mbed_official 68:41613245dfd7 5017 #define UART_IE7816_WTE_MASK 0x80u
mbed_official 68:41613245dfd7 5018 #define UART_IE7816_WTE_SHIFT 7
mbed_official 68:41613245dfd7 5019 /* IS7816 Bit Fields */
mbed_official 68:41613245dfd7 5020 #define UART_IS7816_RXT_MASK 0x1u
mbed_official 68:41613245dfd7 5021 #define UART_IS7816_RXT_SHIFT 0
mbed_official 68:41613245dfd7 5022 #define UART_IS7816_TXT_MASK 0x2u
mbed_official 68:41613245dfd7 5023 #define UART_IS7816_TXT_SHIFT 1
mbed_official 68:41613245dfd7 5024 #define UART_IS7816_GTV_MASK 0x4u
mbed_official 68:41613245dfd7 5025 #define UART_IS7816_GTV_SHIFT 2
mbed_official 68:41613245dfd7 5026 #define UART_IS7816_INITD_MASK 0x10u
mbed_official 68:41613245dfd7 5027 #define UART_IS7816_INITD_SHIFT 4
mbed_official 68:41613245dfd7 5028 #define UART_IS7816_BWT_MASK 0x20u
mbed_official 68:41613245dfd7 5029 #define UART_IS7816_BWT_SHIFT 5
mbed_official 68:41613245dfd7 5030 #define UART_IS7816_CWT_MASK 0x40u
mbed_official 68:41613245dfd7 5031 #define UART_IS7816_CWT_SHIFT 6
mbed_official 68:41613245dfd7 5032 #define UART_IS7816_WT_MASK 0x80u
mbed_official 68:41613245dfd7 5033 #define UART_IS7816_WT_SHIFT 7
mbed_official 68:41613245dfd7 5034 /* WP7816_T_TYPE0 Bit Fields */
mbed_official 68:41613245dfd7 5035 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
mbed_official 68:41613245dfd7 5036 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
mbed_official 68:41613245dfd7 5037 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
mbed_official 68:41613245dfd7 5038 /* WP7816_T_TYPE1 Bit Fields */
mbed_official 68:41613245dfd7 5039 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
mbed_official 68:41613245dfd7 5040 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
mbed_official 68:41613245dfd7 5041 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
mbed_official 68:41613245dfd7 5042 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
mbed_official 68:41613245dfd7 5043 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
mbed_official 68:41613245dfd7 5044 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
mbed_official 68:41613245dfd7 5045 /* WN7816 Bit Fields */
mbed_official 68:41613245dfd7 5046 #define UART_WN7816_GTN_MASK 0xFFu
mbed_official 68:41613245dfd7 5047 #define UART_WN7816_GTN_SHIFT 0
mbed_official 68:41613245dfd7 5048 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
mbed_official 68:41613245dfd7 5049 /* WF7816 Bit Fields */
mbed_official 68:41613245dfd7 5050 #define UART_WF7816_GTFD_MASK 0xFFu
mbed_official 68:41613245dfd7 5051 #define UART_WF7816_GTFD_SHIFT 0
mbed_official 68:41613245dfd7 5052 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
mbed_official 68:41613245dfd7 5053 /* ET7816 Bit Fields */
mbed_official 68:41613245dfd7 5054 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
mbed_official 68:41613245dfd7 5055 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
mbed_official 68:41613245dfd7 5056 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
mbed_official 68:41613245dfd7 5057 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
mbed_official 68:41613245dfd7 5058 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
mbed_official 68:41613245dfd7 5059 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
mbed_official 68:41613245dfd7 5060 /* TL7816 Bit Fields */
mbed_official 68:41613245dfd7 5061 #define UART_TL7816_TLEN_MASK 0xFFu
mbed_official 68:41613245dfd7 5062 #define UART_TL7816_TLEN_SHIFT 0
mbed_official 68:41613245dfd7 5063 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
mbed_official 68:41613245dfd7 5064 /* C6 Bit Fields */
mbed_official 68:41613245dfd7 5065 #define UART_C6_CP_MASK 0x10u
mbed_official 68:41613245dfd7 5066 #define UART_C6_CP_SHIFT 4
mbed_official 68:41613245dfd7 5067 #define UART_C6_CE_MASK 0x20u
mbed_official 68:41613245dfd7 5068 #define UART_C6_CE_SHIFT 5
mbed_official 68:41613245dfd7 5069 #define UART_C6_TX709_MASK 0x40u
mbed_official 68:41613245dfd7 5070 #define UART_C6_TX709_SHIFT 6
mbed_official 68:41613245dfd7 5071 #define UART_C6_EN709_MASK 0x80u
mbed_official 68:41613245dfd7 5072 #define UART_C6_EN709_SHIFT 7
mbed_official 68:41613245dfd7 5073 /* PCTH Bit Fields */
mbed_official 68:41613245dfd7 5074 #define UART_PCTH_PCTH_MASK 0xFFu
mbed_official 68:41613245dfd7 5075 #define UART_PCTH_PCTH_SHIFT 0
mbed_official 68:41613245dfd7 5076 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
mbed_official 68:41613245dfd7 5077 /* PCTL Bit Fields */
mbed_official 68:41613245dfd7 5078 #define UART_PCTL_PCTL_MASK 0xFFu
mbed_official 68:41613245dfd7 5079 #define UART_PCTL_PCTL_SHIFT 0
mbed_official 68:41613245dfd7 5080 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
mbed_official 68:41613245dfd7 5081 /* B1T Bit Fields */
mbed_official 68:41613245dfd7 5082 #define UART_B1T_B1T_MASK 0xFFu
mbed_official 68:41613245dfd7 5083 #define UART_B1T_B1T_SHIFT 0
mbed_official 68:41613245dfd7 5084 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
mbed_official 68:41613245dfd7 5085 /* SDTH Bit Fields */
mbed_official 68:41613245dfd7 5086 #define UART_SDTH_SDTH_MASK 0xFFu
mbed_official 68:41613245dfd7 5087 #define UART_SDTH_SDTH_SHIFT 0
mbed_official 68:41613245dfd7 5088 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
mbed_official 68:41613245dfd7 5089 /* SDTL Bit Fields */
mbed_official 68:41613245dfd7 5090 #define UART_SDTL_SDTL_MASK 0xFFu
mbed_official 68:41613245dfd7 5091 #define UART_SDTL_SDTL_SHIFT 0
mbed_official 68:41613245dfd7 5092 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
mbed_official 68:41613245dfd7 5093 /* PRE Bit Fields */
mbed_official 68:41613245dfd7 5094 #define UART_PRE_PREAMBLE_MASK 0xFFu
mbed_official 68:41613245dfd7 5095 #define UART_PRE_PREAMBLE_SHIFT 0
mbed_official 68:41613245dfd7 5096 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
mbed_official 68:41613245dfd7 5097 /* TPL Bit Fields */
mbed_official 68:41613245dfd7 5098 #define UART_TPL_TPL_MASK 0xFFu
mbed_official 68:41613245dfd7 5099 #define UART_TPL_TPL_SHIFT 0
mbed_official 68:41613245dfd7 5100 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
mbed_official 68:41613245dfd7 5101 /* IE Bit Fields */
mbed_official 68:41613245dfd7 5102 #define UART_IE_TXFIE_MASK 0x1u
mbed_official 68:41613245dfd7 5103 #define UART_IE_TXFIE_SHIFT 0
mbed_official 68:41613245dfd7 5104 #define UART_IE_PSIE_MASK 0x2u
mbed_official 68:41613245dfd7 5105 #define UART_IE_PSIE_SHIFT 1
mbed_official 68:41613245dfd7 5106 #define UART_IE_PCTEIE_MASK 0x4u
mbed_official 68:41613245dfd7 5107 #define UART_IE_PCTEIE_SHIFT 2
mbed_official 68:41613245dfd7 5108 #define UART_IE_PTXIE_MASK 0x8u
mbed_official 68:41613245dfd7 5109 #define UART_IE_PTXIE_SHIFT 3
mbed_official 68:41613245dfd7 5110 #define UART_IE_PRXIE_MASK 0x10u
mbed_official 68:41613245dfd7 5111 #define UART_IE_PRXIE_SHIFT 4
mbed_official 68:41613245dfd7 5112 #define UART_IE_ISDIE_MASK 0x20u
mbed_official 68:41613245dfd7 5113 #define UART_IE_ISDIE_SHIFT 5
mbed_official 68:41613245dfd7 5114 #define UART_IE_WBEIE_MASK 0x40u
mbed_official 68:41613245dfd7 5115 #define UART_IE_WBEIE_SHIFT 6
mbed_official 68:41613245dfd7 5116 /* WB Bit Fields */
mbed_official 68:41613245dfd7 5117 #define UART_WB_WBASE_MASK 0xFFu
mbed_official 68:41613245dfd7 5118 #define UART_WB_WBASE_SHIFT 0
mbed_official 68:41613245dfd7 5119 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
mbed_official 68:41613245dfd7 5120 /* S3 Bit Fields */
mbed_official 68:41613245dfd7 5121 #define UART_S3_TXFF_MASK 0x1u
mbed_official 68:41613245dfd7 5122 #define UART_S3_TXFF_SHIFT 0
mbed_official 68:41613245dfd7 5123 #define UART_S3_PSF_MASK 0x2u
mbed_official 68:41613245dfd7 5124 #define UART_S3_PSF_SHIFT 1
mbed_official 68:41613245dfd7 5125 #define UART_S3_PCTEF_MASK 0x4u
mbed_official 68:41613245dfd7 5126 #define UART_S3_PCTEF_SHIFT 2
mbed_official 68:41613245dfd7 5127 #define UART_S3_PTXF_MASK 0x8u
mbed_official 68:41613245dfd7 5128 #define UART_S3_PTXF_SHIFT 3
mbed_official 68:41613245dfd7 5129 #define UART_S3_PRXF_MASK 0x10u
mbed_official 68:41613245dfd7 5130 #define UART_S3_PRXF_SHIFT 4
mbed_official 68:41613245dfd7 5131 #define UART_S3_ISD_MASK 0x20u
mbed_official 68:41613245dfd7 5132 #define UART_S3_ISD_SHIFT 5
mbed_official 68:41613245dfd7 5133 #define UART_S3_WBEF_MASK 0x40u
mbed_official 68:41613245dfd7 5134 #define UART_S3_WBEF_SHIFT 6
mbed_official 68:41613245dfd7 5135 #define UART_S3_PEF_MASK 0x80u
mbed_official 68:41613245dfd7 5136 #define UART_S3_PEF_SHIFT 7
mbed_official 68:41613245dfd7 5137 /* S4 Bit Fields */
mbed_official 68:41613245dfd7 5138 #define UART_S4_FE_MASK 0x1u
mbed_official 68:41613245dfd7 5139 #define UART_S4_FE_SHIFT 0
mbed_official 68:41613245dfd7 5140 #define UART_S4_ILCV_MASK 0x2u
mbed_official 68:41613245dfd7 5141 #define UART_S4_ILCV_SHIFT 1
mbed_official 68:41613245dfd7 5142 #define UART_S4_CDET_MASK 0xCu
mbed_official 68:41613245dfd7 5143 #define UART_S4_CDET_SHIFT 2
mbed_official 68:41613245dfd7 5144 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
mbed_official 68:41613245dfd7 5145 #define UART_S4_INITF_MASK 0x10u
mbed_official 68:41613245dfd7 5146 #define UART_S4_INITF_SHIFT 4
mbed_official 68:41613245dfd7 5147 /* RPL Bit Fields */
mbed_official 68:41613245dfd7 5148 #define UART_RPL_RPL_MASK 0xFFu
mbed_official 68:41613245dfd7 5149 #define UART_RPL_RPL_SHIFT 0
mbed_official 68:41613245dfd7 5150 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
mbed_official 68:41613245dfd7 5151 /* RPREL Bit Fields */
mbed_official 68:41613245dfd7 5152 #define UART_RPREL_RPREL_MASK 0xFFu
mbed_official 68:41613245dfd7 5153 #define UART_RPREL_RPREL_SHIFT 0
mbed_official 68:41613245dfd7 5154 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
mbed_official 68:41613245dfd7 5155 /* CPW Bit Fields */
mbed_official 68:41613245dfd7 5156 #define UART_CPW_CPW_MASK 0xFFu
mbed_official 68:41613245dfd7 5157 #define UART_CPW_CPW_SHIFT 0
mbed_official 68:41613245dfd7 5158 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
mbed_official 68:41613245dfd7 5159 /* RIDT Bit Fields */
mbed_official 68:41613245dfd7 5160 #define UART_RIDT_RIDT_MASK 0xFFu
mbed_official 68:41613245dfd7 5161 #define UART_RIDT_RIDT_SHIFT 0
mbed_official 68:41613245dfd7 5162 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
mbed_official 68:41613245dfd7 5163 /* TIDT Bit Fields */
mbed_official 68:41613245dfd7 5164 #define UART_TIDT_TIDT_MASK 0xFFu
mbed_official 68:41613245dfd7 5165 #define UART_TIDT_TIDT_SHIFT 0
mbed_official 68:41613245dfd7 5166 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
mbed_official 68:41613245dfd7 5167
mbed_official 68:41613245dfd7 5168 /**
mbed_official 68:41613245dfd7 5169 * @}
mbed_official 68:41613245dfd7 5170 */ /* end of group UART_Register_Masks */
mbed_official 68:41613245dfd7 5171
mbed_official 68:41613245dfd7 5172
mbed_official 68:41613245dfd7 5173 /* UART - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 5174 /** Peripheral UART0 base address */
mbed_official 68:41613245dfd7 5175 #define UART0_BASE (0x4006A000u)
mbed_official 68:41613245dfd7 5176 /** Peripheral UART0 base pointer */
mbed_official 68:41613245dfd7 5177 #define UART0 ((UART_Type *)UART0_BASE)
mbed_official 68:41613245dfd7 5178 /** Peripheral UART1 base address */
mbed_official 68:41613245dfd7 5179 #define UART1_BASE (0x4006B000u)
mbed_official 68:41613245dfd7 5180 /** Peripheral UART1 base pointer */
mbed_official 68:41613245dfd7 5181 #define UART1 ((UART_Type *)UART1_BASE)
mbed_official 68:41613245dfd7 5182 /** Peripheral UART2 base address */
mbed_official 68:41613245dfd7 5183 #define UART2_BASE (0x4006C000u)
mbed_official 68:41613245dfd7 5184 /** Peripheral UART2 base pointer */
mbed_official 68:41613245dfd7 5185 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 68:41613245dfd7 5186
mbed_official 68:41613245dfd7 5187 /**
mbed_official 68:41613245dfd7 5188 * @}
mbed_official 68:41613245dfd7 5189 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 5190
mbed_official 68:41613245dfd7 5191
mbed_official 68:41613245dfd7 5192 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5193 -- USB Peripheral Access Layer
mbed_official 68:41613245dfd7 5194 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5195
mbed_official 68:41613245dfd7 5196 /**
mbed_official 68:41613245dfd7 5197 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 68:41613245dfd7 5198 * @{
mbed_official 68:41613245dfd7 5199 */
mbed_official 68:41613245dfd7 5200
mbed_official 68:41613245dfd7 5201 /** USB - Register Layout Typedef */
mbed_official 68:41613245dfd7 5202 typedef struct {
mbed_official 68:41613245dfd7 5203 __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
mbed_official 68:41613245dfd7 5204 uint8_t RESERVED_0[3];
mbed_official 68:41613245dfd7 5205 __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
mbed_official 68:41613245dfd7 5206 uint8_t RESERVED_1[3];
mbed_official 68:41613245dfd7 5207 __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
mbed_official 68:41613245dfd7 5208 uint8_t RESERVED_2[3];
mbed_official 68:41613245dfd7 5209 __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
mbed_official 68:41613245dfd7 5210 uint8_t RESERVED_3[3];
mbed_official 68:41613245dfd7 5211 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
mbed_official 68:41613245dfd7 5212 uint8_t RESERVED_4[3];
mbed_official 68:41613245dfd7 5213 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
mbed_official 68:41613245dfd7 5214 uint8_t RESERVED_5[3];
mbed_official 68:41613245dfd7 5215 __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
mbed_official 68:41613245dfd7 5216 uint8_t RESERVED_6[3];
mbed_official 68:41613245dfd7 5217 __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
mbed_official 68:41613245dfd7 5218 uint8_t RESERVED_7[99];
mbed_official 68:41613245dfd7 5219 __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
mbed_official 68:41613245dfd7 5220 uint8_t RESERVED_8[3];
mbed_official 68:41613245dfd7 5221 __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
mbed_official 68:41613245dfd7 5222 uint8_t RESERVED_9[3];
mbed_official 68:41613245dfd7 5223 __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
mbed_official 68:41613245dfd7 5224 uint8_t RESERVED_10[3];
mbed_official 68:41613245dfd7 5225 __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
mbed_official 68:41613245dfd7 5226 uint8_t RESERVED_11[3];
mbed_official 68:41613245dfd7 5227 __I uint8_t STAT; /**< Status Register, offset: 0x90 */
mbed_official 68:41613245dfd7 5228 uint8_t RESERVED_12[3];
mbed_official 68:41613245dfd7 5229 __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
mbed_official 68:41613245dfd7 5230 uint8_t RESERVED_13[3];
mbed_official 68:41613245dfd7 5231 __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
mbed_official 68:41613245dfd7 5232 uint8_t RESERVED_14[3];
mbed_official 68:41613245dfd7 5233 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
mbed_official 68:41613245dfd7 5234 uint8_t RESERVED_15[3];
mbed_official 68:41613245dfd7 5235 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
mbed_official 68:41613245dfd7 5236 uint8_t RESERVED_16[3];
mbed_official 68:41613245dfd7 5237 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
mbed_official 68:41613245dfd7 5238 uint8_t RESERVED_17[3];
mbed_official 68:41613245dfd7 5239 __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
mbed_official 68:41613245dfd7 5240 uint8_t RESERVED_18[3];
mbed_official 68:41613245dfd7 5241 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
mbed_official 68:41613245dfd7 5242 uint8_t RESERVED_19[3];
mbed_official 68:41613245dfd7 5243 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 68:41613245dfd7 5244 uint8_t RESERVED_20[3];
mbed_official 68:41613245dfd7 5245 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 68:41613245dfd7 5246 uint8_t RESERVED_21[11];
mbed_official 68:41613245dfd7 5247 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 68:41613245dfd7 5248 __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
mbed_official 68:41613245dfd7 5249 uint8_t RESERVED_0[3];
mbed_official 68:41613245dfd7 5250 } ENDPOINT[16];
mbed_official 68:41613245dfd7 5251 __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
mbed_official 68:41613245dfd7 5252 uint8_t RESERVED_22[3];
mbed_official 68:41613245dfd7 5253 __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
mbed_official 68:41613245dfd7 5254 uint8_t RESERVED_23[3];
mbed_official 68:41613245dfd7 5255 __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
mbed_official 68:41613245dfd7 5256 uint8_t RESERVED_24[3];
mbed_official 68:41613245dfd7 5257 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
mbed_official 68:41613245dfd7 5258 uint8_t RESERVED_25[7];
mbed_official 68:41613245dfd7 5259 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 68:41613245dfd7 5260 } USB_Type;
mbed_official 68:41613245dfd7 5261
mbed_official 68:41613245dfd7 5262 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5263 -- USB Register Masks
mbed_official 68:41613245dfd7 5264 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5265
mbed_official 68:41613245dfd7 5266 /**
mbed_official 68:41613245dfd7 5267 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 68:41613245dfd7 5268 * @{
mbed_official 68:41613245dfd7 5269 */
mbed_official 68:41613245dfd7 5270
mbed_official 68:41613245dfd7 5271 /* PERID Bit Fields */
mbed_official 68:41613245dfd7 5272 #define USB_PERID_ID_MASK 0x3Fu
mbed_official 68:41613245dfd7 5273 #define USB_PERID_ID_SHIFT 0
mbed_official 68:41613245dfd7 5274 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mbed_official 68:41613245dfd7 5275 /* IDCOMP Bit Fields */
mbed_official 68:41613245dfd7 5276 #define USB_IDCOMP_NID_MASK 0x3Fu
mbed_official 68:41613245dfd7 5277 #define USB_IDCOMP_NID_SHIFT 0
mbed_official 68:41613245dfd7 5278 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mbed_official 68:41613245dfd7 5279 /* REV Bit Fields */
mbed_official 68:41613245dfd7 5280 #define USB_REV_REV_MASK 0xFFu
mbed_official 68:41613245dfd7 5281 #define USB_REV_REV_SHIFT 0
mbed_official 68:41613245dfd7 5282 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mbed_official 68:41613245dfd7 5283 /* ADDINFO Bit Fields */
mbed_official 68:41613245dfd7 5284 #define USB_ADDINFO_IEHOST_MASK 0x1u
mbed_official 68:41613245dfd7 5285 #define USB_ADDINFO_IEHOST_SHIFT 0
mbed_official 68:41613245dfd7 5286 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
mbed_official 68:41613245dfd7 5287 #define USB_ADDINFO_IRQNUM_SHIFT 3
mbed_official 68:41613245dfd7 5288 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
mbed_official 68:41613245dfd7 5289 /* OTGISTAT Bit Fields */
mbed_official 68:41613245dfd7 5290 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
mbed_official 68:41613245dfd7 5291 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
mbed_official 68:41613245dfd7 5292 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
mbed_official 68:41613245dfd7 5293 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
mbed_official 68:41613245dfd7 5294 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
mbed_official 68:41613245dfd7 5295 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
mbed_official 68:41613245dfd7 5296 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
mbed_official 68:41613245dfd7 5297 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
mbed_official 68:41613245dfd7 5298 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
mbed_official 68:41613245dfd7 5299 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
mbed_official 68:41613245dfd7 5300 #define USB_OTGISTAT_IDCHG_MASK 0x80u
mbed_official 68:41613245dfd7 5301 #define USB_OTGISTAT_IDCHG_SHIFT 7
mbed_official 68:41613245dfd7 5302 /* OTGICR Bit Fields */
mbed_official 68:41613245dfd7 5303 #define USB_OTGICR_AVBUSEN_MASK 0x1u
mbed_official 68:41613245dfd7 5304 #define USB_OTGICR_AVBUSEN_SHIFT 0
mbed_official 68:41613245dfd7 5305 #define USB_OTGICR_BSESSEN_MASK 0x4u
mbed_official 68:41613245dfd7 5306 #define USB_OTGICR_BSESSEN_SHIFT 2
mbed_official 68:41613245dfd7 5307 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
mbed_official 68:41613245dfd7 5308 #define USB_OTGICR_SESSVLDEN_SHIFT 3
mbed_official 68:41613245dfd7 5309 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
mbed_official 68:41613245dfd7 5310 #define USB_OTGICR_LINESTATEEN_SHIFT 5
mbed_official 68:41613245dfd7 5311 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
mbed_official 68:41613245dfd7 5312 #define USB_OTGICR_ONEMSECEN_SHIFT 6
mbed_official 68:41613245dfd7 5313 #define USB_OTGICR_IDEN_MASK 0x80u
mbed_official 68:41613245dfd7 5314 #define USB_OTGICR_IDEN_SHIFT 7
mbed_official 68:41613245dfd7 5315 /* OTGSTAT Bit Fields */
mbed_official 68:41613245dfd7 5316 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
mbed_official 68:41613245dfd7 5317 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
mbed_official 68:41613245dfd7 5318 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
mbed_official 68:41613245dfd7 5319 #define USB_OTGSTAT_BSESSEND_SHIFT 2
mbed_official 68:41613245dfd7 5320 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
mbed_official 68:41613245dfd7 5321 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
mbed_official 68:41613245dfd7 5322 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
mbed_official 68:41613245dfd7 5323 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
mbed_official 68:41613245dfd7 5324 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
mbed_official 68:41613245dfd7 5325 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
mbed_official 68:41613245dfd7 5326 #define USB_OTGSTAT_ID_MASK 0x80u
mbed_official 68:41613245dfd7 5327 #define USB_OTGSTAT_ID_SHIFT 7
mbed_official 68:41613245dfd7 5328 /* OTGCTL Bit Fields */
mbed_official 68:41613245dfd7 5329 #define USB_OTGCTL_OTGEN_MASK 0x4u
mbed_official 68:41613245dfd7 5330 #define USB_OTGCTL_OTGEN_SHIFT 2
mbed_official 68:41613245dfd7 5331 #define USB_OTGCTL_DMLOW_MASK 0x10u
mbed_official 68:41613245dfd7 5332 #define USB_OTGCTL_DMLOW_SHIFT 4
mbed_official 68:41613245dfd7 5333 #define USB_OTGCTL_DPLOW_MASK 0x20u
mbed_official 68:41613245dfd7 5334 #define USB_OTGCTL_DPLOW_SHIFT 5
mbed_official 68:41613245dfd7 5335 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mbed_official 68:41613245dfd7 5336 #define USB_OTGCTL_DPHIGH_SHIFT 7
mbed_official 68:41613245dfd7 5337 /* ISTAT Bit Fields */
mbed_official 68:41613245dfd7 5338 #define USB_ISTAT_USBRST_MASK 0x1u
mbed_official 68:41613245dfd7 5339 #define USB_ISTAT_USBRST_SHIFT 0
mbed_official 68:41613245dfd7 5340 #define USB_ISTAT_ERROR_MASK 0x2u
mbed_official 68:41613245dfd7 5341 #define USB_ISTAT_ERROR_SHIFT 1
mbed_official 68:41613245dfd7 5342 #define USB_ISTAT_SOFTOK_MASK 0x4u
mbed_official 68:41613245dfd7 5343 #define USB_ISTAT_SOFTOK_SHIFT 2
mbed_official 68:41613245dfd7 5344 #define USB_ISTAT_TOKDNE_MASK 0x8u
mbed_official 68:41613245dfd7 5345 #define USB_ISTAT_TOKDNE_SHIFT 3
mbed_official 68:41613245dfd7 5346 #define USB_ISTAT_SLEEP_MASK 0x10u
mbed_official 68:41613245dfd7 5347 #define USB_ISTAT_SLEEP_SHIFT 4
mbed_official 68:41613245dfd7 5348 #define USB_ISTAT_RESUME_MASK 0x20u
mbed_official 68:41613245dfd7 5349 #define USB_ISTAT_RESUME_SHIFT 5
mbed_official 68:41613245dfd7 5350 #define USB_ISTAT_ATTACH_MASK 0x40u
mbed_official 68:41613245dfd7 5351 #define USB_ISTAT_ATTACH_SHIFT 6
mbed_official 68:41613245dfd7 5352 #define USB_ISTAT_STALL_MASK 0x80u
mbed_official 68:41613245dfd7 5353 #define USB_ISTAT_STALL_SHIFT 7
mbed_official 68:41613245dfd7 5354 /* INTEN Bit Fields */
mbed_official 68:41613245dfd7 5355 #define USB_INTEN_USBRSTEN_MASK 0x1u
mbed_official 68:41613245dfd7 5356 #define USB_INTEN_USBRSTEN_SHIFT 0
mbed_official 68:41613245dfd7 5357 #define USB_INTEN_ERROREN_MASK 0x2u
mbed_official 68:41613245dfd7 5358 #define USB_INTEN_ERROREN_SHIFT 1
mbed_official 68:41613245dfd7 5359 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mbed_official 68:41613245dfd7 5360 #define USB_INTEN_SOFTOKEN_SHIFT 2
mbed_official 68:41613245dfd7 5361 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mbed_official 68:41613245dfd7 5362 #define USB_INTEN_TOKDNEEN_SHIFT 3
mbed_official 68:41613245dfd7 5363 #define USB_INTEN_SLEEPEN_MASK 0x10u
mbed_official 68:41613245dfd7 5364 #define USB_INTEN_SLEEPEN_SHIFT 4
mbed_official 68:41613245dfd7 5365 #define USB_INTEN_RESUMEEN_MASK 0x20u
mbed_official 68:41613245dfd7 5366 #define USB_INTEN_RESUMEEN_SHIFT 5
mbed_official 68:41613245dfd7 5367 #define USB_INTEN_ATTACHEN_MASK 0x40u
mbed_official 68:41613245dfd7 5368 #define USB_INTEN_ATTACHEN_SHIFT 6
mbed_official 68:41613245dfd7 5369 #define USB_INTEN_STALLEN_MASK 0x80u
mbed_official 68:41613245dfd7 5370 #define USB_INTEN_STALLEN_SHIFT 7
mbed_official 68:41613245dfd7 5371 /* ERRSTAT Bit Fields */
mbed_official 68:41613245dfd7 5372 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mbed_official 68:41613245dfd7 5373 #define USB_ERRSTAT_PIDERR_SHIFT 0
mbed_official 68:41613245dfd7 5374 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
mbed_official 68:41613245dfd7 5375 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
mbed_official 68:41613245dfd7 5376 #define USB_ERRSTAT_CRC16_MASK 0x4u
mbed_official 68:41613245dfd7 5377 #define USB_ERRSTAT_CRC16_SHIFT 2
mbed_official 68:41613245dfd7 5378 #define USB_ERRSTAT_DFN8_MASK 0x8u
mbed_official 68:41613245dfd7 5379 #define USB_ERRSTAT_DFN8_SHIFT 3
mbed_official 68:41613245dfd7 5380 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mbed_official 68:41613245dfd7 5381 #define USB_ERRSTAT_BTOERR_SHIFT 4
mbed_official 68:41613245dfd7 5382 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mbed_official 68:41613245dfd7 5383 #define USB_ERRSTAT_DMAERR_SHIFT 5
mbed_official 68:41613245dfd7 5384 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mbed_official 68:41613245dfd7 5385 #define USB_ERRSTAT_BTSERR_SHIFT 7
mbed_official 68:41613245dfd7 5386 /* ERREN Bit Fields */
mbed_official 68:41613245dfd7 5387 #define USB_ERREN_PIDERREN_MASK 0x1u
mbed_official 68:41613245dfd7 5388 #define USB_ERREN_PIDERREN_SHIFT 0
mbed_official 68:41613245dfd7 5389 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mbed_official 68:41613245dfd7 5390 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mbed_official 68:41613245dfd7 5391 #define USB_ERREN_CRC16EN_MASK 0x4u
mbed_official 68:41613245dfd7 5392 #define USB_ERREN_CRC16EN_SHIFT 2
mbed_official 68:41613245dfd7 5393 #define USB_ERREN_DFN8EN_MASK 0x8u
mbed_official 68:41613245dfd7 5394 #define USB_ERREN_DFN8EN_SHIFT 3
mbed_official 68:41613245dfd7 5395 #define USB_ERREN_BTOERREN_MASK 0x10u
mbed_official 68:41613245dfd7 5396 #define USB_ERREN_BTOERREN_SHIFT 4
mbed_official 68:41613245dfd7 5397 #define USB_ERREN_DMAERREN_MASK 0x20u
mbed_official 68:41613245dfd7 5398 #define USB_ERREN_DMAERREN_SHIFT 5
mbed_official 68:41613245dfd7 5399 #define USB_ERREN_BTSERREN_MASK 0x80u
mbed_official 68:41613245dfd7 5400 #define USB_ERREN_BTSERREN_SHIFT 7
mbed_official 68:41613245dfd7 5401 /* STAT Bit Fields */
mbed_official 68:41613245dfd7 5402 #define USB_STAT_ODD_MASK 0x4u
mbed_official 68:41613245dfd7 5403 #define USB_STAT_ODD_SHIFT 2
mbed_official 68:41613245dfd7 5404 #define USB_STAT_TX_MASK 0x8u
mbed_official 68:41613245dfd7 5405 #define USB_STAT_TX_SHIFT 3
mbed_official 68:41613245dfd7 5406 #define USB_STAT_ENDP_MASK 0xF0u
mbed_official 68:41613245dfd7 5407 #define USB_STAT_ENDP_SHIFT 4
mbed_official 68:41613245dfd7 5408 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mbed_official 68:41613245dfd7 5409 /* CTL Bit Fields */
mbed_official 68:41613245dfd7 5410 #define USB_CTL_USBENSOFEN_MASK 0x1u
mbed_official 68:41613245dfd7 5411 #define USB_CTL_USBENSOFEN_SHIFT 0
mbed_official 68:41613245dfd7 5412 #define USB_CTL_ODDRST_MASK 0x2u
mbed_official 68:41613245dfd7 5413 #define USB_CTL_ODDRST_SHIFT 1
mbed_official 68:41613245dfd7 5414 #define USB_CTL_RESUME_MASK 0x4u
mbed_official 68:41613245dfd7 5415 #define USB_CTL_RESUME_SHIFT 2
mbed_official 68:41613245dfd7 5416 #define USB_CTL_HOSTMODEEN_MASK 0x8u
mbed_official 68:41613245dfd7 5417 #define USB_CTL_HOSTMODEEN_SHIFT 3
mbed_official 68:41613245dfd7 5418 #define USB_CTL_RESET_MASK 0x10u
mbed_official 68:41613245dfd7 5419 #define USB_CTL_RESET_SHIFT 4
mbed_official 68:41613245dfd7 5420 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mbed_official 68:41613245dfd7 5421 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mbed_official 68:41613245dfd7 5422 #define USB_CTL_SE0_MASK 0x40u
mbed_official 68:41613245dfd7 5423 #define USB_CTL_SE0_SHIFT 6
mbed_official 68:41613245dfd7 5424 #define USB_CTL_JSTATE_MASK 0x80u
mbed_official 68:41613245dfd7 5425 #define USB_CTL_JSTATE_SHIFT 7
mbed_official 68:41613245dfd7 5426 /* ADDR Bit Fields */
mbed_official 68:41613245dfd7 5427 #define USB_ADDR_ADDR_MASK 0x7Fu
mbed_official 68:41613245dfd7 5428 #define USB_ADDR_ADDR_SHIFT 0
mbed_official 68:41613245dfd7 5429 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mbed_official 68:41613245dfd7 5430 #define USB_ADDR_LSEN_MASK 0x80u
mbed_official 68:41613245dfd7 5431 #define USB_ADDR_LSEN_SHIFT 7
mbed_official 68:41613245dfd7 5432 /* BDTPAGE1 Bit Fields */
mbed_official 68:41613245dfd7 5433 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mbed_official 68:41613245dfd7 5434 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mbed_official 68:41613245dfd7 5435 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mbed_official 68:41613245dfd7 5436 /* FRMNUML Bit Fields */
mbed_official 68:41613245dfd7 5437 #define USB_FRMNUML_FRM_MASK 0xFFu
mbed_official 68:41613245dfd7 5438 #define USB_FRMNUML_FRM_SHIFT 0
mbed_official 68:41613245dfd7 5439 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mbed_official 68:41613245dfd7 5440 /* FRMNUMH Bit Fields */
mbed_official 68:41613245dfd7 5441 #define USB_FRMNUMH_FRM_MASK 0x7u
mbed_official 68:41613245dfd7 5442 #define USB_FRMNUMH_FRM_SHIFT 0
mbed_official 68:41613245dfd7 5443 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mbed_official 68:41613245dfd7 5444 /* TOKEN Bit Fields */
mbed_official 68:41613245dfd7 5445 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
mbed_official 68:41613245dfd7 5446 #define USB_TOKEN_TOKENENDPT_SHIFT 0
mbed_official 68:41613245dfd7 5447 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
mbed_official 68:41613245dfd7 5448 #define USB_TOKEN_TOKENPID_MASK 0xF0u
mbed_official 68:41613245dfd7 5449 #define USB_TOKEN_TOKENPID_SHIFT 4
mbed_official 68:41613245dfd7 5450 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
mbed_official 68:41613245dfd7 5451 /* SOFTHLD Bit Fields */
mbed_official 68:41613245dfd7 5452 #define USB_SOFTHLD_CNT_MASK 0xFFu
mbed_official 68:41613245dfd7 5453 #define USB_SOFTHLD_CNT_SHIFT 0
mbed_official 68:41613245dfd7 5454 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
mbed_official 68:41613245dfd7 5455 /* BDTPAGE2 Bit Fields */
mbed_official 68:41613245dfd7 5456 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mbed_official 68:41613245dfd7 5457 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mbed_official 68:41613245dfd7 5458 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mbed_official 68:41613245dfd7 5459 /* BDTPAGE3 Bit Fields */
mbed_official 68:41613245dfd7 5460 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mbed_official 68:41613245dfd7 5461 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mbed_official 68:41613245dfd7 5462 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mbed_official 68:41613245dfd7 5463 /* ENDPT Bit Fields */
mbed_official 68:41613245dfd7 5464 #define USB_ENDPT_EPHSHK_MASK 0x1u
mbed_official 68:41613245dfd7 5465 #define USB_ENDPT_EPHSHK_SHIFT 0
mbed_official 68:41613245dfd7 5466 #define USB_ENDPT_EPSTALL_MASK 0x2u
mbed_official 68:41613245dfd7 5467 #define USB_ENDPT_EPSTALL_SHIFT 1
mbed_official 68:41613245dfd7 5468 #define USB_ENDPT_EPTXEN_MASK 0x4u
mbed_official 68:41613245dfd7 5469 #define USB_ENDPT_EPTXEN_SHIFT 2
mbed_official 68:41613245dfd7 5470 #define USB_ENDPT_EPRXEN_MASK 0x8u
mbed_official 68:41613245dfd7 5471 #define USB_ENDPT_EPRXEN_SHIFT 3
mbed_official 68:41613245dfd7 5472 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mbed_official 68:41613245dfd7 5473 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mbed_official 68:41613245dfd7 5474 #define USB_ENDPT_RETRYDIS_MASK 0x40u
mbed_official 68:41613245dfd7 5475 #define USB_ENDPT_RETRYDIS_SHIFT 6
mbed_official 68:41613245dfd7 5476 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
mbed_official 68:41613245dfd7 5477 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
mbed_official 68:41613245dfd7 5478 /* USBCTRL Bit Fields */
mbed_official 68:41613245dfd7 5479 #define USB_USBCTRL_PDE_MASK 0x40u
mbed_official 68:41613245dfd7 5480 #define USB_USBCTRL_PDE_SHIFT 6
mbed_official 68:41613245dfd7 5481 #define USB_USBCTRL_SUSP_MASK 0x80u
mbed_official 68:41613245dfd7 5482 #define USB_USBCTRL_SUSP_SHIFT 7
mbed_official 68:41613245dfd7 5483 /* OBSERVE Bit Fields */
mbed_official 68:41613245dfd7 5484 #define USB_OBSERVE_DMPD_MASK 0x10u
mbed_official 68:41613245dfd7 5485 #define USB_OBSERVE_DMPD_SHIFT 4
mbed_official 68:41613245dfd7 5486 #define USB_OBSERVE_DPPD_MASK 0x40u
mbed_official 68:41613245dfd7 5487 #define USB_OBSERVE_DPPD_SHIFT 6
mbed_official 68:41613245dfd7 5488 #define USB_OBSERVE_DPPU_MASK 0x80u
mbed_official 68:41613245dfd7 5489 #define USB_OBSERVE_DPPU_SHIFT 7
mbed_official 68:41613245dfd7 5490 /* CONTROL Bit Fields */
mbed_official 68:41613245dfd7 5491 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mbed_official 68:41613245dfd7 5492 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mbed_official 68:41613245dfd7 5493 /* USBTRC0 Bit Fields */
mbed_official 68:41613245dfd7 5494 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mbed_official 68:41613245dfd7 5495 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mbed_official 68:41613245dfd7 5496 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mbed_official 68:41613245dfd7 5497 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mbed_official 68:41613245dfd7 5498 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mbed_official 68:41613245dfd7 5499 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mbed_official 68:41613245dfd7 5500 #define USB_USBTRC0_USBRESET_MASK 0x80u
mbed_official 68:41613245dfd7 5501 #define USB_USBTRC0_USBRESET_SHIFT 7
mbed_official 68:41613245dfd7 5502 /* USBFRMADJUST Bit Fields */
mbed_official 68:41613245dfd7 5503 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mbed_official 68:41613245dfd7 5504 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mbed_official 68:41613245dfd7 5505 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mbed_official 68:41613245dfd7 5506
mbed_official 68:41613245dfd7 5507 /**
mbed_official 68:41613245dfd7 5508 * @}
mbed_official 68:41613245dfd7 5509 */ /* end of group USB_Register_Masks */
mbed_official 68:41613245dfd7 5510
mbed_official 68:41613245dfd7 5511
mbed_official 68:41613245dfd7 5512 /* USB - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 5513 /** Peripheral USB0 base address */
mbed_official 68:41613245dfd7 5514 #define USB0_BASE (0x40072000u)
mbed_official 68:41613245dfd7 5515 /** Peripheral USB0 base pointer */
mbed_official 68:41613245dfd7 5516 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 68:41613245dfd7 5517
mbed_official 68:41613245dfd7 5518 /**
mbed_official 68:41613245dfd7 5519 * @}
mbed_official 68:41613245dfd7 5520 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 5521
mbed_official 68:41613245dfd7 5522
mbed_official 68:41613245dfd7 5523 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5524 -- USBDCD Peripheral Access Layer
mbed_official 68:41613245dfd7 5525 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5526
mbed_official 68:41613245dfd7 5527 /**
mbed_official 68:41613245dfd7 5528 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
mbed_official 68:41613245dfd7 5529 * @{
mbed_official 68:41613245dfd7 5530 */
mbed_official 68:41613245dfd7 5531
mbed_official 68:41613245dfd7 5532 /** USBDCD - Register Layout Typedef */
mbed_official 68:41613245dfd7 5533 typedef struct {
mbed_official 68:41613245dfd7 5534 __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
mbed_official 68:41613245dfd7 5535 __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
mbed_official 68:41613245dfd7 5536 __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
mbed_official 68:41613245dfd7 5537 uint8_t RESERVED_0[4];
mbed_official 68:41613245dfd7 5538 __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
mbed_official 68:41613245dfd7 5539 __IO uint32_t TIMER1; /**< , offset: 0x14 */
mbed_official 68:41613245dfd7 5540 __IO uint32_t TIMER2; /**< , offset: 0x18 */
mbed_official 68:41613245dfd7 5541 } USBDCD_Type;
mbed_official 68:41613245dfd7 5542
mbed_official 68:41613245dfd7 5543 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5544 -- USBDCD Register Masks
mbed_official 68:41613245dfd7 5545 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5546
mbed_official 68:41613245dfd7 5547 /**
mbed_official 68:41613245dfd7 5548 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
mbed_official 68:41613245dfd7 5549 * @{
mbed_official 68:41613245dfd7 5550 */
mbed_official 68:41613245dfd7 5551
mbed_official 68:41613245dfd7 5552 /* CONTROL Bit Fields */
mbed_official 68:41613245dfd7 5553 #define USBDCD_CONTROL_IACK_MASK 0x1u
mbed_official 68:41613245dfd7 5554 #define USBDCD_CONTROL_IACK_SHIFT 0
mbed_official 68:41613245dfd7 5555 #define USBDCD_CONTROL_IF_MASK 0x100u
mbed_official 68:41613245dfd7 5556 #define USBDCD_CONTROL_IF_SHIFT 8
mbed_official 68:41613245dfd7 5557 #define USBDCD_CONTROL_IE_MASK 0x10000u
mbed_official 68:41613245dfd7 5558 #define USBDCD_CONTROL_IE_SHIFT 16
mbed_official 68:41613245dfd7 5559 #define USBDCD_CONTROL_START_MASK 0x1000000u
mbed_official 68:41613245dfd7 5560 #define USBDCD_CONTROL_START_SHIFT 24
mbed_official 68:41613245dfd7 5561 #define USBDCD_CONTROL_SR_MASK 0x2000000u
mbed_official 68:41613245dfd7 5562 #define USBDCD_CONTROL_SR_SHIFT 25
mbed_official 68:41613245dfd7 5563 /* CLOCK Bit Fields */
mbed_official 68:41613245dfd7 5564 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
mbed_official 68:41613245dfd7 5565 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
mbed_official 68:41613245dfd7 5566 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
mbed_official 68:41613245dfd7 5567 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
mbed_official 68:41613245dfd7 5568 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
mbed_official 68:41613245dfd7 5569 /* STATUS Bit Fields */
mbed_official 68:41613245dfd7 5570 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
mbed_official 68:41613245dfd7 5571 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
mbed_official 68:41613245dfd7 5572 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
mbed_official 68:41613245dfd7 5573 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
mbed_official 68:41613245dfd7 5574 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
mbed_official 68:41613245dfd7 5575 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
mbed_official 68:41613245dfd7 5576 #define USBDCD_STATUS_ERR_MASK 0x100000u
mbed_official 68:41613245dfd7 5577 #define USBDCD_STATUS_ERR_SHIFT 20
mbed_official 68:41613245dfd7 5578 #define USBDCD_STATUS_TO_MASK 0x200000u
mbed_official 68:41613245dfd7 5579 #define USBDCD_STATUS_TO_SHIFT 21
mbed_official 68:41613245dfd7 5580 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
mbed_official 68:41613245dfd7 5581 #define USBDCD_STATUS_ACTIVE_SHIFT 22
mbed_official 68:41613245dfd7 5582 /* TIMER0 Bit Fields */
mbed_official 68:41613245dfd7 5583 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
mbed_official 68:41613245dfd7 5584 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
mbed_official 68:41613245dfd7 5585 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
mbed_official 68:41613245dfd7 5586 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
mbed_official 68:41613245dfd7 5587 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
mbed_official 68:41613245dfd7 5588 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
mbed_official 68:41613245dfd7 5589 /* TIMER1 Bit Fields */
mbed_official 68:41613245dfd7 5590 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
mbed_official 68:41613245dfd7 5591 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
mbed_official 68:41613245dfd7 5592 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
mbed_official 68:41613245dfd7 5593 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
mbed_official 68:41613245dfd7 5594 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
mbed_official 68:41613245dfd7 5595 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
mbed_official 68:41613245dfd7 5596 /* TIMER2 Bit Fields */
mbed_official 68:41613245dfd7 5597 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
mbed_official 68:41613245dfd7 5598 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
mbed_official 68:41613245dfd7 5599 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
mbed_official 68:41613245dfd7 5600 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
mbed_official 68:41613245dfd7 5601 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
mbed_official 68:41613245dfd7 5602 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
mbed_official 68:41613245dfd7 5603
mbed_official 68:41613245dfd7 5604 /**
mbed_official 68:41613245dfd7 5605 * @}
mbed_official 68:41613245dfd7 5606 */ /* end of group USBDCD_Register_Masks */
mbed_official 68:41613245dfd7 5607
mbed_official 68:41613245dfd7 5608
mbed_official 68:41613245dfd7 5609 /* USBDCD - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 5610 /** Peripheral USBDCD base address */
mbed_official 68:41613245dfd7 5611 #define USBDCD_BASE (0x40035000u)
mbed_official 68:41613245dfd7 5612 /** Peripheral USBDCD base pointer */
mbed_official 68:41613245dfd7 5613 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
mbed_official 68:41613245dfd7 5614
mbed_official 68:41613245dfd7 5615 /**
mbed_official 68:41613245dfd7 5616 * @}
mbed_official 68:41613245dfd7 5617 */ /* end of group USBDCD_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 5618
mbed_official 68:41613245dfd7 5619
mbed_official 68:41613245dfd7 5620 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5621 -- VREF Peripheral Access Layer
mbed_official 68:41613245dfd7 5622 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5623
mbed_official 68:41613245dfd7 5624 /**
mbed_official 68:41613245dfd7 5625 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
mbed_official 68:41613245dfd7 5626 * @{
mbed_official 68:41613245dfd7 5627 */
mbed_official 68:41613245dfd7 5628
mbed_official 68:41613245dfd7 5629 /** VREF - Register Layout Typedef */
mbed_official 68:41613245dfd7 5630 typedef struct {
mbed_official 68:41613245dfd7 5631 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
mbed_official 68:41613245dfd7 5632 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
mbed_official 68:41613245dfd7 5633 } VREF_Type;
mbed_official 68:41613245dfd7 5634
mbed_official 68:41613245dfd7 5635 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5636 -- VREF Register Masks
mbed_official 68:41613245dfd7 5637 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5638
mbed_official 68:41613245dfd7 5639 /**
mbed_official 68:41613245dfd7 5640 * @addtogroup VREF_Register_Masks VREF Register Masks
mbed_official 68:41613245dfd7 5641 * @{
mbed_official 68:41613245dfd7 5642 */
mbed_official 68:41613245dfd7 5643
mbed_official 68:41613245dfd7 5644 /* TRM Bit Fields */
mbed_official 68:41613245dfd7 5645 #define VREF_TRM_TRIM_MASK 0x3Fu
mbed_official 68:41613245dfd7 5646 #define VREF_TRM_TRIM_SHIFT 0
mbed_official 68:41613245dfd7 5647 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
mbed_official 68:41613245dfd7 5648 #define VREF_TRM_CHOPEN_MASK 0x40u
mbed_official 68:41613245dfd7 5649 #define VREF_TRM_CHOPEN_SHIFT 6
mbed_official 68:41613245dfd7 5650 /* SC Bit Fields */
mbed_official 68:41613245dfd7 5651 #define VREF_SC_MODE_LV_MASK 0x3u
mbed_official 68:41613245dfd7 5652 #define VREF_SC_MODE_LV_SHIFT 0
mbed_official 68:41613245dfd7 5653 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
mbed_official 68:41613245dfd7 5654 #define VREF_SC_VREFST_MASK 0x4u
mbed_official 68:41613245dfd7 5655 #define VREF_SC_VREFST_SHIFT 2
mbed_official 68:41613245dfd7 5656 #define VREF_SC_REGEN_MASK 0x40u
mbed_official 68:41613245dfd7 5657 #define VREF_SC_REGEN_SHIFT 6
mbed_official 68:41613245dfd7 5658 #define VREF_SC_VREFEN_MASK 0x80u
mbed_official 68:41613245dfd7 5659 #define VREF_SC_VREFEN_SHIFT 7
mbed_official 68:41613245dfd7 5660
mbed_official 68:41613245dfd7 5661 /**
mbed_official 68:41613245dfd7 5662 * @}
mbed_official 68:41613245dfd7 5663 */ /* end of group VREF_Register_Masks */
mbed_official 68:41613245dfd7 5664
mbed_official 68:41613245dfd7 5665
mbed_official 68:41613245dfd7 5666 /* VREF - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 5667 /** Peripheral VREF base address */
mbed_official 68:41613245dfd7 5668 #define VREF_BASE (0x40074000u)
mbed_official 68:41613245dfd7 5669 /** Peripheral VREF base pointer */
mbed_official 68:41613245dfd7 5670 #define VREF ((VREF_Type *)VREF_BASE)
mbed_official 68:41613245dfd7 5671
mbed_official 68:41613245dfd7 5672 /**
mbed_official 68:41613245dfd7 5673 * @}
mbed_official 68:41613245dfd7 5674 */ /* end of group VREF_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 5675
mbed_official 68:41613245dfd7 5676
mbed_official 68:41613245dfd7 5677 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5678 -- WDOG Peripheral Access Layer
mbed_official 68:41613245dfd7 5679 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5680
mbed_official 68:41613245dfd7 5681 /**
mbed_official 68:41613245dfd7 5682 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
mbed_official 68:41613245dfd7 5683 * @{
mbed_official 68:41613245dfd7 5684 */
mbed_official 68:41613245dfd7 5685
mbed_official 68:41613245dfd7 5686 /** WDOG - Register Layout Typedef */
mbed_official 68:41613245dfd7 5687 typedef struct {
mbed_official 68:41613245dfd7 5688 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
mbed_official 68:41613245dfd7 5689 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
mbed_official 68:41613245dfd7 5690 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
mbed_official 68:41613245dfd7 5691 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
mbed_official 68:41613245dfd7 5692 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
mbed_official 68:41613245dfd7 5693 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
mbed_official 68:41613245dfd7 5694 __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
mbed_official 68:41613245dfd7 5695 __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
mbed_official 68:41613245dfd7 5696 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
mbed_official 68:41613245dfd7 5697 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
mbed_official 68:41613245dfd7 5698 __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
mbed_official 68:41613245dfd7 5699 __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
mbed_official 68:41613245dfd7 5700 } WDOG_Type;
mbed_official 68:41613245dfd7 5701
mbed_official 68:41613245dfd7 5702 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5703 -- WDOG Register Masks
mbed_official 68:41613245dfd7 5704 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5705
mbed_official 68:41613245dfd7 5706 /**
mbed_official 68:41613245dfd7 5707 * @addtogroup WDOG_Register_Masks WDOG Register Masks
mbed_official 68:41613245dfd7 5708 * @{
mbed_official 68:41613245dfd7 5709 */
mbed_official 68:41613245dfd7 5710
mbed_official 68:41613245dfd7 5711 /* STCTRLH Bit Fields */
mbed_official 68:41613245dfd7 5712 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
mbed_official 68:41613245dfd7 5713 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
mbed_official 68:41613245dfd7 5714 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
mbed_official 68:41613245dfd7 5715 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
mbed_official 68:41613245dfd7 5716 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
mbed_official 68:41613245dfd7 5717 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
mbed_official 68:41613245dfd7 5718 #define WDOG_STCTRLH_WINEN_MASK 0x8u
mbed_official 68:41613245dfd7 5719 #define WDOG_STCTRLH_WINEN_SHIFT 3
mbed_official 68:41613245dfd7 5720 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
mbed_official 68:41613245dfd7 5721 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
mbed_official 68:41613245dfd7 5722 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
mbed_official 68:41613245dfd7 5723 #define WDOG_STCTRLH_DBGEN_SHIFT 5
mbed_official 68:41613245dfd7 5724 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
mbed_official 68:41613245dfd7 5725 #define WDOG_STCTRLH_STOPEN_SHIFT 6
mbed_official 68:41613245dfd7 5726 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
mbed_official 68:41613245dfd7 5727 #define WDOG_STCTRLH_WAITEN_SHIFT 7
mbed_official 68:41613245dfd7 5728 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
mbed_official 68:41613245dfd7 5729 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
mbed_official 68:41613245dfd7 5730 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
mbed_official 68:41613245dfd7 5731 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
mbed_official 68:41613245dfd7 5732 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
mbed_official 68:41613245dfd7 5733 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
mbed_official 68:41613245dfd7 5734 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
mbed_official 68:41613245dfd7 5735 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
mbed_official 68:41613245dfd7 5736 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
mbed_official 68:41613245dfd7 5737 /* STCTRLL Bit Fields */
mbed_official 68:41613245dfd7 5738 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
mbed_official 68:41613245dfd7 5739 #define WDOG_STCTRLL_INTFLG_SHIFT 15
mbed_official 68:41613245dfd7 5740 /* TOVALH Bit Fields */
mbed_official 68:41613245dfd7 5741 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5742 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
mbed_official 68:41613245dfd7 5743 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
mbed_official 68:41613245dfd7 5744 /* TOVALL Bit Fields */
mbed_official 68:41613245dfd7 5745 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5746 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
mbed_official 68:41613245dfd7 5747 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
mbed_official 68:41613245dfd7 5748 /* WINH Bit Fields */
mbed_official 68:41613245dfd7 5749 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5750 #define WDOG_WINH_WINHIGH_SHIFT 0
mbed_official 68:41613245dfd7 5751 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
mbed_official 68:41613245dfd7 5752 /* WINL Bit Fields */
mbed_official 68:41613245dfd7 5753 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5754 #define WDOG_WINL_WINLOW_SHIFT 0
mbed_official 68:41613245dfd7 5755 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
mbed_official 68:41613245dfd7 5756 /* REFRESH Bit Fields */
mbed_official 68:41613245dfd7 5757 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5758 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
mbed_official 68:41613245dfd7 5759 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
mbed_official 68:41613245dfd7 5760 /* UNLOCK Bit Fields */
mbed_official 68:41613245dfd7 5761 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5762 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
mbed_official 68:41613245dfd7 5763 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
mbed_official 68:41613245dfd7 5764 /* TMROUTH Bit Fields */
mbed_official 68:41613245dfd7 5765 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5766 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
mbed_official 68:41613245dfd7 5767 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
mbed_official 68:41613245dfd7 5768 /* TMROUTL Bit Fields */
mbed_official 68:41613245dfd7 5769 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5770 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
mbed_official 68:41613245dfd7 5771 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
mbed_official 68:41613245dfd7 5772 /* RSTCNT Bit Fields */
mbed_official 68:41613245dfd7 5773 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
mbed_official 68:41613245dfd7 5774 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
mbed_official 68:41613245dfd7 5775 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
mbed_official 68:41613245dfd7 5776 /* PRESC Bit Fields */
mbed_official 68:41613245dfd7 5777 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
mbed_official 68:41613245dfd7 5778 #define WDOG_PRESC_PRESCVAL_SHIFT 8
mbed_official 68:41613245dfd7 5779 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
mbed_official 68:41613245dfd7 5780
mbed_official 68:41613245dfd7 5781 /**
mbed_official 68:41613245dfd7 5782 * @}
mbed_official 68:41613245dfd7 5783 */ /* end of group WDOG_Register_Masks */
mbed_official 68:41613245dfd7 5784
mbed_official 68:41613245dfd7 5785
mbed_official 68:41613245dfd7 5786 /* WDOG - Peripheral instance base addresses */
mbed_official 68:41613245dfd7 5787 /** Peripheral WDOG base address */
mbed_official 68:41613245dfd7 5788 #define WDOG_BASE (0x40052000u)
mbed_official 68:41613245dfd7 5789 /** Peripheral WDOG base pointer */
mbed_official 68:41613245dfd7 5790 #define WDOG ((WDOG_Type *)WDOG_BASE)
mbed_official 68:41613245dfd7 5791
mbed_official 68:41613245dfd7 5792 /**
mbed_official 68:41613245dfd7 5793 * @}
mbed_official 68:41613245dfd7 5794 */ /* end of group WDOG_Peripheral_Access_Layer */
mbed_official 68:41613245dfd7 5795
mbed_official 68:41613245dfd7 5796
mbed_official 68:41613245dfd7 5797 /*
mbed_official 68:41613245dfd7 5798 ** End of section using anonymous unions
mbed_official 68:41613245dfd7 5799 */
mbed_official 68:41613245dfd7 5800
mbed_official 68:41613245dfd7 5801 #if defined(__ARMCC_VERSION)
mbed_official 68:41613245dfd7 5802 #pragma pop
mbed_official 68:41613245dfd7 5803 #elif defined(__CWCC__)
mbed_official 68:41613245dfd7 5804 #pragma pop
mbed_official 68:41613245dfd7 5805 #elif defined(__GNUC__)
mbed_official 68:41613245dfd7 5806 /* leave anonymous unions enabled */
mbed_official 68:41613245dfd7 5807 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 68:41613245dfd7 5808 #pragma language=default
mbed_official 68:41613245dfd7 5809 #else
mbed_official 68:41613245dfd7 5810 #error Not supported compiler type
mbed_official 68:41613245dfd7 5811 #endif
mbed_official 68:41613245dfd7 5812
mbed_official 68:41613245dfd7 5813 /**
mbed_official 68:41613245dfd7 5814 * @}
mbed_official 68:41613245dfd7 5815 */ /* end of group Peripheral_access_layer */
mbed_official 68:41613245dfd7 5816
mbed_official 68:41613245dfd7 5817
mbed_official 68:41613245dfd7 5818 /* ----------------------------------------------------------------------------
mbed_official 68:41613245dfd7 5819 -- Backward Compatibility
mbed_official 68:41613245dfd7 5820 ---------------------------------------------------------------------------- */
mbed_official 68:41613245dfd7 5821
mbed_official 68:41613245dfd7 5822 /**
mbed_official 68:41613245dfd7 5823 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 68:41613245dfd7 5824 * @{
mbed_official 68:41613245dfd7 5825 */
mbed_official 68:41613245dfd7 5826
mbed_official 68:41613245dfd7 5827 /* No backward compatibility issues. */
mbed_official 68:41613245dfd7 5828
mbed_official 68:41613245dfd7 5829 /**
mbed_official 68:41613245dfd7 5830 * @}
mbed_official 68:41613245dfd7 5831 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 68:41613245dfd7 5832
mbed_official 68:41613245dfd7 5833
mbed_official 68:41613245dfd7 5834 #endif /* #if !defined(MK20D5_H_) */
mbed_official 68:41613245dfd7 5835
mbed_official 68:41613245dfd7 5836 /* MK20D5.h, eof. */