Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC82X/spi_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 21 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 static const SWM_Map SWM_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 26 {4, 16},
<> 144:ef7eb2e8f9f7 27 {6, 8},
<> 144:ef7eb2e8f9f7 28 };
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 static const SWM_Map SWM_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 31 {3, 24},
<> 144:ef7eb2e8f9f7 32 {5, 16},
<> 144:ef7eb2e8f9f7 33 };
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 static const SWM_Map SWM_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 36 {4, 0},
<> 144:ef7eb2e8f9f7 37 {5, 24},
<> 144:ef7eb2e8f9f7 38 };
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 static const SWM_Map SWM_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 41 {4, 8},
<> 144:ef7eb2e8f9f7 42 {6, 0},
<> 144:ef7eb2e8f9f7 43 };
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 // bit flags for used SPIs
<> 144:ef7eb2e8f9f7 46 static unsigned char spi_used = 0;
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 static int get_available_spi(void)
<> 144:ef7eb2e8f9f7 49 {
<> 144:ef7eb2e8f9f7 50 int i;
<> 144:ef7eb2e8f9f7 51 for (i=0; i<2; i++) {
<> 144:ef7eb2e8f9f7 52 if ((spi_used & (1 << i)) == 0)
<> 144:ef7eb2e8f9f7 53 return i;
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55 return -1;
<> 144:ef7eb2e8f9f7 56 }
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 static inline void spi_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 59 static inline void spi_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 int spi_n = get_available_spi();
<> 144:ef7eb2e8f9f7 64 if (spi_n == -1) {
<> 144:ef7eb2e8f9f7 65 error("No available SPI");
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67 obj->spi_n = spi_n;
<> 144:ef7eb2e8f9f7 68 spi_used |= (1 << spi_n);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 73 uint32_t regVal;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 if (sclk != (PinName)NC) {
<> 144:ef7eb2e8f9f7 76 swm = &SWM_SPI_SCLK[obj->spi_n];
<> 144:ef7eb2e8f9f7 77 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 78 LPC_SWM->PINASSIGN[swm->n] = regVal | ((sclk >> PIN_SHIFT) << swm->offset);
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 if (mosi != (PinName)NC) {
<> 144:ef7eb2e8f9f7 82 swm = &SWM_SPI_MOSI[obj->spi_n];
<> 144:ef7eb2e8f9f7 83 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 84 LPC_SWM->PINASSIGN[swm->n] = regVal | ((mosi >> PIN_SHIFT) << swm->offset);
<> 144:ef7eb2e8f9f7 85 }
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 if (miso != (PinName)NC) {
<> 144:ef7eb2e8f9f7 88 swm = &SWM_SPI_MISO[obj->spi_n];
<> 144:ef7eb2e8f9f7 89 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 90 LPC_SWM->PINASSIGN[swm->n] = regVal | ((miso >> PIN_SHIFT) << swm->offset);
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 if (ssel != (PinName)NC) {
<> 144:ef7eb2e8f9f7 94 swm = &SWM_SPI_SSEL[obj->spi_n];
<> 144:ef7eb2e8f9f7 95 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 96 LPC_SWM->PINASSIGN[swm->n] = regVal | ((ssel >> PIN_SHIFT) << swm->offset);
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 // clear interrupts
<> 144:ef7eb2e8f9f7 100 obj->spi->INTENCLR = 0x3f;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (11 + obj->spi_n));
<> 144:ef7eb2e8f9f7 103 LPC_SYSCON->PRESETCTRL &= ~(1 << obj->spi_n);
<> 144:ef7eb2e8f9f7 104 LPC_SYSCON->PRESETCTRL |= (1 << obj->spi_n);
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 obj->spi->DLY = 2; // 2 SPI clock times pre-delay
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 void spi_free(spi_t *obj)
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
<> 144:ef7eb2e8f9f7 116 spi_disable(obj);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 obj->spi->CFG &= ~((0x3 << 4) | (1 << 2));
<> 144:ef7eb2e8f9f7 119 obj->spi->CFG |= ((mode & 0x3) << 4) | ((slave ? 0 : 1) << 2);
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 obj->spi->TXCTL &= ~( 0xF << 24);
<> 144:ef7eb2e8f9f7 122 obj->spi->TXCTL |= ((bits - 1) << 24);
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 spi_enable(obj);
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 void spi_frequency(spi_t *obj, int hz)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 spi_disable(obj);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 // rise DIV value if it cannot be divided
<> 144:ef7eb2e8f9f7 132 obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 spi_enable(obj);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 static inline void spi_disable(spi_t *obj)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 obj->spi->CFG &= ~(1 << 0);
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 static inline void spi_enable(spi_t *obj)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 obj->spi->CFG |= (1 << 0);
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 static inline int spi_readable(spi_t *obj)
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 return obj->spi->STAT & (1 << 0);
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 static inline int spi_writeable(spi_t *obj)
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 return obj->spi->STAT & (1 << 1);
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 static inline void spi_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 while (!spi_writeable(obj));
<> 144:ef7eb2e8f9f7 160 // end of transfer
<> 144:ef7eb2e8f9f7 161 obj->spi->TXCTL |= (1 << 20);
<> 144:ef7eb2e8f9f7 162 obj->spi->TXDAT = (value & 0xffff);
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 static inline int spi_read(spi_t *obj)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 while (!spi_readable(obj));
<> 144:ef7eb2e8f9f7 168 return (obj->spi->RXDAT & 0xFFFF);
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 int spi_master_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 spi_write(obj, value);
<> 144:ef7eb2e8f9f7 174 return spi_read(obj);
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 int spi_busy(spi_t *obj)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 // checking RXOV(Receiver Overrun interrupt flag)
<> 144:ef7eb2e8f9f7 180 return obj->spi->STAT & (1 << 2);
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 int spi_slave_receive(spi_t *obj)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 int spi_slave_read(spi_t *obj)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 return (obj->spi->RXDAT & 0xFFFF);
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 void spi_slave_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 while (spi_writeable(obj) == 0);
<> 144:ef7eb2e8f9f7 196 obj->spi->TXDAT = value;
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #endif