Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32620/device/max32620.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Maxim/TARGET_MAX32620/max32620.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MAX32620_H_
<> 144:ef7eb2e8f9f7 35 #define _MAX32620_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #include <stdint.h>
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifndef FALSE
<> 144:ef7eb2e8f9f7 40 #define FALSE (0)
<> 144:ef7eb2e8f9f7 41 #endif
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifndef TRUE
<> 144:ef7eb2e8f9f7 44 #define TRUE (1)
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
<> 144:ef7eb2e8f9f7 48 #if defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 49 #define __weak __attribute__((weak))
<> 144:ef7eb2e8f9f7 50 #endif /* __GNUC__ */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 NonMaskableInt_IRQn = -14,
<> 144:ef7eb2e8f9f7 54 HardFault_IRQn = -13,
<> 144:ef7eb2e8f9f7 55 MemoryManagement_IRQn = -12,
<> 144:ef7eb2e8f9f7 56 BusFault_IRQn = -11,
<> 144:ef7eb2e8f9f7 57 UsageFault_IRQn = -10,
<> 144:ef7eb2e8f9f7 58 SVCall_IRQn = -5,
<> 144:ef7eb2e8f9f7 59 DebugMonitor_IRQn = -4,
<> 144:ef7eb2e8f9f7 60 PendSV_IRQn = -2,
<> 144:ef7eb2e8f9f7 61 SysTick_IRQn = -1,
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Device-specific interrupt sources (external to ARM core) */
<> 144:ef7eb2e8f9f7 64 /* table entry number */
<> 144:ef7eb2e8f9f7 65 /* |||| */
<> 144:ef7eb2e8f9f7 66 /* |||| table offset address */
<> 144:ef7eb2e8f9f7 67 /* vvvv vvvvvv */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 CLKMAN_IRQn = 0, /* 0x10 0x0040 CLKMAN */
<> 144:ef7eb2e8f9f7 70 PWRMAN_IRQn, /* 0x11 0x0044 PWRMAN */
<> 144:ef7eb2e8f9f7 71 FLC_IRQn, /* 0x12 0x0048 Flash Controller */
<> 144:ef7eb2e8f9f7 72 RTC0_IRQn, /* 0x13 0x004C RTC Counter match with Compare 0 */
<> 144:ef7eb2e8f9f7 73 RTC1_IRQn, /* 0x14 0x0050 RTC Counter match with Compare 1 */
<> 144:ef7eb2e8f9f7 74 RTC2_IRQn, /* 0x15 0x0054 RTC Prescaler interval compare match */
<> 144:ef7eb2e8f9f7 75 RTC3_IRQn, /* 0x16 0x0058 RTC Overflow */
<> 144:ef7eb2e8f9f7 76 PMU_IRQn, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */
<> 144:ef7eb2e8f9f7 77 USB_IRQn, /* 0x18 0x0060 USB */
<> 144:ef7eb2e8f9f7 78 AES_IRQn, /* 0x19 0x0064 AES */
<> 144:ef7eb2e8f9f7 79 MAA_IRQn, /* 0x1A 0x0068 MAA */
<> 144:ef7eb2e8f9f7 80 WDT0_IRQn, /* 0x1B 0x006C Watchdog 0 timeout */
<> 144:ef7eb2e8f9f7 81 WDT0_P_IRQn, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
<> 144:ef7eb2e8f9f7 82 WDT1_IRQn, /* 0x1D 0x0074 Watchdog 1 timeout */
<> 144:ef7eb2e8f9f7 83 WDT1_P_IRQn, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
<> 144:ef7eb2e8f9f7 84 GPIO_P0_IRQn, /* 0x1F 0x007C GPIO Port 0 */
<> 144:ef7eb2e8f9f7 85 GPIO_P1_IRQn, /* 0x20 0x0080 GPIO Port 1 */
<> 144:ef7eb2e8f9f7 86 GPIO_P2_IRQn, /* 0x21 0x0084 GPIO Port 2 */
<> 144:ef7eb2e8f9f7 87 GPIO_P3_IRQn, /* 0x22 0x0088 GPIO Port 3 */
<> 144:ef7eb2e8f9f7 88 GPIO_P4_IRQn, /* 0x23 0x008C GPIO Port 4 */
<> 144:ef7eb2e8f9f7 89 GPIO_P5_IRQn, /* 0x24 0x0090 GPIO Port 5 */
<> 144:ef7eb2e8f9f7 90 GPIO_P6_IRQn, /* 0x25 0x0094 GPIO Port 6 */
<> 144:ef7eb2e8f9f7 91 TMR0_0_IRQn, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */
<> 144:ef7eb2e8f9f7 92 TMR0_1_IRQn, /* 0x27 0x009C Timer 0 (16-bit #1) */
<> 144:ef7eb2e8f9f7 93 TMR1_0_IRQn, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */
<> 144:ef7eb2e8f9f7 94 TMR1_1_IRQn, /* 0x29 0x00A4 Timer 1 (16-bit #1) */
<> 144:ef7eb2e8f9f7 95 TMR2_0_IRQn, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */
<> 144:ef7eb2e8f9f7 96 TMR2_1_IRQn, /* 0x2B 0x00AC Timer 2 (16-bit #1) */
<> 144:ef7eb2e8f9f7 97 TMR3_0_IRQn, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */
<> 144:ef7eb2e8f9f7 98 TMR3_1_IRQn, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */
<> 144:ef7eb2e8f9f7 99 TMR4_0_IRQn, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */
<> 144:ef7eb2e8f9f7 100 TMR4_1_IRQn, /* 0x2F 0x00BC Timer 4 (16-bit #1) */
<> 144:ef7eb2e8f9f7 101 TMR5_0_IRQn, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */
<> 144:ef7eb2e8f9f7 102 TMR5_1_IRQn, /* 0x31 0x00C4 Timer 5 (16-bit #1) */
<> 144:ef7eb2e8f9f7 103 UART0_IRQn, /* 0x32 0x00C8 UART 0 */
<> 144:ef7eb2e8f9f7 104 UART1_IRQn, /* 0x33 0x00CC UART 1 */
<> 144:ef7eb2e8f9f7 105 UART2_IRQn, /* 0x34 0x00D0 UART 2 */
<> 144:ef7eb2e8f9f7 106 UART3_IRQn, /* 0x35 0x00D4 UART 3 */
<> 144:ef7eb2e8f9f7 107 PT_IRQn, /* 0x36 0x00D8 Pulse Trains */
<> 144:ef7eb2e8f9f7 108 I2CM0_IRQn, /* 0x37 0x00DC I2C Master 0 */
<> 144:ef7eb2e8f9f7 109 I2CM1_IRQn, /* 0x38 0x00E0 I2C Master 1 */
<> 144:ef7eb2e8f9f7 110 I2CM2_IRQn, /* 0x39 0x00E4 I2C Master 2 */
<> 144:ef7eb2e8f9f7 111 I2CS0_IRQn, /* 0x3A 0x00E8 I2C Slave */
<> 144:ef7eb2e8f9f7 112 SPI0_IRQn, /* 0x3B 0x00EC SPI Master 0 */
<> 144:ef7eb2e8f9f7 113 SPI1_IRQn, /* 0x3C 0x00F0 SPI Master 1 */
<> 144:ef7eb2e8f9f7 114 SPI2_IRQn, /* 0x3D 0x00F4 SPI Master 2 */
<> 144:ef7eb2e8f9f7 115 SPIB_IRQn, /* 0x3E 0x00F8 SPI Bridge */
<> 144:ef7eb2e8f9f7 116 OWM_IRQn, /* 0x3F 0x00FC 1-Wire Master */
<> 144:ef7eb2e8f9f7 117 AFE_IRQn, /* 0x40 0x0100 Analog Front End, ADC */
<> 144:ef7eb2e8f9f7 118 MXC_IRQ_EXT_COUNT,
<> 144:ef7eb2e8f9f7 119 } IRQn_Type;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 125 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 126 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
<> 144:ef7eb2e8f9f7 129 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
<> 144:ef7eb2e8f9f7 130 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 131 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 132 #define __Vendor_SysTickConfig 1 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 133 #define __FPU_PRESENT 1 /*!< FPU present or not */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
<> 144:ef7eb2e8f9f7 136 #include "system_max32620.h" /*!< System Header */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 140 /* ================== Device Specific Memory Section ================== */
<> 144:ef7eb2e8f9f7 141 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #define MXC_FLASH_MEM_BASE 0x00000000UL
<> 144:ef7eb2e8f9f7 144 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
<> 144:ef7eb2e8f9f7 145 #define MXC_FLASH_MEM_SIZE 0x00100000UL
<> 144:ef7eb2e8f9f7 146 #define MXC_SYS_MEM_BASE 0x20000000UL
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 150 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 151 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /*
<> 144:ef7eb2e8f9f7 155 Base addresses and configuration settings for all MAX32620 peripheral modules.
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 160 /* System Clock Manager */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
<> 144:ef7eb2e8f9f7 163 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 168 /* System Power Manager */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
<> 144:ef7eb2e8f9f7 171 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 176 /* Real Time Clock */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 #define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
<> 144:ef7eb2e8f9f7 179 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
<> 144:ef7eb2e8f9f7 180 #define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
<> 144:ef7eb2e8f9f7 181 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
<> 144:ef7eb2e8f9f7 184 i == 1 ? RTC1_IRQn : \
<> 144:ef7eb2e8f9f7 185 i == 2 ? RTC2_IRQn : \
<> 144:ef7eb2e8f9f7 186 i == 3 ? RTC3_IRQn : 0)
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 191 /* Power Sequencer */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
<> 144:ef7eb2e8f9f7 194 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 199 /* System I/O Manager */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 #define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL)
<> 144:ef7eb2e8f9f7 202 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 207 /* Shadow Trim Registers */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
<> 144:ef7eb2e8f9f7 210 #define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 215 /* Flash Controller */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define MXC_BASE_FLC ((uint32_t)0x40002000UL)
<> 144:ef7eb2e8f9f7 218 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #define MXC_FLC_PAGE_SIZE_SHIFT (13)
<> 144:ef7eb2e8f9f7 221 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
<> 144:ef7eb2e8f9f7 222 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 227 /* Instruction Cache */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 #define MXC_BASE_ICC ((uint32_t)0x40003000UL)
<> 144:ef7eb2e8f9f7 230 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 235 /* SPI XIP Interface */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #define MXC_BASE_SPIX ((uint32_t)0x40004000UL)
<> 144:ef7eb2e8f9f7 238 #define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX)
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 243 /* Peripheral Management Unit */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 #define MXC_CFG_PMU_CHANNELS (6)
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
<> 144:ef7eb2e8f9f7 248 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
<> 144:ef7eb2e8f9f7 249 #define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
<> 144:ef7eb2e8f9f7 250 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
<> 144:ef7eb2e8f9f7 251 #define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
<> 144:ef7eb2e8f9f7 252 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
<> 144:ef7eb2e8f9f7 253 #define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
<> 144:ef7eb2e8f9f7 254 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
<> 144:ef7eb2e8f9f7 255 #define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
<> 144:ef7eb2e8f9f7 256 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
<> 144:ef7eb2e8f9f7 257 #define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
<> 144:ef7eb2e8f9f7 258 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 #define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
<> 144:ef7eb2e8f9f7 261 (i) == 1 ? MXC_BASE_PMU1 : \
<> 144:ef7eb2e8f9f7 262 (i) == 2 ? MXC_BASE_PMU2 : \
<> 144:ef7eb2e8f9f7 263 (i) == 3 ? MXC_BASE_PMU3 : \
<> 144:ef7eb2e8f9f7 264 (i) == 4 ? MXC_BASE_PMU4 : \
<> 144:ef7eb2e8f9f7 265 (i) == 5 ? MXC_BASE_PMU5 : 0)
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 #define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
<> 144:ef7eb2e8f9f7 268 (i) == 1 ? MXC_PMU1 : \
<> 144:ef7eb2e8f9f7 269 (i) == 2 ? MXC_PMU2 : \
<> 144:ef7eb2e8f9f7 270 (i) == 3 ? MXC_PMU3 : \
<> 144:ef7eb2e8f9f7 271 (i) == 4 ? MXC_PMU4 : \
<> 144:ef7eb2e8f9f7 272 (i) == 5 ? MXC_PMU5 : 0)
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 #define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
<> 144:ef7eb2e8f9f7 275 (p) == MXC_PMU1 ? 1 : \
<> 144:ef7eb2e8f9f7 276 (p) == MXC_PMU2 ? 2 : \
<> 144:ef7eb2e8f9f7 277 (p) == MXC_PMU3 ? 3 : \
<> 144:ef7eb2e8f9f7 278 (p) == MXC_PMU4 ? 4 : \
<> 144:ef7eb2e8f9f7 279 (p) == MXC_PMU5 ? 5 : -1)
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 288 /* USB Device Controller */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #define MXC_BASE_USB ((uint32_t)0x40100000UL)
<> 144:ef7eb2e8f9f7 291 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 #define MXC_USB_MAX_PACKET (64)
<> 144:ef7eb2e8f9f7 294 #define MXC_USB_NUM_EP (8)
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 299 /* CRC-16/CRC-32 Engine */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #define MXC_BASE_CRC ((uint32_t)0x40006000UL)
<> 144:ef7eb2e8f9f7 302 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
<> 144:ef7eb2e8f9f7 303 #define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
<> 144:ef7eb2e8f9f7 304 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 309 /* Trust Protection Unit (TPU) */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 #define MXC_BASE_TPU ((uint32_t)0x40007000UL)
<> 144:ef7eb2e8f9f7 312 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
<> 144:ef7eb2e8f9f7 313 #define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
<> 144:ef7eb2e8f9f7 314 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 319 /* AES Cryptographic Engine */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #define MXC_BASE_AES ((uint32_t)0x40007400UL)
<> 144:ef7eb2e8f9f7 322 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
<> 144:ef7eb2e8f9f7 323 #define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
<> 144:ef7eb2e8f9f7 324 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 329 /* MAA Cryptographic Engine */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 #define MXC_BASE_MAA ((uint32_t)0x40007800UL)
<> 144:ef7eb2e8f9f7 332 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
<> 144:ef7eb2e8f9f7 333 #define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
<> 144:ef7eb2e8f9f7 334 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 339 /* Watchdog Timers */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 #define MXC_CFG_WDT_INSTANCES (2)
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 #define MXC_BASE_WDT0 ((uint32_t)0x40008000UL)
<> 144:ef7eb2e8f9f7 344 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
<> 144:ef7eb2e8f9f7 345 #define MXC_BASE_WDT1 ((uint32_t)0x40009000UL)
<> 144:ef7eb2e8f9f7 346 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
<> 144:ef7eb2e8f9f7 349 (i) == 1 ? WDT1_IRQn : 0)
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
<> 144:ef7eb2e8f9f7 352 (i) == 1 ? WDT1_P_IRQn : 0)
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
<> 144:ef7eb2e8f9f7 355 (i) == 1 ? MXC_BASE_WDT1 : 0)
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
<> 144:ef7eb2e8f9f7 358 (i) == 1 ? MXC_WDT1 : 0)
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 #define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: (i) == MXC_WDT1 ? 1: -1)
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 365 /* General Purpose I/O Ports (GPIO) */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #define MXC_GPIO_NUM_PORTS (7)
<> 144:ef7eb2e8f9f7 368 #define MXC_GPIO_MAX_PINS_PER_PORT (8)
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 #define MXC_BASE_GPIO ((uint32_t)0x4000A000UL)
<> 144:ef7eb2e8f9f7 371 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO_P0_IRQn : \
<> 144:ef7eb2e8f9f7 374 (i) == 1 ? GPIO_P1_IRQn : \
<> 144:ef7eb2e8f9f7 375 (i) == 2 ? GPIO_P2_IRQn : \
<> 144:ef7eb2e8f9f7 376 (i) == 3 ? GPIO_P3_IRQn : \
<> 144:ef7eb2e8f9f7 377 (i) == 4 ? GPIO_P4_IRQn : \
<> 144:ef7eb2e8f9f7 378 (i) == 5 ? GPIO_P5_IRQn : \
<> 144:ef7eb2e8f9f7 379 (i) == 6 ? GPIO_P6_IRQn : 0)
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 384 /* 16/32 bit Timer/Counters */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 #define MXC_CFG_TMR_INSTANCES (6)
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 #define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL)
<> 144:ef7eb2e8f9f7 389 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
<> 144:ef7eb2e8f9f7 390 #define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL)
<> 144:ef7eb2e8f9f7 391 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
<> 144:ef7eb2e8f9f7 392 #define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL)
<> 144:ef7eb2e8f9f7 393 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
<> 144:ef7eb2e8f9f7 394 #define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL)
<> 144:ef7eb2e8f9f7 395 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
<> 144:ef7eb2e8f9f7 396 #define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL)
<> 144:ef7eb2e8f9f7 397 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
<> 144:ef7eb2e8f9f7 398 #define MXC_BASE_TMR5 ((uint32_t)0x40010000UL)
<> 144:ef7eb2e8f9f7 399 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_0_IRQn : \
<> 144:ef7eb2e8f9f7 402 (i) == 1 ? TMR1_0_IRQn : \
<> 144:ef7eb2e8f9f7 403 (i) == 2 ? TMR2_0_IRQn : \
<> 144:ef7eb2e8f9f7 404 (i) == 3 ? TMR3_0_IRQn : \
<> 144:ef7eb2e8f9f7 405 (i) == 4 ? TMR4_0_IRQn : \
<> 144:ef7eb2e8f9f7 406 (i) == 5 ? TMR5_0_IRQn : 0)
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_0_IRQn : \
<> 144:ef7eb2e8f9f7 409 (i) == 1 ? TMR1_0_IRQn : \
<> 144:ef7eb2e8f9f7 410 (i) == 2 ? TMR2_0_IRQn : \
<> 144:ef7eb2e8f9f7 411 (i) == 3 ? TMR3_0_IRQn : \
<> 144:ef7eb2e8f9f7 412 (i) == 4 ? TMR4_0_IRQn : \
<> 144:ef7eb2e8f9f7 413 (i) == 5 ? TMR5_0_IRQn : \
<> 144:ef7eb2e8f9f7 414 (i) == 6 ? TMR0_1_IRQn : \
<> 144:ef7eb2e8f9f7 415 (i) == 7 ? TMR1_1_IRQn : \
<> 144:ef7eb2e8f9f7 416 (i) == 8 ? TMR2_1_IRQn : \
<> 144:ef7eb2e8f9f7 417 (i) == 9 ? TMR3_1_IRQn : \
<> 144:ef7eb2e8f9f7 418 (i) == 10 ? TMR4_1_IRQn : \
<> 144:ef7eb2e8f9f7 419 (i) == 11 ? TMR5_1_IRQn : 0)
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
<> 144:ef7eb2e8f9f7 422 (i) == 1 ? MXC_BASE_TMR1 : \
<> 144:ef7eb2e8f9f7 423 (i) == 2 ? MXC_BASE_TMR2 : \
<> 144:ef7eb2e8f9f7 424 (i) == 3 ? MXC_BASE_TMR3 : \
<> 144:ef7eb2e8f9f7 425 (i) == 4 ? MXC_BASE_TMR4 : \
<> 144:ef7eb2e8f9f7 426 (i) == 5 ? MXC_BASE_TMR5 : 0)
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
<> 144:ef7eb2e8f9f7 429 (i) == 1 ? MXC_TMR1 : \
<> 144:ef7eb2e8f9f7 430 (i) == 2 ? MXC_TMR2 : \
<> 144:ef7eb2e8f9f7 431 (i) == 3 ? MXC_TMR3 : \
<> 144:ef7eb2e8f9f7 432 (i) == 4 ? MXC_TMR4 : \
<> 144:ef7eb2e8f9f7 433 (i) == 5 ? MXC_TMR5 : 0)
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
<> 144:ef7eb2e8f9f7 436 (p) == MXC_TMR1 ? 1 : \
<> 144:ef7eb2e8f9f7 437 (p) == MXC_TMR2 ? 2 : \
<> 144:ef7eb2e8f9f7 438 (p) == MXC_TMR3 ? 3 : \
<> 144:ef7eb2e8f9f7 439 (p) == MXC_TMR4 ? 4 : \
<> 144:ef7eb2e8f9f7 440 (p) == MXC_TMR5 ? 5 : -1)
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 446 /* Pulse Train Generation */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 #define MXC_CFG_PT_INSTANCES (16)
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #define MXC_BASE_PTG ((uint32_t)0x40011000UL)
<> 144:ef7eb2e8f9f7 451 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
<> 144:ef7eb2e8f9f7 452 #define MXC_BASE_PT0 ((uint32_t)0x40011010UL)
<> 144:ef7eb2e8f9f7 453 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
<> 144:ef7eb2e8f9f7 454 #define MXC_BASE_PT1 ((uint32_t)0x4001101CUL)
<> 144:ef7eb2e8f9f7 455 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
<> 144:ef7eb2e8f9f7 456 #define MXC_BASE_PT2 ((uint32_t)0x40011028UL)
<> 144:ef7eb2e8f9f7 457 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
<> 144:ef7eb2e8f9f7 458 #define MXC_BASE_PT3 ((uint32_t)0x40011034UL)
<> 144:ef7eb2e8f9f7 459 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
<> 144:ef7eb2e8f9f7 460 #define MXC_BASE_PT4 ((uint32_t)0x40011040UL)
<> 144:ef7eb2e8f9f7 461 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
<> 144:ef7eb2e8f9f7 462 #define MXC_BASE_PT5 ((uint32_t)0x4001104CUL)
<> 144:ef7eb2e8f9f7 463 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
<> 144:ef7eb2e8f9f7 464 #define MXC_BASE_PT6 ((uint32_t)0x40011058UL)
<> 144:ef7eb2e8f9f7 465 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
<> 144:ef7eb2e8f9f7 466 #define MXC_BASE_PT7 ((uint32_t)0x40011064UL)
<> 144:ef7eb2e8f9f7 467 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
<> 144:ef7eb2e8f9f7 468 #define MXC_BASE_PT8 ((uint32_t)0x40011070UL)
<> 144:ef7eb2e8f9f7 469 #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
<> 144:ef7eb2e8f9f7 470 #define MXC_BASE_PT9 ((uint32_t)0x4001107CUL)
<> 144:ef7eb2e8f9f7 471 #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
<> 144:ef7eb2e8f9f7 472 #define MXC_BASE_PT10 ((uint32_t)0x40011088UL)
<> 144:ef7eb2e8f9f7 473 #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
<> 144:ef7eb2e8f9f7 474 #define MXC_BASE_PT11 ((uint32_t)0x40011094UL)
<> 144:ef7eb2e8f9f7 475 #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
<> 144:ef7eb2e8f9f7 476 #define MXC_BASE_PT12 ((uint32_t)0x400110A0UL)
<> 144:ef7eb2e8f9f7 477 #define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
<> 144:ef7eb2e8f9f7 478 #define MXC_BASE_PT13 ((uint32_t)0x400110ACUL)
<> 144:ef7eb2e8f9f7 479 #define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
<> 144:ef7eb2e8f9f7 480 #define MXC_BASE_PT14 ((uint32_t)0x400110B8UL)
<> 144:ef7eb2e8f9f7 481 #define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
<> 144:ef7eb2e8f9f7 482 #define MXC_BASE_PT15 ((uint32_t)0x400110C4UL)
<> 144:ef7eb2e8f9f7 483 #define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
<> 144:ef7eb2e8f9f7 486 (i) == 1 ? MXC_BASE_PT1 : \
<> 144:ef7eb2e8f9f7 487 (i) == 2 ? MXC_BASE_PT2 : \
<> 144:ef7eb2e8f9f7 488 (i) == 3 ? MXC_BASE_PT3 : \
<> 144:ef7eb2e8f9f7 489 (i) == 4 ? MXC_BASE_PT4 : \
<> 144:ef7eb2e8f9f7 490 (i) == 5 ? MXC_BASE_PT5 : \
<> 144:ef7eb2e8f9f7 491 (i) == 6 ? MXC_BASE_PT6 : \
<> 144:ef7eb2e8f9f7 492 (i) == 7 ? MXC_BASE_PT7 : \
<> 144:ef7eb2e8f9f7 493 (i) == 8 ? MXC_BASE_PT8 : \
<> 144:ef7eb2e8f9f7 494 (i) == 9 ? MXC_BASE_PT9 : \
<> 144:ef7eb2e8f9f7 495 (i) == 10 ? MXC_BASE_PT10 : \
<> 144:ef7eb2e8f9f7 496 (i) == 11 ? MXC_BASE_PT11 : \
<> 144:ef7eb2e8f9f7 497 (i) == 12 ? MXC_BASE_PT12 : \
<> 144:ef7eb2e8f9f7 498 (i) == 13 ? MXC_BASE_PT13 : \
<> 144:ef7eb2e8f9f7 499 (i) == 14 ? MXC_BASE_PT14 : \
<> 144:ef7eb2e8f9f7 500 (i) == 15 ? MXC_BASE_PT15 : 0)
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
<> 144:ef7eb2e8f9f7 503 (i) == 1 ? MXC_PT1 : \
<> 144:ef7eb2e8f9f7 504 (i) == 2 ? MXC_PT2 : \
<> 144:ef7eb2e8f9f7 505 (i) == 3 ? MXC_PT3 : \
<> 144:ef7eb2e8f9f7 506 (i) == 4 ? MXC_PT4 : \
<> 144:ef7eb2e8f9f7 507 (i) == 5 ? MXC_PT5 : \
<> 144:ef7eb2e8f9f7 508 (i) == 6 ? MXC_PT6 : \
<> 144:ef7eb2e8f9f7 509 (i) == 7 ? MXC_PT7 : \
<> 144:ef7eb2e8f9f7 510 (i) == 8 ? MXC_PT8 : \
<> 144:ef7eb2e8f9f7 511 (i) == 9 ? MXC_PT9 : \
<> 144:ef7eb2e8f9f7 512 (i) == 10 ? MXC_PT10 : \
<> 144:ef7eb2e8f9f7 513 (i) == 11 ? MXC_PT11 : \
<> 144:ef7eb2e8f9f7 514 (i) == 12 ? MXC_PT12 : \
<> 144:ef7eb2e8f9f7 515 (i) == 13 ? MXC_PT13 : \
<> 144:ef7eb2e8f9f7 516 (i) == 14 ? MXC_PT14 : \
<> 144:ef7eb2e8f9f7 517 (i) == 15 ? MXC_PT15 : 0)
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
<> 144:ef7eb2e8f9f7 520 (p) == MXC_PT1 ? 1 : \
<> 144:ef7eb2e8f9f7 521 (p) == MXC_PT2 ? 2 : \
<> 144:ef7eb2e8f9f7 522 (p) == MXC_PT3 ? 3 : \
<> 144:ef7eb2e8f9f7 523 (p) == MXC_PT4 ? 4 : \
<> 144:ef7eb2e8f9f7 524 (p) == MXC_PT5 ? 5 : \
<> 144:ef7eb2e8f9f7 525 (p) == MXC_PT6 ? 6 : \
<> 144:ef7eb2e8f9f7 526 (p) == MXC_PT7 ? 7 : \
<> 144:ef7eb2e8f9f7 527 (p) == MXC_PT8 ? 8 : \
<> 144:ef7eb2e8f9f7 528 (p) == MXC_PT9 ? 9 : \
<> 144:ef7eb2e8f9f7 529 (p) == MXC_PT10 ? 10 : \
<> 144:ef7eb2e8f9f7 530 (p) == MXC_PT11 ? 11 : \
<> 144:ef7eb2e8f9f7 531 (p) == MXC_PT12 ? 12 : \
<> 144:ef7eb2e8f9f7 532 (p) == MXC_PT13 ? 13 : \
<> 144:ef7eb2e8f9f7 533 (p) == MXC_PT14 ? 14 : \
<> 144:ef7eb2e8f9f7 534 (p) == MXC_PT15 ? 15 : -1)
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 539 /* UART / Serial Port Interface */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 #define MXC_CFG_UART_INSTANCES (4)
<> 144:ef7eb2e8f9f7 542 #define MXC_UART_FIFO_DEPTH (32)
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 #define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
<> 144:ef7eb2e8f9f7 545 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
<> 144:ef7eb2e8f9f7 546 #define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
<> 144:ef7eb2e8f9f7 547 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
<> 144:ef7eb2e8f9f7 548 #define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
<> 144:ef7eb2e8f9f7 549 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
<> 144:ef7eb2e8f9f7 550 #define MXC_BASE_UART3 ((uint32_t)0x40015000UL)
<> 144:ef7eb2e8f9f7 551 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
<> 144:ef7eb2e8f9f7 552 #define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
<> 144:ef7eb2e8f9f7 553 #define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
<> 144:ef7eb2e8f9f7 554 #define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
<> 144:ef7eb2e8f9f7 555 #define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
<> 144:ef7eb2e8f9f7 556 #define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
<> 144:ef7eb2e8f9f7 557 #define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
<> 144:ef7eb2e8f9f7 558 #define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL)
<> 144:ef7eb2e8f9f7 559 #define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
<> 144:ef7eb2e8f9f7 562 (i) == 1 ? UART1_IRQn : \
<> 144:ef7eb2e8f9f7 563 (i) == 2 ? UART2_IRQn : \
<> 144:ef7eb2e8f9f7 564 (i) == 3 ? UART3_IRQn : 0)
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
<> 144:ef7eb2e8f9f7 567 (i) == 1 ? MXC_BASE_UART1 : \
<> 144:ef7eb2e8f9f7 568 (i) == 2 ? MXC_BASE_UART2 : \
<> 144:ef7eb2e8f9f7 569 (i) == 3 ? MXC_BASE_UART3 : 0)
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
<> 144:ef7eb2e8f9f7 572 (i) == 1 ? MXC_UART1 : \
<> 144:ef7eb2e8f9f7 573 (i) == 2 ? MXC_UART2 : \
<> 144:ef7eb2e8f9f7 574 (i) == 3 ? MXC_UART3 : 0)
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
<> 144:ef7eb2e8f9f7 577 (p) == MXC_UART1 ? 1 : \
<> 144:ef7eb2e8f9f7 578 (p) == MXC_UART2 ? 2 : \
<> 144:ef7eb2e8f9f7 579 (p) == MXC_UART3 ? 3 : -1)
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 #define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
<> 144:ef7eb2e8f9f7 582 (i) == 1 ? MXC_BASE_UART1_FIFO : \
<> 144:ef7eb2e8f9f7 583 (i) == 2 ? MXC_BASE_UART2_FIFO : \
<> 144:ef7eb2e8f9f7 584 (i) == 3 ? MXC_BASE_UART3_FIFO : 0)
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 #define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
<> 144:ef7eb2e8f9f7 587 (i) == 1 ? MXC_UART1_FIFO : \
<> 144:ef7eb2e8f9f7 588 (i) == 2 ? MXC_UART2_FIFO : \
<> 144:ef7eb2e8f9f7 589 (i) == 3 ? MXC_UART3_FIFO : 0)
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 594 /* I2C Master Interface */
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 #define MXC_CFG_I2CM_INSTANCES (3)
<> 144:ef7eb2e8f9f7 597 #define MXC_I2CM_FIFO_DEPTH (8)
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 #define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
<> 144:ef7eb2e8f9f7 600 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
<> 144:ef7eb2e8f9f7 601 #define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
<> 144:ef7eb2e8f9f7 602 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
<> 144:ef7eb2e8f9f7 603 #define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL)
<> 144:ef7eb2e8f9f7 604 #define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
<> 144:ef7eb2e8f9f7 605 #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
<> 144:ef7eb2e8f9f7 606 #define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
<> 144:ef7eb2e8f9f7 607 #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
<> 144:ef7eb2e8f9f7 608 #define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
<> 144:ef7eb2e8f9f7 609 #define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL)
<> 144:ef7eb2e8f9f7 610 #define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 #define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
<> 144:ef7eb2e8f9f7 613 (i) == 1 ? I2CM1_IRQn : \
<> 144:ef7eb2e8f9f7 614 (i) == 2 ? I2CM2_IRQn : 0)
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
<> 144:ef7eb2e8f9f7 617 (i) == 1 ? MXC_BASE_I2CM1 : \
<> 144:ef7eb2e8f9f7 618 (i) == 2 ? MXC_BASE_I2CM2 : 0)
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
<> 144:ef7eb2e8f9f7 621 (i) == 1 ? MXC_I2CM1 : \
<> 144:ef7eb2e8f9f7 622 (i) == 2 ? MXC_I2CM2 : 0)
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 #define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
<> 144:ef7eb2e8f9f7 625 (p) == MXC_I2CM1 ? 1 : \
<> 144:ef7eb2e8f9f7 626 (p) == MXC_I2CM2 ? 2 : -1)
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
<> 144:ef7eb2e8f9f7 629 (i) == 1 ? MXC_BASE_I2CM1_FIFO : \
<> 144:ef7eb2e8f9f7 630 (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 #define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
<> 144:ef7eb2e8f9f7 633 (i) == 1 ? MXC_I2CM1_FIFO : \
<> 144:ef7eb2e8f9f7 634 (i) == 2 ? MXC_I2CM2_FIFO : 0)
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 639 /* I2C Slave Interface (Mailbox type) */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 #define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
<> 144:ef7eb2e8f9f7 642 #define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 647 /* SPI Master Interface */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #define MXC_CFG_SPI_INSTANCES (3)
<> 144:ef7eb2e8f9f7 650 #define MXC_CFG_SPI_FIFO_DEPTH (16)
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #define MXC_BASE_SPI0 ((uint32_t)0x4001A000UL)
<> 144:ef7eb2e8f9f7 653 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
<> 144:ef7eb2e8f9f7 654 #define MXC_BASE_SPI1 ((uint32_t)0x4001B000UL)
<> 144:ef7eb2e8f9f7 655 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
<> 144:ef7eb2e8f9f7 656 #define MXC_BASE_SPI2 ((uint32_t)0x4001C000UL)
<> 144:ef7eb2e8f9f7 657 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
<> 144:ef7eb2e8f9f7 658 #define MXC_BASE_SPI0_FIFO ((uint32_t)0x4010A000UL)
<> 144:ef7eb2e8f9f7 659 #define MXC_SPI0_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI0_FIFO)
<> 144:ef7eb2e8f9f7 660 #define MXC_BASE_SPI1_FIFO ((uint32_t)0x4010B000UL)
<> 144:ef7eb2e8f9f7 661 #define MXC_SPI1_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI1_FIFO)
<> 144:ef7eb2e8f9f7 662 #define MXC_BASE_SPI2_FIFO ((uint32_t)0x4010C000UL)
<> 144:ef7eb2e8f9f7 663 #define MXC_SPI2_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI2_FIFO)
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 #define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
<> 144:ef7eb2e8f9f7 666 (i) == 1 ? SPI1_IRQn : \
<> 144:ef7eb2e8f9f7 667 (i) == 2 ? SPI2_IRQn : 0)
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
<> 144:ef7eb2e8f9f7 670 (i) == 1 ? MXC_BASE_SPI1 : \
<> 144:ef7eb2e8f9f7 671 (i) == 2 ? MXC_BASE_SPI2 : 0)
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
<> 144:ef7eb2e8f9f7 674 (i) == 1 ? MXC_SPI1 : \
<> 144:ef7eb2e8f9f7 675 (i) == 2 ? MXC_SPI2 : 0)
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : \
<> 144:ef7eb2e8f9f7 678 (p) == MXC_SPI1 ? 1 : \
<> 144:ef7eb2e8f9f7 679 (p) == MXC_SPI2 ? 2 : -1)
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 #define MXC_SPI_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPI0_FIFO : \
<> 144:ef7eb2e8f9f7 682 (i) == 1 ? MXC_BASE_SPI1_FIFO : \
<> 144:ef7eb2e8f9f7 683 (i) == 2 ? MXC_BASE_SPI2_FIFO : 0)
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #define MXC_SPI_GET_SPI_FIFO(i) ((i) == 0 ? MXC_SPI0_FIFO : \
<> 144:ef7eb2e8f9f7 686 (i) == 1 ? MXC_SPI1_FIFO : \
<> 144:ef7eb2e8f9f7 687 (i) == 2 ? MXC_SPI2_FIFO : 0)
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 692 /* 1-Wire Master Interface */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 #define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
<> 144:ef7eb2e8f9f7 695 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 700 /* ADC / AFE */
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 #define MXC_CFG_ADC_FIFO_DEPTH (32)
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
<> 144:ef7eb2e8f9f7 705 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 710 /* SPIB AHB-to-SPI Bridge */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 #define MXC_BASE_SPIB ((uint32_t)0x4000D000UL)
<> 144:ef7eb2e8f9f7 713 #define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB)
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 718 /* Bit Shifting */
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 #define MXC_F_BIT_0 (1 << 0)
<> 144:ef7eb2e8f9f7 721 #define MXC_F_BIT_1 (1 << 1)
<> 144:ef7eb2e8f9f7 722 #define MXC_F_BIT_2 (1 << 2)
<> 144:ef7eb2e8f9f7 723 #define MXC_F_BIT_3 (1 << 3)
<> 144:ef7eb2e8f9f7 724 #define MXC_F_BIT_4 (1 << 4)
<> 144:ef7eb2e8f9f7 725 #define MXC_F_BIT_5 (1 << 5)
<> 144:ef7eb2e8f9f7 726 #define MXC_F_BIT_6 (1 << 6)
<> 144:ef7eb2e8f9f7 727 #define MXC_F_BIT_7 (1 << 7)
<> 144:ef7eb2e8f9f7 728 #define MXC_F_BIT_8 (1 << 8)
<> 144:ef7eb2e8f9f7 729 #define MXC_F_BIT_9 (1 << 9)
<> 144:ef7eb2e8f9f7 730 #define MXC_F_BIT_10 (1 << 10)
<> 144:ef7eb2e8f9f7 731 #define MXC_F_BIT_11 (1 << 11)
<> 144:ef7eb2e8f9f7 732 #define MXC_F_BIT_12 (1 << 12)
<> 144:ef7eb2e8f9f7 733 #define MXC_F_BIT_13 (1 << 13)
<> 144:ef7eb2e8f9f7 734 #define MXC_F_BIT_14 (1 << 14)
<> 144:ef7eb2e8f9f7 735 #define MXC_F_BIT_15 (1 << 15)
<> 144:ef7eb2e8f9f7 736 #define MXC_F_BIT_16 (1 << 16)
<> 144:ef7eb2e8f9f7 737 #define MXC_F_BIT_17 (1 << 17)
<> 144:ef7eb2e8f9f7 738 #define MXC_F_BIT_18 (1 << 18)
<> 144:ef7eb2e8f9f7 739 #define MXC_F_BIT_19 (1 << 19)
<> 144:ef7eb2e8f9f7 740 #define MXC_F_BIT_20 (1 << 20)
<> 144:ef7eb2e8f9f7 741 #define MXC_F_BIT_21 (1 << 21)
<> 144:ef7eb2e8f9f7 742 #define MXC_F_BIT_22 (1 << 22)
<> 144:ef7eb2e8f9f7 743 #define MXC_F_BIT_23 (1 << 23)
<> 144:ef7eb2e8f9f7 744 #define MXC_F_BIT_24 (1 << 24)
<> 144:ef7eb2e8f9f7 745 #define MXC_F_BIT_25 (1 << 25)
<> 144:ef7eb2e8f9f7 746 #define MXC_F_BIT_26 (1 << 26)
<> 144:ef7eb2e8f9f7 747 #define MXC_F_BIT_27 (1 << 27)
<> 144:ef7eb2e8f9f7 748 #define MXC_F_BIT_28 (1 << 28)
<> 144:ef7eb2e8f9f7 749 #define MXC_F_BIT_29 (1 << 29)
<> 144:ef7eb2e8f9f7 750 #define MXC_F_BIT_30 (1 << 30)
<> 144:ef7eb2e8f9f7 751 #define MXC_F_BIT_31 (1 << 31)
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
<> 144:ef7eb2e8f9f7 757 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
<> 144:ef7eb2e8f9f7 758 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
<> 144:ef7eb2e8f9f7 759 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 #endif /* _MAX32620_H_ */
<> 144:ef7eb2e8f9f7 766