Kenny Huang / nRF24L01

Added Flush Tx and Rx Buffer to Owen Edwards version of the library.

Dependents:   HexiComm HexiwearAlertSystem Hexi

Fork of nRF24L01P by Owen Edwards

nRF24L01P.cpp@1:b3ea38f27b69, 2016-10-05 (annotated)

Committer:
khuang
Date:
Wed Oct 05 06:02:50 2016 +0000
Revision:
1:b3ea38f27b69
Parent:
0:8ae48233b4e4 
Added flush tx and rx to startup sequence;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Owen 0:8ae48233b4e4 1 /**
Owen 0:8ae48233b4e4 2 * @file nRF24L01P.cpp
Owen 0:8ae48233b4e4 3 *
Owen 0:8ae48233b4e4 4 * @author Owen Edwards
Owen 0:8ae48233b4e4 5 *
Owen 0:8ae48233b4e4 6 * @section LICENSE
Owen 0:8ae48233b4e4 7 *
Owen 0:8ae48233b4e4 8 * Copyright (c) 2010 Owen Edwards
Owen 0:8ae48233b4e4 9 *
Owen 0:8ae48233b4e4 10 * This program is free software: you can redistribute it and/or modify
Owen 0:8ae48233b4e4 11 * it under the terms of the GNU General Public License as published by
Owen 0:8ae48233b4e4 12 * the Free Software Foundation, either version 3 of the License, or
Owen 0:8ae48233b4e4 13 * (at your option) any later version.
Owen 0:8ae48233b4e4 14 *
Owen 0:8ae48233b4e4 15 * This program is distributed in the hope that it will be useful,
Owen 0:8ae48233b4e4 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Owen 0:8ae48233b4e4 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Owen 0:8ae48233b4e4 18 * GNU General Public License for more details.
Owen 0:8ae48233b4e4 19 *
Owen 0:8ae48233b4e4 20 * You should have received a copy of the GNU General Public License
Owen 0:8ae48233b4e4 21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
Owen 0:8ae48233b4e4 22 *
Owen 0:8ae48233b4e4 23 * The above copyright notice and this permission notice shall be included in
Owen 0:8ae48233b4e4 24 * all copies or substantial portions of the Software.
Owen 0:8ae48233b4e4 25 *
Owen 0:8ae48233b4e4 26 * @section DESCRIPTION
Owen 0:8ae48233b4e4 27 *
Owen 0:8ae48233b4e4 28 * nRF24L01+ Single Chip 2.4GHz Transceiver from Nordic Semiconductor.
Owen 0:8ae48233b4e4 29 *
Owen 0:8ae48233b4e4 30 * Datasheet:
Owen 0:8ae48233b4e4 31 *
Owen 0:8ae48233b4e4 32 * http://www.nordicsemi.no/files/Product/data_sheet/nRF24L01P_Product_Specification_1_0.pdf
Owen 0:8ae48233b4e4 33 */
Owen 0:8ae48233b4e4 34
Owen 0:8ae48233b4e4 35 /**
Owen 0:8ae48233b4e4 36 * Includes
Owen 0:8ae48233b4e4 37 */
Owen 0:8ae48233b4e4 38 #include "nRF24L01P.h"
Owen 0:8ae48233b4e4 39
Owen 0:8ae48233b4e4 40 /**
Owen 0:8ae48233b4e4 41 * Defines
Owen 0:8ae48233b4e4 42 *
Owen 0:8ae48233b4e4 43 * (Note that all defines here start with an underscore, e.g. '_NRF24L01P_MODE_UNKNOWN',
Owen 0:8ae48233b4e4 44 * and are local to this library. The defines in the nRF24L01P.h file do not start
Owen 0:8ae48233b4e4 45 * with the underscore, and can be used by code to access this library.)
Owen 0:8ae48233b4e4 46 */
Owen 0:8ae48233b4e4 47
Owen 0:8ae48233b4e4 48 typedef enum {
Owen 0:8ae48233b4e4 49 _NRF24L01P_MODE_UNKNOWN,
Owen 0:8ae48233b4e4 50 _NRF24L01P_MODE_POWER_DOWN,
Owen 0:8ae48233b4e4 51 _NRF24L01P_MODE_STANDBY,
Owen 0:8ae48233b4e4 52 _NRF24L01P_MODE_RX,
Owen 0:8ae48233b4e4 53 _NRF24L01P_MODE_TX,
Owen 0:8ae48233b4e4 54 } nRF24L01P_Mode_Type;
Owen 0:8ae48233b4e4 55
Owen 0:8ae48233b4e4 56 /*
Owen 0:8ae48233b4e4 57 * The following FIFOs are present in nRF24L01+:
Owen 0:8ae48233b4e4 58 * TX three level, 32 byte FIFO
Owen 0:8ae48233b4e4 59 * RX three level, 32 byte FIFO
Owen 0:8ae48233b4e4 60 */
Owen 0:8ae48233b4e4 61 #define _NRF24L01P_TX_FIFO_COUNT 3
Owen 0:8ae48233b4e4 62 #define _NRF24L01P_RX_FIFO_COUNT 3
Owen 0:8ae48233b4e4 63
Owen 0:8ae48233b4e4 64 #define _NRF24L01P_TX_FIFO_SIZE 32
Owen 0:8ae48233b4e4 65 #define _NRF24L01P_RX_FIFO_SIZE 32
Owen 0:8ae48233b4e4 66
Owen 0:8ae48233b4e4 67 #define _NRF24L01P_SPI_MAX_DATA_RATE 10000000
Owen 0:8ae48233b4e4 68
Owen 0:8ae48233b4e4 69 #define _NRF24L01P_SPI_CMD_RD_REG 0x00
Owen 0:8ae48233b4e4 70 #define _NRF24L01P_SPI_CMD_WR_REG 0x20
Owen 0:8ae48233b4e4 71 #define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61
Owen 0:8ae48233b4e4 72 #define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0
Owen 0:8ae48233b4e4 73 #define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1
Owen 0:8ae48233b4e4 74 #define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2
Owen 0:8ae48233b4e4 75 #define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3
Owen 0:8ae48233b4e4 76 #define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60
Owen 0:8ae48233b4e4 77 #define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8
Owen 0:8ae48233b4e4 78 #define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0
Owen 0:8ae48233b4e4 79 #define _NRF24L01P_SPI_CMD_NOP 0xff
Owen 0:8ae48233b4e4 80
Owen 0:8ae48233b4e4 81
Owen 0:8ae48233b4e4 82 #define _NRF24L01P_REG_CONFIG 0x00
Owen 0:8ae48233b4e4 83 #define _NRF24L01P_REG_EN_AA 0x01
Owen 0:8ae48233b4e4 84 #define _NRF24L01P_REG_EN_RXADDR 0x02
Owen 0:8ae48233b4e4 85 #define _NRF24L01P_REG_SETUP_AW 0x03
Owen 0:8ae48233b4e4 86 #define _NRF24L01P_REG_SETUP_RETR 0x04
Owen 0:8ae48233b4e4 87 #define _NRF24L01P_REG_RF_CH 0x05
Owen 0:8ae48233b4e4 88 #define _NRF24L01P_REG_RF_SETUP 0x06
Owen 0:8ae48233b4e4 89 #define _NRF24L01P_REG_STATUS 0x07
Owen 0:8ae48233b4e4 90 #define _NRF24L01P_REG_OBSERVE_TX 0x08
Owen 0:8ae48233b4e4 91 #define _NRF24L01P_REG_RPD 0x09
Owen 0:8ae48233b4e4 92 #define _NRF24L01P_REG_RX_ADDR_P0 0x0a
Owen 0:8ae48233b4e4 93 #define _NRF24L01P_REG_RX_ADDR_P1 0x0b
Owen 0:8ae48233b4e4 94 #define _NRF24L01P_REG_RX_ADDR_P2 0x0c
Owen 0:8ae48233b4e4 95 #define _NRF24L01P_REG_RX_ADDR_P3 0x0d
Owen 0:8ae48233b4e4 96 #define _NRF24L01P_REG_RX_ADDR_P4 0x0e
Owen 0:8ae48233b4e4 97 #define _NRF24L01P_REG_RX_ADDR_P5 0x0f
Owen 0:8ae48233b4e4 98 #define _NRF24L01P_REG_TX_ADDR 0x10
Owen 0:8ae48233b4e4 99 #define _NRF24L01P_REG_RX_PW_P0 0x11
Owen 0:8ae48233b4e4 100 #define _NRF24L01P_REG_RX_PW_P1 0x12
Owen 0:8ae48233b4e4 101 #define _NRF24L01P_REG_RX_PW_P2 0x13
Owen 0:8ae48233b4e4 102 #define _NRF24L01P_REG_RX_PW_P3 0x14
Owen 0:8ae48233b4e4 103 #define _NRF24L01P_REG_RX_PW_P4 0x15
Owen 0:8ae48233b4e4 104 #define _NRF24L01P_REG_RX_PW_P5 0x16
Owen 0:8ae48233b4e4 105 #define _NRF24L01P_REG_FIFO_STATUS 0x17
Owen 0:8ae48233b4e4 106 #define _NRF24L01P_REG_DYNPD 0x1c
Owen 0:8ae48233b4e4 107 #define _NRF24L01P_REG_FEATURE 0x1d
Owen 0:8ae48233b4e4 108
Owen 0:8ae48233b4e4 109 #define _NRF24L01P_REG_ADDRESS_MASK 0x1f
Owen 0:8ae48233b4e4 110
Owen 0:8ae48233b4e4 111 // CONFIG register:
Owen 0:8ae48233b4e4 112 #define _NRF24L01P_CONFIG_PRIM_RX (1<<0)
Owen 0:8ae48233b4e4 113 #define _NRF24L01P_CONFIG_PWR_UP (1<<1)
Owen 0:8ae48233b4e4 114 #define _NRF24L01P_CONFIG_CRC0 (1<<2)
Owen 0:8ae48233b4e4 115 #define _NRF24L01P_CONFIG_EN_CRC (1<<3)
Owen 0:8ae48233b4e4 116 #define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4)
Owen 0:8ae48233b4e4 117 #define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5)
Owen 0:8ae48233b4e4 118 #define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6)
Owen 0:8ae48233b4e4 119
Owen 0:8ae48233b4e4 120 #define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
Owen 0:8ae48233b4e4 121 #define _NRF24L01P_CONFIG_CRC_NONE (0)
Owen 0:8ae48233b4e4 122 #define _NRF24L01P_CONFIG_CRC_8BIT (_NRF24L01P_CONFIG_EN_CRC)
Owen 0:8ae48233b4e4 123 #define _NRF24L01P_CONFIG_CRC_16BIT (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
Owen 0:8ae48233b4e4 124
Owen 0:8ae48233b4e4 125 // EN_AA register:
Owen 0:8ae48233b4e4 126 #define _NRF24L01P_EN_AA_NONE 0
Owen 0:8ae48233b4e4 127
Owen 0:8ae48233b4e4 128 // EN_RXADDR register:
Owen 0:8ae48233b4e4 129 #define _NRF24L01P_EN_RXADDR_NONE 0
Owen 0:8ae48233b4e4 130
Owen 0:8ae48233b4e4 131 // SETUP_AW register:
Owen 0:8ae48233b4e4 132 #define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0)
Owen 0:8ae48233b4e4 133 #define _NRF24L01P_SETUP_AW_AW_3BYTE (0x1<<0)
Owen 0:8ae48233b4e4 134 #define _NRF24L01P_SETUP_AW_AW_4BYTE (0x2<<0)
Owen 0:8ae48233b4e4 135 #define _NRF24L01P_SETUP_AW_AW_5BYTE (0x3<<0)
Owen 0:8ae48233b4e4 136
Owen 0:8ae48233b4e4 137 // SETUP_RETR register:
Owen 0:8ae48233b4e4 138 #define _NRF24L01P_SETUP_RETR_NONE 0
Owen 0:8ae48233b4e4 139
Owen 0:8ae48233b4e4 140 // RF_SETUP register:
Owen 0:8ae48233b4e4 141 #define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1)
Owen 0:8ae48233b4e4 142 #define _NRF24L01P_RF_SETUP_RF_PWR_0DBM (0x3<<1)
Owen 0:8ae48233b4e4 143 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM (0x2<<1)
Owen 0:8ae48233b4e4 144 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM (0x1<<1)
Owen 0:8ae48233b4e4 145 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM (0x0<<1)
Owen 0:8ae48233b4e4 146
Owen 0:8ae48233b4e4 147 #define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3)
Owen 0:8ae48233b4e4 148 #define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5)
Owen 0:8ae48233b4e4 149 #define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
Owen 0:8ae48233b4e4 150 #define _NRF24L01P_RF_SETUP_RF_DR_250KBPS (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT)
Owen 0:8ae48233b4e4 151 #define _NRF24L01P_RF_SETUP_RF_DR_1MBPS (0)
Owen 0:8ae48233b4e4 152 #define _NRF24L01P_RF_SETUP_RF_DR_2MBPS (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
Owen 0:8ae48233b4e4 153
Owen 0:8ae48233b4e4 154 // STATUS register:
Owen 0:8ae48233b4e4 155 #define _NRF24L01P_STATUS_TX_FULL (1<<0)
Owen 0:8ae48233b4e4 156 #define _NRF24L01P_STATUS_RX_P_NO (0x7<<1)
Owen 0:8ae48233b4e4 157 #define _NRF24L01P_STATUS_MAX_RT (1<<4)
Owen 0:8ae48233b4e4 158 #define _NRF24L01P_STATUS_TX_DS (1<<5)
Owen 0:8ae48233b4e4 159 #define _NRF24L01P_STATUS_RX_DR (1<<6)
Owen 0:8ae48233b4e4 160
Owen 0:8ae48233b4e4 161 // RX_PW_P0..RX_PW_P5 registers:
Owen 0:8ae48233b4e4 162 #define _NRF24L01P_RX_PW_Px_MASK 0x3F
Owen 0:8ae48233b4e4 163
Owen 0:8ae48233b4e4 164 #define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS
Owen 0:8ae48233b4e4 165 #define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS
Owen 0:8ae48233b4e4 166 #define _NRF24L01P_TIMING_Thce_us 10 // 10uS
Owen 0:8ae48233b4e4 167 #define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case
Owen 0:8ae48233b4e4 168 #define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS
Owen 0:8ae48233b4e4 169
Owen 0:8ae48233b4e4 170 /**
Owen 0:8ae48233b4e4 171 * Methods
Owen 0:8ae48233b4e4 172 */
Owen 0:8ae48233b4e4 173
Owen 0:8ae48233b4e4 174 nRF24L01P::nRF24L01P(PinName mosi,
Owen 0:8ae48233b4e4 175 PinName miso,
Owen 0:8ae48233b4e4 176 PinName sck,
Owen 0:8ae48233b4e4 177 PinName csn,
Owen 0:8ae48233b4e4 178 PinName ce,
Owen 0:8ae48233b4e4 179 PinName irq) : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) {
Owen 0:8ae48233b4e4 180
khuang 1:b3ea38f27b69 181
Owen 0:8ae48233b4e4 182 nCS_ = 1;
Owen 0:8ae48233b4e4 183
Owen 0:8ae48233b4e4 184 spi_.frequency(_NRF24L01P_SPI_MAX_DATA_RATE/5); // 2Mbit, 1/5th the maximum transfer rate for the SPI bus
Owen 0:8ae48233b4e4 185 spi_.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
khuang 1:b3ea38f27b69 186 }
Owen 0:8ae48233b4e4 187
khuang 1:b3ea38f27b69 188 void nRF24L01P::init(void)
khuang 1:b3ea38f27b69 189 {
khuang 1:b3ea38f27b69 190 mode = _NRF24L01P_MODE_UNKNOWN;
khuang 1:b3ea38f27b69 191 disable();
Owen 0:8ae48233b4e4 192 wait_us(_NRF24L01P_TIMING_Tundef2pd_us); // Wait for Power-on reset
khuang 1:b3ea38f27b69 193
Owen 0:8ae48233b4e4 194 setRegister(_NRF24L01P_REG_CONFIG, 0); // Power Down
Owen 0:8ae48233b4e4 195
Owen 0:8ae48233b4e4 196 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT|_NRF24L01P_STATUS_TX_DS|_NRF24L01P_STATUS_RX_DR); // Clear any pending interrupts
Owen 0:8ae48233b4e4 197
Owen 0:8ae48233b4e4 198 //
Owen 0:8ae48233b4e4 199 // Setup default configuration
Owen 0:8ae48233b4e4 200 //
Owen 0:8ae48233b4e4 201 disableAllRxPipes();
Owen 0:8ae48233b4e4 202 setRfFrequency();
Owen 0:8ae48233b4e4 203 setRfOutputPower();
Owen 0:8ae48233b4e4 204 setAirDataRate();
Owen 0:8ae48233b4e4 205 setCrcWidth();
Owen 0:8ae48233b4e4 206 setTxAddress();
Owen 0:8ae48233b4e4 207 setRxAddress();
Owen 0:8ae48233b4e4 208 disableAutoAcknowledge();
Owen 0:8ae48233b4e4 209 disableAutoRetransmit();
Owen 0:8ae48233b4e4 210 setTransferSize();
khuang 1:b3ea38f27b69 211
khuang 1:b3ea38f27b69 212 nCS_ = 0;
khuang 1:b3ea38f27b69 213 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_TX);
khuang 1:b3ea38f27b69 214 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
khuang 1:b3ea38f27b69 215 nCS_ = 1;
Owen 0:8ae48233b4e4 216
Owen 0:8ae48233b4e4 217 mode = _NRF24L01P_MODE_POWER_DOWN;
Owen 0:8ae48233b4e4 218
Owen 0:8ae48233b4e4 219 }
Owen 0:8ae48233b4e4 220
Owen 0:8ae48233b4e4 221
Owen 0:8ae48233b4e4 222 void nRF24L01P::powerUp(void) {
Owen 0:8ae48233b4e4 223
Owen 0:8ae48233b4e4 224 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 225
Owen 0:8ae48233b4e4 226 config |= _NRF24L01P_CONFIG_PWR_UP;
Owen 0:8ae48233b4e4 227
Owen 0:8ae48233b4e4 228 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 229
Owen 0:8ae48233b4e4 230 // Wait until the nRF24L01+ powers up
Owen 0:8ae48233b4e4 231 wait_us( _NRF24L01P_TIMING_Tpd2stby_us );
Owen 0:8ae48233b4e4 232
Owen 0:8ae48233b4e4 233 mode = _NRF24L01P_MODE_STANDBY;
Owen 0:8ae48233b4e4 234
Owen 0:8ae48233b4e4 235 }
Owen 0:8ae48233b4e4 236
Owen 0:8ae48233b4e4 237
Owen 0:8ae48233b4e4 238 void nRF24L01P::powerDown(void) {
Owen 0:8ae48233b4e4 239
Owen 0:8ae48233b4e4 240 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 241
Owen 0:8ae48233b4e4 242 config &= ~_NRF24L01P_CONFIG_PWR_UP;
Owen 0:8ae48233b4e4 243
Owen 0:8ae48233b4e4 244 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 245
Owen 0:8ae48233b4e4 246 // Wait until the nRF24L01+ powers down
Owen 0:8ae48233b4e4 247 wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This *may* not be necessary (no timing is shown in the Datasheet), but just to be safe
Owen 0:8ae48233b4e4 248
Owen 0:8ae48233b4e4 249 mode = _NRF24L01P_MODE_POWER_DOWN;
Owen 0:8ae48233b4e4 250
Owen 0:8ae48233b4e4 251 }
Owen 0:8ae48233b4e4 252
Owen 0:8ae48233b4e4 253
Owen 0:8ae48233b4e4 254 void nRF24L01P::setReceiveMode(void) {
Owen 0:8ae48233b4e4 255
Owen 0:8ae48233b4e4 256 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
Owen 0:8ae48233b4e4 257
Owen 0:8ae48233b4e4 258 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 259
Owen 0:8ae48233b4e4 260 config |= _NRF24L01P_CONFIG_PRIM_RX;
Owen 0:8ae48233b4e4 261
Owen 0:8ae48233b4e4 262 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 263
Owen 0:8ae48233b4e4 264 mode = _NRF24L01P_MODE_RX;
Owen 0:8ae48233b4e4 265
Owen 0:8ae48233b4e4 266 }
Owen 0:8ae48233b4e4 267
Owen 0:8ae48233b4e4 268
Owen 0:8ae48233b4e4 269 void nRF24L01P::setTransmitMode(void) {
Owen 0:8ae48233b4e4 270
Owen 0:8ae48233b4e4 271 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
Owen 0:8ae48233b4e4 272
Owen 0:8ae48233b4e4 273 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 274
Owen 0:8ae48233b4e4 275 config &= ~_NRF24L01P_CONFIG_PRIM_RX;
Owen 0:8ae48233b4e4 276
Owen 0:8ae48233b4e4 277 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 278
Owen 0:8ae48233b4e4 279 mode = _NRF24L01P_MODE_TX;
Owen 0:8ae48233b4e4 280
Owen 0:8ae48233b4e4 281 }
Owen 0:8ae48233b4e4 282
Owen 0:8ae48233b4e4 283
Owen 0:8ae48233b4e4 284 void nRF24L01P::enable(void) {
Owen 0:8ae48233b4e4 285
Owen 0:8ae48233b4e4 286 ce_ = 1;
Owen 0:8ae48233b4e4 287 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
Owen 0:8ae48233b4e4 288
Owen 0:8ae48233b4e4 289 }
Owen 0:8ae48233b4e4 290
Owen 0:8ae48233b4e4 291
Owen 0:8ae48233b4e4 292 void nRF24L01P::disable(void) {
Owen 0:8ae48233b4e4 293
Owen 0:8ae48233b4e4 294 ce_ = 0;
Owen 0:8ae48233b4e4 295
Owen 0:8ae48233b4e4 296 }
Owen 0:8ae48233b4e4 297
Owen 0:8ae48233b4e4 298 void nRF24L01P::setRfFrequency(int frequency) {
Owen 0:8ae48233b4e4 299
Owen 0:8ae48233b4e4 300 if ( ( frequency < NRF24L01P_MIN_RF_FREQUENCY ) || ( frequency > NRF24L01P_MAX_RF_FREQUENCY ) ) {
Owen 0:8ae48233b4e4 301
Owen 0:8ae48233b4e4 302 error( "nRF24L01P: Invalid RF Frequency setting %d\r\n", frequency );
Owen 0:8ae48233b4e4 303 return;
Owen 0:8ae48233b4e4 304
Owen 0:8ae48233b4e4 305 }
Owen 0:8ae48233b4e4 306
Owen 0:8ae48233b4e4 307 int channel = ( frequency - NRF24L01P_MIN_RF_FREQUENCY ) & 0x7F;
Owen 0:8ae48233b4e4 308
Owen 0:8ae48233b4e4 309 setRegister(_NRF24L01P_REG_RF_CH, channel);
Owen 0:8ae48233b4e4 310
Owen 0:8ae48233b4e4 311 }
Owen 0:8ae48233b4e4 312
Owen 0:8ae48233b4e4 313
Owen 0:8ae48233b4e4 314 int nRF24L01P::getRfFrequency(void) {
Owen 0:8ae48233b4e4 315
Owen 0:8ae48233b4e4 316 int channel = getRegister(_NRF24L01P_REG_RF_CH) & 0x7F;
Owen 0:8ae48233b4e4 317
Owen 0:8ae48233b4e4 318 return ( channel + NRF24L01P_MIN_RF_FREQUENCY );
Owen 0:8ae48233b4e4 319
Owen 0:8ae48233b4e4 320 }
Owen 0:8ae48233b4e4 321
Owen 0:8ae48233b4e4 322
Owen 0:8ae48233b4e4 323 void nRF24L01P::setRfOutputPower(int power) {
Owen 0:8ae48233b4e4 324
Owen 0:8ae48233b4e4 325 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_PWR_MASK;
Owen 0:8ae48233b4e4 326
Owen 0:8ae48233b4e4 327 switch ( power ) {
Owen 0:8ae48233b4e4 328
Owen 0:8ae48233b4e4 329 case NRF24L01P_TX_PWR_ZERO_DB:
Owen 0:8ae48233b4e4 330 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_0DBM;
Owen 0:8ae48233b4e4 331 break;
Owen 0:8ae48233b4e4 332
Owen 0:8ae48233b4e4 333 case NRF24L01P_TX_PWR_MINUS_6_DB:
Owen 0:8ae48233b4e4 334 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM;
Owen 0:8ae48233b4e4 335 break;
Owen 0:8ae48233b4e4 336
Owen 0:8ae48233b4e4 337 case NRF24L01P_TX_PWR_MINUS_12_DB:
Owen 0:8ae48233b4e4 338 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM;
Owen 0:8ae48233b4e4 339 break;
Owen 0:8ae48233b4e4 340
Owen 0:8ae48233b4e4 341 case NRF24L01P_TX_PWR_MINUS_18_DB:
Owen 0:8ae48233b4e4 342 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM;
Owen 0:8ae48233b4e4 343 break;
Owen 0:8ae48233b4e4 344
Owen 0:8ae48233b4e4 345 default:
Owen 0:8ae48233b4e4 346 error( "nRF24L01P: Invalid RF Output Power setting %d\r\n", power );
Owen 0:8ae48233b4e4 347 return;
Owen 0:8ae48233b4e4 348
Owen 0:8ae48233b4e4 349 }
Owen 0:8ae48233b4e4 350
Owen 0:8ae48233b4e4 351 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
Owen 0:8ae48233b4e4 352
Owen 0:8ae48233b4e4 353 }
Owen 0:8ae48233b4e4 354
Owen 0:8ae48233b4e4 355
Owen 0:8ae48233b4e4 356 int nRF24L01P::getRfOutputPower(void) {
Owen 0:8ae48233b4e4 357
Owen 0:8ae48233b4e4 358 int rfPwr = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_PWR_MASK;
Owen 0:8ae48233b4e4 359
Owen 0:8ae48233b4e4 360 switch ( rfPwr ) {
Owen 0:8ae48233b4e4 361
Owen 0:8ae48233b4e4 362 case _NRF24L01P_RF_SETUP_RF_PWR_0DBM:
Owen 0:8ae48233b4e4 363 return NRF24L01P_TX_PWR_ZERO_DB;
Owen 0:8ae48233b4e4 364
Owen 0:8ae48233b4e4 365 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM:
Owen 0:8ae48233b4e4 366 return NRF24L01P_TX_PWR_MINUS_6_DB;
Owen 0:8ae48233b4e4 367
Owen 0:8ae48233b4e4 368 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM:
Owen 0:8ae48233b4e4 369 return NRF24L01P_TX_PWR_MINUS_12_DB;
Owen 0:8ae48233b4e4 370
Owen 0:8ae48233b4e4 371 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM:
Owen 0:8ae48233b4e4 372 return NRF24L01P_TX_PWR_MINUS_18_DB;
Owen 0:8ae48233b4e4 373
Owen 0:8ae48233b4e4 374 default:
Owen 0:8ae48233b4e4 375 error( "nRF24L01P: Unknown RF Output Power value %d\r\n", rfPwr );
Owen 0:8ae48233b4e4 376 return 0;
Owen 0:8ae48233b4e4 377
Owen 0:8ae48233b4e4 378 }
Owen 0:8ae48233b4e4 379 }
Owen 0:8ae48233b4e4 380
Owen 0:8ae48233b4e4 381
Owen 0:8ae48233b4e4 382 void nRF24L01P::setAirDataRate(int rate) {
Owen 0:8ae48233b4e4 383
Owen 0:8ae48233b4e4 384 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_DR_MASK;
Owen 0:8ae48233b4e4 385
Owen 0:8ae48233b4e4 386 switch ( rate ) {
Owen 0:8ae48233b4e4 387
Owen 0:8ae48233b4e4 388 case NRF24L01P_DATARATE_250_KBPS:
Owen 0:8ae48233b4e4 389 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_250KBPS;
Owen 0:8ae48233b4e4 390 break;
Owen 0:8ae48233b4e4 391
Owen 0:8ae48233b4e4 392 case NRF24L01P_DATARATE_1_MBPS:
Owen 0:8ae48233b4e4 393 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_1MBPS;
Owen 0:8ae48233b4e4 394 break;
Owen 0:8ae48233b4e4 395
Owen 0:8ae48233b4e4 396 case NRF24L01P_DATARATE_2_MBPS:
Owen 0:8ae48233b4e4 397 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_2MBPS;
Owen 0:8ae48233b4e4 398 break;
Owen 0:8ae48233b4e4 399
Owen 0:8ae48233b4e4 400 default:
Owen 0:8ae48233b4e4 401 error( "nRF24L01P: Invalid Air Data Rate setting %d\r\n", rate );
Owen 0:8ae48233b4e4 402 return;
Owen 0:8ae48233b4e4 403
Owen 0:8ae48233b4e4 404 }
Owen 0:8ae48233b4e4 405
Owen 0:8ae48233b4e4 406 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
Owen 0:8ae48233b4e4 407
Owen 0:8ae48233b4e4 408 }
Owen 0:8ae48233b4e4 409
Owen 0:8ae48233b4e4 410
Owen 0:8ae48233b4e4 411 int nRF24L01P::getAirDataRate(void) {
Owen 0:8ae48233b4e4 412
Owen 0:8ae48233b4e4 413 int rfDataRate = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_DR_MASK;
Owen 0:8ae48233b4e4 414
Owen 0:8ae48233b4e4 415 switch ( rfDataRate ) {
Owen 0:8ae48233b4e4 416
Owen 0:8ae48233b4e4 417 case _NRF24L01P_RF_SETUP_RF_DR_250KBPS:
Owen 0:8ae48233b4e4 418 return NRF24L01P_DATARATE_250_KBPS;
Owen 0:8ae48233b4e4 419
Owen 0:8ae48233b4e4 420 case _NRF24L01P_RF_SETUP_RF_DR_1MBPS:
Owen 0:8ae48233b4e4 421 return NRF24L01P_DATARATE_1_MBPS;
Owen 0:8ae48233b4e4 422
Owen 0:8ae48233b4e4 423 case _NRF24L01P_RF_SETUP_RF_DR_2MBPS:
Owen 0:8ae48233b4e4 424 return NRF24L01P_DATARATE_2_MBPS;
Owen 0:8ae48233b4e4 425
Owen 0:8ae48233b4e4 426 default:
Owen 0:8ae48233b4e4 427 error( "nRF24L01P: Unknown Air Data Rate value %d\r\n", rfDataRate );
Owen 0:8ae48233b4e4 428 return 0;
Owen 0:8ae48233b4e4 429
Owen 0:8ae48233b4e4 430 }
Owen 0:8ae48233b4e4 431 }
Owen 0:8ae48233b4e4 432
Owen 0:8ae48233b4e4 433
Owen 0:8ae48233b4e4 434 void nRF24L01P::setCrcWidth(int width) {
Owen 0:8ae48233b4e4 435
Owen 0:8ae48233b4e4 436 int config = getRegister(_NRF24L01P_REG_CONFIG) & ~_NRF24L01P_CONFIG_CRC_MASK;
Owen 0:8ae48233b4e4 437
Owen 0:8ae48233b4e4 438 switch ( width ) {
Owen 0:8ae48233b4e4 439
Owen 0:8ae48233b4e4 440 case NRF24L01P_CRC_NONE:
Owen 0:8ae48233b4e4 441 config |= _NRF24L01P_CONFIG_CRC_NONE;
Owen 0:8ae48233b4e4 442 break;
Owen 0:8ae48233b4e4 443
Owen 0:8ae48233b4e4 444 case NRF24L01P_CRC_8_BIT:
Owen 0:8ae48233b4e4 445 config |= _NRF24L01P_CONFIG_CRC_8BIT;
Owen 0:8ae48233b4e4 446 break;
Owen 0:8ae48233b4e4 447
Owen 0:8ae48233b4e4 448 case NRF24L01P_CRC_16_BIT:
Owen 0:8ae48233b4e4 449 config |= _NRF24L01P_CONFIG_CRC_16BIT;
Owen 0:8ae48233b4e4 450 break;
Owen 0:8ae48233b4e4 451
Owen 0:8ae48233b4e4 452 default:
Owen 0:8ae48233b4e4 453 error( "nRF24L01P: Invalid CRC Width setting %d\r\n", width );
Owen 0:8ae48233b4e4 454 return;
Owen 0:8ae48233b4e4 455
Owen 0:8ae48233b4e4 456 }
Owen 0:8ae48233b4e4 457
Owen 0:8ae48233b4e4 458 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 459
Owen 0:8ae48233b4e4 460 }
Owen 0:8ae48233b4e4 461
Owen 0:8ae48233b4e4 462
Owen 0:8ae48233b4e4 463 int nRF24L01P::getCrcWidth(void) {
Owen 0:8ae48233b4e4 464
Owen 0:8ae48233b4e4 465 int crcWidth = getRegister(_NRF24L01P_REG_CONFIG) & _NRF24L01P_CONFIG_CRC_MASK;
Owen 0:8ae48233b4e4 466
Owen 0:8ae48233b4e4 467 switch ( crcWidth ) {
Owen 0:8ae48233b4e4 468
Owen 0:8ae48233b4e4 469 case _NRF24L01P_CONFIG_CRC_NONE:
Owen 0:8ae48233b4e4 470 return NRF24L01P_CRC_NONE;
Owen 0:8ae48233b4e4 471
Owen 0:8ae48233b4e4 472 case _NRF24L01P_CONFIG_CRC_8BIT:
Owen 0:8ae48233b4e4 473 return NRF24L01P_CRC_8_BIT;
Owen 0:8ae48233b4e4 474
Owen 0:8ae48233b4e4 475 case _NRF24L01P_CONFIG_CRC_16BIT:
Owen 0:8ae48233b4e4 476 return NRF24L01P_CRC_16_BIT;
Owen 0:8ae48233b4e4 477
Owen 0:8ae48233b4e4 478 default:
Owen 0:8ae48233b4e4 479 error( "nRF24L01P: Unknown CRC Width value %d\r\n", crcWidth );
Owen 0:8ae48233b4e4 480 return 0;
Owen 0:8ae48233b4e4 481
Owen 0:8ae48233b4e4 482 }
Owen 0:8ae48233b4e4 483 }
Owen 0:8ae48233b4e4 484
Owen 0:8ae48233b4e4 485
Owen 0:8ae48233b4e4 486 void nRF24L01P::setTransferSize(int size, int pipe) {
Owen 0:8ae48233b4e4 487
Owen 0:8ae48233b4e4 488 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 489
Owen 0:8ae48233b4e4 490 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 491 return;
Owen 0:8ae48233b4e4 492
Owen 0:8ae48233b4e4 493 }
Owen 0:8ae48233b4e4 494
Owen 0:8ae48233b4e4 495 if ( ( size < 0 ) || ( size > _NRF24L01P_RX_FIFO_SIZE ) ) {
Owen 0:8ae48233b4e4 496
Owen 0:8ae48233b4e4 497 error( "nRF24L01P: Invalid Transfer Size setting %d\r\n", size );
Owen 0:8ae48233b4e4 498 return;
Owen 0:8ae48233b4e4 499
Owen 0:8ae48233b4e4 500 }
Owen 0:8ae48233b4e4 501
Owen 0:8ae48233b4e4 502 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 503
Owen 0:8ae48233b4e4 504 setRegister(rxPwPxRegister, ( size & _NRF24L01P_RX_PW_Px_MASK ) );
Owen 0:8ae48233b4e4 505
Owen 0:8ae48233b4e4 506 }
Owen 0:8ae48233b4e4 507
Owen 0:8ae48233b4e4 508
Owen 0:8ae48233b4e4 509 int nRF24L01P::getTransferSize(int pipe) {
Owen 0:8ae48233b4e4 510
Owen 0:8ae48233b4e4 511 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 512
Owen 0:8ae48233b4e4 513 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 514 return 0;
Owen 0:8ae48233b4e4 515
Owen 0:8ae48233b4e4 516 }
Owen 0:8ae48233b4e4 517
Owen 0:8ae48233b4e4 518 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 519
Owen 0:8ae48233b4e4 520 int size = getRegister(rxPwPxRegister);
Owen 0:8ae48233b4e4 521
Owen 0:8ae48233b4e4 522 return ( size & _NRF24L01P_RX_PW_Px_MASK );
Owen 0:8ae48233b4e4 523
Owen 0:8ae48233b4e4 524 }
Owen 0:8ae48233b4e4 525
Owen 0:8ae48233b4e4 526
Owen 0:8ae48233b4e4 527 void nRF24L01P::disableAllRxPipes(void) {
Owen 0:8ae48233b4e4 528
Owen 0:8ae48233b4e4 529 setRegister(_NRF24L01P_REG_EN_RXADDR, _NRF24L01P_EN_RXADDR_NONE);
Owen 0:8ae48233b4e4 530
Owen 0:8ae48233b4e4 531 }
Owen 0:8ae48233b4e4 532
Owen 0:8ae48233b4e4 533
Owen 0:8ae48233b4e4 534 void nRF24L01P::disableAutoAcknowledge(void) {
Owen 0:8ae48233b4e4 535
Owen 0:8ae48233b4e4 536 setRegister(_NRF24L01P_REG_EN_AA, _NRF24L01P_EN_AA_NONE);
Owen 0:8ae48233b4e4 537
Owen 0:8ae48233b4e4 538 }
Owen 0:8ae48233b4e4 539
Owen 0:8ae48233b4e4 540
Owen 0:8ae48233b4e4 541 void nRF24L01P::enableAutoAcknowledge(int pipe) {
Owen 0:8ae48233b4e4 542
Owen 0:8ae48233b4e4 543 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 544
Owen 0:8ae48233b4e4 545 error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 546 return;
Owen 0:8ae48233b4e4 547
Owen 0:8ae48233b4e4 548 }
Owen 0:8ae48233b4e4 549
Owen 0:8ae48233b4e4 550 int enAA = getRegister(_NRF24L01P_REG_EN_AA);
Owen 0:8ae48233b4e4 551
Owen 0:8ae48233b4e4 552 enAA |= ( 1 << (pipe - NRF24L01P_PIPE_P0) );
Owen 0:8ae48233b4e4 553
Owen 0:8ae48233b4e4 554 setRegister(_NRF24L01P_REG_EN_AA, enAA);
Owen 0:8ae48233b4e4 555
Owen 0:8ae48233b4e4 556 }
Owen 0:8ae48233b4e4 557
Owen 0:8ae48233b4e4 558
Owen 0:8ae48233b4e4 559 void nRF24L01P::disableAutoRetransmit(void) {
Owen 0:8ae48233b4e4 560
Owen 0:8ae48233b4e4 561 setRegister(_NRF24L01P_REG_SETUP_RETR, _NRF24L01P_SETUP_RETR_NONE);
Owen 0:8ae48233b4e4 562
Owen 0:8ae48233b4e4 563 }
Owen 0:8ae48233b4e4 564
Owen 0:8ae48233b4e4 565 void nRF24L01P::setRxAddress(unsigned long long address, int width, int pipe) {
Owen 0:8ae48233b4e4 566
Owen 0:8ae48233b4e4 567 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 568
Owen 0:8ae48233b4e4 569 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 570 return;
Owen 0:8ae48233b4e4 571
Owen 0:8ae48233b4e4 572 }
Owen 0:8ae48233b4e4 573
Owen 0:8ae48233b4e4 574 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
Owen 0:8ae48233b4e4 575
Owen 0:8ae48233b4e4 576 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 577
Owen 0:8ae48233b4e4 578 switch ( width ) {
Owen 0:8ae48233b4e4 579
Owen 0:8ae48233b4e4 580 case 3:
Owen 0:8ae48233b4e4 581 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
Owen 0:8ae48233b4e4 582 break;
Owen 0:8ae48233b4e4 583
Owen 0:8ae48233b4e4 584 case 4:
Owen 0:8ae48233b4e4 585 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
Owen 0:8ae48233b4e4 586 break;
Owen 0:8ae48233b4e4 587
Owen 0:8ae48233b4e4 588 case 5:
Owen 0:8ae48233b4e4 589 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
Owen 0:8ae48233b4e4 590 break;
Owen 0:8ae48233b4e4 591
Owen 0:8ae48233b4e4 592 default:
Owen 0:8ae48233b4e4 593 error( "nRF24L01P: Invalid setRxAddress width setting %d\r\n", width );
Owen 0:8ae48233b4e4 594 return;
Owen 0:8ae48233b4e4 595
Owen 0:8ae48233b4e4 596 }
Owen 0:8ae48233b4e4 597
Owen 0:8ae48233b4e4 598 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
Owen 0:8ae48233b4e4 599
Owen 0:8ae48233b4e4 600 } else {
Owen 0:8ae48233b4e4 601
Owen 0:8ae48233b4e4 602 width = 1;
Owen 0:8ae48233b4e4 603
Owen 0:8ae48233b4e4 604 }
Owen 0:8ae48233b4e4 605
Owen 0:8ae48233b4e4 606 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 607
Owen 0:8ae48233b4e4 608 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 609
Owen 0:8ae48233b4e4 610 nCS_ = 0;
Owen 0:8ae48233b4e4 611
Owen 0:8ae48233b4e4 612 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 613
Owen 0:8ae48233b4e4 614 while ( width-- > 0 ) {
Owen 0:8ae48233b4e4 615
Owen 0:8ae48233b4e4 616 //
Owen 0:8ae48233b4e4 617 // LSByte first
Owen 0:8ae48233b4e4 618 //
Owen 0:8ae48233b4e4 619 spi_.write((int) (address & 0xFF));
Owen 0:8ae48233b4e4 620 address >>= 8;
Owen 0:8ae48233b4e4 621
Owen 0:8ae48233b4e4 622 }
Owen 0:8ae48233b4e4 623
Owen 0:8ae48233b4e4 624 nCS_ = 1;
Owen 0:8ae48233b4e4 625
Owen 0:8ae48233b4e4 626 int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
Owen 0:8ae48233b4e4 627
Owen 0:8ae48233b4e4 628 enRxAddr |= (1 << ( pipe - NRF24L01P_PIPE_P0 ) );
Owen 0:8ae48233b4e4 629
Owen 0:8ae48233b4e4 630 setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
Owen 0:8ae48233b4e4 631 }
Owen 0:8ae48233b4e4 632
Owen 0:8ae48233b4e4 633 /*
Owen 0:8ae48233b4e4 634 * This version of setRxAddress is just a wrapper for the version that takes 'long long's,
Owen 0:8ae48233b4e4 635 * in case the main code doesn't want to deal with long long's.
Owen 0:8ae48233b4e4 636 */
Owen 0:8ae48233b4e4 637 void nRF24L01P::setRxAddress(unsigned long msb_address, unsigned long lsb_address, int width, int pipe) {
Owen 0:8ae48233b4e4 638
Owen 0:8ae48233b4e4 639 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
Owen 0:8ae48233b4e4 640
Owen 0:8ae48233b4e4 641 setRxAddress(address, width, pipe);
Owen 0:8ae48233b4e4 642
Owen 0:8ae48233b4e4 643 }
Owen 0:8ae48233b4e4 644
Owen 0:8ae48233b4e4 645
Owen 0:8ae48233b4e4 646 /*
Owen 0:8ae48233b4e4 647 * This version of setTxAddress is just a wrapper for the version that takes 'long long's,
Owen 0:8ae48233b4e4 648 * in case the main code doesn't want to deal with long long's.
Owen 0:8ae48233b4e4 649 */
Owen 0:8ae48233b4e4 650 void nRF24L01P::setTxAddress(unsigned long msb_address, unsigned long lsb_address, int width) {
Owen 0:8ae48233b4e4 651
Owen 0:8ae48233b4e4 652 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
Owen 0:8ae48233b4e4 653
Owen 0:8ae48233b4e4 654 setTxAddress(address, width);
Owen 0:8ae48233b4e4 655
Owen 0:8ae48233b4e4 656 }
Owen 0:8ae48233b4e4 657
Owen 0:8ae48233b4e4 658
Owen 0:8ae48233b4e4 659 void nRF24L01P::setTxAddress(unsigned long long address, int width) {
Owen 0:8ae48233b4e4 660
Owen 0:8ae48233b4e4 661 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 662
Owen 0:8ae48233b4e4 663 switch ( width ) {
Owen 0:8ae48233b4e4 664
Owen 0:8ae48233b4e4 665 case 3:
Owen 0:8ae48233b4e4 666 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
Owen 0:8ae48233b4e4 667 break;
Owen 0:8ae48233b4e4 668
Owen 0:8ae48233b4e4 669 case 4:
Owen 0:8ae48233b4e4 670 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
Owen 0:8ae48233b4e4 671 break;
Owen 0:8ae48233b4e4 672
Owen 0:8ae48233b4e4 673 case 5:
Owen 0:8ae48233b4e4 674 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
Owen 0:8ae48233b4e4 675 break;
Owen 0:8ae48233b4e4 676
Owen 0:8ae48233b4e4 677 default:
Owen 0:8ae48233b4e4 678 error( "nRF24L01P: Invalid setTxAddress width setting %d\r\n", width );
Owen 0:8ae48233b4e4 679 return;
Owen 0:8ae48233b4e4 680
Owen 0:8ae48233b4e4 681 }
Owen 0:8ae48233b4e4 682
Owen 0:8ae48233b4e4 683 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
Owen 0:8ae48233b4e4 684
Owen 0:8ae48233b4e4 685 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 686
Owen 0:8ae48233b4e4 687 nCS_ = 0;
Owen 0:8ae48233b4e4 688
Owen 0:8ae48233b4e4 689 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 690
Owen 0:8ae48233b4e4 691 while ( width-- > 0 ) {
Owen 0:8ae48233b4e4 692
Owen 0:8ae48233b4e4 693 //
Owen 0:8ae48233b4e4 694 // LSByte first
Owen 0:8ae48233b4e4 695 //
Owen 0:8ae48233b4e4 696 spi_.write((int) (address & 0xFF));
Owen 0:8ae48233b4e4 697 address >>= 8;
Owen 0:8ae48233b4e4 698
Owen 0:8ae48233b4e4 699 }
Owen 0:8ae48233b4e4 700
Owen 0:8ae48233b4e4 701 nCS_ = 1;
Owen 0:8ae48233b4e4 702
Owen 0:8ae48233b4e4 703 }
Owen 0:8ae48233b4e4 704
Owen 0:8ae48233b4e4 705
Owen 0:8ae48233b4e4 706 unsigned long long nRF24L01P::getRxAddress(int pipe) {
Owen 0:8ae48233b4e4 707
Owen 0:8ae48233b4e4 708 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 709
Owen 0:8ae48233b4e4 710 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 711 return 0;
Owen 0:8ae48233b4e4 712
Owen 0:8ae48233b4e4 713 }
Owen 0:8ae48233b4e4 714
Owen 0:8ae48233b4e4 715 int width;
Owen 0:8ae48233b4e4 716
Owen 0:8ae48233b4e4 717 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
Owen 0:8ae48233b4e4 718
Owen 0:8ae48233b4e4 719 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 720
Owen 0:8ae48233b4e4 721 switch ( setupAw ) {
Owen 0:8ae48233b4e4 722
Owen 0:8ae48233b4e4 723 case _NRF24L01P_SETUP_AW_AW_3BYTE:
Owen 0:8ae48233b4e4 724 width = 3;
Owen 0:8ae48233b4e4 725 break;
Owen 0:8ae48233b4e4 726
Owen 0:8ae48233b4e4 727 case _NRF24L01P_SETUP_AW_AW_4BYTE:
Owen 0:8ae48233b4e4 728 width = 4;
Owen 0:8ae48233b4e4 729 break;
Owen 0:8ae48233b4e4 730
Owen 0:8ae48233b4e4 731 case _NRF24L01P_SETUP_AW_AW_5BYTE:
Owen 0:8ae48233b4e4 732 width = 5;
Owen 0:8ae48233b4e4 733 break;
Owen 0:8ae48233b4e4 734
Owen 0:8ae48233b4e4 735 default:
Owen 0:8ae48233b4e4 736 error( "nRF24L01P: Unknown getRxAddress width value %d\r\n", setupAw );
Owen 0:8ae48233b4e4 737 return 0;
Owen 0:8ae48233b4e4 738
Owen 0:8ae48233b4e4 739 }
Owen 0:8ae48233b4e4 740
Owen 0:8ae48233b4e4 741 } else {
Owen 0:8ae48233b4e4 742
Owen 0:8ae48233b4e4 743 width = 1;
Owen 0:8ae48233b4e4 744
Owen 0:8ae48233b4e4 745 }
Owen 0:8ae48233b4e4 746
Owen 0:8ae48233b4e4 747 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 748
Owen 0:8ae48233b4e4 749 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 750
Owen 0:8ae48233b4e4 751 unsigned long long address = 0;
Owen 0:8ae48233b4e4 752
Owen 0:8ae48233b4e4 753 nCS_ = 0;
Owen 0:8ae48233b4e4 754
Owen 0:8ae48233b4e4 755 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 756
Owen 0:8ae48233b4e4 757 for ( int i=0; i<width; i++ ) {
Owen 0:8ae48233b4e4 758
Owen 0:8ae48233b4e4 759 //
Owen 0:8ae48233b4e4 760 // LSByte first
Owen 0:8ae48233b4e4 761 //
Owen 0:8ae48233b4e4 762 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
Owen 0:8ae48233b4e4 763
Owen 0:8ae48233b4e4 764 }
Owen 0:8ae48233b4e4 765
Owen 0:8ae48233b4e4 766 nCS_ = 1;
Owen 0:8ae48233b4e4 767
Owen 0:8ae48233b4e4 768 if ( !( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) ) {
Owen 0:8ae48233b4e4 769
Owen 0:8ae48233b4e4 770 address |= ( getRxAddress(NRF24L01P_PIPE_P1) & ~((unsigned long long) 0xFF) );
Owen 0:8ae48233b4e4 771
Owen 0:8ae48233b4e4 772 }
Owen 0:8ae48233b4e4 773
Owen 0:8ae48233b4e4 774 return address;
Owen 0:8ae48233b4e4 775
Owen 0:8ae48233b4e4 776 }
Owen 0:8ae48233b4e4 777
Owen 0:8ae48233b4e4 778
Owen 0:8ae48233b4e4 779 unsigned long long nRF24L01P::getTxAddress(void) {
Owen 0:8ae48233b4e4 780
Owen 0:8ae48233b4e4 781 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 782
Owen 0:8ae48233b4e4 783 int width;
Owen 0:8ae48233b4e4 784
Owen 0:8ae48233b4e4 785 switch ( setupAw ) {
Owen 0:8ae48233b4e4 786
Owen 0:8ae48233b4e4 787 case _NRF24L01P_SETUP_AW_AW_3BYTE:
Owen 0:8ae48233b4e4 788 width = 3;
Owen 0:8ae48233b4e4 789 break;
Owen 0:8ae48233b4e4 790
Owen 0:8ae48233b4e4 791 case _NRF24L01P_SETUP_AW_AW_4BYTE:
Owen 0:8ae48233b4e4 792 width = 4;
Owen 0:8ae48233b4e4 793 break;
Owen 0:8ae48233b4e4 794
Owen 0:8ae48233b4e4 795 case _NRF24L01P_SETUP_AW_AW_5BYTE:
Owen 0:8ae48233b4e4 796 width = 5;
Owen 0:8ae48233b4e4 797 break;
Owen 0:8ae48233b4e4 798
Owen 0:8ae48233b4e4 799 default:
Owen 0:8ae48233b4e4 800 error( "nRF24L01P: Unknown getTxAddress width value %d\r\n", setupAw );
Owen 0:8ae48233b4e4 801 return 0;
Owen 0:8ae48233b4e4 802
Owen 0:8ae48233b4e4 803 }
Owen 0:8ae48233b4e4 804
Owen 0:8ae48233b4e4 805 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 806
Owen 0:8ae48233b4e4 807 unsigned long long address = 0;
Owen 0:8ae48233b4e4 808
Owen 0:8ae48233b4e4 809 nCS_ = 0;
Owen 0:8ae48233b4e4 810
Owen 0:8ae48233b4e4 811 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 812
Owen 0:8ae48233b4e4 813 for ( int i=0; i<width; i++ ) {
Owen 0:8ae48233b4e4 814
Owen 0:8ae48233b4e4 815 //
Owen 0:8ae48233b4e4 816 // LSByte first
Owen 0:8ae48233b4e4 817 //
Owen 0:8ae48233b4e4 818 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
Owen 0:8ae48233b4e4 819
Owen 0:8ae48233b4e4 820 }
Owen 0:8ae48233b4e4 821
Owen 0:8ae48233b4e4 822 nCS_ = 1;
Owen 0:8ae48233b4e4 823
Owen 0:8ae48233b4e4 824 return address;
Owen 0:8ae48233b4e4 825 }
Owen 0:8ae48233b4e4 826
Owen 0:8ae48233b4e4 827
Owen 0:8ae48233b4e4 828 bool nRF24L01P::readable(int pipe) {
Owen 0:8ae48233b4e4 829
Owen 0:8ae48233b4e4 830 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 831
Owen 0:8ae48233b4e4 832 error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 833 return false;
Owen 0:8ae48233b4e4 834
Owen 0:8ae48233b4e4 835 }
Owen 0:8ae48233b4e4 836
Owen 0:8ae48233b4e4 837 int status = getStatusRegister();
Owen 0:8ae48233b4e4 838
Owen 0:8ae48233b4e4 839 return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) );
Owen 0:8ae48233b4e4 840
Owen 0:8ae48233b4e4 841 }
Owen 0:8ae48233b4e4 842
Owen 0:8ae48233b4e4 843
Owen 0:8ae48233b4e4 844 int nRF24L01P::write(int pipe, char *data, int count) {
Owen 0:8ae48233b4e4 845
Owen 0:8ae48233b4e4 846 // Note: the pipe number is ignored in a Transmit / write
Owen 0:8ae48233b4e4 847
Owen 0:8ae48233b4e4 848 //
Owen 0:8ae48233b4e4 849 // Save the CE state
Owen 0:8ae48233b4e4 850 //
Owen 0:8ae48233b4e4 851 int originalCe = ce_;
Owen 0:8ae48233b4e4 852 disable();
Owen 0:8ae48233b4e4 853
Owen 0:8ae48233b4e4 854 if ( count <= 0 ) return 0;
Owen 0:8ae48233b4e4 855
Owen 0:8ae48233b4e4 856 if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE;
Owen 0:8ae48233b4e4 857
Owen 0:8ae48233b4e4 858 // Clear the Status bit
Owen 0:8ae48233b4e4 859 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
Owen 0:8ae48233b4e4 860
Owen 0:8ae48233b4e4 861 nCS_ = 0;
Owen 0:8ae48233b4e4 862
Owen 0:8ae48233b4e4 863 int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
Owen 0:8ae48233b4e4 864
Owen 0:8ae48233b4e4 865 for ( int i = 0; i < count; i++ ) {
Owen 0:8ae48233b4e4 866
Owen 0:8ae48233b4e4 867 spi_.write(*data++);
Owen 0:8ae48233b4e4 868
Owen 0:8ae48233b4e4 869 }
Owen 0:8ae48233b4e4 870
Owen 0:8ae48233b4e4 871 nCS_ = 1;
Owen 0:8ae48233b4e4 872
Owen 0:8ae48233b4e4 873 int originalMode = mode;
Owen 0:8ae48233b4e4 874 setTransmitMode();
Owen 0:8ae48233b4e4 875
Owen 0:8ae48233b4e4 876 enable();
Owen 0:8ae48233b4e4 877 wait_us(_NRF24L01P_TIMING_Thce_us);
Owen 0:8ae48233b4e4 878 disable();
Owen 0:8ae48233b4e4 879
Owen 0:8ae48233b4e4 880 while ( !( getStatusRegister() & _NRF24L01P_STATUS_TX_DS ) ) {
Owen 0:8ae48233b4e4 881
Owen 0:8ae48233b4e4 882 // Wait for the transfer to complete
Owen 0:8ae48233b4e4 883
Owen 0:8ae48233b4e4 884 }
Owen 0:8ae48233b4e4 885
Owen 0:8ae48233b4e4 886 // Clear the Status bit
Owen 0:8ae48233b4e4 887 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
Owen 0:8ae48233b4e4 888
Owen 0:8ae48233b4e4 889 if ( originalMode == _NRF24L01P_MODE_RX ) {
Owen 0:8ae48233b4e4 890
Owen 0:8ae48233b4e4 891 setReceiveMode();
Owen 0:8ae48233b4e4 892
Owen 0:8ae48233b4e4 893 }
Owen 0:8ae48233b4e4 894
Owen 0:8ae48233b4e4 895 ce_ = originalCe;
Owen 0:8ae48233b4e4 896 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
Owen 0:8ae48233b4e4 897
Owen 0:8ae48233b4e4 898 return count;
Owen 0:8ae48233b4e4 899
Owen 0:8ae48233b4e4 900 }
Owen 0:8ae48233b4e4 901
Owen 0:8ae48233b4e4 902
Owen 0:8ae48233b4e4 903 int nRF24L01P::read(int pipe, char *data, int count) {
Owen 0:8ae48233b4e4 904
Owen 0:8ae48233b4e4 905 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 906
Owen 0:8ae48233b4e4 907 error( "nRF24L01P: Invalid read pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 908 return -1;
Owen 0:8ae48233b4e4 909
Owen 0:8ae48233b4e4 910 }
Owen 0:8ae48233b4e4 911
Owen 0:8ae48233b4e4 912 if ( count <= 0 ) return 0;
Owen 0:8ae48233b4e4 913
Owen 0:8ae48233b4e4 914 if ( count > _NRF24L01P_RX_FIFO_SIZE ) count = _NRF24L01P_RX_FIFO_SIZE;
Owen 0:8ae48233b4e4 915
Owen 0:8ae48233b4e4 916 if ( readable(pipe) ) {
Owen 0:8ae48233b4e4 917
Owen 0:8ae48233b4e4 918 nCS_ = 0;
Owen 0:8ae48233b4e4 919
Owen 0:8ae48233b4e4 920 int status = spi_.write(_NRF24L01P_SPI_CMD_R_RX_PL_WID);
Owen 0:8ae48233b4e4 921
Owen 0:8ae48233b4e4 922 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 923
Owen 0:8ae48233b4e4 924 nCS_ = 1;
Owen 0:8ae48233b4e4 925
Owen 0:8ae48233b4e4 926 if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
Owen 0:8ae48233b4e4 927
Owen 0:8ae48233b4e4 928 // Received payload error: need to flush the FIFO
Owen 0:8ae48233b4e4 929
Owen 0:8ae48233b4e4 930 nCS_ = 0;
Owen 0:8ae48233b4e4 931
Owen 0:8ae48233b4e4 932 int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
Owen 0:8ae48233b4e4 933
Owen 0:8ae48233b4e4 934 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 935
Owen 0:8ae48233b4e4 936 nCS_ = 1;
Owen 0:8ae48233b4e4 937
Owen 0:8ae48233b4e4 938 //
Owen 0:8ae48233b4e4 939 // At this point, we should retry the reception,
Owen 0:8ae48233b4e4 940 // but for now we'll just fall through...
Owen 0:8ae48233b4e4 941 //
Owen 0:8ae48233b4e4 942
Owen 0:8ae48233b4e4 943 } else {
Owen 0:8ae48233b4e4 944
Owen 0:8ae48233b4e4 945 if ( rxPayloadWidth < count ) count = rxPayloadWidth;
Owen 0:8ae48233b4e4 946
Owen 0:8ae48233b4e4 947 nCS_ = 0;
Owen 0:8ae48233b4e4 948
Owen 0:8ae48233b4e4 949 int status = spi_.write(_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD);
Owen 0:8ae48233b4e4 950
Owen 0:8ae48233b4e4 951 for ( int i = 0; i < count; i++ ) {
Owen 0:8ae48233b4e4 952
Owen 0:8ae48233b4e4 953 *data++ = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 954
Owen 0:8ae48233b4e4 955 }
Owen 0:8ae48233b4e4 956
Owen 0:8ae48233b4e4 957 nCS_ = 1;
Owen 0:8ae48233b4e4 958
Owen 0:8ae48233b4e4 959 // Clear the Status bit
Owen 0:8ae48233b4e4 960 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_RX_DR);
Owen 0:8ae48233b4e4 961
Owen 0:8ae48233b4e4 962 return count;
Owen 0:8ae48233b4e4 963
Owen 0:8ae48233b4e4 964 }
Owen 0:8ae48233b4e4 965
Owen 0:8ae48233b4e4 966 } else {
Owen 0:8ae48233b4e4 967
Owen 0:8ae48233b4e4 968 //
Owen 0:8ae48233b4e4 969 // What should we do if there is no 'readable' data?
Owen 0:8ae48233b4e4 970 // We could wait for data to arrive, but for now, we'll
Owen 0:8ae48233b4e4 971 // just return with no data.
Owen 0:8ae48233b4e4 972 //
Owen 0:8ae48233b4e4 973 return 0;
Owen 0:8ae48233b4e4 974
Owen 0:8ae48233b4e4 975 }
Owen 0:8ae48233b4e4 976
Owen 0:8ae48233b4e4 977 //
Owen 0:8ae48233b4e4 978 // We get here because an error condition occured;
Owen 0:8ae48233b4e4 979 // We could wait for data to arrive, but for now, we'll
Owen 0:8ae48233b4e4 980 // just return with no data.
Owen 0:8ae48233b4e4 981 //
Owen 0:8ae48233b4e4 982 return -1;
Owen 0:8ae48233b4e4 983
Owen 0:8ae48233b4e4 984 }
Owen 0:8ae48233b4e4 985
Owen 0:8ae48233b4e4 986 void nRF24L01P::setRegister(int regAddress, int regData) {
Owen 0:8ae48233b4e4 987
Owen 0:8ae48233b4e4 988 //
Owen 0:8ae48233b4e4 989 // Save the CE state
Owen 0:8ae48233b4e4 990 //
Owen 0:8ae48233b4e4 991 int originalCe = ce_;
Owen 0:8ae48233b4e4 992 disable();
Owen 0:8ae48233b4e4 993
Owen 0:8ae48233b4e4 994 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 995
Owen 0:8ae48233b4e4 996 nCS_ = 0;
Owen 0:8ae48233b4e4 997
Owen 0:8ae48233b4e4 998 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 999
Owen 0:8ae48233b4e4 1000 spi_.write(regData & 0xFF);
Owen 0:8ae48233b4e4 1001
Owen 0:8ae48233b4e4 1002 nCS_ = 1;
Owen 0:8ae48233b4e4 1003
Owen 0:8ae48233b4e4 1004 ce_ = originalCe;
Owen 0:8ae48233b4e4 1005 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
Owen 0:8ae48233b4e4 1006
Owen 0:8ae48233b4e4 1007 }
Owen 0:8ae48233b4e4 1008
Owen 0:8ae48233b4e4 1009
Owen 0:8ae48233b4e4 1010 int nRF24L01P::getRegister(int regAddress) {
Owen 0:8ae48233b4e4 1011
Owen 0:8ae48233b4e4 1012 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 1013
Owen 0:8ae48233b4e4 1014 nCS_ = 0;
Owen 0:8ae48233b4e4 1015
Owen 0:8ae48233b4e4 1016 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 1017
Owen 0:8ae48233b4e4 1018 int dn = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 1019
Owen 0:8ae48233b4e4 1020 nCS_ = 1;
Owen 0:8ae48233b4e4 1021
Owen 0:8ae48233b4e4 1022 return dn;
Owen 0:8ae48233b4e4 1023
Owen 0:8ae48233b4e4 1024 }
Owen 0:8ae48233b4e4 1025
Owen 0:8ae48233b4e4 1026 int nRF24L01P::getStatusRegister(void) {
Owen 0:8ae48233b4e4 1027
Owen 0:8ae48233b4e4 1028 nCS_ = 0;
Owen 0:8ae48233b4e4 1029
Owen 0:8ae48233b4e4 1030 int status = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 1031
Owen 0:8ae48233b4e4 1032 nCS_ = 1;
Owen 0:8ae48233b4e4 1033
Owen 0:8ae48233b4e4 1034 return status;
Owen 0:8ae48233b4e4 1035
Owen 0:8ae48233b4e4 1036 }
khuang 1:b3ea38f27b69 1037
khuang 1:b3ea38f27b69 1038 bool nRF24L01P::getRPD(){
khuang 1:b3ea38f27b69 1039 uint8_t rpd = getRegister(_NRF24L01P_REG_RPD);
khuang 1:b3ea38f27b69 1040 return (rpd>0);
khuang 1:b3ea38f27b69 1041 }
khuang 1:b3ea38f27b69 1042
khuang 1:b3ea38f27b69 1043 uint8_t nRF24L01P::getRSSI(){
khuang 1:b3ea38f27b69 1044 uint8_t rssi =0;
khuang 1:b3ea38f27b69 1045 for(int i=0; i<256; i++){
khuang 1:b3ea38f27b69 1046 rssi += getRPD();
khuang 1:b3ea38f27b69 1047 Thread::wait(50);
khuang 1:b3ea38f27b69 1048 flushRx();
khuang 1:b3ea38f27b69 1049 }
khuang 1:b3ea38f27b69 1050 return rssi;
khuang 1:b3ea38f27b69 1051 }
khuang 1:b3ea38f27b69 1052
khuang 1:b3ea38f27b69 1053 void nRF24L01P::flushRx(void)
khuang 1:b3ea38f27b69 1054 {
khuang 1:b3ea38f27b69 1055 nCS_ = 0;
khuang 1:b3ea38f27b69 1056 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
khuang 1:b3ea38f27b69 1057 nCS_ = 1;
khuang 1:b3ea38f27b69 1058 }
khuang 1:b3ea38f27b69 1059
khuang 1:b3ea38f27b69 1060 void nRF24L01P::flushTx(void)
khuang 1:b3ea38f27b69 1061 {
khuang 1:b3ea38f27b69 1062 nCS_ = 0;
khuang 1:b3ea38f27b69 1063 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_TX);
khuang 1:b3ea38f27b69 1064 nCS_ = 1;
khuang 1:b3ea38f27b69 1065 }