Kiyoshi Hayakawa / lwip-eth_ccx

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Dependents:   EthernetInterface_ccx

Fork of lwip-eth by mbed official

arch/lpc_phy_dp83848.c@7:f974fe69517d, 2013-09-28 (annotated)

Committer:
khayakawa
Date:
Sat Sep 28 16:34:46 2013 +0000
Revision:
7:f974fe69517d
Parent:
5:698d868a5285 
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 4:d827a085afd9 1 /**********************************************************************
khayakawa 7:f974fe69517d 2 * $Id$ lpc_phy_dp83848.c 2011-11-20
emilmont 4:d827a085afd9 3 *//**
khayakawa 7:f974fe69517d 4 * @file lpc_phy_dp83848.c
khayakawa 7:f974fe69517d 5 * @brief DP83848C PHY status and control.
khayakawa 7:f974fe69517d 6 * @version 1.0
khayakawa 7:f974fe69517d 7 * @date 20 Nov. 2011
khayakawa 7:f974fe69517d 8 * @author NXP MCU SW Application Team
emilmont 4:d827a085afd9 9 *
emilmont 4:d827a085afd9 10 * Copyright(C) 2011, NXP Semiconductor
emilmont 4:d827a085afd9 11 * All rights reserved.
emilmont 4:d827a085afd9 12 *
emilmont 4:d827a085afd9 13 ***********************************************************************
emilmont 4:d827a085afd9 14 * Software that is described herein is for illustrative purposes only
emilmont 4:d827a085afd9 15 * which provides customers with programming information regarding the
emilmont 4:d827a085afd9 16 * products. This software is supplied "AS IS" without any warranties.
emilmont 4:d827a085afd9 17 * NXP Semiconductors assumes no responsibility or liability for the
emilmont 4:d827a085afd9 18 * use of the software, conveys no license or title under any patent,
emilmont 4:d827a085afd9 19 * copyright, or mask work right to the product. NXP Semiconductors
emilmont 4:d827a085afd9 20 * reserves the right to make changes in the software without
emilmont 4:d827a085afd9 21 * notification. NXP Semiconductors also make no representation or
emilmont 4:d827a085afd9 22 * warranty that such application will be suitable for the specified
emilmont 4:d827a085afd9 23 * use without further testing or modification.
emilmont 4:d827a085afd9 24 **********************************************************************/
emilmont 4:d827a085afd9 25
emilmont 4:d827a085afd9 26 #include "lwip/opt.h"
emilmont 4:d827a085afd9 27 #include "lwip/err.h"
emilmont 4:d827a085afd9 28 #include "lwip/tcpip.h"
emilmont 4:d827a085afd9 29 #include "lwip/snmp.h"
emilmont 4:d827a085afd9 30 #include "lpc_emac_config.h"
emilmont 4:d827a085afd9 31 #include "lpc_phy.h"
emilmont 4:d827a085afd9 32
khayakawa 7:f974fe69517d 33 /** @defgroup dp83848_phy PHY status and control for the DP83848.
emilmont 4:d827a085afd9 34 * @ingroup lwip_phy
emilmont 4:d827a085afd9 35 *
emilmont 4:d827a085afd9 36 * Various functions for controlling and monitoring the status of the
emilmont 4:d827a085afd9 37 * DP83848 PHY. In polled (standalone) systems, the PHY state must be
emilmont 4:d827a085afd9 38 * monitored as part of the application. In a threaded (RTOS) system,
emilmont 4:d827a085afd9 39 * the PHY state is monitored by the PHY handler thread. The MAC
emilmont 4:d827a085afd9 40 * driver will not transmit unless the PHY link is active.
emilmont 4:d827a085afd9 41 * @{
emilmont 4:d827a085afd9 42 */
emilmont 4:d827a085afd9 43
emilmont 4:d827a085afd9 44 /** \brief DP83848 PHY register offsets */
emilmont 4:d827a085afd9 45 #define DP8_BMCR_REG 0x0 /**< Basic Mode Control Register */
emilmont 4:d827a085afd9 46 #define DP8_BMSR_REG 0x1 /**< Basic Mode Status Reg */
emilmont 5:698d868a5285 47 #define DP8_IDR1_REG 0x2 /**< Basic Mode Status Reg */
emilmont 5:698d868a5285 48 #define DP8_IDR2_REG 0x3 /**< Basic Mode Status Reg */
emilmont 4:d827a085afd9 49 #define DP8_ANADV_REG 0x4 /**< Auto_Neg Advt Reg */
emilmont 4:d827a085afd9 50 #define DP8_ANLPA_REG 0x5 /**< Auto_neg Link Partner Ability Reg */
emilmont 4:d827a085afd9 51 #define DP8_ANEEXP_REG 0x6 /**< Auto-neg Expansion Reg */
emilmont 4:d827a085afd9 52 #define DP8_PHY_STAT_REG 0x10 /**< PHY Status Register */
emilmont 4:d827a085afd9 53 #define DP8_PHY_INT_CTL_REG 0x11 /**< PHY Interrupt Control Register */
emilmont 4:d827a085afd9 54 #define DP8_PHY_RBR_REG 0x17 /**< PHY RMII and Bypass Register */
emilmont 4:d827a085afd9 55 #define DP8_PHY_STS_REG 0x19 /**< PHY Status Register */
emilmont 4:d827a085afd9 56
emilmont 5:698d868a5285 57 #define DP8_PHY_SCSR_REG 0x1f /**< PHY Special Control/Status Register (LAN8720) */
emilmont 5:698d868a5285 58
emilmont 4:d827a085afd9 59 /** \brief DP83848 Control register definitions */
emilmont 4:d827a085afd9 60 #define DP8_RESET (1 << 15) /**< 1= S/W Reset */
emilmont 4:d827a085afd9 61 #define DP8_LOOPBACK (1 << 14) /**< 1=loopback Enabled */
emilmont 4:d827a085afd9 62 #define DP8_SPEED_SELECT (1 << 13) /**< 1=Select 100MBps */
emilmont 4:d827a085afd9 63 #define DP8_AUTONEG (1 << 12) /**< 1=Enable auto-negotiation */
emilmont 4:d827a085afd9 64 #define DP8_POWER_DOWN (1 << 11) /**< 1=Power down PHY */
emilmont 4:d827a085afd9 65 #define DP8_ISOLATE (1 << 10) /**< 1=Isolate PHY */
emilmont 4:d827a085afd9 66 #define DP8_RESTART_AUTONEG (1 << 9) /**< 1=Restart auto-negoatiation */
emilmont 4:d827a085afd9 67 #define DP8_DUPLEX_MODE (1 << 8) /**< 1=Full duplex mode */
emilmont 4:d827a085afd9 68 #define DP8_COLLISION_TEST (1 << 7) /**< 1=Perform collsion test */
emilmont 4:d827a085afd9 69
emilmont 4:d827a085afd9 70 /** \brief DP83848 Status register definitions */
emilmont 4:d827a085afd9 71 #define DP8_100BASE_T4 (1 << 15) /**< T4 mode */
emilmont 4:d827a085afd9 72 #define DP8_100BASE_TX_FD (1 << 14) /**< 100MBps full duplex */
emilmont 4:d827a085afd9 73 #define DP8_100BASE_TX_HD (1 << 13) /**< 100MBps half duplex */
emilmont 4:d827a085afd9 74 #define DP8_10BASE_T_FD (1 << 12) /**< 100Bps full duplex */
emilmont 4:d827a085afd9 75 #define DP8_10BASE_T_HD (1 << 11) /**< 10MBps half duplex */
emilmont 4:d827a085afd9 76 #define DP8_MF_PREAMB_SUPPR (1 << 6) /**< Preamble suppress */
emilmont 4:d827a085afd9 77 #define DP8_AUTONEG_COMP (1 << 5) /**< Auto-negotation complete */
emilmont 4:d827a085afd9 78 #define DP8_RMT_FAULT (1 << 4) /**< Fault */
emilmont 4:d827a085afd9 79 #define DP8_AUTONEG_ABILITY (1 << 3) /**< Auto-negotation supported */
emilmont 4:d827a085afd9 80 #define DP8_LINK_STATUS (1 << 2) /**< 1=Link active */
emilmont 4:d827a085afd9 81 #define DP8_JABBER_DETECT (1 << 1) /**< Jabber detect */
emilmont 4:d827a085afd9 82 #define DP8_EXTEND_CAPAB (1 << 0) /**< Supports extended capabilities */
emilmont 4:d827a085afd9 83
emilmont 4:d827a085afd9 84 /** \brief DP83848 PHY RBR MII dode definitions */
emilmont 4:d827a085afd9 85 #define DP8_RBR_RMII_MODE (1 << 5) /**< Use RMII mode */
emilmont 4:d827a085afd9 86
emilmont 4:d827a085afd9 87 /** \brief DP83848 PHY status definitions */
emilmont 4:d827a085afd9 88 #define DP8_REMOTEFAULT (1 << 6) /**< Remote fault */
emilmont 4:d827a085afd9 89 #define DP8_FULLDUPLEX (1 << 2) /**< 1=full duplex */
emilmont 4:d827a085afd9 90 #define DP8_SPEED10MBPS (1 << 1) /**< 1=10MBps speed */
emilmont 4:d827a085afd9 91 #define DP8_VALID_LINK (1 << 0) /**< 1=Link active */
emilmont 4:d827a085afd9 92
emilmont 4:d827a085afd9 93 /** \brief DP83848 PHY ID register definitions */
emilmont 4:d827a085afd9 94 #define DP8_PHYID1_OUI 0x2000 /**< Expected PHY ID1 */
emilmont 4:d827a085afd9 95 #define DP8_PHYID2_OUI 0x5c90 /**< Expected PHY ID2 */
emilmont 4:d827a085afd9 96
emilmont 5:698d868a5285 97 /** \brief LAN8720 PHY Special Control/Status Register */
emilmont 5:698d868a5285 98 #define PHY_SCSR_100MBIT 0x0008 /**< Speed: 1=100 MBit, 0=10Mbit */
emilmont 5:698d868a5285 99 #define PHY_SCSR_DUPLEX 0x0010 /**< PHY Duplex Mask */
emilmont 5:698d868a5285 100
emilmont 5:698d868a5285 101 /** \brief Link status bits */
emilmont 5:698d868a5285 102 #define LNK_STAT_VALID 0x01
emilmont 5:698d868a5285 103 #define LNK_STAT_FULLDUPLEX 0x02
emilmont 5:698d868a5285 104 #define LNK_STAT_SPEED10MPS 0x04
emilmont 5:698d868a5285 105
emilmont 5:698d868a5285 106 /** \brief PHY ID definitions */
emilmont 5:698d868a5285 107 #define DP83848C_ID 0x20005C90 /**< PHY Identifier - DP83848C */
emilmont 5:698d868a5285 108 #define LAN8720_ID 0x0007C0F0 /**< PHY Identifier - LAN8720 */
emilmont 5:698d868a5285 109
emilmont 4:d827a085afd9 110 /** \brief PHY status structure used to indicate current status of PHY.
emilmont 4:d827a085afd9 111 */
emilmont 4:d827a085afd9 112 typedef struct {
khayakawa 7:f974fe69517d 113 u32_t phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
khayakawa 7:f974fe69517d 114 u32_t phy_full_duplex:1; /**< Half/full duplex connection speed flag. */
khayakawa 7:f974fe69517d 115 u32_t phy_link_active:1; /**< Phy link active flag. */
emilmont 4:d827a085afd9 116 } PHY_STATUS_TYPE;
emilmont 4:d827a085afd9 117
emilmont 4:d827a085afd9 118 /** \brief PHY update flags */
emilmont 4:d827a085afd9 119 static PHY_STATUS_TYPE physts;
emilmont 4:d827a085afd9 120
emilmont 4:d827a085afd9 121 /** \brief Last PHY update flags, used for determing if something has changed */
emilmont 4:d827a085afd9 122 static PHY_STATUS_TYPE olddphysts;
emilmont 4:d827a085afd9 123
emilmont 4:d827a085afd9 124 /** \brief PHY update counter for state machine */
emilmont 4:d827a085afd9 125 static s32_t phyustate;
emilmont 4:d827a085afd9 126
emilmont 5:698d868a5285 127 /** \brief Holds the PHY ID */
emilmont 5:698d868a5285 128 static u32_t phy_id;
emilmont 5:698d868a5285 129
emilmont 5:698d868a5285 130 /** \brief Temporary holder of link status for LAN7420 */
emilmont 5:698d868a5285 131 static u32_t phy_lan7420_sts_tmp;
emilmont 5:698d868a5285 132
emilmont 4:d827a085afd9 133 /** \brief Update PHY status from passed value
emilmont 4:d827a085afd9 134 *
emilmont 4:d827a085afd9 135 * This function updates the current PHY status based on the
emilmont 4:d827a085afd9 136 * passed PHY status word. The PHY status indicate if the link
emilmont 4:d827a085afd9 137 * is active, the connection speed, and duplex.
emilmont 4:d827a085afd9 138 *
emilmont 4:d827a085afd9 139 * \param[in] netif NETIF structure
emilmont 4:d827a085afd9 140 * \param[in] linksts Status word from PHY
emilmont 4:d827a085afd9 141 * \return 1 if the status has changed, otherwise 0
emilmont 4:d827a085afd9 142 */
emilmont 4:d827a085afd9 143 static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts)
emilmont 4:d827a085afd9 144 {
khayakawa 7:f974fe69517d 145 s32_t changed = 0;
emilmont 4:d827a085afd9 146
khayakawa 7:f974fe69517d 147 /* Update link active status */
khayakawa 7:f974fe69517d 148 if (linksts & LNK_STAT_VALID)
khayakawa 7:f974fe69517d 149 physts.phy_link_active = 1;
khayakawa 7:f974fe69517d 150 else
khayakawa 7:f974fe69517d 151 physts.phy_link_active = 0;
emilmont 4:d827a085afd9 152
khayakawa 7:f974fe69517d 153 /* Full or half duplex */
khayakawa 7:f974fe69517d 154 if (linksts & LNK_STAT_FULLDUPLEX)
khayakawa 7:f974fe69517d 155 physts.phy_full_duplex = 1;
khayakawa 7:f974fe69517d 156 else
khayakawa 7:f974fe69517d 157 physts.phy_full_duplex = 0;
emilmont 4:d827a085afd9 158
khayakawa 7:f974fe69517d 159 /* Configure 100MBit/10MBit mode. */
khayakawa 7:f974fe69517d 160 if (linksts & LNK_STAT_SPEED10MPS)
khayakawa 7:f974fe69517d 161 physts.phy_speed_100mbs = 0;
khayakawa 7:f974fe69517d 162 else
khayakawa 7:f974fe69517d 163 physts.phy_speed_100mbs = 1;
emilmont 4:d827a085afd9 164
khayakawa 7:f974fe69517d 165 if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
khayakawa 7:f974fe69517d 166 changed = 1;
khayakawa 7:f974fe69517d 167 if (physts.phy_speed_100mbs) {
khayakawa 7:f974fe69517d 168 /* 100MBit mode. */
khayakawa 7:f974fe69517d 169 lpc_emac_set_speed(1);
emilmont 4:d827a085afd9 170
khayakawa 7:f974fe69517d 171 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
khayakawa 7:f974fe69517d 172 }
khayakawa 7:f974fe69517d 173 else {
khayakawa 7:f974fe69517d 174 /* 10MBit mode. */
khayakawa 7:f974fe69517d 175 lpc_emac_set_speed(0);
emilmont 4:d827a085afd9 176
khayakawa 7:f974fe69517d 177 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
khayakawa 7:f974fe69517d 178 }
emilmont 4:d827a085afd9 179
khayakawa 7:f974fe69517d 180 olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
khayakawa 7:f974fe69517d 181 }
emilmont 4:d827a085afd9 182
khayakawa 7:f974fe69517d 183 if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
khayakawa 7:f974fe69517d 184 changed = 1;
khayakawa 7:f974fe69517d 185 if (physts.phy_full_duplex)
khayakawa 7:f974fe69517d 186 lpc_emac_set_duplex(1);
khayakawa 7:f974fe69517d 187 else
khayakawa 7:f974fe69517d 188 lpc_emac_set_duplex(0);
emilmont 4:d827a085afd9 189
khayakawa 7:f974fe69517d 190 olddphysts.phy_full_duplex = physts.phy_full_duplex;
khayakawa 7:f974fe69517d 191 }
emilmont 4:d827a085afd9 192
khayakawa 7:f974fe69517d 193 if (physts.phy_link_active != olddphysts.phy_link_active) {
khayakawa 7:f974fe69517d 194 changed = 1;
emilmont 4:d827a085afd9 195 #if NO_SYS == 1
khayakawa 7:f974fe69517d 196 if (physts.phy_link_active)
khayakawa 7:f974fe69517d 197 netif_set_link_up(netif);
khayakawa 7:f974fe69517d 198 else
khayakawa 7:f974fe69517d 199 netif_set_link_down(netif);
emilmont 4:d827a085afd9 200 #else
emilmont 4:d827a085afd9 201 if (physts.phy_link_active)
emilmont 4:d827a085afd9 202 tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
emilmont 4:d827a085afd9 203 (void*) netif, 1);
emilmont 4:d827a085afd9 204 else
emilmont 4:d827a085afd9 205 tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
emilmont 4:d827a085afd9 206 (void*) netif, 1);
emilmont 4:d827a085afd9 207 #endif
emilmont 4:d827a085afd9 208
khayakawa 7:f974fe69517d 209 olddphysts.phy_link_active = physts.phy_link_active;
khayakawa 7:f974fe69517d 210 }
emilmont 4:d827a085afd9 211
khayakawa 7:f974fe69517d 212 return changed;
emilmont 4:d827a085afd9 213 }
emilmont 4:d827a085afd9 214
emilmont 4:d827a085afd9 215 /** \brief Initialize the DP83848 PHY.
emilmont 4:d827a085afd9 216 *
emilmont 4:d827a085afd9 217 * This function initializes the DP83848 PHY. It will block until
emilmont 4:d827a085afd9 218 * complete. This function is called as part of the EMAC driver
emilmont 4:d827a085afd9 219 * initialization. Configuration of the PHY at startup is
emilmont 4:d827a085afd9 220 * controlled by setting up configuration defines in lpc_phy.h.
emilmont 4:d827a085afd9 221 *
emilmont 4:d827a085afd9 222 * \param[in] netif NETIF structure
emilmont 4:d827a085afd9 223 * \param[in] rmii If set, configures the PHY for RMII mode
emilmont 4:d827a085afd9 224 * \return ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
emilmont 4:d827a085afd9 225 */
emilmont 4:d827a085afd9 226 err_t lpc_phy_init(struct netif *netif, int rmii)
emilmont 4:d827a085afd9 227 {
khayakawa 7:f974fe69517d 228 u32_t tmp;
khayakawa 7:f974fe69517d 229 s32_t i;
emilmont 5:698d868a5285 230
khayakawa 7:f974fe69517d 231 physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
khayakawa 7:f974fe69517d 232 physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
khayakawa 7:f974fe69517d 233 physts.phy_link_active = olddphysts.phy_link_active = 2;
khayakawa 7:f974fe69517d 234 phyustate = 0;
emilmont 4:d827a085afd9 235
khayakawa 7:f974fe69517d 236 /* Only first read and write are checked for failure */
khayakawa 7:f974fe69517d 237 /* Put the DP83848C in reset mode and wait for completion */
khayakawa 7:f974fe69517d 238 if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
khayakawa 7:f974fe69517d 239 return ERR_TIMEOUT;
khayakawa 7:f974fe69517d 240 i = 400;
khayakawa 7:f974fe69517d 241 while (i > 0) {
khayakawa 7:f974fe69517d 242 osDelay(1); /* 1 ms */
khayakawa 7:f974fe69517d 243 if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
khayakawa 7:f974fe69517d 244 return ERR_TIMEOUT;
emilmont 4:d827a085afd9 245
khayakawa 7:f974fe69517d 246 if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
khayakawa 7:f974fe69517d 247 i = -1;
khayakawa 7:f974fe69517d 248 else
khayakawa 7:f974fe69517d 249 i--;
khayakawa 7:f974fe69517d 250 }
khayakawa 7:f974fe69517d 251 /* Timeout? */
khayakawa 7:f974fe69517d 252 if (i == 0)
khayakawa 7:f974fe69517d 253 return ERR_TIMEOUT;
emilmont 4:d827a085afd9 254
khayakawa 7:f974fe69517d 255 // read PHY ID
khayakawa 7:f974fe69517d 256 lpc_mii_read(DP8_IDR1_REG, &tmp);
khayakawa 7:f974fe69517d 257 phy_id = (tmp << 16);
khayakawa 7:f974fe69517d 258 lpc_mii_read(DP8_IDR2_REG, &tmp);
khayakawa 7:f974fe69517d 259 phy_id |= (tmp & 0XFFF0);
emilmont 4:d827a085afd9 260
khayakawa 7:f974fe69517d 261 /* Setup link based on configuration options */
emilmont 4:d827a085afd9 262 #if PHY_USE_AUTONEG==1
khayakawa 7:f974fe69517d 263 tmp = DP8_AUTONEG;
emilmont 4:d827a085afd9 264 #else
khayakawa 7:f974fe69517d 265 tmp = 0;
emilmont 4:d827a085afd9 266 #endif
emilmont 4:d827a085afd9 267 #if PHY_USE_100MBS==1
khayakawa 7:f974fe69517d 268 tmp |= DP8_SPEED_SELECT;
emilmont 4:d827a085afd9 269 #endif
emilmont 4:d827a085afd9 270 #if PHY_USE_FULL_DUPLEX==1
khayakawa 7:f974fe69517d 271 tmp |= DP8_DUPLEX_MODE;
emilmont 4:d827a085afd9 272 #endif
khayakawa 7:f974fe69517d 273 lpc_mii_write(DP8_BMCR_REG, tmp);
emilmont 4:d827a085afd9 274
emilmont 4:d827a085afd9 275 /* Enable RMII mode for PHY */
emilmont 4:d827a085afd9 276 if (rmii)
emilmont 4:d827a085afd9 277 lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
emilmont 4:d827a085afd9 278
khayakawa 7:f974fe69517d 279 /* The link is not set active at this point, but will be detected
emilmont 4:d827a085afd9 280 later */
emilmont 4:d827a085afd9 281
khayakawa 7:f974fe69517d 282 return ERR_OK;
emilmont 4:d827a085afd9 283 }
emilmont 4:d827a085afd9 284
emilmont 4:d827a085afd9 285 /* Phy status update state machine */
emilmont 4:d827a085afd9 286 s32_t lpc_phy_sts_sm(struct netif *netif)
emilmont 4:d827a085afd9 287 {
khayakawa 7:f974fe69517d 288 s32_t changed = 0;
khayakawa 7:f974fe69517d 289 u32_t data = 0;
khayakawa 7:f974fe69517d 290 u32_t tmp;
emilmont 4:d827a085afd9 291
khayakawa 7:f974fe69517d 292 switch (phyustate) {
khayakawa 7:f974fe69517d 293 default:
khayakawa 7:f974fe69517d 294 case 0:
khayakawa 7:f974fe69517d 295 if (phy_id == DP83848C_ID) {
khayakawa 7:f974fe69517d 296 lpc_mii_read_noblock(DP8_PHY_STAT_REG);
khayakawa 7:f974fe69517d 297 phyustate = 2;
khayakawa 7:f974fe69517d 298 }
khayakawa 7:f974fe69517d 299 else if (phy_id == LAN8720_ID) {
khayakawa 7:f974fe69517d 300 lpc_mii_read_noblock(DP8_PHY_SCSR_REG);
khayakawa 7:f974fe69517d 301 phyustate = 1;
khayakawa 7:f974fe69517d 302 }
khayakawa 7:f974fe69517d 303 break;
emilmont 5:698d868a5285 304
khayakawa 7:f974fe69517d 305 case 1:
khayakawa 7:f974fe69517d 306 if (phy_id == LAN8720_ID) {
khayakawa 7:f974fe69517d 307 tmp = lpc_mii_read_data();
khayakawa 7:f974fe69517d 308 // we get speed and duplex here.
khayakawa 7:f974fe69517d 309 phy_lan7420_sts_tmp = (tmp & PHY_SCSR_DUPLEX) ? LNK_STAT_FULLDUPLEX : 0;
khayakawa 7:f974fe69517d 310 phy_lan7420_sts_tmp |= (tmp & PHY_SCSR_100MBIT) ? 0 : LNK_STAT_SPEED10MPS;
emilmont 4:d827a085afd9 311
khayakawa 7:f974fe69517d 312 //read the status register to get link status
khayakawa 7:f974fe69517d 313 lpc_mii_read_noblock(DP8_BMSR_REG);
khayakawa 7:f974fe69517d 314 phyustate = 2;
khayakawa 7:f974fe69517d 315 }
khayakawa 7:f974fe69517d 316 break;
emilmont 5:698d868a5285 317
khayakawa 7:f974fe69517d 318 case 2:
khayakawa 7:f974fe69517d 319 /* Wait for read status state */
khayakawa 7:f974fe69517d 320 if (!lpc_mii_is_busy()) {
khayakawa 7:f974fe69517d 321 /* Update PHY status */
khayakawa 7:f974fe69517d 322 tmp = lpc_mii_read_data();
emilmont 4:d827a085afd9 323
khayakawa 7:f974fe69517d 324 if (phy_id == DP83848C_ID) {
khayakawa 7:f974fe69517d 325 // STS register contains all needed status bits
khayakawa 7:f974fe69517d 326 data = (tmp & DP8_VALID_LINK) ? LNK_STAT_VALID : 0;
khayakawa 7:f974fe69517d 327 data |= (tmp & DP8_FULLDUPLEX) ? LNK_STAT_FULLDUPLEX : 0;
khayakawa 7:f974fe69517d 328 data |= (tmp & DP8_SPEED10MBPS) ? LNK_STAT_SPEED10MPS : 0;
khayakawa 7:f974fe69517d 329 }
khayakawa 7:f974fe69517d 330 else if (phy_id == LAN8720_ID) {
khayakawa 7:f974fe69517d 331 // we only get the link status here.
khayakawa 7:f974fe69517d 332 phy_lan7420_sts_tmp |= (tmp & DP8_LINK_STATUS) ? LNK_STAT_VALID : 0;
khayakawa 7:f974fe69517d 333 data = phy_lan7420_sts_tmp;
khayakawa 7:f974fe69517d 334 }
emilmont 5:698d868a5285 335
khayakawa 7:f974fe69517d 336 changed = lpc_update_phy_sts(netif, data);
khayakawa 7:f974fe69517d 337 phyustate = 0;
khayakawa 7:f974fe69517d 338 }
khayakawa 7:f974fe69517d 339 break;
khayakawa 7:f974fe69517d 340 }
emilmont 5:698d868a5285 341
khayakawa 7:f974fe69517d 342 return changed;
emilmont 4:d827a085afd9 343 }
emilmont 4:d827a085afd9 344
emilmont 4:d827a085afd9 345 /**
emilmont 4:d827a085afd9 346 * @}
emilmont 4:d827a085afd9 347 */
emilmont 4:d827a085afd9 348
emilmont 4:d827a085afd9 349 /* --------------------------------- End Of File ------------------------------ */