lpc_phy_dp83848.c

00001 /**********************************************************************
00002 * $Id$        lpc_phy_dp83848.c            2011-11-20
00003 *//**
00004 * @file        lpc_phy_dp83848.c
00005 * @brief    DP83848C PHY status and control.
00006 * @version    1.0
00007 * @date        20 Nov. 2011
00008 * @author    NXP MCU SW Application Team
00009 *
00010 * Copyright(C) 2011, NXP Semiconductor
00011 * All rights reserved.
00012 *
00013 ***********************************************************************
00014 * Software that is described herein is for illustrative purposes only
00015 * which provides customers with programming information regarding the
00016 * products. This software is supplied "AS IS" without any warranties.
00017 * NXP Semiconductors assumes no responsibility or liability for the
00018 * use of the software, conveys no license or title under any patent,
00019 * copyright, or mask work right to the product. NXP Semiconductors
00020 * reserves the right to make changes in the software without
00021 * notification. NXP Semiconductors also make no representation or
00022 * warranty that such application will be suitable for the specified
00023 * use without further testing or modification.
00024 **********************************************************************/
00025 
00026 #include "lwip/opt.h"
00027 #include "lwip/err.h"
00028 #include "lwip/tcpip.h"
00029 #include "lwip/snmp.h"
00030 #include "lpc_emac_config.h"
00031 #include "lpc_phy.h"
00032 
00033 /** @defgroup dp83848_phy    PHY status and control for the DP83848.
00034  * @ingroup lwip_phy
00035  *
00036  * Various functions for controlling and monitoring the status of the
00037  * DP83848 PHY. In polled (standalone) systems, the PHY state must be
00038  * monitored as part of the application. In a threaded (RTOS) system,
00039  * the PHY state is monitored by the PHY handler thread. The MAC
00040  * driver will not transmit unless the PHY link is active.
00041  * @{
00042  */
00043 
00044 /** \brief  DP83848 PHY register offsets */
00045 #define DP8_BMCR_REG        0x0  /**< Basic Mode Control Register */
00046 #define DP8_BMSR_REG        0x1  /**< Basic Mode Status Reg */
00047 #define DP8_IDR1_REG        0x2  /**< Basic Mode Status Reg */
00048 #define DP8_IDR2_REG        0x3  /**< Basic Mode Status Reg */
00049 #define DP8_ANADV_REG       0x4  /**< Auto_Neg Advt Reg  */
00050 #define DP8_ANLPA_REG       0x5  /**< Auto_neg Link Partner Ability Reg */
00051 #define DP8_ANEEXP_REG      0x6  /**< Auto-neg Expansion Reg  */
00052 #define DP8_PHY_STAT_REG    0x10 /**< PHY Status Register  */
00053 #define DP8_PHY_INT_CTL_REG 0x11 /**< PHY Interrupt Control Register */
00054 #define DP8_PHY_RBR_REG     0x17 /**< PHY RMII and Bypass Register  */
00055 #define DP8_PHY_STS_REG     0x19 /**< PHY Status Register  */
00056 
00057 #define DP8_PHY_SCSR_REG    0x1f /**< PHY Special Control/Status Register (LAN8720)  */
00058 
00059 /** \brief DP83848 Control register definitions */
00060 #define DP8_RESET          (1 << 15)  /**< 1= S/W Reset */
00061 #define DP8_LOOPBACK       (1 << 14)  /**< 1=loopback Enabled */
00062 #define DP8_SPEED_SELECT   (1 << 13)  /**< 1=Select 100MBps */
00063 #define DP8_AUTONEG        (1 << 12)  /**< 1=Enable auto-negotiation */
00064 #define DP8_POWER_DOWN     (1 << 11)  /**< 1=Power down PHY */
00065 #define DP8_ISOLATE        (1 << 10)  /**< 1=Isolate PHY */
00066 #define DP8_RESTART_AUTONEG (1 << 9)  /**< 1=Restart auto-negoatiation */
00067 #define DP8_DUPLEX_MODE    (1 << 8)   /**< 1=Full duplex mode */
00068 #define DP8_COLLISION_TEST (1 << 7)   /**< 1=Perform collsion test */
00069 
00070 /** \brief DP83848 Status register definitions */
00071 #define DP8_100BASE_T4     (1 << 15)  /**< T4 mode */
00072 #define DP8_100BASE_TX_FD  (1 << 14)  /**< 100MBps full duplex */
00073 #define DP8_100BASE_TX_HD  (1 << 13)  /**< 100MBps half duplex */
00074 #define DP8_10BASE_T_FD    (1 << 12)  /**< 100Bps full duplex */
00075 #define DP8_10BASE_T_HD    (1 << 11)  /**< 10MBps half duplex */
00076 #define DP8_MF_PREAMB_SUPPR (1 << 6)  /**< Preamble suppress */
00077 #define DP8_AUTONEG_COMP   (1 << 5)   /**< Auto-negotation complete */
00078 #define DP8_RMT_FAULT      (1 << 4)   /**< Fault */
00079 #define DP8_AUTONEG_ABILITY (1 << 3)  /**< Auto-negotation supported */
00080 #define DP8_LINK_STATUS    (1 << 2)   /**< 1=Link active */
00081 #define DP8_JABBER_DETECT  (1 << 1)   /**< Jabber detect */
00082 #define DP8_EXTEND_CAPAB   (1 << 0)   /**< Supports extended capabilities */
00083 
00084 /** \brief DP83848 PHY RBR MII dode definitions */
00085 #define DP8_RBR_RMII_MODE  (1 << 5)   /**< Use RMII mode */
00086 
00087 /** \brief DP83848 PHY status definitions */
00088 #define DP8_REMOTEFAULT    (1 << 6)   /**< Remote fault */
00089 #define DP8_FULLDUPLEX     (1 << 2)   /**< 1=full duplex */
00090 #define DP8_SPEED10MBPS    (1 << 1)   /**< 1=10MBps speed */
00091 #define DP8_VALID_LINK     (1 << 0)   /**< 1=Link active */
00092 
00093 /** \brief DP83848 PHY ID register definitions */
00094 #define DP8_PHYID1_OUI     0x2000     /**< Expected PHY ID1 */
00095 #define DP8_PHYID2_OUI     0x5c90     /**< Expected PHY ID2 */
00096 
00097 /** \brief LAN8720 PHY Special Control/Status Register */
00098 #define PHY_SCSR_100MBIT    0x0008    /**< Speed: 1=100 MBit, 0=10Mbit */
00099 #define PHY_SCSR_DUPLEX     0x0010    /**< PHY Duplex Mask             */
00100 
00101 /** \brief Link status bits */
00102 #define LNK_STAT_VALID       0x01 
00103 #define LNK_STAT_FULLDUPLEX  0x02
00104 #define LNK_STAT_SPEED10MPS  0x04
00105 
00106 /** \brief PHY ID definitions */
00107 #define DP83848C_ID         0x20005C90  /**< PHY Identifier - DP83848C */
00108 #define LAN8720_ID          0x0007C0F0  /**< PHY Identifier - LAN8720  */
00109 
00110 /** \brief PHY status structure used to indicate current status of PHY.
00111  */
00112 typedef struct {
00113     u32_t     phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
00114     u32_t     phy_full_duplex:1;  /**< Half/full duplex connection speed flag. */
00115     u32_t     phy_link_active:1;  /**< Phy link active flag. */
00116 } PHY_STATUS_TYPE;
00117 
00118 /** \brief  PHY update flags */
00119 static PHY_STATUS_TYPE physts;
00120 
00121 /** \brief  Last PHY update flags, used for determing if something has changed */
00122 static PHY_STATUS_TYPE olddphysts;
00123 
00124 /** \brief  PHY update counter for state machine */
00125 static s32_t phyustate;
00126 
00127 /** \brief  Holds the PHY ID */
00128 static u32_t phy_id;
00129 
00130 /** \brief  Temporary holder of link status for LAN7420 */
00131 static u32_t phy_lan7420_sts_tmp;
00132 
00133 /** \brief  Update PHY status from passed value
00134  *
00135  *  This function updates the current PHY status based on the
00136  *  passed PHY status word. The PHY status indicate if the link
00137  *  is active, the connection speed, and duplex.
00138  *
00139  *  \param[in]    netif   NETIF structure
00140  *  \param[in]    linksts Status word from PHY
00141  *  \return        1 if the status has changed, otherwise 0
00142  */
00143 static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts)
00144 {
00145     s32_t changed = 0;
00146 
00147     /* Update link active status */
00148     if (linksts & LNK_STAT_VALID)
00149         physts.phy_link_active = 1;
00150     else
00151         physts.phy_link_active = 0;
00152 
00153     /* Full or half duplex */
00154     if (linksts & LNK_STAT_FULLDUPLEX)
00155         physts.phy_full_duplex = 1;
00156     else
00157         physts.phy_full_duplex = 0;
00158 
00159     /* Configure 100MBit/10MBit mode. */
00160     if (linksts & LNK_STAT_SPEED10MPS)
00161         physts.phy_speed_100mbs = 0;
00162     else
00163         physts.phy_speed_100mbs = 1;
00164 
00165     if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
00166         changed = 1;
00167         if (physts.phy_speed_100mbs) {
00168             /* 100MBit mode. */
00169             lpc_emac_set_speed(1);
00170 
00171             NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
00172         }
00173         else {
00174             /* 10MBit mode. */
00175             lpc_emac_set_speed(0);
00176 
00177             NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
00178         }
00179 
00180         olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
00181     }
00182 
00183     if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
00184         changed = 1;
00185         if (physts.phy_full_duplex)
00186             lpc_emac_set_duplex(1);
00187         else
00188             lpc_emac_set_duplex(0);
00189 
00190         olddphysts.phy_full_duplex = physts.phy_full_duplex;
00191     }
00192 
00193     if (physts.phy_link_active != olddphysts.phy_link_active) {
00194         changed = 1;
00195 #if NO_SYS == 1
00196         if (physts.phy_link_active)
00197             netif_set_link_up(netif);
00198         else
00199             netif_set_link_down(netif);
00200 #else
00201         if (physts.phy_link_active)
00202             tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
00203                 (void*) netif, 1);
00204          else
00205             tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
00206                 (void*) netif, 1);
00207 #endif
00208 
00209         olddphysts.phy_link_active = physts.phy_link_active;
00210     }
00211 
00212     return changed;
00213 }
00214 
00215 /** \brief  Initialize the DP83848 PHY.
00216  *
00217  *  This function initializes the DP83848 PHY. It will block until
00218  *  complete. This function is called as part of the EMAC driver
00219  *  initialization. Configuration of the PHY at startup is
00220  *  controlled by setting up configuration defines in lpc_phy.h.
00221  *
00222  *  \param[in]     netif   NETIF structure
00223  *  \param[in]     rmii    If set, configures the PHY for RMII mode
00224  *  \return         ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
00225  */
00226 err_t lpc_phy_init(struct netif *netif, int rmii)
00227 {
00228     u32_t tmp;
00229     s32_t i;
00230 
00231     physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
00232     physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
00233     physts.phy_link_active = olddphysts.phy_link_active = 2;
00234     phyustate = 0;
00235 
00236     /* Only first read and write are checked for failure */
00237     /* Put the DP83848C in reset mode and wait for completion */
00238     if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
00239         return ERR_TIMEOUT;
00240     i = 400;
00241     while (i > 0) {
00242         osDelay(1);   /* 1 ms */
00243         if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
00244             return ERR_TIMEOUT;
00245 
00246         if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
00247             i = -1;
00248         else
00249             i--;
00250     }
00251     /* Timeout? */
00252     if (i == 0)
00253         return ERR_TIMEOUT;
00254 
00255     // read PHY ID
00256     lpc_mii_read(DP8_IDR1_REG, &tmp);
00257     phy_id = (tmp << 16);
00258     lpc_mii_read(DP8_IDR2_REG, &tmp);    
00259     phy_id |= (tmp & 0XFFF0);    
00260 
00261     /* Setup link based on configuration options */
00262 #if PHY_USE_AUTONEG==1
00263     tmp = DP8_AUTONEG;
00264 #else
00265     tmp = 0;
00266 #endif
00267 #if PHY_USE_100MBS==1
00268     tmp |= DP8_SPEED_SELECT;
00269 #endif
00270 #if PHY_USE_FULL_DUPLEX==1
00271     tmp |= DP8_DUPLEX_MODE;
00272 #endif
00273     lpc_mii_write(DP8_BMCR_REG, tmp);
00274 
00275     /* Enable RMII mode for PHY */
00276     if (rmii)
00277         lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
00278 
00279     /* The link is not set active at this point, but will be detected
00280        later */
00281 
00282     return ERR_OK;
00283 }
00284 
00285 /* Phy status update state machine */
00286 s32_t lpc_phy_sts_sm(struct netif *netif)
00287 {
00288     s32_t changed = 0;
00289     u32_t data = 0;
00290     u32_t tmp;
00291 
00292     switch (phyustate) {
00293         default:
00294         case 0:
00295             if (phy_id == DP83848C_ID) {    
00296                 lpc_mii_read_noblock(DP8_PHY_STAT_REG);
00297                 phyustate = 2;
00298             }
00299             else if (phy_id == LAN8720_ID) {
00300                 lpc_mii_read_noblock(DP8_PHY_SCSR_REG);
00301                 phyustate = 1;        
00302             }
00303             break;
00304 
00305         case 1:
00306             if (phy_id == LAN8720_ID) {
00307                 tmp = lpc_mii_read_data();
00308                 // we get speed and duplex here. 
00309                 phy_lan7420_sts_tmp =  (tmp & PHY_SCSR_DUPLEX)  ? LNK_STAT_FULLDUPLEX : 0;
00310                 phy_lan7420_sts_tmp |= (tmp & PHY_SCSR_100MBIT) ? 0 : LNK_STAT_SPEED10MPS;
00311 
00312                 //read the status register to get link status 
00313                 lpc_mii_read_noblock(DP8_BMSR_REG);
00314                 phyustate = 2;        
00315             }
00316             break;
00317 
00318         case 2:
00319             /* Wait for read status state */
00320             if (!lpc_mii_is_busy()) {
00321                 /* Update PHY status */
00322                 tmp = lpc_mii_read_data();
00323 
00324                 if (phy_id == DP83848C_ID) {
00325                     // STS register contains all needed status bits
00326                     data  = (tmp & DP8_VALID_LINK) ? LNK_STAT_VALID : 0;
00327                     data |= (tmp & DP8_FULLDUPLEX) ? LNK_STAT_FULLDUPLEX : 0;
00328                     data |= (tmp & DP8_SPEED10MBPS) ? LNK_STAT_SPEED10MPS : 0;
00329                 }
00330                 else if (phy_id == LAN8720_ID) {    
00331                     // we only get the link status here.
00332                     phy_lan7420_sts_tmp |= (tmp & DP8_LINK_STATUS) ? LNK_STAT_VALID : 0;
00333                     data = phy_lan7420_sts_tmp;          
00334                 }
00335 
00336                 changed = lpc_update_phy_sts(netif, data);        
00337                 phyustate = 0;                
00338             }
00339             break;
00340     }
00341 
00342     return changed;
00343 }
00344 
00345 /**
00346  * @}
00347  */
00348 
00349 /* --------------------------------- End Of File ------------------------------ */